Bump addins/riscv-arch-test-cvw from fe87aaf to 2e65596 - #1822
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Bump addins/riscv-arch-test-cvw from fe87aaf to 2e65596#1822dependabot[bot] wants to merge 1 commit into
fe87aaf to 2e65596#1822dependabot[bot] wants to merge 1 commit into
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Bumps [addins/riscv-arch-test-cvw](https://github.com/riscv-non-isa/riscv-arch-test) from `fe87aaf` to `2e65596`. - [Release notes](https://github.com/riscv-non-isa/riscv-arch-test/releases) - [Commits](riscv/riscv-arch-test@fe87aaf...2e65596) --- updated-dependencies: - dependency-name: addins/riscv-arch-test-cvw dependency-version: 2e655961f9edc688c5cf0c0ea129a368a17a5731 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Superseded by #1823. |
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August 31, 2026 13:34
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Bumps addins/riscv-arch-test-cvw from
fe87aafto2e65596.Commits
2e65596Update dependency riscv-collab/riscv-gnu-toolchain to v2026.08.24 (#2176)09ec4e4Lock file maintenance (#2177)9d85ed6Update pre-commit hook renovatebot/pre-commit-hooks to v44.32.2 (#2180)7dae682Imperas override to fix MISA dependency (#2178)3561c2bT-SBI for ExceptionsS/Sm (#2166)010d9acSmV speedup and reduce default TESTCASES_PER_PRIV_FILE (#2171)4ed3584Lock file maintenance (#2174)806a076T-SBI conversion of S, UF, UV: run in S-mode, move M-mode coverpoints to Sm (...a03e7a4Update pre-commit hooks (#2173)8111623Fix for CVW RV32IMC (#2167)Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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