Bump addins/riscv-arch-test-cvw from fe87aaf to 3561c2b - #1820
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Bump addins/riscv-arch-test-cvw from fe87aaf to 3561c2b#1820dependabot[bot] wants to merge 1 commit into
fe87aaf to 3561c2b#1820dependabot[bot] wants to merge 1 commit into
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Bumps [addins/riscv-arch-test-cvw](https://github.com/riscv-non-isa/riscv-arch-test) from `fe87aaf` to `3561c2b`. - [Release notes](https://github.com/riscv-non-isa/riscv-arch-test/releases) - [Commits](riscv/riscv-arch-test@fe87aaf...3561c2b) --- updated-dependencies: - dependency-name: addins/riscv-arch-test-cvw dependency-version: 3561c2b4548feb214cc83373a78e9af47e276f8b dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Superseded by #1822. |
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August 28, 2026 13:33
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Bumps addins/riscv-arch-test-cvw from
fe87aafto3561c2b.Commits
3561c2bT-SBI for ExceptionsS/Sm (#2166)010d9acSmV speedup and reduce default TESTCASES_PER_PRIV_FILE (#2171)4ed3584Lock file maintenance (#2174)806a076T-SBI conversion of S, UF, UV: run in S-mode, move M-mode coverpoints to Sm (...a03e7a4Update pre-commit hooks (#2173)8111623Fix for CVW RV32IMC (#2167)39bcbbcUpdate dependency prek to v0.4.14 (#2172)4690c5eT-SBI guidance (#2160)2b03500Reenable Spike RV32 Sm1p13 (#2163)0cdc2b0Update riscv/riscv-isa-sim digest to 231e0d5 (#2164)Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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