Vector

config/rv32e/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 0;
 localparam logic ZFA_SUPPORTED = 0;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 0;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 0; // Supervisor mode
 localparam logic U_SUPPORTED = 0; // User mode

config/rv32gc/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 1;
 localparam logic ZFA_SUPPORTED = 1;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 1;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 1; // Supervisor mode
 localparam logic U_SUPPORTED = 1; // User mode

config/rv32i/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 0;
 localparam logic ZFA_SUPPORTED = 0;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 0;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 0; // Supervisor mode
 localparam logic U_SUPPORTED = 0; // User mode

config/rv32imc/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 0;
 localparam logic ZFA_SUPPORTED = 0;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 0;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 0; // Supervisor mode
 localparam logic U_SUPPORTED = 1; // User mode

config/rv64gc/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 1;
 localparam logic ZFA_SUPPORTED = 1;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 0;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 1; // Supervisor mode
 localparam logic U_SUPPORTED = 1; // User mode

config/rv64i/config.vh

@@ -84,6 +84,19 @@ localparam logic Q_SUPPORTED   = 0;
 localparam logic ZFH_SUPPORTED = 0;
 localparam logic ZFA_SUPPORTED = 0;
 
+// Vector extensions
+localparam logic V_SUPPORTED = 0;
+localparam VLEN = 32'd256;
+localparam VPU_MAX_EU = 32'd4;
+localparam VPU_INT_EU = 32'd2;
+localparam VPU_INT_LANES = 32'd2;
+localparam VPU_INT_MUL = 32'd2;
+localparam VPU_INT_MUL_LANES = 32'd2;
+localparam VPU_FP_EU = 32'd2;
+localparam VPU_FP_LANES = 32'd2;
+localparam VPU_LSU_EU = 32'd2;
+localparam VPU_LSU_LANES = 32'd2;
+
 // privilege modes
 localparam logic S_SUPPORTED = 0; // Supervisor mode
 localparam logic U_SUPPORTED = 0; // User mode

config/shared/config-shared.vh

@@ -127,3 +127,9 @@ localparam FMALEN = 3*NF + 6;
 localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
 
 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
+
+// *** change 64 to the max vector element length
+localparam VPU_LSU_BLEN = 64 * VPU_LSU_LANES;
+localparam VPU_INT_BLEN = 64 * VPU_INT_LANES;
+localparam VPU_INT_MUL_BLEN = 64 * VPU_INT_MUL_LANES;
+localparam VPU_FP_BLEN = 64 * VPU_FP_LANES;

config/shared/parameter-defs.vh

@@ -17,6 +17,21 @@ localparam cvw_t P = '{
   ZIHPM_SUPPORTED :      ZIHPM_SUPPORTED,
   ZFH_SUPPORTED :        ZFH_SUPPORTED,
   ZFA_SUPPORTED :        ZFA_SUPPORTED,
+  V_SUPPORTED :          V_SUPPORTED,
+  VLEN :                 VLEN,
+  VPU_MAX_EU :           VPU_MAX_EU,
+  VPU_INT_EU :           VPU_INT_EU,
+  VPU_INT_LANES :        VPU_INT_LANES,
+  VPU_INT_MUL :          VPU_INT_MUL,
+  VPU_INT_MUL_LANES :    VPU_INT_MUL_LANES,
+  VPU_FP_EU :            VPU_FP_EU,
+  VPU_FP_LANES :         VPU_FP_LANES,
+  VPU_LSU_EU :           VPU_LSU_EU,
+  VPU_LSU_LANES :        VPU_LSU_LANES,
+  VPU_LSU_BLEN : VPU_LSU_BLEN,
+  VPU_INT_BLEN : VPU_INT_BLEN,
+  VPU_INT_MUL_BLEN : VPU_INT_MUL_BLEN,
+  VPU_FP_BLEN : VPU_FP_BLEN,
   SSTC_SUPPORTED :       SSTC_SUPPORTED,
   VIRTMEM_SUPPORTED :    VIRTMEM_SUPPORTED,
   SV32_SUPPORTED :       SV32_SUPPORTED,

src/cvw.sv

@@ -229,6 +229,7 @@ typedef struct packed {
   logic D_SUPPORTED;
   logic E_SUPPORTED;
   logic F_SUPPORTED;
+  logic V_SUPPORTED;
   logic I_SUPPORTED;
   logic M_SUPPORTED;
   logic Q_SUPPORTED;
@@ -302,6 +303,23 @@ typedef struct packed {
   int DIVBLEN    ;
 // integer division/remainder constants
   int INTDIVb    ;
+
+  // Vector extensions
+  int VLEN;
+  int VPU_MAX_EU;
+  int VPU_INT_EU;
+  int VPU_INT_LANES;
+  int VPU_INT_MUL;
+  int VPU_INT_MUL_LANES;
+  int VPU_FP_EU;
+  int VPU_FP_LANES;
+  int VPU_LSU_EU;
+  int VPU_LSU_LANES;
+  int VPU_LSU_BLEN;
+  int VPU_INT_BLEN;
+  int VPU_INT_MUL_BLEN;
+  int VPU_FP_BLEN;
+
 } cvw_t;
 
 endpackage

src/ieu/controller.sv

@@ -44,6 +44,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        LoadStallD,              // Structural stalls for load, sent to performance counters
   output logic        StoreStallD,             // load after store hazard
   output logic [4:0]  Rs1D, Rs2D, Rs2E,        // Register sources to read in Decode or Execute stage
+  output logic        VectorD,                 // Instruction is a Vector, transfer control to VPU
   // Execute stage control signals
   input  logic        StallE, FlushE,          // Stall, flush Execute stage
   input  logic [1:0]  FlagsE,                  // Comparison flags ({eq, lt})
@@ -142,6 +143,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
   logic        FLSFunctD;                      // Detect floating-point loads and stores
+  logic        VLSFunctD;                      // Detect vector loads and stores
   logic        JRFunctD;                       // detect jalr instruction
   logic        FenceFunctD;                    // Detect fence instruction
   logic        CMOFunctD;                      // Detect CMO instruction
@@ -190,6 +192,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign MFunctD          = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 |
                               ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
+    assign VLSFunctD        = (Funct3D == 3'b000 | Funct3D == 3'b101 | Funct3D == 3'b110 | Funct3D == 3'b111) & P.V_SUPPORTED;  //*** needed in else branch?
     assign FLSFunctD        = (STATUS_FS != 2'b00) & ((Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) |
                               (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED));
     assign FenceFunctD      = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001);
@@ -223,6 +226,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD = 1'b1; // don't bother to check Funct3 for loads
     assign FLSFunctD = 1'b1; // don't bother to check Func3 for floating-point loads/stores
+    assign VLSFunctD = 1'b1; // **** ?
     assign FenceFunctD = 1'b1; // don't bother to check fields for fences
     assign CMOFunctD = 1'b1; // don't bother to check fields for CMO instructions
     assign AFunctD = 1'b1; // don't bother to check fields for atomics
@@ -294,6 +298,13 @@ module controller import cvw::*;  #(parameter cvw_t P) (
                   end
     endcase
   end
+
+  if (P.V_SUPPORTED) begin
+    assign VectorD = ((OpD == 7'b0000111 | OpD == 7'b0100111) & VLSFunctD) | OpD == 7'b1010111;
+  end else begin
+    assign VectorD = '0;
+  end
+
   /* verilator lint_on CASEINCOMPLETE */
 
   // Unswizzle control bits

src/ieu/ieu.sv

@@ -35,6 +35,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   input  logic [3:0]        ENVCFG_CBE,                      // Cache block operation enables
   input  logic              IllegalIEUFPUInstrD,             // Illegal instruction
   output logic              IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  output logic              VectorD,                         // Instruction is a Vector, transfer control to VPU
   // Execute stage signals
   input  logic [P.XLEN-1:0] PCE,                             // PC
   input  logic [P.XLEN-1:0] PCLinkE,                         // PC + 4
@@ -109,7 +110,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   controller #(P) c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
-    .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,  .Rs2E,
+    .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,  .Rs2E, .VectorD,
     .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE,
     .Funct3E, .Funct7E, .IntDivE, .W64E, .UW64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE,

src/vpu/lmulsequencer.sv

@@ -0,0 +1,95 @@
+///////////////////////////////////////////
+// lmulsequencer.sv
+//
+// Written: Rose Thompson rose.thompson@skyworksinc.com
+// Created: 1 September 2026
+// Modified: 1 September 2026
+//
+// Purpose: sequence multiple micro-op vector instructions based on lmul
+//
+// Documentation: RISC-V System on Chip Design Volume 2
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+//
+// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module lmulsequencer (
+  input  logic        clk, reset,
+  // Decode stage control signals
+  input  logic        StallD, FlushD,          // Stall, flush Decode stage
+  input  logic        VectorD,                 // This instruction is a vector
+  input  logic [4:0]  Vs1D, Vs2D, VdD,
+  input  logic [6:0]  lmulDecodedD,
+  // hand shaking controls
+  input  logic        AnyExecutionUnitReadyD,
+  // output micro vector instruction
+  output logic [4:0]  Vs1FinalD, Vs2FinalD, VdFinalD
+);
+
+  logic        IncrMicroOpD;            // Next micro vector instruction when lmul > 1
+
+  logic        IncrD;
+  logic [4:0]  Vs1P1D, Vs2P1D, VdP1D;
+  logic [4:0]  Vs1P1QD, Vs2P1QD, VdP1QD;
+  logic [3:0]  lmulCntrD, lmulCntrP1;
+  logic        lmulCntrDone, lmulCntrLoad;
+  logic        lmulCntrFirstCaptureD;
+  logic [3:0]  lmulIntD;
+
+  typedef enum logic {STATE_BEGIN, STATE_INCR} statetype;
+  statetype CurrState, NextState;
+
+  assign lmulIntD = lmulDecodedD[6:3];
+  assign lmulCntrFirstCaptureD = lmulCntrD > 1;
+
+  assign Vs1P1D = Vs1FinalD + 5'b00001;
+  flopenr #(5) Vs1IncrReg (clk, reset, IncrD, Vs1P1D, Vs1P1QD);
+  mux2 #(5) Vs1Mux (Vs1D, Vs1P1QD, lmulCntrFirstCaptureD, Vs1FinalD);
+
+  assign Vs2P1D = Vs2FinalD + 5'b00001;
+  flopenr #(5) Vs2IncrReg (clk, reset, IncrD, Vs2P1D, Vs2P1QD);
+  mux2 #(5) Vs2Mux (Vs2D, Vs2P1QD, lmulCntrFirstCaptureD, Vs2FinalD);
+
+  assign VdP1D = VdFinalD + 5'b00001;
+  flopenr #(5) VdIncrReg  (clk, reset, IncrD, VdP1D,  VdP1QD);
+  mux2 #(5) VdMux (VdD, VdP1QD, lmulCntrFirstCaptureD, VdFinalD);
+
+
+  flopenl #(4) counter (clk, lmulCntrLoad, IncrD, lmulCntrP1, 4'b0001, lmulCntrD);
+  assign lmulCntrDone = lmulCntrD == lmulIntD; // *** this is a bug for lmul less than 1
+  assign lmulCntrP1 = lmulCntrD + 4'b0001;
+
+  always_ff @(posedge clk)
+    if(reset | FlushD) CurrState <= STATE_BEGIN;
+    else CurrState <= NextState;
+
+  assign IncrD = AnyExecutionUnitReadyD & VectorD;
+
+  always_comb begin
+    NextState = STATE_BEGIN;
+    case(CurrState)
+      STATE_BEGIN: if(VectorD & (lmulIntD > 4'd1) & IncrD) NextState = STATE_INCR;
+      STATE_INCR:  if(lmulCntrD == lmulIntD) NextState = STATE_BEGIN;
+      else NextState = STATE_INCR;
+      default: NextState = STATE_BEGIN;
+    endcase
+  end
+
+  assign lmulCntrLoad = CurrState == STATE_BEGIN & VectorD;
+
+endmodule