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1. dtmf dtmf Public

   Verilog

2. hdl_projects hdl_projects Public

   Verilog

3. zephyr-intermediate zephyr-intermediate Public

   Forked from iomico-public/zephyr-intermediate

   C

4. RISCV RISCV Public

   A riscv processor implementation. Also planning to connect to other peripherals and devices using busses and memory mapping.

   Verilog

5. uart_streamed_fir_filter uart_streamed_fir_filter Public

   Fir low pass filter streamed with signal through python. Implemented it using verilog on icebreaker fpga.

   Verilog