MCPWM Peripheral functions

common_patches/mcpwm.yaml

@@ -0,0 +1,26 @@
+CAP_STATUS:
+  _array:
+    CAP?_EDGE:
+      description: Describes the last captured edge on channel%s.
+  CAP?_EDGE:
+    Rising: [0, "Rising edge"]
+    Falling: [1, "Falling edge"]
+
+CAP_CH?_CFG:
+  _modify:
+    CAP?_MODE:
+      description: Describes which edges to trigger a capture event
+  CAP?_MODE:
+    None: [0, "Capture nothing"]
+    FallingEdge: [1, "Capture falling edges"]
+    RisingEdge: [2, "Capture rising edges"]
+    AnyEdge: [3, "Capture any edges"]
+
+TIMER_SYNCI_CFG:
+  _array:
+    TIMER?_SYNCISEL: {}
+    EXTERNAL_SYNCI?_INVERT: {}
+
+OPERATOR_TIMERSEL:
+  _array:
+    OPERATOR?_TIMERSEL: {}

common_patches/mcpwm_collect.yaml

@@ -91,4 +91,4 @@ _array:
     description: Value of last capture on channel %s
     _strip: CAP?_
 
-_include: int_strip.yaml
+_include: int_strip.yaml

esp32/src/mcpwm0/cap_ch_cfg.rs

@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - "]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - "]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - "]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP0_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP0_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP0_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP0_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP0_MODE {}
+#[doc = "Field `MODE` reader - Describes which edges to trigger a capture event"]
+pub type MODE_R = crate::FieldReader<CAP0_MODE>;
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_MODE {
+        match self.bits {
+            0 => CAP0_MODE::None,
+            1 => CAP0_MODE::FallingEdge,
+            2 => CAP0_MODE::RisingEdge,
+            3 => CAP0_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP0_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP0_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP0_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP0_MODE::AnyEdge
+    }
+}
+#[doc = "Field `MODE` writer - Describes which edges to trigger a capture event"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP0_MODE, crate::Safe>;
+impl<'a, REG> MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - "]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - "]
@@ -26,7 +109,7 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)

esp32/src/mcpwm0/cap_status.rs

@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - "]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - "]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - "]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]

esp32/src/mcpwm0/cap_timer_phase.rs

@@ -2,30 +2,30 @@
 pub type R = crate::R<CAP_TIMER_PHASE_SPEC>;
 #[doc = "Register `CAP_TIMER_PHASE` writer"]
 pub type W = crate::W<CAP_TIMER_PHASE_SPEC>;
-#[doc = "Field `CAP_TIMER_PHASE` reader - "]
-pub type CAP_TIMER_PHASE_R = crate::FieldReader<u32>;
-#[doc = "Field `CAP_TIMER_PHASE` writer - "]
-pub type CAP_TIMER_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+#[doc = "Field `CAP_PHASE` reader - "]
+pub type CAP_PHASE_R = crate::FieldReader<u32>;
+#[doc = "Field `CAP_PHASE` writer - "]
+pub type CAP_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl R {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    pub fn cap_timer_phase(&self) -> CAP_TIMER_PHASE_R {
-        CAP_TIMER_PHASE_R::new(self.bits)
+    pub fn cap_phase(&self) -> CAP_PHASE_R {
+        CAP_PHASE_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_timer_phase", &self.cap_timer_phase())
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    pub fn cap_timer_phase(&mut self) -> CAP_TIMER_PHASE_W<'_, CAP_TIMER_PHASE_SPEC> {
-        CAP_TIMER_PHASE_W::new(self, 0)
+    pub fn cap_phase(&mut self) -> CAP_PHASE_W<'_, CAP_TIMER_PHASE_SPEC> {
+        CAP_PHASE_W::new(self, 0)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_phase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_phase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]