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M68k rzil base - #6706
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M68k rzil base#6706
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b1llow
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Rot127
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Just did a quick check on the test coverage. Please add tests to check the following:
m68k_fill_fpu_hidden_dst- The uncovered code guarded by
RZ_CAPSTONE_HAS_M68K_FP_FORMATSandRZ_CAPSTONE_HAS_M68K_COLDFIRE - Codecov is buggy and I can't see the m68k_il.c coverage. But please make sure that the most common instructions (branches etc.) are all tested.
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also needs to resolve the conflicts |
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Rot127
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I checked the wrong PR before (#6547 (review)). Sorry.
But lgtm.
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Co-authored-by agent: Codex/GPT-5 Co-authored-by agent: Codex/GPT-6
Integrate the lifter with the M68K analysis plugin and provide shared effective-address, register, condition-code, and stack-bank helpers. Implement integer arithmetic, bit operations, control flow, and privileged operations, including CPU32 table interpolation and ColdFire MAC/EMAC instructions with CPU-specific behavior. Add IL snapshots and execution regressions covering arithmetic flags, effective addresses, register aliasing, exception returns, privilege checks, and decoder edge cases. Leave floating-point instruction lifting outside this change. Co-authored-by agent: Codex/GPT-5 Co-authored-by agent: Codex/GPT-6
Exercise hidden FPU destinations, floating-point format metadata, ColdFire operand values, every integer condition, and representative integer and control-flow effects through public analysis and IL VM APIs. Register the suite for bundled Capstone builds. Sign-extend absolute-short memory addresses consistently in analysis values, OPEX, and JMP/JSR targets, matching the architectural execution result. Co-authored-by agent: Codex/GPT-6
Construct integer and fractional EV expressions only in the EMAC branch that attaches them to the returned IL tree. Non-EMAC accumulator copies preserve EV without allocating unused expression trees. Add 18 accumulator-copy execution cases across ColdFire, CFv4e, and CFv5, covering signed, unsigned, and fractional modes with both initial EV values. The LSan unit suite reports 6912 leaked bytes before the fix and none after. Co-authored-by agent: Codex/GPT-6
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@b1llow please resolve the conflict and feel free to merge |
Preserve the M68K RzIL feature flags and filtered-list entries alongside upstream TMS320 c28x metadata and corresponding table widths. Co-authored-by agent: Codex/OpenAI (model unspecified)
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Your checklist for this pull request
RZ_APIfunction and struct this PR changes.RZ_API).Detailed description
Adds core RzIL support for M68K, CPU32, and ColdFire, split from #6547 to make review easier. FP lifting will follow separately.
Covers integer arithmetic, bit operations, data transfers, control flow, stack operations, CPU32 table interpolation, and ColdFire MAC/EMAC.
FP decoding and register metadata remain available, but FP instructions produce no IL.
AI assistance: OpenAI Codex (GPT-5), used for implementation, fixes, and tests.
Test plan
Trace testing used Rizin
691e12265854, QEMUbce9b9d04d72(trace producer PR), and rz-tracetesta4cf3ba22a4c(M68K adapter PR).The non-FP matrix covers 210 instruction IDs, 44,627 encoding/profile cases, and 116,831 case/path executions. ColdFire
FF1is included.680006801068020680306804068060cpu32coldfirecfv1cfv2cfv3cfv4cfv4ecfv5QEMU is not the architectural oracle; semantic adjudications use official manuals. Raw results are retained, and exclusions are qualified by specific encoding/state/trace evidence rather than mnemonic-wide skips.
Producer limitations:
cpu32uses QEMUm68020;coldfire,cfv1,cfv3,cfv4, andcfv5useany;cfv2usesm5208. These results are not hardware validation.Closing issues
Related to #5847. FP lifting remains follow-up work.