An IEEE 754 Floating Point adder in VHDL done from scratch with basic components.
Repository of the project developed for the "Final project in Digital Logic Design" course, part of the Bachelor of Science in Engineering of Computing System at Politecnico di Milano.
| First name | Last Name | GitHub |
|---|---|---|
| Kevin | Guglietmetti | https://github.com/kevinGuglielmetti |
| Rafael Francesco | Mosca Aguilar | https://github.com/rfma23 |