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Fix spr_eear to save appropriate value for each exception #108

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Fix spr_eear to save appropriate value for each exception #108

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4 changes: 2 additions & 2 deletions rtl/verilog/mor1kx_ctrl_cappuccino.v
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Original file line number Diff line number Diff line change
Expand Up @@ -833,9 +833,9 @@ module mor1kx_ctrl_cappuccino
spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}};
else if (/*padv_ctrl & exception*/ exception_re)
begin
if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i)
if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i | except_illegal_i)
spr_eear <= pc_ctrl_i;
else
else if (except_dbus_i | except_dtlb_miss_i | except_dpagefault_i | except_align_i)

@skristiansson skristiansson Oct 15, 2020

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why is this needed?
either this list is covering all the cases that are not covered in the previous if and then it is superfluous,
or it does not contain all the cases that are not covered in the previous if and then it is wrong

@stffrdhrn stffrdhrn Oct 15, 2020

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I agree, with verilog we should always have an else case otherwise the logic is incomplete. Also, the reason I am looking at this is because I noticed during linux debugging with mor1kx the trap instructions are appearing to have incorrect EEAR set. The trap case doesn't seem to be handler here, maybe its somewhere else?

@stffrdhrn stffrdhrn Oct 18, 2020

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Well, my comment is wrong here l.trap doesn't set eear as per spec.

spr_eear <= ctrl_lsu_adr_i;
end

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