Check reserved bits in non-leaf PTEs - #1815
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Pull request overview
This PR tightens hypervisor page-table-walk (HPTW) validation for non-leaf PTEs in the MMU by expanding the reserved-bit check to cover the full PTE[63:54] range on RV64, aligning behavior with the expectation that N/PBMT/reserved upper bits must be zero for non-leaf entries.
Changes:
- Expand non-leaf PTE reserved-bit fault detection from
PTE[62:61](PBMT only) toPTE[63:54](includes N + reserved bits) on RV64. - Preserve RV32 behavior by keeping the fault disabled when
P.XLEN != 64.
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Non-leaf checking covered PBMT but ignored N plus reserved bits. Check
PTE[63:54].