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PWM Peripheral - #1803

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naichewa wants to merge 21 commits into
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naichewa:pwm
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PWM Peripheral#1803
naichewa wants to merge 21 commits into
openhwgroup:mainfrom
naichewa:pwm

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@naichewa

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Adds a PWM peripheral with 4 16 bit comparators and 2 tests. WALLY-pwm-01.S contains "dumb" functions that wait the estimated duration of X pwm cycles, allowing for tests by inspection. WALLY-pwms-01.S counts the number of high/low cycles and compares to reference

//
// WALLY-pwm
//
// Author: Naiche Whyte-Aguayo naichewa@gmail.com>

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Tests should have some introductory text explaining what they are testing. The reference_output of pwm-01.S suggests it isn't testing much. Is it worth keeping this one?

Most of the test is commented out. Is it worth keeping the commented out parts? If so, explain why they are there.

All the features of the module should be fully tested in a self-checking fashion.

Same comments on pwms.

Comment thread src/uncore/pwm_apb.sv Outdated
// Purpose: PWM module
// https://docs.google.com/document/d/1erHBVchBtwmgZ0bCNjb88spYfN7CpRbhmSNFH6cO8CY/edit?tab=t.0
//
// Documentation: RISC-V System on Chip Design

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Not documented in the book.

Comment thread src/uncore/pwm_apb.sv Outdated
// Modified:
//
// Purpose: PWM module
// https://docs.google.com/document/d/1erHBVchBtwmgZ0bCNjb88spYfN7CpRbhmSNFH6cO8CY/edit?tab=t.0

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This URL doesn't describe the PWM.

Comment thread src/uncore/pwm_apb.sv Outdated
// https://docs.google.com/document/d/1erHBVchBtwmgZ0bCNjb88spYfN7CpRbhmSNFH6cO8CY/edit?tab=t.0
//
// Documentation: RISC-V System on Chip Design
// Based on PWM design from SiFive 5U540-C000 manual version 1.0

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Is this the FU540 chip, not 5U540? Include a link i possible, such as https://pdos.csail.mit.edu/6.828/2025/readings/FU540-C000-v1.0.pdf
or one to the SiFive site if available.

Comment thread src/uncore/pwm_apb.sv Outdated
assign PWMCountPrescaled = ((Memwrite & (Entry == PWM_COUNT)) ? Din[30:0] : PWMCountIncrement) >> PWMScale;


// Combinatorial signal logic

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Combinational

Comment thread src/uncore/pwm_apb.sv Outdated
end else if (Memwrite & (Entry == PWM_COUNT)) begin
PWMCount <= Din[30:0];
PWMScaled <= PWMCountPrescaled[15:0];
end else if (Memwrite & (Entry == PWM_S))PWMScaled <= Din[15:0];

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Space after paren

Comment thread src/uncore/pwm_apb.sv Outdated
PWMScaled <= PWMCountPrescaled[15:0];
end

flop #(1) pwmholdreg(PCLK,

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weird line break. Several places

Comment thread src/uncore/pwm_apb.sv Outdated
PWMHoldIn, PWMHoldOut);

//pwm comparators
assign PWMDeglitchMux[0] = PWMScaled[15] & PWMCompareCenter[0];

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This needs a better name. It is not a mux, and is also an input to an xor.

Comment thread src/uncore/pwm_apb.sv Outdated
//pwm comparators
assign PWMDeglitchMux[0] = PWMScaled[15] & PWMCompareCenter[0];
assign PWMCompareXNOR[15:0] = PWMDeglitchMux[0] ? ~PWMScaled : PWMScaled;
assign PWMCompareBoolean[0] = PWMCompareXNOR[15:0] >= PWMCompare0;

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Rename. Boolean isn't a helpful name for a binary signal.

Comment thread src/uncore/pwm_apb.sv Outdated
always_ff @(posedge PCLK)
if (PWMCountReset | ~PRESETn) begin
PWMCount <= 31'b0;
PWMScaled <= 16'b0;

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I'm not clear whether pwmscaled needs to be a separate 16-bit register, or if it can just be the result of combinational logic shifting pwmcount by up to 15. Although it is drawn as a register in Fig 6, it looks like it could be combinational because it doesn't hold any new state.

@naichewa naichewa Jul 21, 2026

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Spec has it as an acessible read/write-able register, although I agree other than following that it could be combinational. I also don't see why you would want to write to it and not PWM Count

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