Adding support for Qmtech Kintex-7 dev board.

[juanschroeder]

MIG .prj file was generated in Vivado.
Digilent SD card Pmod is assumed in J13.
Running at 40 MHz (not fully meeting constraints
but boots without issues).

Board: http://www.aliexpress.com/item/1005006765717166.html

[Copilot]

Pull request overview

Adds a new FPGA/Linux configuration target to run the Wally SoC on the Qmtech Kintex-7 (xc7k325t) development board, including Vivado IP generation and board-specific constraints/device-tree.

Changes:

• Introduces a new fpgaTopQmtechk7 top-level and Vivado generator targets/scripts for qmtechk7 (MMCM + DDR3 MIG).
• Adds a Qmtech-specific XDC constraints file and Linux device tree for booting at 40 MHz with 256 MB DDR3.
• Extends the config derivation list to include fpgaqmtechk7.

Reviewed changes

Copilot reviewed 12 out of 12 changed files in this pull request and generated 9 comments.

Show a summary per file

File	Description
linux/devicetree/wally-qmtechk7.dts	New device tree describing the qmtechk7 memory map and peripherals at 40 MHz.
fpga/src/fpgaTopQmtechk7.sv	New FPGA top-level integrating Wally SoC + DDR3 MIG + clocking for qmtechk7.
fpga/generator/xlnx_ddr3-qmtechk7-mig.prj	MIG project settings for the qmtechk7 DDR3 configuration.
fpga/generator/wally.tcl	Adds qmtechk7 selection for top + constraints + DDR3/MMCM IP import.
fpga/generator/sysrst.tcl	Skips board_part assignment for non-Xilinx qmtechk7 board identifier.
fpga/generator/mmcm-qmtechk7.tcl	New MMCM IP configuration for 50 MHz input and required output clocks.
fpga/generator/Makefile	Adds qmtechk7 make targets for IP generation and FPGA build flow.
fpga/generator/ddr3-qmtechk7.tcl	New DDR3 MIG IP generation script using the qmtechk7 MIG .prj.
fpga/generator/clkconverter.tcl	Skips board_part assignment for qmtechk7.
fpga/generator/ahbaxibridge.tcl	Skips board_part assignment for qmtechk7.
fpga/constraints/constraints-qmtechk7.xdc	New board constraints for clocks, IO pinout, SD, UART, DDR3.
config/derivlist.txt	Adds fpgaqmtechk7 derivation entry and external memory range.

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[davidharrishmc]

@juanschroeder would you be able to review the Copilot feedback above and click resolve conversation on each item when you are satisfied it is either fixed or irrelevant?

I don't have the FPGA expertise to review this well and Rose is not very active reviewing right now, but this is valuable work worth incorporating, so I will merge it when you have resolved the copilot feedback.

[juanschroeder]

Hi @davidharrishmc , yes, I will look into this after I finish the Nexys A7 one.

[rosethompson]

@juanschroeder I would be happy to merge this PR once the merge conflicts are resolved. We've merged the Nexys A7 PR.

[juanschroeder]

Hi @rosethompson, I've rebased this on a recent 'main' branch, applied Copilot suggestions, some fixes to eliminate critical warnings and warnings in the .xdc file and reduced the ambitious target clock frequency to 32 MHz. I've tested the updates in Buildroot and it seems to work.

Regarding the clock frequency, even if this FPGA is very similar to the one in Genesys 2, the speed grade is 'slower', and somehow for the same design there's way more routing congestion in the critical path area. The build without any extra optimization is 'close' to meet timing requirements and with the extra commented code in wally.tcl it would normally meet the timing requirements (build takes a bit longer).

Just some extra comments on this board:

• serial RX/TX pins are in the J3 50-pin connector
• Digilent micro SD card PMOD should be connected to 'J13' PMOD connector
• JTAG programming is done with the JTAG connector in the middle of the board.
• For programming and ILA within Vivado I've used an FT232H programmer like this one and xvcd tool running in the background (communication is a bit slow). In my Vivado versions I have issues with 'cs_server' and 'hw_server' and normally I need to disable the first one and often start manually the second one.
• Bear in mind that (as far as I know) all the 'peripherals' in this Qmtech board are only accessible from the RPi compute module, which is a waste for pure FPGA development. Only the PMODs and the 50-pin connector are useful for connecting other hardware.