Project Overview

Mentor

• Johnny Hazboun

Authors

• Mixuan Pan
• Myles Querimit
• Cristian Martinez
• Safa Islam

Description FPGA implementation of Tetris with VGA display. Features an AI Accelerator for infernces on a CNN model.

Instructions

sv2v

# without miguel's magic 
~ece270/bin/sv2v -w [newfile.v] [oldfile.sv] # e.g. ~ece270/bin/sv2v -w tetrisFSM.v /home/shay/a/mart2667/July18/starboy-5/source/tetrisFSM.sv 

# MIGUEL'S MAGIC 
make sv2v [filname] # e.g. make sv2v_tetrisFSM
make sim_[filename]_src_converted # e.g. make sim_tetrisFSM_src_converted

Git Source Control

Terminal Console (preferred/sometimes VScode takes forever to sync changes)

git pull 
git status # shows the modified/added/deleted files  
git add . # add all changes or add [filename] to add specific files 

# commit - short message 
git commit -m "[commit message]" 

# commit - long message/additional details
git commit 

G // go to the last line
o // make a new line 
[esc key] // escape insert mode 
// make a short commit comment
// (optional) make a blank line after and comment longer messages  
:x // execute 

git push -u origin main 

VScode

git pull 
git push

• go to source control and comment your commit
• sync changes

Testbench current CPU Performance

python3 test_mmu.py --depth 4 --size 4 --iters 100000

Nebula Repo

• clone the repo

make bus-wrap-setup

• add all submodules to verilog/rtl/team_projects/team_01/src
• all submodules should follow the naming with "t01_*"
• all files should be added to verilog/rtl/team_projects/team_01/includes
• to make cram:

make cram_team_01 

• add all testbenches to verilog/dv/team_01/module_tests

$dumpfile("[module_name].vcd"); // instead of $dumpfile("waves/[module_name].vcd"); 

make tb-module-team_01-[module_name]

Brain rot

i love matcha

Cristian Andres Martinez is 6'3 and buff and a feminist

References

Main Python/Model Repository: GitHub

Sources: Zotero Library

Testing: Documentation

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