RTL / FPGA 설계와 SystemVerilog/UVM 검증을 중심으로 FPGA 기반 시스템 통합 경험을 쌓아왔습니다.
Contact: tmdduf1101@naver.com
Portfolio: 이승열 | Notion Portfolio
| Project | Focus |
|---|---|
| Parallel Decision Tree Hardware | Parallel Datapath · 6→4-state FSM · 37-vector equivalence |
| FPGA VGA Conductor Game | XY Detection · FPGA-PC Integration · MAESTRO UI |
| RV32I Single-Cycle CPU | 37 RV32I Instructions · Datapath / Control |
| UART · FIFO · Sensor System | DHT11 · HC-SR04 · UART/FIFO Integration |
| FPGA Stopwatch & Watch | FSM / Datapath · Moment Capture |
| Project | Focus |
|---|---|
| MicroBlaze AXI4-Lite Peripheral System | 5 Custom IP · SPI 32/32 · I2C 30/30 · UVM |
| SPI & I2C UVM Verification | Scoreboard · Random Test · Functional Coverage |
| UART + FIFO + Parity Verification | Class-based TB · Queue Reference Model · Error Injection |
| Project | Focus |
|---|---|
| Multi-Camera Re-ID Tracking | Jetson 4-Node · Re-ID · MQTT |
| Jetson AI Rock-Paper-Scissors | MobileNetV2 · TensorRT · Hand ROI |
- HDL / Verification: Verilog, SystemVerilog, UVM, Scoreboard, Functional Coverage
- FPGA / SoC: Vivado, Basys3, MicroBlaze, AXI4-Lite, UART, SPI, I2C
- Software / Edge AI: C, Python, Jetson Orin Nano, TensorRT, OpenCV