Problem: Although the division algorithm yields correct results, the missing input registers in DSP48, namely AREG and BREG (and ACASREG and BCASREG), hurts timing.
Solution: Activate DSP48 input registers and reimplement the algorithm considering an additional one clock cycle delay in DSP48.
Problem: Although the division algorithm yields correct results, the missing input registers in DSP48, namely AREG and BREG (and ACASREG and BCASREG), hurts timing.
Solution: Activate DSP48 input registers and reimplement the algorithm considering an additional one clock cycle delay in DSP48.