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Cvwsoc rework - #21

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juanschroeder merged 3 commits into
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cvwsoc_rework
Jul 26, 2026
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Cvwsoc rework#21
juanschroeder merged 3 commits into
cvwsocfrom
cvwsoc_rework

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Configuration, throughput, cleanup improvements.
Some bugfixes on previous MR

Adapted VGA settings for Nexys A7 to release some resources.
It would normally also help timing but affect performance.
Tests did not show any difference.

Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
- Cleanup: simulation makefile including old bridge version
- fix: DDR constraints issues with DDR3 (Genesys 2)
- Cleanup: removed dependency on Xilinx MIG even when not used
- Bridge changes:
  - Updated to bridge version that has improvements for bursts of reads
    and writes, as used by caches' type of accesses.
  - The improvements make the custom bridge only 2% slower than Xilinx one.
  - Added some performance counters and probes for future perf evaluation
  - Most of traffic during 'fbdoom' run is data cache reads rather than
    writes. Something to check for improvements later.
- Set UberDDR3 the default for Genesys 2 RV32. Dmatest issues in parallel to
  cyclic dma to be checked later.

Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
@juanschroeder
juanschroeder merged commit 1cc0ad9 into cvwsoc Jul 26, 2026
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