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1. About_Me About_Me Public

2. VLSI_PD_ORCA_TOP_28nm VLSI_PD_ORCA_TOP_28nm Public

   PD_ORCA_TOP_28nm demonstrated a complete block-level ASIC PnR flow using Synopsys ICC2, transforming gate-level netlist to GDSII across floorplanning, power planning, placement, CTS, routing, and s…

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3. VLSI_Chip_Top_32nm VLSI_Chip_Top_32nm Public

   RTL synthesis of a 32nm CMOS ASIC block using Synopsys Design Compiler. Focuses on SDC constraint development, timing-driven logic optimization, QoR analysis, and generation of an optimized gate-le…

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4. VLSI_CHIP_TOP_45nm VLSI_CHIP_TOP_45nm Public

   Full RTL-to-GDSII physical design in 45nm CMOS using Cadence Innovus, Genus & Tempus. 64K+ std cells, 48 macros, 200 MHz timing closure.

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