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Si5351C refactoring #1747

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Merged
mossmann merged 4 commits into from
May 18, 2026
+868 −251
Merged

Si5351C refactoring #1747

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d00dae3
si5351c: API: change terminology to refer to XTAL/CLKIN as "inputs".
martinling May 3, 2026
098b9dd
si5351c: API: distinguish between PLL IDs and PLL masks.
martinling May 3, 2026
a1cdbad
si5351c: internal: Add register definitions and helpers.
martinling May 3, 2026
0169105
si5351c: internal: reimplement using register helpers.
martinling May 3, 2026
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13 changes: 7 additions & 6 deletions firmware/common/clock_gen.c
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Original file line number Diff line number Diff line change
Expand Up @@ -111,9 +111,9 @@ void clock_gen_init(void)
sample_rate_set(SR_FP_MHZ(10), true);

si5351c_configure_clock_control(&si5351c);
si5351c_set_clock_source(&si5351c, PLL_SOURCE_XTAL);
si5351c_change_input(&si5351c, SI5351C_INPUT_XTAL);
// soft reset
si5351c_reset_pll(&si5351c, SI5351C_PLL_BOTH);
si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_BOTH);
si5351c_enable_clock_outputs(&si5351c);
}

Expand Down Expand Up @@ -159,9 +159,10 @@ clock_source_t activate_best_clock_source(void)
/* No external or PortaPack clock was found. Use HackRF Si5351C crystal. */
}

si5351c_set_clock_source(
&si5351c,
(source == CLOCK_SOURCE_HACKRF) ? PLL_SOURCE_XTAL : PLL_SOURCE_CLKIN);
si5351c_input_t input = (source == CLOCK_SOURCE_HACKRF) ? SI5351C_INPUT_XTAL :
SI5351C_INPUT_CLKIN;
si5351c_change_input(&si5351c, input);

hackrf_ui()->set_clock_source(source);

return source;
Expand Down Expand Up @@ -411,7 +412,7 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
}

/* Reset PLL to synchronize output clock phase. */
si5351c_reset_pll(&si5351c, SI5351C_PLL_A);
si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_A);
}
#endif

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