Update C5 LP_I2C

esp32c5/src/lp_i2c0/clk_conf.rs

@@ -0,0 +1,105 @@
+#[doc = "Register `CLK_CONF` reader"]
+pub type R = crate::R<CLK_CONF_SPEC>;
+#[doc = "Register `CLK_CONF` writer"]
+pub type W = crate::W<CLK_CONF_SPEC>;
+#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_A_R = crate::FieldReader;
+#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_B_R = crate::FieldReader;
+#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"]
+pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
+pub type SCLK_SEL_R = crate::BitReader;
+#[doc = "Field `SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
+pub type SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SCLK_ACTIVE` reader - The clock switch for i2c module"]
+pub type SCLK_ACTIVE_R = crate::BitReader;
+#[doc = "Field `SCLK_ACTIVE` writer - The clock switch for i2c module"]
+pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
+        SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
+        SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8)
+    }
+    #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
+        SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8)
+    }
+    #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
+    #[inline(always)]
+    pub fn sclk_sel(&self) -> SCLK_SEL_R {
+        SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - The clock switch for i2c module"]
+    #[inline(always)]
+    pub fn sclk_active(&self) -> SCLK_ACTIVE_R {
+        SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLK_CONF")
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<'_, CLK_CONF_SPEC> {
+        SCLK_DIV_NUM_W::new(self, 0)
+    }
+    #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<'_, CLK_CONF_SPEC> {
+        SCLK_DIV_A_W::new(self, 8)
+    }
+    #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"]
+    #[inline(always)]
+    pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<'_, CLK_CONF_SPEC> {
+        SCLK_DIV_B_W::new(self, 14)
+    }
+    #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
+    #[inline(always)]
+    pub fn sclk_sel(&mut self) -> SCLK_SEL_W<'_, CLK_CONF_SPEC> {
+        SCLK_SEL_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - The clock switch for i2c module"]
+    #[inline(always)]
+    pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<'_, CLK_CONF_SPEC> {
+        SCLK_ACTIVE_W::new(self, 21)
+    }
+}
+#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLK_CONF_SPEC;
+impl crate::RegisterSpec for CLK_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
+impl crate::Readable for CLK_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
+impl crate::Writable for CLK_CONF_SPEC {
+    type Safety = crate::Unsafe;
+}
+#[doc = "`reset()` method sets CLK_CONF to value 0x0020_0000"]
+impl crate::Resettable for CLK_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0020_0000;
+}

esp32c5/src/lp_i2c0/comd.rs

@@ -0,0 +1,58 @@
+#[doc = "Register `COMD%s` reader"]
+pub type R = crate::R<COMD_SPEC>;
+#[doc = "Register `COMD%s` writer"]
+pub type W = crate::W<COMD_SPEC>;
+#[doc = "Field `COMMAND` reader - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."]
+pub type COMMAND_R = crate::FieldReader<u16>;
+#[doc = "Field `COMMAND` writer - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."]
+pub type COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
+#[doc = "Field `COMMAND_DONE` reader - When command 0 is done in I2C Master mode, this bit changes to highlevel."]
+pub type COMMAND_DONE_R = crate::BitReader;
+#[doc = "Field `COMMAND_DONE` writer - When command 0 is done in I2C Master mode, this bit changes to highlevel."]
+pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."]
+    #[inline(always)]
+    pub fn command(&self) -> COMMAND_R {
+        COMMAND_R::new((self.bits & 0x3fff) as u16)
+    }
+    #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."]
+    #[inline(always)]
+    pub fn command_done(&self) -> COMMAND_DONE_R {
+        COMMAND_DONE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMD")
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."]
+    #[inline(always)]
+    pub fn command(&mut self) -> COMMAND_W<'_, COMD_SPEC> {
+        COMMAND_W::new(self, 0)
+    }
+    #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."]
+    #[inline(always)]
+    pub fn command_done(&mut self) -> COMMAND_DONE_W<'_, COMD_SPEC> {
+        COMMAND_DONE_W::new(self, 31)
+    }
+}
+#[doc = "I2C command register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`comd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMD_SPEC;
+impl crate::RegisterSpec for COMD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comd::R`](R) reader structure"]
+impl crate::Readable for COMD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`comd::W`](W) writer structure"]
+impl crate::Writable for COMD_SPEC {
+    type Safety = crate::Unsafe;
+}
+#[doc = "`reset()` method sets COMD%s to value 0"]
+impl crate::Resettable for COMD_SPEC {}

esp32c5/src/lp_i2c0/ctr.rs

@@ -0,0 +1,171 @@
+#[doc = "Register `CTR` reader"]
+pub type R = crate::R<CTR_SPEC>;
+#[doc = "Register `CTR` writer"]
+pub type W = crate::W<CTR_SPEC>;
+#[doc = "Field `SDA_FORCE_OUT` reader - 1: direct output, 0: open drain output."]
+pub type SDA_FORCE_OUT_R = crate::BitReader;
+#[doc = "Field `SDA_FORCE_OUT` writer - 1: direct output, 0: open drain output."]
+pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SCL_FORCE_OUT` reader - 1: direct output, 0: open drain output."]
+pub type SCL_FORCE_OUT_R = crate::BitReader;
+#[doc = "Field `SCL_FORCE_OUT` writer - 1: direct output, 0: open drain output."]
+pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAMPLE_SCL_LEVEL` reader - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."]
+pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
+#[doc = "Field `SAMPLE_SCL_LEVEL` writer - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."]
+pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_FULL_ACK_LEVEL` reader - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
+pub type RX_FULL_ACK_LEVEL_R = crate::BitReader;
+#[doc = "Field `RX_FULL_ACK_LEVEL` writer - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
+pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRANS_START` writer - Set this bit to start sending the data in txfifo."]
+pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."]
+pub type TX_LSB_FIRST_R = crate::BitReader;
+#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."]
+pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."]
+pub type RX_LSB_FIRST_R = crate::BitReader;
+#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."]
+pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN` reader - Reserved"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - Reserved"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ARBITRATION_EN` reader - This is the enable bit for arbitration_lost."]
+pub type ARBITRATION_EN_R = crate::BitReader;
+#[doc = "Field `ARBITRATION_EN` writer - This is the enable bit for arbitration_lost."]
+pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FSM_RST` writer - This register is used to reset the scl FMS."]
+pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CONF_UPGATE` writer - synchronization bit"]
+pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
+    #[inline(always)]
+    pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
+        SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - 1: direct output, 0: open drain output."]
+    #[inline(always)]
+    pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
+        SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."]
+    #[inline(always)]
+    pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
+        SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
+    #[inline(always)]
+    pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R {
+        RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."]
+    #[inline(always)]
+    pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
+        TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."]
+    #[inline(always)]
+    pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
+        RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Reserved"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
+    #[inline(always)]
+    pub fn arbitration_en(&self) -> ARBITRATION_EN_R {
+        ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTR")
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
+    #[inline(always)]
+    pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<'_, CTR_SPEC> {
+        SDA_FORCE_OUT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - 1: direct output, 0: open drain output."]
+    #[inline(always)]
+    pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<'_, CTR_SPEC> {
+        SCL_FORCE_OUT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."]
+    #[inline(always)]
+    pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<'_, CTR_SPEC> {
+        SAMPLE_SCL_LEVEL_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
+    #[inline(always)]
+    pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<'_, CTR_SPEC> {
+        RX_FULL_ACK_LEVEL_W::new(self, 3)
+    }
+    #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."]
+    #[inline(always)]
+    pub fn trans_start(&mut self) -> TRANS_START_W<'_, CTR_SPEC> {
+        TRANS_START_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."]
+    #[inline(always)]
+    pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<'_, CTR_SPEC> {
+        TX_LSB_FIRST_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."]
+    #[inline(always)]
+    pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<'_, CTR_SPEC> {
+        RX_LSB_FIRST_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Reserved"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<'_, CTR_SPEC> {
+        CLK_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
+    #[inline(always)]
+    pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<'_, CTR_SPEC> {
+        ARBITRATION_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - This register is used to reset the scl FMS."]
+    #[inline(always)]
+    pub fn fsm_rst(&mut self) -> FSM_RST_W<'_, CTR_SPEC> {
+        FSM_RST_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - synchronization bit"]
+    #[inline(always)]
+    pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<'_, CTR_SPEC> {
+        CONF_UPGATE_W::new(self, 11)
+    }
+}
+#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTR_SPEC;
+impl crate::RegisterSpec for CTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
+impl crate::Readable for CTR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
+impl crate::Writable for CTR_SPEC {
+    type Safety = crate::Unsafe;
+}
+#[doc = "`reset()` method sets CTR to value 0x0208"]
+impl crate::Resettable for CTR_SPEC {
+    const RESET_VALUE: u32 = 0x0208;
+}