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Merged
i509VCB merged 2 commits into from
Aug 10, 2026
Merged

MSPM0: Update mspm0-metapac #6652

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0e3d76d
Update mspm0-metapac to mspm0-data-f78bc71
CordlessCoder Jul 29, 2026
e1dd87e
Merge pull request #4 from embassy-rs/main
CordlessCoder Aug 1, 2026
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4 changes: 2 additions & 2 deletions embassy-mspm0/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ critical-section = "1.2.0"
micromath = "2.0.0"

# mspm0-metapac = { version = "" }
mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-1da5eda11bf1ae69a604ba62df6242884df15d68" }
mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df" }
rand_core = "0.9"
# Force no cache padding or the types are too large.
maitake-sync = { version = "0.3.0", default-features = false, features = ["critical-section", "no-cache-pad"]}
Expand All @@ -88,7 +88,7 @@ quote = "1.0.40"
cfg_aliases = "0.2.1"

# mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-1da5eda11bf1ae69a604ba62df6242884df15d68", default-features = false, features = ["metadata"] }
mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df", default-features = false, features = ["metadata"] }

[features]
default = ["rt"]
Expand Down
4 changes: 2 additions & 2 deletions embassy-mspm0/build.rs
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Expand Up @@ -202,11 +202,11 @@ fn generate_groups() -> TokenStream {
let stat = group.iidx().read().stat();

// check for spurious interrupts
if stat == crate::pac::cpuss::vals::Iidx::NO_INTR {
if stat == crate::pac::cpuss::vals::Iidx::NoIntr {
return;
}

// MUST subtract by 1 because NO_INTR offsets IIDX values.
// MUST subtract by 1 because NoIntr offsets IIDX values.
let iidx = stat.to_bits() - 1;

let Ok(group) = #group_enum::try_from(iidx as u8) else {
Expand Down
50 changes: 25 additions & 25 deletions embassy-mspm0/src/adc.rs
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Expand Up @@ -211,7 +211,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
});

r.ctl1().modify(|w| {
w.set_sc(vals::Sc::START);
w.set_sc(vals::Sc::Start);
});

// Wait for conversion
Expand Down Expand Up @@ -297,7 +297,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> {
});

r.ctl1().modify(|w| {
w.set_sc(vals::Sc::START);
w.set_sc(vals::Sc::Start);
});

Self::wait_for_conversion().await;
Expand Down Expand Up @@ -344,7 +344,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> {
});

r.ctl1().modify(|w| {
w.set_sc(vals::Sc::START);
w.set_sc(vals::Sc::Start);
});

Self::wait_for_conversion().await;
Expand Down Expand Up @@ -432,41 +432,41 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
r.gprcm(0).rstctl().write(|w| {
w.set_resetstkyclr(true);
w.set_resetassert(true);
w.set_key(vals::ResetKey::KEY);
w.set_key(vals::ResetKey::Key);
});

r.gprcm(0).pwren().modify(|reg| {
reg.set_enable(true);
reg.set_key(vals::PwrenKey::KEY);
reg.set_key(vals::PwrenKey::Key);
});

// Wait for power up
cortex_m::asm::delay(16);

r.gprcm(0).clkcfg().write(|w| {
w.set_key(vals::ClkcfgKey::KEY);
w.set_sampclk(vals::Sampclk::SYSOSC);
w.set_key(vals::ClkcfgKey::Key);
w.set_sampclk(vals::Sampclk::Sysosc);
});

// FIXME: Consider clock config
// This code assumes the 24/32 MHz boot frequency
r.ctl0().write(|w| {
w.set_enc(false);
// TODO: power down config
w.set_pwrdn(vals::Pwrdn::MANUAL);
w.set_sclkdiv(vals::Sclkdiv::DIV_BY_4);
w.set_pwrdn(vals::Pwrdn::Manual);
w.set_sclkdiv(vals::Sclkdiv::DivBy4);
});

r.clkfreq().write(|w| {
w.set_frange(vals::Frange::RANGE24TO32);
w.set_frange(vals::Frange::Range24to32);
});

r.ctl1().write(|w| {
w.set_trigsrc(vals::Trigsrc::SOFTWARE);
w.set_sc(vals::Sc::STOP);
w.set_conseq(vals::Conseq::SEQUENCE);
w.set_sampmode(vals::Sampmode::AUTO);
w.set_avgn(vals::Avgn::DISABLE);
w.set_trigsrc(vals::Trigsrc::Software);
w.set_sc(vals::Sc::Stop);
w.set_conseq(vals::Conseq::Sequence);
w.set_sampmode(vals::Sampmode::Auto);
w.set_avgn(vals::Avgn::Disable);
w.set_avgd(0);
});

Expand All @@ -477,7 +477,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
w.set_rstsampcapen(false);
w.set_dmaen(false);
w.set_fifoen(false);
w.set_sampcnt(vals::Sampcnt::MIN);
w.set_sampcnt(vals::Sampcnt::Min);
w.set_startadd(0);
w.set_endadd(0);
});
Expand Down Expand Up @@ -510,7 +510,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
// TODO: More parameters
w.set_avgen(false);
w.set_bcsen(false);
w.set_trig(vals::Trig::AUTO_NEXT);
w.set_trig(vals::Trig::AutoNext);
w.set_wincomp(false);
});
}
Expand Down Expand Up @@ -576,26 +576,26 @@ trait SealedBorrowedChannel<'a, T> {

const fn to_res(resolution: Resolution) -> vals::Res {
match resolution {
Resolution::Bits12 => vals::Res::BIT_12,
Resolution::Bits10 => vals::Res::BIT_10,
Resolution::Bits8 => vals::Res::BIT_8,
Resolution::Bits12 => vals::Res::Bit12,
Resolution::Bits10 => vals::Res::Bit10,
Resolution::Bits8 => vals::Res::Bit8,
}
}

const fn from_res(res: vals::Res) -> Resolution {
match res {
vals::Res::BIT_12 => Resolution::Bits12,
vals::Res::BIT_10 => Resolution::Bits10,
vals::Res::BIT_8 => Resolution::Bits8,
vals::Res::Bit12 => Resolution::Bits12,
vals::Res::Bit10 => Resolution::Bits10,
vals::Res::Bit8 => Resolution::Bits8,
// SAFETY: The HAL will never program an invalid valid.
vals::Res::_RESERVED_3 => unsafe { unreachable_unchecked() },
}
}

const fn convert_stime(stime: SampleTimeComparator) -> vals::Stime {
match stime {
SampleTimeComparator::Scomp0 => vals::Stime::SEL_SCOMP0,
SampleTimeComparator::Scomp1 => vals::Stime::SEL_SCOMP1,
SampleTimeComparator::Scomp0 => vals::Stime::SelScomp0,
SampleTimeComparator::Scomp1 => vals::Stime::SelScomp1,
}
}

Expand Down
36 changes: 18 additions & 18 deletions embassy-mspm0/src/dma.rs
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Expand Up @@ -202,7 +202,7 @@ pub trait Word: SealedWord + 'static {

impl SealedWord for u8 {
fn width() -> vals::Wdth {
vals::Wdth::BYTE
vals::Wdth::Byte
}
}
impl Word for u8 {
Expand All @@ -213,7 +213,7 @@ impl Word for u8 {

impl SealedWord for u16 {
fn width() -> vals::Wdth {
vals::Wdth::HALF
vals::Wdth::Half
}
}
impl Word for u16 {
Expand All @@ -224,7 +224,7 @@ impl Word for u16 {

impl SealedWord for u32 {
fn width() -> vals::Wdth {
vals::Wdth::WORD
vals::Wdth::Word
}
}
impl Word for u32 {
Expand All @@ -235,7 +235,7 @@ impl Word for u32 {

impl SealedWord for u64 {
fn width() -> vals::Wdth {
vals::Wdth::LONG
vals::Wdth::Long
}
}
impl Word for u64 {
Expand Down Expand Up @@ -399,17 +399,17 @@ fn verify_transfer<W: Word>(ptr: *const [W]) -> Result<(), Error> {

fn convert_burst_size(value: BurstSize) -> vals::Burstsz {
match value {
BurstSize::Complete => vals::Burstsz::INFINITI,
BurstSize::_8 => vals::Burstsz::BURST_8,
BurstSize::_16 => vals::Burstsz::BURST_16,
BurstSize::_32 => vals::Burstsz::BURST_32,
BurstSize::Complete => vals::Burstsz::Infiniti,
BurstSize::_8 => vals::Burstsz::Burst8,
BurstSize::_16 => vals::Burstsz::Burst16,
BurstSize::_32 => vals::Burstsz::Burst32,
}
}

fn convert_mode(mode: TransferMode) -> vals::Tm {
match mode {
TransferMode::Single => vals::Tm::SINGLE,
TransferMode::Block => vals::Tm::BLOCK,
TransferMode::Single => vals::Tm::Single,
TransferMode::Block => vals::Tm::Block,
}
}

Expand Down Expand Up @@ -517,30 +517,30 @@ impl<'d> Channel<'d> {
w.set_req(false);

// Not every part supports auto enable, so force its value to 0.
w.set_autoen(Autoen::NONE);
w.set_preirq(Preirq::PREIRQ_DISABLE);
w.set_autoen(Autoen::None);
w.set_preirq(Preirq::PreirqDisable);
w.set_srcwdth(src_wdth);
w.set_dstwdth(dst_wdth);
w.set_srcincr(if increment_src {
Incr::INCREMENT
Incr::Increment
} else {
Incr::UNCHANGED
Incr::Unchanged
});
w.set_dstincr(if increment_dst {
Incr::INCREMENT
Incr::Increment
} else {
Incr::UNCHANGED
Incr::Unchanged
});

w.set_em(Em::NORMAL);
w.set_em(Em::Normal);
// Single and block will clear the enable bit when the transfers finish.
w.set_tm(convert_mode(options.mode));
});

self.tctl().write(|w| {
w.set_tsel(trigger_sel);
// Basic channels do not implement cross triggering.
w.set_tint(vals::Tint::EXTERNAL);
w.set_tint(vals::Tint::External);
});

self.sz().write(|w| {
Expand Down
12 changes: 6 additions & 6 deletions embassy-mspm0/src/gpio.rs
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Expand Up @@ -318,19 +318,19 @@ impl<'d> Flex<'d> {
// Per https://tweedegolf.nl/en/blog/235/debloat-your-async-rust
//
// We match the async pass-through suggestion to reduce async bloat.
self.wait_inner(Polarity::RISE)
self.wait_inner(Polarity::Rise)
}

/// Wait for the pin to undergo a transition from high to low.
#[inline]
pub fn wait_for_falling_edge(&mut self) -> impl Future<Output = ()> {
self.wait_inner(Polarity::FALL)
self.wait_inner(Polarity::Fall)
}

/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
#[inline]
pub fn wait_for_any_edge(&mut self) -> impl Future<Output = ()> {
self.wait_inner(Polarity::RISE_FALL)
self.wait_inner(Polarity::RiseFall)
}

async fn wait_inner(&mut self, polarity: Polarity) {
Expand Down Expand Up @@ -1029,17 +1029,17 @@ pub(crate) fn init(gpio: gpio::Gpio) {
gpio.gprcm().rstctl().write(|w| {
w.set_resetstkyclr(true);
w.set_resetassert(true);
w.set_key(ResetKey::KEY);
w.set_key(ResetKey::Key);
});

gpio.gprcm().pwren().write(|w| {
w.set_enable(true);
w.set_key(PwrenKey::KEY);
w.set_key(PwrenKey::Key);
});

gpio.evt_mode().modify(|w| {
// The CPU will clear it's own interrupts
w.set_cpu_cfg(EvtCfg::SOFTWARE);
w.set_cpu_cfg(EvtCfg::Software);
});
}

Expand Down
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