Add memory 2 stage

src/main/scala/vexriscv/VexRiscv.scala

@@ -6,19 +6,21 @@ import spinal.core._
 import scala.collection.mutable.ArrayBuffer
 
 object VexRiscvConfig{
-  def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = {
+  def apply(withMemoryStage : Boolean, withMemory2Stage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = {
     val config = VexRiscvConfig()
     config.plugins ++= plugins
     config.withMemoryStage = withMemoryStage
+    config.withMemory2Stage = withMemory2Stage
     config.withWriteBackStage = withWriteBackStage
     config
   }
 
-  def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = apply(true,true,plugins)
+  def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = apply(true,true,true,plugins)
 }
 
 case class VexRiscvConfig(){
   var withMemoryStage = true
+  var withMemory2Stage = false
   var withWriteBackStage = true
   val plugins = ArrayBuffer[Plugin[VexRiscv]]()
 
@@ -28,6 +30,7 @@ case class VexRiscvConfig(){
   object IS_RVC extends Stageable(Bool)
   object BYPASSABLE_EXECUTE_STAGE   extends Stageable(Bool)
   object BYPASSABLE_MEMORY_STAGE   extends Stageable(Bool)
+  object BYPASSABLE_MEMORY2_STAGE   extends Stageable(Bool)
   object RS1   extends Stageable(Bits(32 bits))
   object RS2   extends Stageable(Bits(32 bits))
   object RS1_USE extends Stageable(Bool)
@@ -92,6 +95,7 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
   val decode    = newStage()
   val execute   = newStage()
   val memory    = ifGen(config.withMemoryStage)    (newStage())
+  val memory2   = ifGen(config.withMemory2Stage)   (newStage())
   val writeBack = ifGen(config.withWriteBackStage) (newStage())
 
   def stagesFromExecute = stages.dropWhile(_ != execute)
@@ -109,6 +113,9 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
   if(withMemoryStage){
     memory.arbitration.removeIt.noBackendCombMerge
   }
+  if(withMemory2Stage){
+    memory2.arbitration.removeIt.noBackendCombMerge
+  }
   execute.arbitration.flushAll.noBackendCombMerge
 
   this(RVC_GEN) = false

src/main/scala/vexriscv/demo/GenMicroNoCsr.scala

@@ -11,6 +11,7 @@ object GenMicroNoCsr extends App{
   def cpu() = new VexRiscv(
     config = VexRiscvConfig(
       withMemoryStage = false,
+      withMemory2Stage = false,
       withWriteBackStage = false,
       plugins = List(
         new IBusSimplePlugin(

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -384,7 +384,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
       IS_CSR                   -> True,
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
-      BYPASSABLE_MEMORY_STAGE  -> True
+      BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True
     ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil)
 
     val nonImmediatActions = defaultCsrActions ++ List(

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -71,6 +71,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
       REGFILE_WRITE_VALID -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE -> False,
+      BYPASSABLE_MEMORY2_STAGE -> False,
       MEMORY_WR -> False
     ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
 
@@ -104,6 +105,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
           REGFILE_WRITE_VALID -> True,
           BYPASSABLE_EXECUTE_STAGE -> False,
           BYPASSABLE_MEMORY_STAGE -> False,
+          BYPASSABLE_MEMORY2_STAGE -> False,
           MEMORY_LRSC -> True
         )
       )

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -259,6 +259,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
       REGFILE_WRITE_VALID -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE  -> Bool(earlyInjection),
+      BYPASSABLE_MEMORY2_STAGE -> Bool(earlyInjection),
       MEMORY_STORE -> False
     ) ++ (if(catchAccessFault || catchAddressMisaligned) List(HAS_SIDE_EFFECT -> True) else Nil)
 

src/main/scala/vexriscv/plugin/DivPlugin.scala

@@ -21,6 +21,7 @@ class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mul
 //       REGFILE_WRITE_VALID      -> True,
 //       BYPASSABLE_EXECUTE_STAGE -> False,
 //       BYPASSABLE_MEMORY_STAGE  -> True,
+//       BYPASSABLE_MEMORY2_STAGE -> True,
 //       RS1_USE                 -> True,
 //       RS2_USE                 -> True,
 //       IS_DIV                   -> True

src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala

@@ -10,6 +10,7 @@ trait HazardService{
 
 class HazardSimplePlugin(bypassExecute : Boolean = false,
                          bypassMemory: Boolean = false,
+                         bypassMemory2: Boolean = false,
                          bypassWriteBack: Boolean = false,
                          bypassWriteBackBuffer : Boolean = false,
                          pessimisticUseSrc : Boolean = false,
@@ -95,6 +96,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
     }
 
     if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null)
+    if(withMemory2Stage)   trackHazardWithStage(memory2  ,bypassMemory2  ,BYPASSABLE_MEMORY2_STAGE)
     if(withMemoryStage)    trackHazardWithStage(memory   ,bypassMemory   ,BYPASSABLE_MEMORY_STAGE)
     if(readStage != execute) trackHazardWithStage(execute  ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE)
 
@@ -119,4 +121,4 @@ class NoHazardPlugin extends Plugin[VexRiscv] with HazardService {
   override def build(pipeline: VexRiscv): Unit = {}
 
   def hazardOnExecuteRS = False
-}
+}

src/main/scala/vexriscv/plugin/IntAluPlugin.scala

@@ -28,6 +28,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> True,
       BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True,
       RS1_USE -> True
     )
 
@@ -37,14 +38,16 @@ class IntAluPlugin extends Plugin[VexRiscv]{
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> True,
       BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True,
       RS1_USE -> True,
       RS2_USE -> True
     )
 
     val otherAction = List[(Stageable[_ <: BaseType],Any)](
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> True,
-      BYPASSABLE_MEMORY_STAGE  -> True
+      BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True
     )
 
 

src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala

@@ -33,6 +33,7 @@ class MulDivIterativePlugin(genMul : Boolean = true,
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True,
       RS1_USE                 -> True,
       RS2_USE                 -> True
     )

src/main/scala/vexriscv/plugin/MulPlugin.scala

@@ -24,6 +24,7 @@ class MulPlugin extends Plugin[VexRiscv]{
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE  -> False,
+      BYPASSABLE_MEMORY2_STAGE -> False,
       RS1_USE                 -> True,
       RS2_USE                 -> True,
       IS_MUL                   -> True

src/main/scala/vexriscv/plugin/ShiftPlugins.scala

@@ -26,6 +26,7 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
       BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True,
       RS1_USE                  -> True
     )
 
@@ -35,6 +36,7 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection),
       BYPASSABLE_MEMORY_STAGE  -> True,
+      BYPASSABLE_MEMORY2_STAGE -> True,
       RS1_USE                  -> True,
       RS2_USE                  -> True
     )

src/test/scala/vexriscv/TestIndividualFeatures.scala

@@ -579,6 +579,7 @@ class TestIndividualFeatures extends FunSuite {
       SpinalVerilog{
         val config = VexRiscvConfig(
           withMemoryStage = !noMemory,
+          withMemory2Stage = false,
           withWriteBackStage = !noWriteback,
           plugins = List(
             new IntAluPlugin,
@@ -682,4 +683,4 @@ FAIL AltQTest_rv32i_O3
 
   val seed = 4331444545509090137l
 1 => flops i O0
- */
+ */