Add support for CVA6 + HPDC

.gitmodules

@@ -1,6 +1,6 @@
 [submodule "piton/design/chip/tile/ariane"]
 	path = piton/design/chip/tile/ariane
-	url = https://github.com/pulp-platform/ariane.git
+	url = https://github.com/openhwgroup/cva6.git
 [submodule "aws"]
 	path = piton/design/aws
 	url = https://github.com/PrincetonUniversity/openpiton-aws.git

piton/ariane_build_tools.sh

@@ -70,7 +70,7 @@ else
   ci/install-verilator.sh
 
   # build the RISCV tests if necessary
-  VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f"
+  VERSION="master"
   cd tmp
 
   [ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
@@ -83,8 +83,8 @@ else
   # link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB
   cd benchmarks/common/
   rm syscalls.c util.h
-  ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c
-  ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h
+  ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/syscalls.c
+  ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/util.h
   cd -
 
   cd build

piton/ariane_setup.sh

@@ -70,7 +70,6 @@ fi
 
 # set root directory
 export PITON_ROOT=`pwd`
-export ARIANE_ROOT=${PITON_ROOT}/piton/design/chip/tile/ariane/
 
 ## GCC and RISCV GCC setup
 export CXX=g++ CC=gcc
@@ -80,7 +79,7 @@ if [ "$RISCV" ==  "" ]
 then
   export RISCV=$HOME/scratch/riscv_install
 fi
-export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-4.014/
+export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-5.008/
 
 # setup paths
 export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
@@ -93,6 +92,9 @@ export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
 # note: customize this script to reflect your tool setup
 source ./piton/piton_settings.bash
 
+# HPDCACHE dir depends on ariane
+export HPDCACHE_DIR=$ARIANE_ROOT/core/cache_subsystem/hpdcache
+
 if [[ $(readlink -e "${RISCV}/bin/spike") == "" ]]
 then
     echo

piton/design/chip/tile/l15/rtl/Flist.l15

@@ -48,3 +48,5 @@ l15_priority_encoder.v
 sram_wrappers/sram_l15_tag.v
 sram_wrappers/sram_l15_data.v
 sram_wrappers/sram_l15_hmt.v
+
+l15_pkg.sv

piton/design/chip/tile/l15/rtl/l15.v

@@ -66,6 +66,9 @@ module l15 (
     input [63:0]                            transducer_l15_data,
     input [63:0]                            transducer_l15_data_next_entry,
     input [`TLB_CSM_WIDTH-1:0]              transducer_l15_csm_data,
+    `ifdef WRITE_BYTE_MASK
+    input [`L15_BYTE_MASK_WIDTH-1:0]        transducer_l15_be,  
+    `endif
 
     output                                  l15_transducer_ack,
     output                                  l15_transducer_header_ack,
@@ -85,7 +88,7 @@ module l15 (
     output [63:0]                           l15_transducer_data_3,
     output                                  l15_transducer_inval_icache_all_way,
     output                                  l15_transducer_inval_dcache_all_way,
-    output [15:4]                           l15_transducer_inval_address_15_4,
+    output [`L15_PADDR_MASK]                l15_transducer_inval_address,
     output                                  l15_transducer_cross_invalidate,
     output [1:0]                            l15_transducer_cross_invalidate_way,
     output                                  l15_transducer_inval_dcache_inval,
@@ -486,6 +489,7 @@ wire [`L15_MSHR_ID_WIDTH-1:0] pipe_mshr_readreq_mshrid_s1;
 wire [`L15_CONTROL_WIDTH-1:0] mshr_pipe_readres_control_s1;
 wire [`PACKET_HOME_ID_WIDTH-1:0] mshr_pipe_readres_homeid_s1;
 wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1;
+wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address;
 wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address;
 wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address;
 wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1;
@@ -522,6 +526,7 @@ l15_mshr mshr(
     .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
     .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
     .mshr_pipe_vals_s1(mshr_pipe_vals_s1),
+    .mshr_pipe_ifill_address(mshr_pipe_ifill_address),
     .mshr_pipe_ld_address(mshr_pipe_ld_address),
     .mshr_pipe_st_address(mshr_pipe_st_address),
     .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),
@@ -608,7 +613,7 @@ rf_l15_lrsc_flag lrsc_flag(
 //    );
 
 
-
+`ifndef PITON_ARIANE_HPDC // L1D is NOT HPDC
 // way map table
 wire l15_wmt_read_val_s2;
 wire [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2;
@@ -628,7 +633,7 @@ rf_l15_wmt wmc(
     .write_data(l15_wmt_write_data_s3),
     .read_data(wmt_l15_data_s3)
 );
-
+`endif
 // lru array, psuedo
 wire l15_lruarray_read_val_s1;
 wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1;
@@ -658,7 +663,6 @@ l15_pipeline pipeline(
     .mesi_l15_dout_s2(mesi_l15_dout_s2),
     .lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2),
     .lruarray_l15_dout_s2(lruarray_l15_dout_s2),
-    .wmt_l15_data_s3(wmt_l15_data_s3),
     .pcxdecoder_l15_rqtype               (transducer_l15_rqtype),
     .pcxdecoder_l15_amo_op               (transducer_l15_amo_op),
     .pcxdecoder_l15_nc                   (transducer_l15_nc),
@@ -675,6 +679,9 @@ l15_pipeline pipeline(
     .pcxdecoder_l15_data                 (transducer_l15_data),
     .pcxdecoder_l15_data_next_entry      (transducer_l15_data_next_entry),
     .pcxdecoder_l15_csm_data             (transducer_l15_csm_data),
+    `ifdef WRITE_BYTE_MASK
+    .pcxdecoder_l15_be                   (transducer_l15_be),
+    `endif
     .noc2decoder_l15_val(noc2decoder_l15_val),
     .noc2decoder_l15_mshrid(noc2decoder_l15_mshrid),
     .noc2decoder_l15_l2miss(noc2decoder_l15_l2miss),
@@ -724,12 +731,15 @@ l15_pipeline pipeline(
     .l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2),
     .l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2),
     .l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2),
+    `ifndef PITON_ARIANE_HPDC
     .l15_wmt_read_val_s2(l15_wmt_read_val_s2),
     .l15_wmt_read_index_s2(l15_wmt_read_index_s2),
+    .wmt_l15_data_s3(wmt_l15_data_s3),
     .l15_wmt_write_val_s3(l15_wmt_write_val_s3),
     .l15_wmt_write_index_s3(l15_wmt_write_index_s3),
     .l15_wmt_write_mask_s3(l15_wmt_write_mask_s3),
     .l15_wmt_write_data_s3(l15_wmt_write_data_s3),
+    `endif
     .l15_lruarray_read_val_s1(l15_lruarray_read_val_s1),
     .l15_lruarray_read_index_s1(l15_lruarray_read_index_s1),
     .l15_lruarray_write_val_s3(l15_lruarray_write_val_s3),
@@ -751,7 +761,7 @@ l15_pipeline pipeline(
     .l15_cpxencoder_data_3               (l15_transducer_data_3),
     .l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way),
     .l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way),
-    .l15_cpxencoder_inval_address_15_4   (l15_transducer_inval_address_15_4),
+    .l15_cpxencoder_inval_address        (l15_transducer_inval_address),
     .l15_cpxencoder_cross_invalidate     (l15_transducer_cross_invalidate),
     .l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way),
     .l15_cpxencoder_inval_dcache_inval   (l15_transducer_inval_dcache_inval),
@@ -834,6 +844,7 @@ l15_pipeline pipeline(
     .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
     .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
     .mshr_pipe_vals_s1(mshr_pipe_vals_s1),
+    .mshr_pipe_ifill_address(mshr_pipe_ifill_address),
     .mshr_pipe_ld_address(mshr_pipe_ld_address),
     .mshr_pipe_st_address(mshr_pipe_st_address),
     .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),

piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv

@@ -66,6 +66,7 @@ module l15_mshr(
 
     // s1/2/3 (address conflict checking)
     output reg [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1,
+    output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address,
     output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address,
     output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address,
     output reg [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1,
@@ -118,7 +119,7 @@ reg [`L15_CONTROL_WIDTH-1:0] ld_control [0:`L15_NUM_THREADS-1];
 reg [`L15_NUM_THREADS-1:0] ld_val;
 reg [`PACKET_HOME_ID_WIDTH-1:0] ld_homeid [0:`L15_NUM_THREADS-1];
 
-// reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
+reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
 reg [`L15_CONTROL_WIDTH-1:0] ifill_control [0:`L15_NUM_THREADS-1];
 reg [`L15_NUM_THREADS-1:0] ifill_val;
 // reg [`PACKET_HOME_ID_WIDTH-1:0] ifill_homeid [0:`L15_NUM_THREADS-1];
@@ -156,6 +157,7 @@ end
 reg [`L15_NUM_MSHRID_PER_THREAD-1:0] tmp_vals [`L15_NUM_THREADS-1:0];
 reg [`L15_PADDR_HI:0] tmp_st_address [`L15_NUM_THREADS-1:0];
 reg [`L15_PADDR_HI:0] tmp_ld_address [`L15_NUM_THREADS-1:0];
+reg [`L15_PADDR_HI:0] tmp_ifill_address [`L15_NUM_THREADS-1:0];
 reg [2-1:0] tmp_st_way [`L15_NUM_THREADS-1:0];
 reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] tmp_st_state [`L15_NUM_THREADS-1:0];
 always @ *
@@ -169,6 +171,7 @@ begin
 
         tmp_st_address[THREADID] = st_address[THREADID];
         tmp_ld_address[THREADID] = ld_address[THREADID];
+        tmp_ifill_address[THREADID] = ifill_address[THREADID];
         tmp_st_way[THREADID] = st_way[THREADID];
         tmp_st_state[THREADID] =st_state[THREADID];
         '''
@@ -178,6 +181,7 @@ begin
             print(tt)
     %>
     mshr_pipe_vals_s1 = {tmp_vals[1], tmp_vals[0]};
+    mshr_pipe_ifill_address = {tmp_ifill_address[1], tmp_ifill_address[0]};
     mshr_pipe_ld_address = {tmp_ld_address[1], tmp_ld_address[0]};
     mshr_pipe_st_address = {tmp_st_address[1], tmp_st_address[0]};
     mshr_pipe_st_way_s1 = {tmp_st_way[1], tmp_st_way[0]};
@@ -238,7 +242,7 @@ begin
         case (mshrid_s1)
             `L15_MSHR_ID_IFILL:
             begin
-                // ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
+                ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
                 ifill_control[threadid_s1] <= pipe_mshr_writereq_control_s1;
             end
             `L15_MSHR_ID_LD: