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Add support for CVA6 + HPDC #172

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4b43c60
Added ariane+HPDC repository
AileonN Jun 19, 2023
1887cc5
Support for building the HPDC files
AileonN Jun 19, 2023
9aaaecf
Update ariane submodule commit
AileonN Jul 20, 2023
0c9b4eb
Update ariane submodule commit
AileonN Jul 21, 2023
949cdbb
Invalidation first draft
AileonN Jul 31, 2023
e1b7ac0
Fix: Store requests must send the data replicated
AileonN Aug 1, 2023
34b3d21
Fix: Invalidations asserts
AileonN Aug 7, 2023
a759701
Fix: Uncached L1.5 responses
AileonN Aug 7, 2023
8df64ba
Added support for AMOs
AileonN Aug 10, 2023
b0c6f16
Bug fix: Inval address when L1.5 evicts and Back-off for lrsc added
AileonN Aug 22, 2023
114d9d7
Bug fix: Onehot access to cache directory (invals and amo)
AileonN Aug 23, 2023
e4e33b0
Bug fixed: WBUF coalescing
AileonN Aug 30, 2023
0f0f627
Write coalescing enabled (WRITE_BYTE_MASK)
AileonN Sep 7, 2023
95020e3
Bug fix: PITON_NO_CHIP_BRIDGE
AileonN Sep 12, 2023
be4cb32
ft added: Free thid list
AileonN Sep 14, 2023
58c5288
Enabled the possibility to use or not WRITE_BYTE_MASK
AileonN Sep 19, 2023
1c83647
Added some comments & parametric thid free list
AileonN Sep 21, 2023
cfdb343
ft added: Parametric size of I$ non cachable requests
AileonN Oct 27, 2023
1d96ead
INVAL fifo entries increased to a high value.
AileonN Oct 27, 2023
2b9ed8d
Changing inval address signal + Added PITON_ARIANE_HPDC macro
AileonN Oct 28, 2023
c162264
Solved compile errors due to monitor and flist
AileonN Oct 28, 2023
1785a7b
Add -hpdc option for Ariane builds
ArnauBigas Dec 1, 2023
d22ee40
Fix makefiles -march variables depending on RVV compiler version
ArnauBigas Sep 13, 2024
44c4202
Enable usage of verilator 5
ArnauBigas Nov 30, 2023
28f2884
Force linux risc-v bootrom makefile to make dtb before compiling anyt…
ArnauBigas Oct 22, 2025
bee1ceb
Update riscv-tests, rv64 util.h & fix symlink paths in ariane_build_t…
ArnauBigas Oct 22, 2025
8ff301f
Fix sims not substituting env variables in curly brackets
ArnauBigas Oct 28, 2025
d471578
Add verilator VCD & FST tracing options to sims
ArnauBigas Sep 6, 2024
fdd5d9e
Fix hpdc paths in setup and flist order
ArnauBigas Oct 30, 2025
5d1e22d
Update HPDC with refill & invalidation FIFO
AileonN Mar 14, 2024
8e9652d
Add l15 SystemVerilog pkg to expose types & interfaces to the cores
ArnauBigas Nov 4, 2025
2bef931
Update with working & upstream-ish ariane+hpdc
ArnauBigas Nov 4, 2025
a097e60
Update ariane with multidriven signal fix
ArnauBigas Nov 6, 2025
b16f8ad
Update Ariane to latest upstream
ArnauBigas May 7, 2026
f6e5b9c
Fix typo WIDHT -> WIDTH
ArnauBigas May 7, 2026
3d7c498
Fix gitmodules
ArnauBigas May 7, 2026
d76dfa6
Revert ARIANE_ROOT location and update verilator version
ArnauBigas May 7, 2026
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6 changes: 3 additions & 3 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,6 +1,3 @@
[submodule "piton/design/chip/tile/ariane"]
path = piton/design/chip/tile/ariane
url = https://github.com/pulp-platform/ariane.git
[submodule "aws"]
path = piton/design/aws
url = https://github.com/PrincetonUniversity/openpiton-aws.git
Expand All @@ -13,3 +10,6 @@
[submodule "piton/design/chip/tile/sparc"]
path = piton/design/chip/tile/sparc
url = git@github.com:openpiton/ost1-core.git
[submodule "piton/design/chip/tile/ariane"]

@Jbalkind Jbalkind May 7, 2026

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This isn't a valid change to .gitmodules

@ArnauBigas ArnauBigas May 7, 2026

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Will fix.

@Jbalkind Jbalkind May 7, 2026

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Actually can we just remove this? The repo should be redirecting already and I'd rather not force every user to git submodule sync

path = piton/design/chip/tile/ariane
url = https://github.com/AileonN/cva6_openpiton_noliete.git
6 changes: 3 additions & 3 deletions piton/ariane_build_tools.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ else
ci/install-verilator.sh

# build the RISCV tests if necessary
VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f"
VERSION="master"
Comment thread
Jbalkind marked this conversation as resolved.
cd tmp

[ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
Expand All @@ -83,8 +83,8 @@ else
# link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB
cd benchmarks/common/
rm syscalls.c util.h
ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c
ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h
ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/syscalls.c
ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/util.h
cd -

cd build
Expand Down
2 changes: 1 addition & 1 deletion piton/design/chip/tile/ariane
Open in desktop
Submodule ariane updated 16 files
+3 −0 .gitmodules
+3 −0 Flist.ariane
+3 −1 Makefile
+6 −1 core/cache_subsystem/wt_dcache_ctrl.sv
+3 −3 core/cache_subsystem/wt_l15_adapter.sv
+71 −3 core/cva6.sv
+14 −1 core/include/ariane_pkg.sv
+1 −0 core/include/cv32a60x_config_pkg.sv
+1 −0 core/include/cv32a6_imac_sv0_config_pkg.sv
+1 −0 core/include/cv32a6_imac_sv32_config_pkg.sv
+1 −0 core/include/cv32a6_imafc_sv32_config_pkg.sv
+1 −0 core/include/cv64a6_imafdc_sv39_config_pkg.sv
+3 −0 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+4 −1 core/include/wt_cache_pkg.sv
+130 −80 core/load_unit.sv
+1 −0 cv-hpdcache
21 changes: 16 additions & 5 deletions piton/design/chip/tile/l15/rtl/l15.v
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,9 @@ module l15 (
input [63:0] transducer_l15_data,
input [63:0] transducer_l15_data_next_entry,
input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data,
`ifdef WRITE_BYTE_MASK
input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be,
`endif

output l15_transducer_ack,
output l15_transducer_header_ack,
Expand All @@ -85,7 +88,7 @@ module l15 (
output [63:0] l15_transducer_data_3,
output l15_transducer_inval_icache_all_way,
output l15_transducer_inval_dcache_all_way,
output [15:4] l15_transducer_inval_address_15_4,
output [`L15_PADDR_MASK] l15_transducer_inval_address,
output l15_transducer_cross_invalidate,
output [1:0] l15_transducer_cross_invalidate_way,
output l15_transducer_inval_dcache_inval,
Expand Down Expand Up @@ -486,6 +489,7 @@ wire [`L15_MSHR_ID_WIDTH-1:0] pipe_mshr_readreq_mshrid_s1;
wire [`L15_CONTROL_WIDTH-1:0] mshr_pipe_readres_control_s1;
wire [`PACKET_HOME_ID_WIDTH-1:0] mshr_pipe_readres_homeid_s1;
wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address;
wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1;
Expand Down Expand Up @@ -522,6 +526,7 @@ l15_mshr mshr(
.mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
.mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
.mshr_pipe_vals_s1(mshr_pipe_vals_s1),
.mshr_pipe_ifill_address(mshr_pipe_ifill_address),
.mshr_pipe_ld_address(mshr_pipe_ld_address),
.mshr_pipe_st_address(mshr_pipe_st_address),
.mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),
Expand Down Expand Up @@ -608,7 +613,7 @@ rf_l15_lrsc_flag lrsc_flag(
// );



`ifndef PITON_ARIANE_HPDC // L1D is NOT HPDC
// way map table
wire l15_wmt_read_val_s2;
wire [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2;
Expand All @@ -628,7 +633,7 @@ rf_l15_wmt wmc(
.write_data(l15_wmt_write_data_s3),
.read_data(wmt_l15_data_s3)
);

`endif
// lru array, psuedo
wire l15_lruarray_read_val_s1;
wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1;
Expand Down Expand Up @@ -658,7 +663,6 @@ l15_pipeline pipeline(
.mesi_l15_dout_s2(mesi_l15_dout_s2),
.lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2),
.lruarray_l15_dout_s2(lruarray_l15_dout_s2),
.wmt_l15_data_s3(wmt_l15_data_s3),
.pcxdecoder_l15_rqtype (transducer_l15_rqtype),
.pcxdecoder_l15_amo_op (transducer_l15_amo_op),
.pcxdecoder_l15_nc (transducer_l15_nc),
Expand All @@ -675,6 +679,9 @@ l15_pipeline pipeline(
.pcxdecoder_l15_data (transducer_l15_data),
.pcxdecoder_l15_data_next_entry (transducer_l15_data_next_entry),
.pcxdecoder_l15_csm_data (transducer_l15_csm_data),
`ifdef WRITE_BYTE_MASK
.pcxdecoder_l15_be (transducer_l15_be),
`endif
.noc2decoder_l15_val(noc2decoder_l15_val),
.noc2decoder_l15_mshrid(noc2decoder_l15_mshrid),
.noc2decoder_l15_l2miss(noc2decoder_l15_l2miss),
Expand Down Expand Up @@ -724,12 +731,15 @@ l15_pipeline pipeline(
.l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2),
.l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2),
.l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2),
`ifndef PITON_ARIANE_HPDC
.l15_wmt_read_val_s2(l15_wmt_read_val_s2),
.l15_wmt_read_index_s2(l15_wmt_read_index_s2),
.wmt_l15_data_s3(wmt_l15_data_s3),
.l15_wmt_write_val_s3(l15_wmt_write_val_s3),
.l15_wmt_write_index_s3(l15_wmt_write_index_s3),
.l15_wmt_write_mask_s3(l15_wmt_write_mask_s3),
.l15_wmt_write_data_s3(l15_wmt_write_data_s3),
`endif
.l15_lruarray_read_val_s1(l15_lruarray_read_val_s1),
.l15_lruarray_read_index_s1(l15_lruarray_read_index_s1),
.l15_lruarray_write_val_s3(l15_lruarray_write_val_s3),
Expand All @@ -751,7 +761,7 @@ l15_pipeline pipeline(
.l15_cpxencoder_data_3 (l15_transducer_data_3),
.l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way),
.l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way),
.l15_cpxencoder_inval_address_15_4 (l15_transducer_inval_address_15_4),
.l15_cpxencoder_inval_address (l15_transducer_inval_address),
.l15_cpxencoder_cross_invalidate (l15_transducer_cross_invalidate),
.l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way),
.l15_cpxencoder_inval_dcache_inval (l15_transducer_inval_dcache_inval),
Expand Down Expand Up @@ -834,6 +844,7 @@ l15_pipeline pipeline(
.mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
.mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
.mshr_pipe_vals_s1(mshr_pipe_vals_s1),
.mshr_pipe_ifill_address(mshr_pipe_ifill_address),
.mshr_pipe_ld_address(mshr_pipe_ld_address),
.mshr_pipe_st_address(mshr_pipe_st_address),
.mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),
Expand Down
8 changes: 6 additions & 2 deletions piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv
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Expand Up @@ -66,6 +66,7 @@ module l15_mshr(

// s1/2/3 (address conflict checking)
output reg [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address,
output reg [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1,
Expand Down Expand Up @@ -118,7 +119,7 @@ reg [`L15_CONTROL_WIDTH-1:0] ld_control [0:`L15_NUM_THREADS-1];
reg [`L15_NUM_THREADS-1:0] ld_val;
reg [`PACKET_HOME_ID_WIDTH-1:0] ld_homeid [0:`L15_NUM_THREADS-1];

// reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
reg [`L15_CONTROL_WIDTH-1:0] ifill_control [0:`L15_NUM_THREADS-1];
reg [`L15_NUM_THREADS-1:0] ifill_val;
// reg [`PACKET_HOME_ID_WIDTH-1:0] ifill_homeid [0:`L15_NUM_THREADS-1];
Expand Down Expand Up @@ -156,6 +157,7 @@ end
reg [`L15_NUM_MSHRID_PER_THREAD-1:0] tmp_vals [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_st_address [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_ld_address [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_ifill_address [`L15_NUM_THREADS-1:0];
reg [2-1:0] tmp_st_way [`L15_NUM_THREADS-1:0];
reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] tmp_st_state [`L15_NUM_THREADS-1:0];
always @ *
Expand All @@ -169,6 +171,7 @@ begin

tmp_st_address[THREADID] = st_address[THREADID];
tmp_ld_address[THREADID] = ld_address[THREADID];
tmp_ifill_address[THREADID] = ifill_address[THREADID];
tmp_st_way[THREADID] = st_way[THREADID];
tmp_st_state[THREADID] =st_state[THREADID];
'''
Expand All @@ -178,6 +181,7 @@ begin
print(tt)
%>
mshr_pipe_vals_s1 = {tmp_vals[1], tmp_vals[0]};
mshr_pipe_ifill_address = {tmp_ifill_address[1], tmp_ifill_address[0]};
mshr_pipe_ld_address = {tmp_ld_address[1], tmp_ld_address[0]};
mshr_pipe_st_address = {tmp_st_address[1], tmp_st_address[0]};
mshr_pipe_st_way_s1 = {tmp_st_way[1], tmp_st_way[0]};
Expand Down Expand Up @@ -238,7 +242,7 @@ begin
case (mshrid_s1)
`L15_MSHR_ID_IFILL:
begin
// ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
ifill_control[threadid_s1] <= pipe_mshr_writereq_control_s1;
end
`L15_MSHR_ID_LD:
Expand Down
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