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Add LG19A4_BOARD prototype to openpiton #164

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105c215
add xcvu19p
LOCKEDGATE Apr 10, 2025
a99afa8
add LG19A4_BOARD(vu19p)
LOCKEDGATE Apr 11, 2025
6e7ff27
add LG19A4_BOARD(vu19p)
LOCKEDGATE Apr 11, 2025
980a3b6
add LG19A4_BOARD(vu19p)
LOCKEDGATE Apr 11, 2025
60588f7
add LG19A4_BOARD(vu19p)
LOCKEDGATE Apr 11, 2025
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3 changes: 3 additions & 0 deletions env.sh
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@@ -0,0 +1,3 @@
export PITON_ROOT=$PWD
source piton/piton_settings.bash
source piton/ariane_setup.sh
3 changes: 2 additions & 1 deletion piton/design/chipset/include/chipset_define.vh
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Expand Up @@ -89,7 +89,8 @@
`define ADDR_TRANS_SECTION_MULT 1
`endif

`define ASM_TIMEOUT_CYCLES 64'd5000000000
//`define ASM_TIMEOUT_CYCLES 64'd5000000000
`define ASM_TIMEOUT_CYCLES 64'd50000000000000

`define CFG_DONE_STRING 0
`define PASSED_STRING 1
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19 changes: 19 additions & 0 deletions piton/design/chipset/include/mc_define.h
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Expand Up @@ -86,6 +86,25 @@
`define DDR3_CS_WIDTH 1
`define DDR3_BG_WIDTH 1
`define DDR3_ODT_WIDTH 1
`elsif LG19A4_BOARD
`define BOARD_MEM_SIZE_MB 2048
`define WORDS_PER_BURST 8
`define WORD_SIZE 8 // in bytes
`define MIG_APP_ADDR_WIDTH 28
`define MIG_APP_CMD_WIDTH 3
`define MIG_APP_DATA_WIDTH 512
`define MIG_APP_MASK_WIDTH 64

`define DDR3_DQ_WIDTH 64
`define DDR3_DQS_WIDTH 8
`define DDR3_ADDR_WIDTH 17
`define DDR3_BA_WIDTH 2
`define DDR3_DM_WIDTH 8
`define DDR3_CK_WIDTH 1
`define DDR3_CKE_WIDTH 1
`define DDR3_CS_WIDTH 1
`define DDR3_BG_WIDTH 2
`define DDR3_ODT_WIDTH 1
`elsif XUPP3R_BOARD
`define BOARD_MEM_SIZE_MB 32768
`define WORDS_PER_BURST 8
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396 changes: 396 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/LG19A4/ip_cores/atg_uart_init/atg_uart_init.xci
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19 changes: 19 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/LG19A4/ip_cores/atg_uart_init/uart_addr.coe
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; Address file for UART initialization
;
memory_initialization_radix = 16;
memory_initialization_vector =
0000100C,
00001000,
00001004,
0000100C,
00001004,
00000000,
00000000,
00000000,
00000000,
00000000,
00000000,
00000000,
00000000,
00000000,
00000000;
2 changes: 2 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/LG19A4/ip_cores/atg_uart_init/uart_data.coe
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memory_initialization_radix=16;
memory_initialization_vector=00000080 00000005 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000;
693 changes: 693 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/LG19A4/ip_cores/uart_16550/uart_16550.xci
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2 changes: 1 addition & 1 deletion piton/design/chipset/mc/rtl/mc_top.v
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Expand Up @@ -523,7 +523,7 @@ wire app_hi_pri;
assign app_hi_pri = 1'b0;

ddr4_0 i_ddr4_0 (
.sys_rst ( ~sys_rst_n ),
.sys_rst ( 1'b0 ),
.c0_sys_clk_p ( sys_clk_p ),
.c0_sys_clk_n ( sys_clk_n ),
.dbg_clk ( ), // not used
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466 changes: 466 additions & 0 deletions piton/design/chipset/mc/xilinx/LG19A4/ip_cores/ddr4_0/ddr4_0.xci
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260 changes: 260 additions & 0 deletions piton/design/chipset/noc_sd_bridge/xilinx/LG19A4/ip_cores/sd_cache_bram/sd_cache_bram.xci
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481 changes: 481 additions & 0 deletions piton/design/chipset/noc_sd_bridge/xilinx/LG19A4/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci
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481 changes: 481 additions & 0 deletions piton/design/chipset/noc_sd_bridge/xilinx/LG19A4/ip_cores/sd_data_fifo/sd_data_fifo.xci
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31 changes: 26 additions & 5 deletions piton/design/chipset/rtl/chipset.v
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Expand Up @@ -456,13 +456,21 @@ module chipset(
input btnu,
input btnd,
input btnc,
`endif
`elsif LG19A4_BOARD
input btnl,
input btnr,
input btnu,
input btnd,
input btnc,
`endif

// Switches
`ifdef VCU118_BOARD
// we only have 4 gpio dip switches on this board
input [3:0] sw,
`elsif XUPP3R_BOARD
`elsif LG19A4_BOARD
input [3:0] sw,
`elsif XUPP3R_BOARD
// no switches :(
`else
input [7:0] sw,
Expand Down Expand Up @@ -755,7 +763,10 @@ end
`ifdef VCU118_BOARD
assign uart_boot_en = sw[0];
assign uart_timeout_en = sw[1];
`elsif XUPP3R_BOARD
`elsif LG19A4_BOARD
assign uart_boot_en = sw[0];
assign uart_timeout_en = sw[1];
`elsif XUPP3R_BOARD
assign uart_boot_en = 1'b1;
assign uart_timeout_en = 1'b0;
`else
Expand All @@ -770,6 +781,8 @@ end
`ifdef VCU118_BOARD
// only two switches available...
assign noc_power_test_hop_count = {2'b0, sw[3:2]};
`elsif LG19A4_BOARD
assign noc_power_test_hop_count = {2'b0, sw[3:2]};
`elsif XUPP3R_BOARD
// no switches :(
assign noc_power_test_hop_count = 4'b0;
Expand Down Expand Up @@ -886,10 +899,10 @@ end
`endif // endif PITON_FPGA_MC_DDR3
`endif // endif PITONSYS_NO_MC

`ifdef PITONSYS_SPI
//`ifdef PITONSYS_SPI
// SPI system clock
, .sd_sys_clk(sd_sys_clk)
`endif // endif PITONSYS_SPI
//`endif // endif PITONSYS_SPI

// Chipset<->passthru clocks
`ifdef PITONSYS_INC_PASSTHRU
Expand Down Expand Up @@ -1588,6 +1601,14 @@ chipset_impl_noc_power_test chipset_impl (
.D2(0),
.SR(0)
);
`elsif LG19A4_BOARD
ODDRE1 sd_clk_oddr (
.Q(sd_clk_out),
.C(sd_clk_out_internal),
.D1(1),
.D2(0),
.SR(0)
);
`else
ODDR sd_clk_oddr (
.Q(sd_clk_out),
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1 change: 0 additions & 1 deletion piton/design/chipset/rv64_platform/bootrom/baremetal/rv64_platform.dts
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113 changes: 113 additions & 0 deletions piton/design/chipset/rv64_platform/bootrom/baremetal/rv64_platform.dts
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// DTS generated with gen_riscv_dts(...)
// OpenPiton + Ariane framework
// Date: Jan 20 2025 11:31:19

/dts-v1/;

/ {
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
compatible = "openpiton,cva6platform";

chosen {
u-boot,dm-pre-reloc;
stdout-path = "uart0:115200";
};

aliases {
u-boot,dm-pre-reloc;
console = &uart0;
serial0 = &uart0;
};

cpus {
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
timebase-frequency = <78125>;

CPU0: cpu@0 {
clock-frequency = <10000000>;
u-boot,dm-pre-reloc;
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "openhwgroup, cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

CPU1: cpu@1 {
clock-frequency = <10000000>;
u-boot,dm-pre-reloc;
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "openhwgroup, cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

};

memory@80000000 {
u-boot,dm-pre-reloc;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x80000000 >;
};

sdhci_0: sdhci@f000000000 {
u-boot,dm-pre-reloc;
status = "okay";
compatible = "openpiton,piton-mmc";
reg = < 0x000000f0 0x00000000 0x0000000f 0xf0300000 >;
};

uart0: uart@fff0c2c000 {
u-boot,dm-pre-reloc;
compatible = "ns16550";
reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
clock-frequency = <100000000>;
current-speed = <115200>;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <0>; // regs are spaced on 8 bit boundary (modified from Xilinx UART16550 to be ns16550 compatible)
};

clint@fff1020000 {
u-boot,dm-pre-reloc;
compatible = "riscv,clint0";
interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 &CPU1_intc 3 &CPU1_intc 7 >;
reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
reg-names = "control";
};

PLIC0: plic@fff1100000 {
u-boot,dm-pre-reloc;
#address-cells = <0>;
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 >;
reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
riscv,max-priority = <7>;
riscv,ndev = <1>;
};

};

1 change: 0 additions & 1 deletion piton/design/chipset/rv64_platform/bootrom/linux/rv64_platform.dts
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113 changes: 113 additions & 0 deletions piton/design/chipset/rv64_platform/bootrom/linux/rv64_platform.dts
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// DTS generated with gen_riscv_dts(...)
// OpenPiton + Ariane framework
// Date: Jan 20 2025 11:31:19

/dts-v1/;

/ {
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
compatible = "openpiton,cva6platform";

chosen {
u-boot,dm-pre-reloc;
stdout-path = "uart0:115200";
};

aliases {
u-boot,dm-pre-reloc;
console = &uart0;
serial0 = &uart0;
};

cpus {
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
timebase-frequency = <78125>;

CPU0: cpu@0 {
clock-frequency = <10000000>;
u-boot,dm-pre-reloc;
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "openhwgroup, cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

CPU1: cpu@1 {
clock-frequency = <10000000>;
u-boot,dm-pre-reloc;
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "openhwgroup, cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

};

memory@80000000 {
u-boot,dm-pre-reloc;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x80000000 >;
};

sdhci_0: sdhci@f000000000 {
u-boot,dm-pre-reloc;
status = "okay";
compatible = "openpiton,piton-mmc";
reg = < 0x000000f0 0x00000000 0x0000000f 0xf0300000 >;
};

uart0: uart@fff0c2c000 {
u-boot,dm-pre-reloc;
compatible = "ns16550";
reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
clock-frequency = <100000000>;
current-speed = <115200>;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <0>; // regs are spaced on 8 bit boundary (modified from Xilinx UART16550 to be ns16550 compatible)
};

clint@fff1020000 {
u-boot,dm-pre-reloc;
compatible = "riscv,clint0";
interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 &CPU1_intc 3 &CPU1_intc 7 >;
reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
reg-names = "control";
};

PLIC0: plic@fff1100000 {
u-boot,dm-pre-reloc;
#address-cells = <0>;
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 >;
reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
riscv,max-priority = <7>;
riscv,ndev = <1>;
};

};

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