feat(recipes): modernize DeepSeek V4 library configs - #5554
Draft
cuichenx wants to merge 9 commits into
Draft
Conversation
Signed-off-by: Chen Cui <chcui@nvidia.com>
|
Auto-sync is disabled for draft pull requests in this repository. Workflows must be run manually. Contributors can view more details about this message here. |
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
Signed-off-by: Chen Cui <chcui@nvidia.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What does this PR do?
The library variants retain natural routing, convergence batch sizes, validation and correctness checks, optimizer precision, and checkpoint behavior. They do not enable expert-rank capacity, paged stash, forced load balancing, full-iteration CUDA graphs, or reduced-precision gradient reduction. FP8 parameter gather/buffer reuse is enabled for the provisional B200 PP8 and GB200 PP1 MXFP8 recipes.
The performance recipes are unchanged and are used only as reference configurations. All training validation uses the library recipe through
scripts/training/run_recipe.py.Depends on NVIDIA/Megatron-LM#6509 for stateless grouped FP8 checkpoint saves.
Verification card
The card preserves the GPU conversion, packed SFT, SFT export/HF inference, and canonical performance evidence from #5360 at its item-pinned Bridge revision. It uses the current PP1/MXFP8 library recipe for the pretraining and resume commands, but keeps both items unverified because the exact PP1 candidate has only an eight-step screen. The imported 1K packed SFT run is not presented as long-context evidence, so
sft_long_context.GB200is also unverified.No changes from #5360 were taken for
verify_hf_inference.py, model conversion, DeepSeek V4 bridge implementation, or performance recipes.Validation
256 passed, 1 deselected359 passed15 passed11 passed33 passeduv run --no-project pre-commit run --all-filesgit diff --check139.700versus137.533 TFLOP/s/GPUover steps 2-4 and used the same151.44 GiBpeak allocated memory135.38 TFLOP/s/GPUand5538.41 msPP1 exploration
PP1 was evaluated separately to identify a lower-memory path. The combined configuration in this table is now recorded in the GB200 library recipe. The early-throughput column reports steps 2-4 in order.
The combined configuration removed the early PP1 OOM without an early throughput regression, but the unbounded-routing run slowed after step 4 as routing became imbalanced. The recipe remains a draft candidate and does not yet have a 100-step PP1 validation.
Capacity
1.5was also evaluated as an explicit token-drop alternative:The measured drop rates are too large for a convergence recipe. The library recipe therefore keeps unlimited capacity; PP1 requires routing stabilization rather than a small fixed capacity.
B200 NVL8 candidate
The 64-GPU B200 recipe records TP1/PP8/VPP2/EP8 with portable all-to-all dispatch, full-MoE selective recompute, attention activation offload, and MXFP8 parameter gather/buffer reuse. Expert capacity remains unlimited; paged stash and CUDA graphs remain disabled.
The conservative candidate completed eight finite real-data steps with zero skipped or NaN iterations. Steps 2-8 averaged
143.54 TFLOP/s/GPU(135.8, 148.1, 148.7, 149.0, 135.2, 144.5, 143.5) and reached116.41 GiBpeak allocated /118.61 GiBpeak reserved memory. A combined lighter-recompute/no-offload candidate OOMed before its first step, so the library recipe keeps the conservative recompute and activation-offload settings.The screen used a 64-rank Blackwell topology with eight contiguous eight-rank communication domains. Each domain spanned two four-GPU hosts rather than one physical B200 NVL8 host, so this validates the all-to-all layout and memory candidate but not physical-B200 throughput or flex-dispatcher behavior. Cross-host CUDA IPC prevented meaningful DeepEP/HybridEP validation; neither backend is claimed by this recipe.
Remaining validation
complete an exact 100-step PP1 natural-routing run with model/optimizer/RNG checkpoint save and direct resume
complete physical 64-GPU B200 NVL8 100-step checkpoint/save/resume validation
complete representative 100-step natural-routing validation for the 256-GPU GB300 Pro library recipe
I, the PR author, have personally reviewed every line of this PR.