Analog-and-Digital-VLSI-Design

This repository contains the final report of my ADVD final assignment, wherein I designed 4 input PSUEDO NMOS NOR logic for 180nm SCL technology.

The working schematic is as shown below :

Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
DSCH		DSCH
Design Rules		Design Rules
Microwind_Examples		Microwind_Examples
Pics		Pics
BOOKCH0 Deep-Submicron CMOS Circuit Design Simulator in hands (8).PDF		BOOKCH0 Deep-Submicron CMOS Circuit Design Simulator in hands (8).PDF
BOOKCH1 Introduction (12).PDF		BOOKCH1 Introduction (12).PDF
BOOKCH10 Memories (61).PDF		BOOKCH10 Memories (61).PDF
BOOKCH11 Analog Cells (58).PDF		BOOKCH11 Analog Cells (58).PDF
BOOKCH12 RF Circuits (60).PDF		BOOKCH12 RF Circuits (60).PDF
BOOKCH13 Converters and Sensors (32).PDF		BOOKCH13 Converters and Sensors (32).PDF
BOOKCH14 IO Interfacing (48).PDF		BOOKCH14 IO Interfacing (48).PDF
BOOKCH15 Silicon on Isulator (14).PDF		BOOKCH15 Silicon on Isulator (14).PDF
BOOKCH16 Future and Conclusion (3).PDF		BOOKCH16 Future and Conclusion (3).PDF
BOOKCH2 The MOS devices and technology (41).PDF		BOOKCH2 The MOS devices and technology (41).PDF
BOOKCH3 The MOS Modelling (47).PDF		BOOKCH3 The MOS Modelling (47).PDF
BOOKCH4 The Inverter (44).PDF		BOOKCH4 The Inverter (44).PDF
BOOKCH5 Interconnects (46).PDF		BOOKCH5 Interconnects (46).PDF
BOOKCH6 Basic Gates (56).PDF		BOOKCH6 Basic Gates (56).PDF
BOOKCH7 Arithmetics (46).PDF		BOOKCH7 Arithmetics (46).PDF
BOOKCH8 Sequential Cell Design (38).PDF		BOOKCH8 Sequential Cell Design (38).PDF
BOOKCH9 FPGA (24).PDF		BOOKCH9 FPGA (24).PDF
Cadence.md		Cadence.md
Design Recipes for FPGAs_ Using Verilog and VHDL ( PDFDrive.com ).pdf		Design Recipes for FPGAs_ Using Verilog and VHDL ( PDFDrive.com ).pdf
README.md		README.md
final.pdf		final.pdf
manual_lite.pdf		manual_lite.pdf

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