I work at the intersection of digital hardware, FPGA toolchains, ASIC design, embedded systems, and open-source EDA.

I'm particularly interested in understanding the complete hardware stack — from RTL and synthesis to placement, routing, bitstreams, and physical design.

• 🔭 Working on FPGA toolchains, RTL design, and open-source EDA
• 🧩 Exploring FPGA architecture, device databases, synthesis, place & route, and bitstream generation
• 🔬 Building and experimenting with RTL → GDS flows using open-source tools
• ⚡ Developing FPGA + embedded hardware/software systems
• 🤖 Exploring AI/LLMs, reinforcement learning, and agentic workflows for hardware engineering
• 🌱 Currently deepening my knowledge of digital design, computer architecture, RISC-V, FPGA architecture, and physical design
• 🤝 Interested in collaborating on FPGA, ASIC, RTL, EDA, RISC-V, Embedded, and AI × Hardware projects

My current interests span the hardware development stack:

              Hardware Architecture
                       │
                       ▼
                 RTL / HDL
                       │
                       ▼
              Simulation / Verification
                       │
                       ▼
                   Synthesis
                    /     \
                   /       \
                  ▼         ▼
               FPGA        ASIC
                  │          │
                  ▼          ▼
            Place & Route   Physical Design
                  │          │
                  ▼          ▼
               Bitstream    GDSII

• FPGA architecture and fabric
• LUTs, routing resources and configuration
• FPGA device databases
• Synthesis
• Placement & routing
• Bitstream generation
• Open-source FPGA toolchains
• Xilinx 7-Series / XC7 ecosystem

• Verilog / SystemVerilog
• RTL architecture
• Digital logic design
• RTL simulation & verification
• Synthesis
• Floorplanning
• Placement
• Clock Tree Synthesis
• Routing
• RTL-to-GDS flows
• SKY130 / open-source PDK ecosystem

I'm exploring how AI can interact with traditional hardware-development workflows:

• LLM-assisted RTL development
• AI-assisted EDA workflows
• Agentic hardware engineering
• Reinforcement learning for optimization
• Automated hardware reasoning
• LLMs for semiconductor tooling

Currently exploring: SystemVerilog, Veryl, and modern hardware-description approaches.

• OpenLane / OpenROAD
• nextpnr
• Project X-Ray
• APIO
• Yosys
• Verilator
• Icarus Verilog
• GTKWave
• Vivado
• RISC-V toolchains
• FPGA device databases & tooling

I actively explore and contribute to open-source hardware ecosystems.

Some of the projects and ecosystems I'm working with:

• 🔹 APIO
• 🔹 nextpnr-xilinx
• 🔹 Project X-Ray
• 🔹 Project X-Ray databases
• 🔹 OpenXC7
• 🔹 OpenLane / OpenROAD
• 🔹 Veryl
• 🔹 RISC-V

I'm especially interested in making FPGA and semiconductor development more open, reproducible, and accessible.

I've also worked on hardware/software integrated systems involving:

• FPGA peripherals
• UART
• Custom IP
• Real-time sensor acquisition
• FPGA ↔ software communication

Digital Design
      │
      ├── RTL Design
      ├── Verification
      ├── Computer Architecture
      │
      ├── FPGA Architecture
      │      ├── LUTs
      │      ├── Routing
      │      ├── Device Databases
      │      └── Bitstreams
      │
      ├── ASIC Physical Design
      │      ├── Synthesis
      │      ├── Floorplanning
      │      ├── Placement
      │      ├── CTS
      │      └── Routing
      │
      └── AI × EDA
             ├── LLMs
             ├── Agents
             ├── RL
             └── Automated Hardware Design

Click to expand

Interested in open-source silicon, FPGA tooling, EDA, RISC-V, embedded systems, and AI × hardware.