Support All Mandatory RVA23 Extensions

[kathlenemagnus]

RVA23U64 Mandatory Extensions

• Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic.
• Ziccrs Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.
• Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support all atomics in A.
• Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.
• Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.
• Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
• Zkt Data-independent execution latency.
• Zvfhmin Vector minimal half-precision floating-point. Add Support for "Zvfh" and "Zvfhmin" Extensions for Vector Half-Precision Floating-Point #372
• Zvkt Vector data-independent execution latency.
• Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

RVA23S64 Mandatory Extensions

• Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.
• Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.
• Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.
• Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.
• Svpbmt Page-based memory types
• Svnapot NAPOT translation contiguity.
• Sstc supervisor-mode timer interrupts.
• Sscofpmf count overflow and mode-based filtering.
• Ssnpm Pointer masking, with senvcfg.PME and henvcfg.PME supporting, at minimum, settings PMLEN=0 and PMLEN=7.
• Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).
• H The hypervisor extension.
• Ssstateen Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen10-3 and hypervisor-mode (hstateen0-3) state-enable registers must be provided.
• Shcounterenw For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren
  must be writable.
• Shvstvala vstval must be written in all cases described above for stval.
• Shtvala htval must be written with the faulting guest physical address in all circumstances permitted by the ISA.
• Shvstvecd vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address.
• Shvsatpa All translation modes supported in satp must be supported in vsatp.
• Shgatpa For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported.