[demo] FPGA smoke demo: sum integers 0..5 = 15

[marcos-mendez]

First tangible-on-real-silicon-equivalent-hardware demo. The simplest possible end-to-end loop:

1. Synthesize inner_jib_top.sv for the chosen FPGA target
2. Generate bitstream
3. Program the FPGA (USB JTAG)
4. RISC-V binary on board sums 0..5 and prints '15' on UART
5. Host computer reads UART output, displays it

Why this matters:
This is the first demo that proves the toolchain runs all the way from MAST RTL to physical silicon-equivalent hardware. It's small, but it's tangible. We can show it to:

• Cooperative members
• Potential funders (FINEP, BNDES, OpenCollective backers)
• Universities (USP, UNICAMP, UFMG) who could host us
• Talks at conferences (FISL, RISC-V Summit Brasil)

Tasks:

• Wait on issues [hw] inner_jib_top.sv — top-level integration (1 CU + AXI4 + axi4_mem_model + UART) #4 (top.sv integration) and [hw] FPGA target board pick (ULX3S vs Arty A7 vs Kintex) #5 (FPGA target pick)
• Cross-compile the sum-ints program (existing in upstream examples/direct/sum_ints.asm)
• Run synthesis + place & route + bitgen
• Program FPGA, verify UART output reads '15'
• Record a video, post to PopSolutions blog and skills.sh