From 21c9fd4845ca25c2b59caca1b58a2cec0d25204c Mon Sep 17 00:00:00 2001
From: Frederik Haxel <haxel@fzi.de>
Date: Mon, 31 Aug 2026 15:11:18 +0200
Subject: [PATCH 1/2] isolde.json: Add safety-gen description

---
 ips/isolde.json | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/ips/isolde.json b/ips/isolde.json
index 2d70e69..a21e895 100644
--- a/ips/isolde.json
+++ b/ips/isolde.json
@@ -1364,21 +1364,25 @@
   },
   {
     "Project": "ISOLDE",
-    "Name": "Model-based generation framework for hardware safety pattern",
-    "URL": "",
-    "License": "Others",
-    "Status": "",
-    "Description": "TBD",
+    "Name": "safety-gen",
+    "URL": "https://github.com/fzi-forschungszentrum-informatik/safety-gen",
+    "License": [
+      "Apache-2.0",
+      "LLVM-exception"
+    ],
+    "Status": "Released",
+    "Description": "CIRCT/MLIR toolkit that automates the insertion of safety patterns into an existing SoC design.",
     "WI": [
       "ID 4.2.03"
     ],
     "Partners": "FZI",
-    "Comment": "TBD. ISOLDE Category 'Operating systems and applications SW'",
+    "Comment": "Apache V2.0 with LLVM Exceptions. ISOLDE Category 'Operating systems and applications SW'",
     "Category": [
-      "Software"
+      "Software",
+      "Tool"
     ],
-    "IP_CARD_URL": "",
-    "IP_CARD_PDF_URL": ""
+    "IP_CARD_URL": "https://github.com/fzi-forschungszentrum-informatik/safety-gen/blob/main/ip-card/safety-gen.json",
+    "IP_CARD_PDF_URL": "https://github.com/fzi-forschungszentrum-informatik/safety-gen/blob/main/ip-card/safety-gen.pdf"
   },
   {
     "Project": "ISOLDE",

From 97eb31f28126fbaa9e2f486077283345a60f88a4 Mon Sep 17 00:00:00 2001
From: Frederik Haxel <haxel@fzi.de>
Date: Mon, 31 Aug 2026 15:12:56 +0200
Subject: [PATCH 2/2] isolde.json: Add cosim-gen description

---
 ips/isolde.json | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/ips/isolde.json b/ips/isolde.json
index a21e895..6ab834b 100644
--- a/ips/isolde.json
+++ b/ips/isolde.json
@@ -1763,22 +1763,25 @@
   },
   {
     "Project": "ISOLDE",
-    "Name": "Simulation-based HW/SW co-verification approach",
-    "URL": "",
-    "License": "Others",
-    "Status": "",
-    "Description": "TBD",
+    "Name": "cosim-gen",
+    "URL": "https://github.com/fzi-forschungszentrum-informatik/cosim-gen",
+    "License": [
+      "Apache-2.0",
+      "LLVM-exception"
+    ],
+    "Status": "Released",
+    "Description": "Generates a QEMU/RTL co-simulation from an RTL design and its device tree, allowing users to freely configure which components run in RTL while the remaining platform runs in QEMU.",
     "WI": [
       "ID 4.3.05"
     ],
     "Partners": "FZI",
-    "Comment": "TBD. ISOLDE Category 'Operating systems and applications SW'",
+    "Comment": "Apache V2.0 with LLVM Exceptions. ISOLDE Category 'Operating systems and applications SW'",
     "Category": [
       "Software",
       "Tool"
     ],
-    "IP_CARD_URL": "",
-    "IP_CARD_PDF_URL": ""
+    "IP_CARD_URL": "https://github.com/fzi-forschungszentrum-informatik/cosim-gen/blob/main/ip-card/cosim-gen.json",
+    "IP_CARD_PDF_URL": "https://github.com/fzi-forschungszentrum-informatik/cosim-gen/blob/main/ip-card/cosim-gen.pdf"
   },
   {
     "Project": "ISOLDE",