diff --git a/src/vpu/lmulsequencer.sv b/src/vpu/lmulsequencer.sv new file mode 100644 index 000000000..8a4b15ff1 --- /dev/null +++ b/src/vpu/lmulsequencer.sv @@ -0,0 +1,95 @@ +/////////////////////////////////////////// +// lmulsequencer.sv +// +// Written: Rose Thompson rose.thompson@skyworksinc.com +// Created: 1 September 2026 +// Modified: 1 September 2026 +// +// Purpose: sequence multiple micro-op vector instructions based on lmul +// +// Documentation: RISC-V System on Chip Design Volume 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module lmulsequencer ( + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic VectorD, // This instruction is a vector + input logic [4:0] Vs1D, Vs2D, VdD, + input logic [6:0] lmulDecodedD, + // hand shaking controls + input logic AnyExecutionUnitReadyD, + // output micro vector instruction + output logic [4:0] Vs1FinalD, Vs2FinalD, VdFinalD +); + + logic IncrMicroOpD; // Next micro vector instruction when lmul > 1 + + logic IncrD; + logic [4:0] Vs1P1D, Vs2P1D, VdP1D; + logic [4:0] Vs1P1QD, Vs2P1QD, VdP1QD; + logic [3:0] lmulCntrD, lmulCntrP1; + logic lmulCntrDone, lmulCntrLoad; + logic lmulCntrFirstCaptureD; + logic [3:0] lmulIntD; + + typedef enum logic {STATE_BEGIN, STATE_INCR} statetype; + statetype CurrState, NextState; + + assign lmulIntD = lmulDecodedD[6:3]; + assign lmulCntrFirstCaptureD = lmulCntrD > 1; + + assign Vs1P1D = Vs1FinalD + 5'b00001; + flopenr #(5) Vs1IncrReg (clk, reset, IncrD, Vs1P1D, Vs1P1QD); + mux2 #(5) Vs1Mux (Vs1D, Vs1P1QD, lmulCntrFirstCaptureD, Vs1FinalD); + + assign Vs2P1D = Vs2FinalD + 5'b00001; + flopenr #(5) Vs2IncrReg (clk, reset, IncrD, Vs2P1D, Vs2P1QD); + mux2 #(5) Vs2Mux (Vs2D, Vs2P1QD, lmulCntrFirstCaptureD, Vs2FinalD); + + assign VdP1D = VdFinalD + 5'b00001; + flopenr #(5) VdIncrReg (clk, reset, IncrD, VdP1D, VdP1QD); + mux2 #(5) VdMux (VdD, VdP1QD, lmulCntrFirstCaptureD, VdFinalD); + + + flopenl #(4) counter (clk, lmulCntrLoad, IncrD, lmulCntrP1, 4'b0001, lmulCntrD); + assign lmulCntrDone = lmulCntrD == lmulIntD; // *** this is a bug for lmul less than 1 + assign lmulCntrP1 = lmulCntrD + 4'b0001; + + always_ff @(posedge clk) + if(reset | FlushD) CurrState <= STATE_BEGIN; + else CurrState <= NextState; + + assign IncrD = AnyExecutionUnitReadyD & VectorD; + + always_comb begin + NextState = STATE_BEGIN; + case(CurrState) + STATE_BEGIN: if(VectorD & (lmulIntD > 4'd1) & IncrD) NextState = STATE_INCR; + STATE_INCR: if(lmulCntrD == lmulIntD) NextState = STATE_BEGIN; + else NextState = STATE_INCR; + default: NextState = STATE_BEGIN; + endcase + end + + assign lmulCntrLoad = CurrState == STATE_BEGIN & VectorD; + +endmodule diff --git a/src/vpu/vcontroller.sv b/src/vpu/vcontroller.sv new file mode 100644 index 000000000..b9c2dc24a --- /dev/null +++ b/src/vpu/vcontroller.sv @@ -0,0 +1,73 @@ +/////////////////////////////////////////// +// vcontroller.sv +// +// Written: Rose Thompson rose.thompson@skyworksinc.com +// Created: 31 August 2026 +// Modified: 31 August 2026 +// +// Purpose: vector controller module +// +// Documentation: RISC-V System on Chip Design Volume 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module vcontroller import cvw::*; #(parameter cvw_t P) ( + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic [31:0] InstrD, // Instruction in Decode stage + input logic VectorD, // This instruction is a vector + + // Decode stage outputs + output logic [4:0] Vs1FinalD, Vs2FinalD, // Vector Source 1 and 2 + output logic [4:0] VdFinalD, // Vector Destination read (overwrite) + output logic VMD, // 0 = mask enabled, 1 mask disabled + output logic [5:0] Funct6D, + output logic [2:0] Funct3D, + output logic RegWriteD, + output logic VRegWriteD, + output logic [1:0] VALUSrcAD, + output logic VALUSrcBD, + output logic VALUResultD, + output logic IllegalVectorInstructionD, + // hand shaking controls + output logic [P.VPU_MAX_EU-1:0] ControllerValidD, + input logic [P.VPU_MAX_EU-1:0] ExecutionUnitReadyD +); + + logic MicroVectorD; + logic [4:0] Vs1D, Vs2D; // Vector Source 1 and 2 + logic [4:0] VdD; // Vector Destination read (overwrite) + logic [6:0] lmulDecodedD; + //logic [2:0] lmulD; // *** should be set by vset* instruction + + assign lmulDecodedD = 7'b0001_000; // m1 + + + vdecoder #(P) vdecoder(.clk, .reset, .StallD, .FlushD, + .InstrD, .Vs1D, .Vs2D, .VdD, .VMD, + .Funct6D, .Funct3D, .RegWriteD, .VRegWriteD, + .VALUResultD, .VALUSrcAD, .VALUSrcBD, .IllegalVectorInstructionD); + + vdispatcher #(P) vdispatcher(.clk, .reset, .StallD, .FlushD, + .VectorD, .Vs1D, .Vs2D, .VdD, .ControllerValidD, .ExecutionUnitReadyD, + .MicroVectorD, .Vs1FinalD, .Vs2FinalD, .VdFinalD, .lmulDecodedD); + +endmodule diff --git a/src/vpu/vdatapath.sv b/src/vpu/vdatapath.sv new file mode 100644 index 000000000..75453a52f --- /dev/null +++ b/src/vpu/vdatapath.sv @@ -0,0 +1,86 @@ +/////////////////////////////////////////// +// vdatapath.sv +// +// Written: Rose Thompson rose.thompson@skyworksinc.com +// Created: 2 September 2026 +// Modified: 2 September 2026 +// +// Purpose: vector datapath module +// +// Documentation: RISC-V System on Chip Design Volume 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module vdatapath import cvw::*; #(parameter cvw_t P) ( + input logic clk, + input logic reset, + // Hazards + input logic StallD, StallE, StallM, StallW, // stall signals (from HZU) + input logic FlushD, FlushE, FlushM, FlushW, // flush signals (from HZU) + // flow control + input logic [P.VPU_MAX_EU-1:0] ControllerValidD, + output logic [P.VPU_MAX_EU-1:0] ExecutionUnitReadyD, + // control input + input logic [4:0] Vs1FinalD, Vs2FinalD, // Vector Source 1 and 2 + input logic [4:0] VdFinalD, // Vector Destination read (overwrite) + input logic VMD, // 0 = mask enabled, 1 mask disabled + input logic [5:0] Funct6D, + input logic [2:0] Funct3D, + input logic RegWriteD, + input logic VRegWriteD, + input logic [1:0] VALUSrcAD, + input logic VALUSrcBD, + input logic VALUResultD, + input logic IllegalVectorInstructionD, + // from/to the scalar core + input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer/FP input for convert, move (from IEU) + output logic [P.VPU_LSU_BLEN-1:0] VWriteDataM [P.VPU_LSU_EU-1:0], // Data to be written to memory (to LSU) + output logic [P.XLEN-1:0] VEUAdrM [P.VPU_LSU_EU-1:0], // Data to be written to memory (to LSU) + input logic [P.VPU_LSU_BLEN-1:0] VReadDataM [P.VPU_LSU_EU-1:0], // Read data (from LSU) + output logic [P.XLEN-1:0] VIEUFPResultW // Int or FP result for X or F regs. + // +); + + logic [P.VLEN-1:0] SrcAD, SrcBD, SrcCD; + logic [P.VLEN-1:0] v0D; + logic [P.VLEN-1:0] VResultFinalW; + + + logic VdFinalweW; + logic [4:0] VdFinalW; + + vregfile #(P.VLEN) vregfile(clk, reset, VdFinalweW, Vs1FinalD, Vs2FinalD, VdFinalD, VdFinalW, + VResultFinalW, SrcAD, SrcBD, SrcCD, v0D); + + + // *** remove all of this when ready + genvar i; + for(i = 0; i < P.VPU_LSU_LANES; i++) begin + assign VWriteDataM[i] = '0; + assign VEUAdrM[i] = '0; + end + + assign ExecutionUnitReadyD = '1; + assign VIEUFPResultW = '0; + assign VdFinalweW = '0; + assign VdFinalW = '0; + assign VResultFinalW = '0; + +endmodule diff --git a/src/vpu/vdecoder.sv b/src/vpu/vdecoder.sv new file mode 100644 index 000000000..00516ea93 --- /dev/null +++ b/src/vpu/vdecoder.sv @@ -0,0 +1,117 @@ +/////////////////////////////////////////// +// vdecoder.sv +// +// Written: Rose Thompson rose.thompson@skyworksinc.com +// Created: 26 August 2026 +// Modified: 26 August 2026 +// +// Purpose: vector decoder module +// +// Documentation: RISC-V System on Chip Design Volume 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +/* verilator lint_off UNUSEDPARAM */ +// *** this will be useful later. Remove the lint_off when ready +module vdecoder import cvw::*; #(parameter cvw_t P) ( +/* verilator lint_on UNUSEDPARAM */ + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic [31:0] InstrD, // lmul sequenced micro-op instruction in Decode stage + + // Decode stage outputs + output logic [4:0] Vs1D, Vs2D, // Vector Source 1 and 2 + output logic [4:0] VdD, // Vector Destination read (overwrite) + output logic VMD, // 0 = mask enabled, 1 mask disabled + output logic [5:0] Funct6D, + output logic [2:0] Funct3D, + output logic RegWriteD, + output logic VRegWriteD, + output logic [1:0] VALUSrcAD, + output logic VALUSrcBD, + output logic VALUResultD, + output logic IllegalVectorInstructionD +); + + +`define VCTRLW 7 + + logic [6:0] OpD; // Opcode in Decode stage + logic OPIVVD, OPFVVD, OPMVVD, OPIVID; + logic OPIVXD, OPFVFD, OPMVXD, VSETD; + logic VLSFunctD; + logic MewD; + + + assign OpD = InstrD[6:0]; + assign Funct3D = InstrD[14:12]; + assign Funct6D = InstrD[31:26]; + assign Vs1D = InstrD[19:15]; + assign Vs2D = InstrD[24:20]; + assign VdD = InstrD[11:7]; + assign OPIVVD = Funct3D == 3'b000; + assign OPFVVD = Funct3D == 3'b001; + assign OPMVVD = Funct3D == 3'b010; + assign OPIVID = Funct3D == 3'b011; + assign OPIVXD = Funct3D == 3'b100; + assign OPFVFD = Funct3D == 3'b101; + assign OPMVXD = Funct3D == 3'b110; + assign VSETD = Funct3D == 3'b111; + assign VMD = InstrD[25]; + assign MewD = InstrD[28]; + + assign VLSFunctD = (Funct3D == 3'b000) | (Funct3D == 3'b101) | (Funct3D == 3'b110) | (Funct3D == 3'b111) & ~MewD; + + logic [`VCTRLW-1:0] ControlsD; // Main Instruction Decoder control signals // *** far from complete + + always_comb begin + case(OpD) + // RegWrite_VRegWrite_ALUSrc(A_B)_ALUResult_Illegal + 7'b0000111: if(VLSFunctD) + ControlsD = `VCTRLW'b0_1_10_0_1_0; // unit-strip; vl // *** add the address modes later + 7'b0100111: if(VLSFunctD) + ControlsD = `VCTRLW'b0_0_10_1_0_0; // unit-strip; vs + 7'b1010111: begin // vector data operation + if(OPIVVD) + ControlsD = `VCTRLW'b0_1_00_0_0_0; + else if(OPFVVD) + ControlsD = `VCTRLW'b0_1_00_0_0_0; // *** expand later writes either GPR or VRF + else if(OPMVVD) + ControlsD = `VCTRLW'b0_1_00_0_0_0; // *** expand later writes either GPR or VRF + else if(OPIVID) + ControlsD = `VCTRLW'b0_1_01_0_0_0; + else if(OPIVXD) + ControlsD = `VCTRLW'b0_1_10_0_0_0; + else if(OPFVFD) + ControlsD = `VCTRLW'b0_1_10_0_0_0; + else if(OPMVXD) + ControlsD = `VCTRLW'b0_1_10_0_0_0; // *** expand later writes either GPR or VRF + else if(VSETD) + ControlsD = `VCTRLW'b1_0_10_0_0_0; // *** incomplete + end + default: + ControlsD = `VCTRLW'b0_0_00_0_0_1; + endcase + end + + assign {RegWriteD, VRegWriteD, VALUSrcAD, VALUSrcBD, VALUResultD, IllegalVectorInstructionD} = ControlsD; + +endmodule diff --git a/src/vpu/vdispatcher.sv b/src/vpu/vdispatcher.sv new file mode 100644 index 000000000..c8f0f99f8 --- /dev/null +++ b/src/vpu/vdispatcher.sv @@ -0,0 +1,70 @@ +/////////////////////////////////////////// +// vdispatcher.sv +// +// Written: Rose Thompson rose.thompson@skyworksinc.com +// Created: 1 September 2026 +// Modified: 1 September 2026 +// +// Purpose: vector dispatcher module +// +// Documentation: RISC-V System on Chip Design Volume 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module vdispatcher import cvw::*; #(parameter cvw_t P) ( + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic VectorD, // This instruction is a vector + input logic [4:0] Vs1D, Vs2D, VdD, + input logic [6:0] lmulDecodedD, + // hand shaking controls + output logic [P.VPU_MAX_EU-1:0] ControllerValidD, + input logic [P.VPU_MAX_EU-1:0] ExecutionUnitReadyD, + // output micro vector instruction + output logic MicroVectorD, + output logic [4:0] Vs1FinalD, Vs2FinalD, VdFinalD +); + + logic IncrMicroOpD; // Next micro vector instruction when lmul > 1 + + //input logic SelectedControllerValidD, + + // The EU selector + // ExecutionUnitReadyD indications which EUs can take a new vector instruction this cycle + // However not all EUs can take the same instructions. They may only accept int, float, load/store, fixed, + // or specific sub categories. + // For this initial version All EUs will accept all instructions. *** fix me later. + // Selection mechanism is currently priority encoder. Should be round robin. *** fix me later. + + logic [P.VPU_MAX_EU-1:0] SelectedD; + logic AnyExecutionUnitReadyD; + + priorityonehot #(P.VPU_MAX_EU) SelectedEUPriority(ExecutionUnitReadyD, SelectedD); + assign AnyExecutionUnitReadyD = |ExecutionUnitReadyD; + + lmulsequencer lmulsequencer(.clk, .reset, .StallD, .FlushD, + .VectorD, .Vs1D, .Vs2D, .VdD, .lmulDecodedD, + .AnyExecutionUnitReadyD, .Vs1FinalD, .Vs2FinalD, .VdFinalD); + + assign ControllerValidD = SelectedD & {P.VPU_MAX_EU{VectorD}}; // demux to selected EU + assign MicroVectorD = |ControllerValidD; + +endmodule diff --git a/src/vpu/vpu.sv b/src/vpu/vpu.sv index 81234bac2..e5f6567c2 100644 --- a/src/vpu/vpu.sv +++ b/src/vpu/vpu.sv @@ -47,12 +47,30 @@ module vpu import cvw::*; #(parameter cvw_t P) ( // Memory stage // TODO *** Cannot use decoded control from IEU because the there are overlapping vector instructions? output logic [P.VPU_LSU_BLEN-1:0] VWriteDataM [P.VPU_LSU_EU-1:0], // Data to be written to memory (to LSU) - output logic IllegalVPUInstrD, // Is the instruction an illegal fpu instruction (to IFU) + output logic [P.XLEN-1:0] VEUAdrM [P.VPU_LSU_EU-1:0], // Data to be written to memory (to LSU) + input logic [P.VPU_LSU_BLEN-1:0] VReadDataM [P.VPU_LSU_EU-1:0], // Read data (from LSU) + output logic IllegalVectorInstructionD, // Is the instruction an illegal fpu instruction (to IFU) // Writeback stage - input logic [P.VPU_LSU_BLEN-1:0] VReadDataW [P.VPU_LSU_EU-1:0], // Read data (from LSU) - output logic [P.XLEN-1:0] VResultIntFPW // Int or FP result for X or F regs. + output logic [P.XLEN-1:0] VIEUFPResultW // Int or FP result for X or F regs. ); + logic [4:0] Vs1FinalD, Vs2FinalD; // Vector Source 1 and 2 + logic [4:0] VdFinalD; // Vector Destination read (overwrite) + logic VMD; // 0 = mask enabled; 1 mask disabled + logic [5:0] Funct6D; + logic [2:0] Funct3D; + logic RegWriteD; + logic VRegWriteD; + logic [1:0] VALUSrcAD; + logic VALUSrcBD; + logic VALUResultD; + //logic IllegalVectorInstructionD; + + logic [P.VPU_MAX_EU-1:0] ControllerValidD; + logic [P.VPU_MAX_EU-1:0] ExecutionUnitReadyD; + + + // divide into control and data path // decoder inputs @@ -68,15 +86,22 @@ module vpu import cvw::*; #(parameter cvw_t P) ( // the VPU must be delayed to ensure inorder commit. StallE, StallM, and StallW need to post pone the progress of // vector instruction progress under this condiction. - assign VResultIntFPW = '0; - assign IllegalVPUInstrD = '0; - genvar i; - for(i = 0; i < P.VPU_LSU_LANES; i++) begin - assign VWriteDataM[i] = '0; - end - assign VPUFrontEndBusyD = '0; + assign VPUFrontEndBusyD = '0; // *** vcontroller needs to drive VPUFrontEndBusyD when all the EUs are busy + + vcontroller #(P) vcontroller(.clk, .reset, .StallD, .FlushD, + .InstrD, .VectorD, .Vs1FinalD, .Vs2FinalD, .VdFinalD, + .VMD, .Funct6D, .Funct3D, .RegWriteD, .VRegWriteD, .VALUSrcAD, .VALUSrcBD, + .VALUResultD, .IllegalVectorInstructionD, .ControllerValidD, .ExecutionUnitReadyD); + + vdatapath #(P) vdatapath(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .ControllerValidD, .ExecutionUnitReadyD, .Vs1FinalD, .Vs2FinalD, .VdFinalD, .VMD, .Funct6D, .Funct3D, + .RegWriteD, .VRegWriteD, .VALUSrcAD, .VALUSrcBD, .VALUResultD, .IllegalVectorInstructionD, + .ForwardedSrcAE, .ForwardedSrcBE, .VWriteDataM, .VEUAdrM, .VReadDataM, .VIEUFPResultW); + + // **** add EUs here. Remove this code + assign ExecutionUnitReadyD = '1; -endmodule; // vpu +endmodule diff --git a/src/vpu/vregfile.sv b/src/vpu/vregfile.sv new file mode 100644 index 000000000..3dec7de7a --- /dev/null +++ b/src/vpu/vregfile.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// vregfile.sv +// +// Written: Rose Thompson Rose.Thompson@skyworksinc.com +// based on regfile.sv by David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Created: 2 September +// Modified: +// +// Purpose: 4-port register file +// +// Documentation: RISC-V System on Chip Design Vol 2 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-26 Harvey Mudd College & Oklahoma State University & Skyworks Solutions Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module vregfile #(parameter VLEN) ( + input logic clk, reset, + input logic we4, // Write enable + input logic [4:0] a1, a2, a3, a4, // Source registers to read (a1, a2, a3), destination register to write (a4) + input logic [VLEN-1:0] wd4, // Write data for port 4 + output logic [VLEN-1:0] rd1, rd2, rd3, v0); // Read data for ports 1, 2, 3, v0 always available for masks + + logic [VLEN-1:0] rf[31:0]; + integer i; + + // four ported register file + // Read three ports combinationally (a1/rd1, a2/rd2, a3/rd3) + // Write four port on falling edge of clock (a3/wd3/we3) + // Write occurs on falling edge of clock + + // reset is intended for simulation only, not synthesis + // can logic be adjusted to not need resettable registers? + + always_ff @(negedge clk) + if (reset) for(i=0; i<32; i++) rf[i] <= '0; + else if (we4) rf[a4] <= wd4; + + assign rd1 = rf[a1]; + assign rd2 = rf[a2]; + assign rd3 = rf[a3]; + assign v0 = rf[0]; + +endmodule diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 7cf5b4d11..ad7c08c07 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -173,10 +173,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic VectorD; logic VPUFrontEndBusyD; - logic IllegalVPUInstrD; - logic [P.XLEN-1:0] VResultIntFPW; + logic IllegalVectorInstructionD; + logic [P.XLEN-1:0] VIEUFPResultW; logic [P.VPU_LSU_BLEN-1:0] VWriteDataM [P.VPU_LSU_EU-1:0]; - logic [P.VPU_LSU_BLEN-1:0] VReadDataW [P.VPU_LSU_EU-1:0]; + logic [P.XLEN-1:0] VEUAdrM [P.VPU_LSU_EU-1:0]; + logic [P.VPU_LSU_BLEN-1:0] VReadDataM [P.VPU_LSU_EU-1:0]; + // instruction fetch unit: PC, branch prediction, instruction cache @@ -370,13 +372,13 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // *** fix me replace with driver from LSU genvar i; for(i = 0; i < P.VPU_LSU_LANES; i++) begin - assign VReadDataW[i] = '0; + assign VReadDataM[i] = '0; end if (P.V_SUPPORTED) begin : vpu vpu #(P) vpu(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .VPUFrontEndBusyD, .InstrD, .VectorD, .ForwardedSrcAE, .ForwardedSrcBE, - .VWriteDataM, .IllegalVPUInstrD, .VReadDataW, .VResultIntFPW); + .VWriteDataM, .VEUAdrM, .IllegalVectorInstructionD, .VReadDataM, .VIEUFPResultW); end else begin //assign {VPUFrontEndBusyD, IllegalVPUInstrD, VResultIntFPW} = '0; end