From f19f8971f0228813727670e7b475ac8aa902d361 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 14 Aug 2026 14:30:59 +0200 Subject: [PATCH 01/24] [sw,rom_ext,topgen] fix size of rom_ext_virtual - The size must be equal to half the RRAM space and to one slot. - The reserved_bytes are deducted in the virtual linker scripts. This was missed in #30424 because as long as both rram_ctrl and flash_ctrl are present, topgen was selecting the memory region of flash_ctrl "eflash" which is 512kB for the virtual memory slot size. This was inconsistent because other branches in topgen were selecting RRAM. Signed-off-by: Michael Gautschi --- .../sw/autogen/top_earlgrey_memory.ld | 4 +-- sw/device/silicon_creator/rom/rom.ld | 7 +++++ .../silicon_creator/rom_ext/e2e/handoff/BUILD | 2 +- .../imm_section/imm_section_slot_virtual.ld | 3 +- .../rom_ext/rom_ext_slot_virtual.ld | 21 ++++++++++--- util/topgen/templates/toplevel_memory.ld.tpl | 30 +++++++++++-------- 6 files changed, 47 insertions(+), 20 deletions(-) diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld index 5992cb1c708e1..ad47e753e98a7 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld @@ -20,8 +20,8 @@ MEMORY { ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 ram_secondary(rwx) : ORIGIN = 0x10020000, LENGTH = 0x10000 rom(rx) : ORIGIN = 0x00040000, LENGTH = 0xc000 - rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000 - owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000 + rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x100000 + owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x100000 } /** diff --git a/sw/device/silicon_creator/rom/rom.ld b/sw/device/silicon_creator/rom/rom.ld index 804eb71453ddc..25439d23f60dc 100644 --- a/sw/device/silicon_creator/rom/rom.ld +++ b/sw/device/silicon_creator/rom/rom.ld @@ -28,6 +28,13 @@ _rom_boot_address = ORIGIN(rom); */ _rom_ext_virtual_start_address = ORIGIN(rom_ext_virtual); _rom_ext_virtual_size = LENGTH(rom_ext_virtual); +/* + * Sanity check that the remap window topgen computed doesn't exceed the + * physical slot it gets mapped into. Compared against the unreduced slot + * size -- unlike rom_ext_slot_virtual.ld's placement region, this window's + * own size must stay a power of two for ibex_addr_remap_set()'s NAPOT-style + * alignment masking, so it is not shrunk by `_nvm_slot_reserved_bytes`. + */ ASSERT((_rom_ext_virtual_size <= (LENGTH(nvm) / 2)), "Error: rom ext NVM is bigger than slot."); diff --git a/sw/device/silicon_creator/rom_ext/e2e/handoff/BUILD b/sw/device/silicon_creator/rom_ext/e2e/handoff/BUILD index 2d190b74af48c..bcab7c88a3420 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/handoff/BUILD +++ b/sw/device/silicon_creator/rom_ext/e2e/handoff/BUILD @@ -112,7 +112,7 @@ opentitan_test( "1: 00000000 ----- ---- sz=00000000", "2: a....... ----- ---- sz=00000000", # Application code start. "3: a....... TOR -X-R sz=........", # Application code end. - "4: a0000000 NAPOT ---R sz=00080000", # Application rodata region. + "4: a0000000 NAPOT ---R sz=00100000", # Application rodata region. "5: 10020000 NAPOT --WR sz=00010000", # Secondary SRAM region. "6: 00000000 ----- ---- sz=00000000", "7: 00000000 ----- ---- sz=00000000", diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld index 2c2b133932793..d5b26e1038382 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld @@ -20,7 +20,8 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld */ MEMORY { - imm_section_virtual(rx) : ORIGIN = ORIGIN(rom_ext_virtual) + 0x400, LENGTH = 0x80000 - 0x400 + imm_section_virtual(rx) : ORIGIN = ORIGIN(rom_ext_virtual) + 0x400, + LENGTH = LENGTH(rom_ext_virtual) - 0x400 - _nvm_slot_reserved_bytes } REGION_ALIAS("rom_ext_nvm", imm_section_virtual); diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld index f8c8e9d308010..1fbcfc1a0d1a6 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld @@ -21,12 +21,25 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld */ _rom_ext_start_address = ORIGIN(rom_ext_virtual); _rom_ext_size = LENGTH(rom_ext_virtual); + +/* + * rom_ext_virtual must be a power of two (NAPOT remap masking) and equal + * one NVM slot. rom.ld/test_rom.ld check this too, but for a different + * link unit than the ROM_EXT itself. + */ +ASSERT((_rom_ext_size & (_rom_ext_size - 1)) == 0, + "Error: rom_ext_virtual must be a power of two (NAPOT remap/ePMP)."); +ASSERT(_rom_ext_size == LENGTH(nvm) / 2, + "Error: rom_ext_virtual does not match the NVM slot size."); + /* - * Bounded to leave `_nvm_slot_reserved_bytes` empty at the end of whichever - * physical slot this virtual image ends up mapped into. + * Leaves `_nvm_slot_reserved_bytes` empty at the end of the physical slot. */ -ASSERT((_rom_ext_size <= (LENGTH(nvm) / 2 - _nvm_slot_reserved_bytes)), "Error: rom ext NVM is bigger than slot"); +MEMORY { + rom_ext_virtual_usable(rx) : ORIGIN = ORIGIN(rom_ext_virtual), + LENGTH = LENGTH(rom_ext_virtual) - _nvm_slot_reserved_bytes +} -REGION_ALIAS("rom_ext_nvm", rom_ext_virtual); +REGION_ALIAS("rom_ext_nvm", rom_ext_virtual_usable); INCLUDE sw/device/silicon_creator/rom_ext/rom_ext_common.ld diff --git a/util/topgen/templates/toplevel_memory.ld.tpl b/util/topgen/templates/toplevel_memory.ld.tpl index 7c69ebfce752b..3f1f2e5cca2fc 100644 --- a/util/topgen/templates/toplevel_memory.ld.tpl +++ b/util/topgen/templates/toplevel_memory.ld.tpl @@ -42,18 +42,24 @@ def flags(mem): return flags_str def get_virtual_memory_size(top): - for mod in top["module"]: - if "memory" in mod: - for _, mem in mod["memory"].items(): - if mem["label"] == "eflash" or mem["label"] == "rram": - return hex(int(mem["size"], 0) // 2) - # if no flash_ctrl or rram_ctrl is present, but a ctn memory region is, - # use that size instead - for mod in top["module"]: - if "memory" in mod: - for _, mem in mod["memory"].items(): - if mem["label"] == "ctn": - return hex(0x00100000 // 2) + if lib.has_module_type(top, "rram_ctrl") or lib.has_module_type(top, "flash_ctrl"): + if lib.has_module_type(top, "rram_ctrl"): + label = "rram" + else: + label = "eflash" + for mod in top["module"]: + if "memory" in mod: + for _, mem in mod["memory"].items(): + if mem["label"] == label: + return hex(int(mem["size"], 0) // 2) + else: + # No flash_ctrl or rram_ctrl -- if a ctn memory region is present, + # use that size instead. + for mod in top["module"]: + if "memory" in mod: + for _, mem in mod["memory"].items(): + if mem["label"] == "ctn": + return hex(0x00100000 // 2) return None %>\ From 0578b374c1c81157fa2a4f234d06f2f9d85e1596 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 19 Aug 2026 00:17:09 +0200 Subject: [PATCH 02/24] [sw,linker] reserve nvm slot tail in ottf_silicon_* scripts The ottf_silicon_owner/creator linker script also need to deduct the reserved area to make sure nothing is placed inside this region. Signed-off-by: Michael Gautschi --- .../testing/test_framework/ottf_ld_top_config.ld | 3 +++ .../test_framework/ottf_silicon_creator_a.ld | 12 ++++++++++-- .../test_framework/ottf_silicon_creator_b.ld | 14 +++++++++++--- .../test_framework/ottf_silicon_creator_virtual.ld | 12 ++++++++++-- .../testing/test_framework/ottf_silicon_owner_a.ld | 12 ++++++++++-- .../testing/test_framework/ottf_silicon_owner_b.ld | 12 ++++++++++-- .../test_framework/ottf_silicon_owner_virtual.ld | 11 +++++++++-- 7 files changed, 63 insertions(+), 13 deletions(-) diff --git a/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld b/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld index 732466d0588e5..329dfe584d7ee 100644 --- a/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld +++ b/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld @@ -10,6 +10,9 @@ MEMORY { ctn_ram(rwx) : ORIGIN = ORIGIN(ctn) + 0x1000000, LENGTH = 0x100000 } REGION_ALIAS("ottf_storage", ctn_ram) + +/* Darjeeling has no flash_ctrl/rram_ctrl, so no NVM slot tail to reserve. */ +_nvm_slot_reserved_bytes = 0; #else REGION_ALIAS("ottf_storage", nvm) #endif diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld index a80b494a64135..5e85f1afd0a8f 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld @@ -20,9 +20,17 @@ INCLUDE OPENTITAN_TOP_MEMORY_LD * Symbols to be used in the setup of the address translation for the OTTF run * at the Silicon Creator boot stage in slot A. */ -_ottf_size = LENGTH(ottf_storage) / 2; _ottf_start_address = ORIGIN(ottf_storage); -REGION_ALIAS("ottf_nvm", ottf_storage); +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of Slot A. + */ +MEMORY { + ottf_creator_a(rx) : ORIGIN = _ottf_start_address, + LENGTH = (LENGTH(ottf_storage) / 2) - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_creator_a); + +REGION_ALIAS("ottf_nvm", ottf_creator_a); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld index 9d05b14f8b8f9..329c5ba9d771b 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld @@ -18,9 +18,17 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld * Symbols to be used in the setup of the address translation for the OTTF run * at the Silicon Creator boot stage in slot B. */ -_ottf_size = LENGTH(ottf_storage) / 2; -_ottf_start_address = ORIGIN(ottf_storage) + _ottf_size; +_ottf_start_address = ORIGIN(ottf_storage) + (LENGTH(ottf_storage) / 2); -REGION_ALIAS("ottf_nvm", ottf_storage); +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of Slot B. + */ +MEMORY { + ottf_creator_b(rx) : ORIGIN = _ottf_start_address, + LENGTH = (LENGTH(ottf_storage) / 2) - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_creator_b); + +REGION_ALIAS("ottf_nvm", ottf_creator_b); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld index ee3012341f464..056bc3eff12d3 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld @@ -21,8 +21,16 @@ INCLUDE OPENTITAN_TOP_MEMORY_LD * at the Silicon Creator boot stage in the virtual slot. */ _ottf_start_address = ORIGIN(rom_ext_virtual); -_ottf_size = LENGTH(rom_ext_virtual); -REGION_ALIAS("ottf_nvm", rom_ext_virtual); +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of the physical slot. + */ +MEMORY { + ottf_creator_virtual(rx) : ORIGIN = _ottf_start_address, + LENGTH = LENGTH(rom_ext_virtual) - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_creator_virtual); + +REGION_ALIAS("ottf_nvm", ottf_creator_virtual); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld index 0160672a882a9..829814bfb935f 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld @@ -20,9 +20,17 @@ INCLUDE OPENTITAN_TOP_MEMORY_LD * Symbols to be used in the setup of the address translation for the OTTF run * at the BL0 boot stage in slot A. */ -_ottf_size = (LENGTH(ottf_storage) / 2) - _rom_ext_size; _ottf_start_address = ORIGIN(ottf_storage) + _rom_ext_size; -REGION_ALIAS("ottf_nvm", ottf_storage); +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of Slot A. + */ +MEMORY { + ottf_owner_a(rx) : ORIGIN = _ottf_start_address, + LENGTH = (LENGTH(ottf_storage) / 2) - _rom_ext_size - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_owner_a); + +REGION_ALIAS("ottf_nvm", ottf_owner_a); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld index 585613fc00e22..75c9410ab2277 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld @@ -20,9 +20,17 @@ INCLUDE OPENTITAN_TOP_MEMORY_LD * Symbols to be used in the setup of the address translation for the OTTF run * at the BL0 boot stage in slot B. */ -_ottf_size = (LENGTH(ottf_storage) / 2) - _rom_ext_size; _ottf_start_address = ORIGIN(ottf_storage) + (LENGTH(ottf_storage) / 2) + _rom_ext_size; -REGION_ALIAS("ottf_nvm", ottf_storage); +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of Slot B. + */ +MEMORY { + ottf_owner_b(rx) : ORIGIN = _ottf_start_address, + LENGTH = (LENGTH(ottf_storage) / 2) - _rom_ext_size - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_owner_b); + +REGION_ALIAS("ottf_nvm", ottf_owner_b); INCLUDE ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld index 0a2169d0e6bd5..885b8a03fc214 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld @@ -19,11 +19,18 @@ INCLUDE OPENTITAN_TOP_MEMORY_LD /** * Symbols to be used in the setup of the address translation for ROM_EXT. */ -_ottf_size = LENGTH(owner_virtual) - _rom_ext_size; _ottf_start_address = ORIGIN(owner_virtual) + _rom_ext_size; + +/* + * Leaves `_nvm_slot_reserved_bytes` empty at the end of the physical slot. + */ +MEMORY { + ottf_owner_virtual(rx) : ORIGIN = _ottf_start_address, LENGTH = LENGTH(owner_virtual) - _rom_ext_size - _nvm_slot_reserved_bytes +} +_ottf_size = LENGTH(ottf_owner_virtual); ASSERT((_ottf_size <= (LENGTH(ottf_storage) / 2)), "Error: BL0 NVM is bigger than slot."); -REGION_ALIAS("ottf_nvm", owner_virtual); +REGION_ALIAS("ottf_nvm", ottf_owner_virtual); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld From 1d3a86675e72ec9b76ac193dd759322217567b83 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 13:49:10 +0200 Subject: [PATCH 03/24] [rtl,earlgrey] remove flash_ctrl from earlgrey Signed-off-by: Michael Gautschi --- hw/top_earlgrey/chip_earlgrey_asic.core | 3 - hw/top_earlgrey/chip_earlgrey_cw340.core | 2 - hw/top_earlgrey/chip_earlgrey_verilator.core | 2 - hw/top_earlgrey/data/top_earlgrey.hjson | 89 +++--------------- hw/top_earlgrey/data/xbar_main.hjson | 30 +----- hw/top_earlgrey/dv/chip_sim.core | 1 - hw/top_earlgrey/dv/env/chip_env.core | 3 - hw/top_earlgrey/dv/env/chip_env_pkg.sv | 1 - hw/top_earlgrey/dv/env/chip_if.sv | 33 ------- .../seq_lib/chip_padctrl_attributes_vseq.sv | 91 ------------------- .../chip_sw_all_escalation_resets_vseq.sv | 4 - .../chip_sw_flash_host_gnt_err_inj_vseq.sv | 24 ----- .../dv/env/seq_lib/chip_vseq_list.sv | 1 - .../top_earlgrey_error_injection_ifs_bind.sv | 4 +- hw/top_earlgrey/dv/tb/chip_hier_macros.svh | 10 -- hw/top_earlgrey/dv/tb/tb.sv | 55 ----------- .../lint/top_earlgrey_dv_lint_cfgs.hjson | 6 -- .../lint/top_earlgrey_lint_cfgs.hjson | 6 -- hw/top_earlgrey/rtl/pad_orient_pkg.sv | 3 - hw/top_earlgrey/rtl/scan_role_pkg.sv | 3 - hw/top_earlgrey/templates/chiplevel.sv.tpl | 28 +++--- .../templates/earlgrey_pd_main.sv.tpl | 6 -- hw/top_earlgrey/top_earlgrey.core | 3 - 23 files changed, 29 insertions(+), 379 deletions(-) delete mode 100644 hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_host_gnt_err_inj_vseq.sv diff --git a/hw/top_earlgrey/chip_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core index dbf5c7d3de11b..7409ae1011f2f 100644 --- a/hw/top_earlgrey/chip_earlgrey_asic.core +++ b/hw/top_earlgrey/chip_earlgrey_asic.core @@ -10,17 +10,14 @@ filesets: - lowrisc:systems:top_earlgrey:0.1 - lowrisc:systems:top_earlgrey_pkg - lowrisc:systems:top_earlgrey_padring - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top - "fileset_partner ? (partner:systems:top_earlgrey_ast)" - "fileset_partner ? (partner:systems:top_earlgrey_pad_orient_pkg)" - "fileset_partner ? (partner:systems:top_earlgrey_scan_role_pkg)" - "fileset_partner ? (partner:prim_tech:all)" - - "fileset_partner ? (partner:prim_tech:flash)" - "!fileset_partner ? (lowrisc:systems:top_earlgrey_ast)" - "!fileset_partner ? (lowrisc:earlgrey_systems:pad_orient_pkg)" - "!fileset_partner ? (lowrisc:earlgrey_systems:scan_role_pkg)" - "!fileset_partner ? (lowrisc:prim_generic:all)" - - "!fileset_partner ? (lowrisc:prim_generic:flash)" files: - rtl/autogen/chip_earlgrey_asic.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core index 21fcd5e527197..ae535a1da485d 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw340.core +++ b/hw/top_earlgrey/chip_earlgrey_cw340.core @@ -13,9 +13,7 @@ filesets: - lowrisc:systems:top_earlgrey_padring - lowrisc:earlgrey_systems:pad_orient_pkg - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top - lowrisc:prim_xilinx_ultrascale:all - - lowrisc:prim_generic:flash - lowrisc:ip:bkdr_loader files: - rtl/clkgen_xil_ultrascale.sv diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core index e65afe8a465f5..f608c066c8c9d 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.core +++ b/hw/top_earlgrey/chip_earlgrey_verilator.core @@ -14,9 +14,7 @@ filesets: - lowrisc:systems:top_earlgrey_ast - lowrisc:earlgrey_systems:pad_orient_pkg - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top - lowrisc:prim_generic:all - - lowrisc:prim_generic:flash files: - rtl/padring_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index be3e4821e7920..089eb4e5de0c9 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -202,7 +202,7 @@ { name: "mmio", desc: ''' MMIO region excludes any memory that is separate from the module configuration - space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device + space, i.e. ROM, main SRAM, and RRAM are excluded but retention SRAM, spi_device memory, or usbdev memory are included. ''' nodes: [ @@ -232,8 +232,6 @@ "ast", "sensor_ctrl", "sram_ctrl_ret", - "flash_ctrl.core", - "flash_ctrl.prim", "rram_ctrl.core" "rram_macro.prim" "rv_plic", @@ -754,37 +752,6 @@ } } }, - { name: "flash_ctrl", - type: "flash_ctrl", - template_type: "flash_ctrl", - clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, - clock_group: "infra", - reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, - base_addrs: { - core: {hart: "0x41000000"}, - prim: {hart: "0x41008000"}, - mem: {hart: "0x20000000"} - } - param_decl: { - ProgFifoDepth: "4", - }, - memory: { - mem: { - label: "eflash", - swaccess: "ro", - data_intg_passthru: "true", - exec: "True", - byte_write: "False", - config: { - type: "flash", - banks: 2, - pages_per_bank: 256, - program_resolution: 8, // maximum number of flash words allowed to program at one time - } - } - }, - attr: "ipgen", - }, { name: "rram_ctrl", type: "rram_ctrl", clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, @@ -1147,11 +1114,10 @@ // requester: [ resp1, resp2, ... ], // // the field and value should be module_inst.port_name - // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] + // e.g csrng.csrng_cmd: ['edn0.csrng_cmd', 'edn1.csrng_cmd'] inter_module: { 'connect': { - 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl', - 'rram_macro.obs_ctrl'], + 'ast.obs_ctrl' : ['rram_macro.obs_ctrl'], 'alert_handler.crashdump' : ['rstmgr.alert_dump'], 'alert_handler.esc_rx' : ['rv_core_ibex.esc_rx', 'lc_ctrl.esc_scrap_state0_rx', @@ -1165,7 +1131,7 @@ 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'], 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'], 'rram_ctrl.otp_key' : ['otp_ctrl.nvm_otp_key'], - 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed', 'rram_ctrl.rma_seed'], + 'lc_ctrl.lc_nvm_rma_seed' : ['rram_ctrl.rma_seed'], 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', 'sram_ctrl_sec.sram_otp_key', 'sram_ctrl_ret.sram_otp_key', @@ -1183,9 +1149,9 @@ 'rom_ctrl.keymgr_data' : ['keymgr_dpe.rom_digest'], 'alert_handler.crashdump' : ['rstmgr.alert_dump'], - // LC RMA req/ack interface: LC --> Flash -> LC + // LC RMA req/ack interface: LC --> RRAM -> LC // |-> OTBN -> LC - 'lc_ctrl.lc_nvm_rma_req' : ['flash_ctrl.rma_req', 'otbn.lc_rma_req', 'rram_ctrl.rma_req'], + 'lc_ctrl.lc_nvm_rma_req' : ['otbn.lc_rma_req', 'rram_ctrl.rma_req'], 'lc_ctrl.lc_nvm_rma_ack' : ['rram_ctrl.rma_ack', 'otbn.lc_rma_ack'], // usbdev connection to pinmux @@ -1247,8 +1213,7 @@ 'pwrmgr.lc_dft_en', 'rv_dm.lc_dft_en' ], - 'lc_ctrl.lc_nvm_debug_en' : ['flash_ctrl.lc_nvm_debug_en', - 'rram_macro.lc_nvm_debug_en'], + 'lc_ctrl.lc_nvm_debug_en' : ['rram_macro.lc_nvm_debug_en'], 'lc_ctrl.lc_hw_debug_clr' : ['pinmux.lc_hw_debug_clr', 'rv_dm.lc_hw_debug_clr'], 'lc_ctrl.lc_init_done' : ['rv_dm.lc_init_done'], @@ -1269,7 +1234,6 @@ 'sram_ctrl_sec.lc_escalate_en', 'sram_ctrl_ret.lc_escalate_en', 'aon_timer.lc_escalate_en', - 'flash_ctrl.lc_escalate_en', 'rram_ctrl.lc_escalate_en', 'pinmux.lc_escalate_en'], @@ -1280,16 +1244,11 @@ // LC access control signal broadcast 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['otp_ctrl.lc_creator_seed_sw_rw_en', - 'flash_ctrl.lc_creator_seed_sw_rw_en', 'rram_ctrl.lc_creator_seed_sw_rw_en'], - 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['flash_ctrl.lc_owner_seed_sw_rw_en', - 'rram_ctrl.lc_owner_seed_sw_rw_en'], - 'lc_ctrl.lc_iso_part_sw_rd_en' : ['flash_ctrl.lc_iso_part_sw_rd_en', - 'rram_ctrl.lc_iso_part_sw_rd_en'], - 'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en', - 'rram_ctrl.lc_iso_part_sw_wr_en'], + 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['rram_ctrl.lc_owner_seed_sw_rw_en'], + 'lc_ctrl.lc_iso_part_sw_rd_en' : ['rram_ctrl.lc_iso_part_sw_rd_en'], + 'lc_ctrl.lc_iso_part_sw_wr_en' : ['rram_ctrl.lc_iso_part_sw_wr_en'], 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en', - 'flash_ctrl.lc_seed_hw_rd_en', 'rram_ctrl.lc_seed_hw_rd_en'], 'lc_ctrl.lc_rma_state' : ['otp_ctrl.lc_rma_state'], @@ -1345,11 +1304,6 @@ // hardwired connections 'rv_core_ibex.hart_id', 'rv_core_ibex.boot_addr', - // Xbars - - // Temporary RRAM helpers - 'flash_ctrl.otp', - // Pinmux JTAG signals for the tool-inserted DFT TAP 'pinmux.dft_jtag', @@ -1402,12 +1356,6 @@ 'clkmgr.hi_speed_sel' : 'hi_speed_sel', 'clkmgr.div_step_down_req' : 'div_step_down_req', 'clkmgr.calib_rdy' : 'calib_rdy', - 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable', - 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', - 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', - 'flash_ctrl.flash_test_mode_a' : 'flash_test_mode_a', - 'flash_ctrl.flash_test_voltage_h' : 'flash_test_voltage_h', - 'flash_ctrl.fla_obs' : 'flash_obs', 'entropy_src.entropy_src_rng_enable' : 'es_rng_enable', 'entropy_src.entropy_src_rng_valid' : 'es_rng_valid', 'entropy_src.entropy_src_rng_bits' : 'es_rng_bit', @@ -1500,9 +1448,6 @@ { name: 'USB_N' , type: 'DualBidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB N signal'}, { name: 'CC1' , type: 'BidirTol', bank: 'AVCC', connection: 'manual', desc: 'ADC input 1', port_type: '`INOUT_AI'}, { name: 'CC2' , type: 'BidirTol', bank: 'AVCC', connection: 'manual', desc: 'ADC input 2', port_type: '`INOUT_AI'}, - { name: 'FLASH_TEST_VOLT' , type: 'AnalogIn0', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'}, - { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, - { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, { name: 'RRAM_ANALOG' , type: 'AnalogIn0', bank: 'VCC' , connection: 'manual', desc: 'RRAM analog test signal'}, // Dedicated IOs { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, @@ -1639,7 +1584,6 @@ { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''}, { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "rram_macro", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "sensor_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, // Sysrst ctrl has both muxed and dedicated IOs @@ -1689,8 +1633,6 @@ 'clkmgr.calib_rdy' : { signal: 'ast_init_done' }, 'clkmgr.cg_en' : { unused: true }, 'rstmgr.rst_en' : { unused: true }, - 'flash_ctrl.flash_test_mode_a' : { signal: "{FLASH_TEST_MODE1, FLASH_TEST_MODE0}"}, - 'flash_ctrl.flash_test_voltage_h' : { signal: 'FLASH_TEST_VOLT' }, 'rram_macro.rram_test_analog' : { signal: 'RRAM_ANALOG' }, 'sensor_ctrl.ast_alert' : { signal: 'ast_alert' }, 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, @@ -1773,7 +1715,7 @@ // padring_verilator module. Most signals therefore flow through the // common (shared with ASIC) path, except: // - the USB tx signals, which are observed by the usbdpi model - // - the flash/OTP IO (bidir) test pads + // - the OTP IO (bidir) test pad chiplevel: { port_overrides: { 'ast.lc_dft_en' : { signal: 'lc_dft_en' }, @@ -1783,8 +1725,6 @@ // These are inout pads on the ASIC; the verilator target has no pads, // so leave them open (empty connection) rather than tying them off // ('0 on a multi-bit inout is rejected by Verilator). - 'flash_ctrl.flash_test_mode_a' : { unused: true, tie_value: "" }, - 'flash_ctrl.flash_test_voltage_h' : { unused: true, tie_value: "" }, 'rram_macro.rram_test_analog' : { unused: true, tie_value: "" }, 'sensor_ctrl.ast_alert' : { signal: 'ast_alert' }, 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, @@ -1855,10 +1795,6 @@ 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, 'entropy_src.rng_fips' : { unused: true }, 'rram_macro.rram_test_analog' : { unused: true }, - 'flash_ctrl.flash_test_mode_a' : { unused: true }, - 'flash_ctrl.flash_test_voltage_h' : { unused: true }, - 'flash_ctrl.flash_power_down_h' : { unused: true }, - 'flash_ctrl.flash_power_ready_h' : { unused: true, tie_value: "1'b1" }, } } @@ -1866,8 +1802,7 @@ remove_ports: [], remove_pads: [ 'CC1', 'CC2', - 'FLASH_TEST_VOLT', 'RRAM_ANALOG', - 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', + 'RRAM_ANALOG', 'USB_P', 'USB_N' ], diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 0943a4af00c87..90286fed9da6e 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson @@ -20,7 +20,7 @@ // For device interfaces, especially configuration registers, latency is // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline // true. - // For device accesses to memories (ram / rom / flash / rram), performance is a concern, + // For device accesses to memories (ram / rom / rram), performance is a concern, // so use pipeline false where permissible by timing. If not, find a combination // that works. nodes: [ @@ -102,29 +102,6 @@ req_fifo_pass: false, rsp_fifo_pass: false, }, - { name: "flash_ctrl.core", - type: "device", - clock: "clk_main_i", - reset: "rst_main_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "flash_ctrl.prim", - type: "device", - clock: "clk_main_i", - reset: "rst_main_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - // Return and examine whether this path - // latency can be improved. - { name: "flash_ctrl.mem", - type: "device", - clock: "clk_main_i", - reset: "rst_main_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - }, { name: "rram_ctrl.core", type: "device", clock: "clk_main_i", @@ -252,13 +229,11 @@ }, ], connections: { - rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", - "flash_ctrl.mem", "rram_ctrl.host" + rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "rram_ctrl.host" ], rv_core_ibex.cored: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "peri", "spi_host0", "spi_host1", "usbdev", - "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "rram_ctrl.core", "rram_ctrl.host", "rram_macro.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", "sram_ctrl_sec.regs", @@ -267,7 +242,6 @@ rv_dm.sba: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "peri", "spi_host0", "spi_host1", "usbdev", - "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "rram_ctrl.core", "rram_ctrl.host", "rram_macro.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", "sram_ctrl_sec.regs", diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index c088873b60ca5..3d40ae650425e 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -32,7 +32,6 @@ filesets: - lowrisc:dv:sim_sram - lowrisc:dv:sw_test_status - lowrisc:dv:sw_logger_if - - lowrisc:earlgrey_dv:flash_ctrl_bkdr_util - lowrisc:dv:rom_ctrl_bkdr_util - lowrisc:dv:sram_ctrl_bkdr_util - lowrisc:dv_dpi_c:gpiodpi diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index be5ba3246972d..c799e57fdbc0f 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -21,7 +21,6 @@ filesets: - lowrisc:dv:jtag_riscv_agent - lowrisc:dv:jtag_dmi_agent - lowrisc:dv:lc_ctrl_dv_utils - - lowrisc:earlgrey_dv:flash_ctrl_bkdr_util - lowrisc:dv:rram_ctrl_bkdr_util - lowrisc:earlgrey_dv:otp_ctrl_mem_bkdr_util - lowrisc:dv:spi_agent @@ -135,7 +134,6 @@ filesets: - seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_rv_core_ibex_icache_invalidate_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_aes_masking_off_vseq.sv: {is_include_file: true} - - seq_lib/chip_sw_flash_host_gnt_err_inj_vseq.sv: {is_include_file: true} - seq_lib/chip_padctrl_attributes_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv: {is_include_file: true} @@ -158,7 +156,6 @@ filesets: - ast_supply_if.sv - pwrmgr_low_power_if.sv - rstmgr_cnsty_fault_if.sv - - flash_ctrl_host_gnt_fault_if.sv - tb_dpi_if.sv - top_earlgrey_error_injection_ifs_bind.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/dv/env/chip_env_pkg.sv b/hw/top_earlgrey/dv/env/chip_env_pkg.sv index 06569e14361d6..a025e4e104d51 100644 --- a/hw/top_earlgrey/dv/env/chip_env_pkg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_pkg.sv @@ -35,7 +35,6 @@ package chip_env_pkg; import lc_ctrl_state_pkg::*; import lc_ctrl_token_pkg::*; import lc_ctrl_dv_utils_pkg::*; - import flash_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import rom_ctrl_bkdr_util_pkg::*; import sram_ctrl_bkdr_util_pkg::*; diff --git a/hw/top_earlgrey/dv/env/chip_if.sv b/hw/top_earlgrey/dv/env/chip_if.sv index 3e2fa0662d931..948968e8e86f8 100644 --- a/hw/top_earlgrey/dv/env/chip_if.sv +++ b/hw/top_earlgrey/dv/env/chip_if.sv @@ -53,7 +53,6 @@ interface chip_if; `define CSRNG_HIER `PD_MAIN_HIER.u_csrng `define ENTROPY_SRC_HIER `PD_MAIN_HIER.u_entropy_src `define EDN_HIER(i) `PD_MAIN_HIER.u_edn``i -`define FLASH_CTRL_HIER `PD_MAIN_HIER.u_flash_ctrl `define RRAM_CTRL_HIER `PD_MAIN_HIER.u_rram_ctrl `define RRAM_MACRO_HIER `PD_MAIN_HIER.u_rram_macro `define GPIO_HIER `PD_MAIN_HIER.u_gpio @@ -195,16 +194,6 @@ interface chip_if; .pins(dios[top_earlgrey_pkg::DioPadCc2:top_earlgrey_pkg::DioPadCc1]) ); - // Functional (dedicated) interface (analog input): flash test volt. - pins_if #(.Width(1), .PullStrength("Weak")) flash_test_volt_if( - .pins(dios[top_earlgrey_pkg::DioPadFlashTestVolt]) - ); - - // Functional (dedicated) interface (input): flash test mode0. - pins_if #(.Width(2), .PullStrength("Weak")) flash_test_mode_if( - .pins(dios[top_earlgrey_pkg::DioPadFlashTestMode1:top_earlgrey_pkg::DioPadFlashTestMode0]) - ); - // Functional (dedicated) interface: SPI host interface (drives traffic into the chip). bit enable_spi_host = 1; bit enable_spi_tpm; @@ -451,22 +440,6 @@ interface chip_if; end endfunction - // Functional (muxed) interface: Flash controller JTAG. - bit enable_flash_ctrl_jtag, flash_ctrl_jtag_enabled; - jtag_if flash_ctrl_jtag_if(); - - // TODO: Revisit this logic. - wire lc_hw_debug_en = (`LC_CTRL_HIER.lc_hw_debug_en_o == lc_ctrl_pkg::On); - assign flash_ctrl_jtag_enabled = enable_flash_ctrl_jtag && lc_hw_debug_en; - assign mios[top_earlgrey_pkg::MioPadIob0] = flash_ctrl_jtag_enabled ? - flash_ctrl_jtag_if.tms : 1'bz; - assign flash_ctrl_jtag_if.tdo = flash_ctrl_jtag_enabled ? - mios[top_earlgrey_pkg::MioPadIob1] : 1'bz; - assign mios[top_earlgrey_pkg::MioPadIob2] = flash_ctrl_jtag_enabled ? - flash_ctrl_jtag_if.tdi : 1'bz; - assign mios[top_earlgrey_pkg::MioPadIob3] = flash_ctrl_jtag_enabled ? - flash_ctrl_jtag_if.tck : 1'bz; - // Functional (muxed) interface: AST2PAD. pins_if #(.Width(9), .PullStrength("Weak")) ast2pad_if( .pins({mios[top_earlgrey_pkg::MioPadIoa0], mios[top_earlgrey_pkg::MioPadIoa1], @@ -638,7 +611,6 @@ interface chip_if; wire sram_main_init_done = `SRAM_CTRL_MAIN_HIER.u_reg_regs.u_status_init_done.qs[0:0]; wire sram_ret_init_done = `SRAM_CTRL_RET_HIER.u_reg_regs.u_status_init_done.qs[0:0]; - wire flash_core1_host_req = 0; `else wire rom_ctrl_done = `PWRMGR_HIER.rom_ctrl_i[0].done == prim_mubi_pkg::MuBi4True; wire rom_ctrl_good = `PWRMGR_HIER.rom_ctrl_i[0].good == prim_mubi_pkg::MuBi4True; @@ -649,7 +621,6 @@ interface chip_if; wire sram_main_init_done = `SRAM_CTRL_MAIN_HIER.u_reg_regs.status_init_done_qs; wire sram_ret_init_done = `SRAM_CTRL_RET_HIER.u_reg_regs.status_init_done_qs; - wire flash_core1_host_req = `FLASH_CTRL_HIER.u_eflash.gen_flash_cores[1].u_core.host_req_i; `endif wire adc_data_valid = `AST_HIER.u_ast_aon.u_adc.adc_d_val_o; wire rram_rd_buf_rdy = ~((|`RRAM_CTRL_HIER.u_rram_phy.u_rram_phy_rd.buf_valid) || @@ -961,8 +932,6 @@ interface chip_if; if (disconnect_default_pulls) dios_if.disconnect(); mios_if.disconnect(); cc_if.disconnect(); - flash_test_volt_if.disconnect(); - flash_test_mode_if.disconnect(); ec_rst_l_if.disconnect(); flash_wp_l_if.disconnect(); pwrb_in_if.disconnect(); @@ -971,7 +940,6 @@ interface chip_if; tap_straps_if.disconnect(); sw_straps_if.disconnect(); gpios_if.disconnect(); - enable_flash_ctrl_jtag = 0; ast2pad_if.disconnect(); pad2ast_if.disconnect(); pinmux_wkup_if.disconnect(); @@ -1281,7 +1249,6 @@ assign spi_host_1_state = {tb.dut.top_earlgrey.earlgrey_pd_main.u_spi_host1.u_sp `undef CSRNG_HIER `undef ENTROPY_SRC_HIER `undef EDN_HIER -`undef FLASH_CTRL_HIER `undef GPIO_HIER `undef HMAC_HIER `undef I2C_HIER diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv index 9e297bd552e35..e3a31bb08510a 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_padctrl_attributes_vseq.sv @@ -210,8 +210,6 @@ class chip_padctrl_attributes_vseq extends chip_stub_cpu_base_vseq; // all tests asserting a reset. begin : manual_dio_test // Make sure nothing drives these pins before testing the pull values. - cfg.chip_vif.flash_test_mode_if.disconnect(); - cfg.chip_vif.flash_test_volt_if.disconnect(); cfg.chip_vif.cc_if.disconnect(); cfg.chip_vif.io_div4_clk_rst_if.wait_clks(1); check_manual_dios_pull(); @@ -611,10 +609,6 @@ class chip_padctrl_attributes_vseq extends chip_stub_cpu_base_vseq; task check_manual_dios_pull(); string obs_strength; - // Pad `FLASH_TEST_VOLT` is always high impedance. - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_volt_if.pins[0]); - `DV_CHECK_STREQ(obs_strength, "HiZ", "on FLASH_TEST_VOLT") - // The other four manual pads are high impedance unless their pull-up/down is activated. // CC1 ----------------------------------------------------------------------------------------- @@ -689,77 +683,6 @@ class chip_padctrl_attributes_vseq extends chip_stub_cpu_base_vseq; `DV_CHECK_STREQ(obs_strength, "HiZ", "on CC2") // --------------------------------------------------------------------------------------------- - // FLASH_TEST_MODE0 ---------------------------------------------------------------------------- - // - pull disabled (post-reset configuration) - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[0]); - `DV_CHECK_STREQ(obs_strength, "HiZ", "on FLASH_TEST_MODE0") - // - pull-down - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[2].pull_select), .value(1'b0), .blocking(1), - .predict(1)); - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[2].pull_en), .value(1'b1), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[0]); -`ifdef VCS - // TODO(#18988): Drive strength seems to be reported incorrectly by VCS. - `DV_CHECK_STREQ(obs_strength, "St0", "on FLASH_TEST_MODE0") -`else - `DV_CHECK_STREQ(obs_strength, "We0", "on FLASH_TEST_MODE0") -`endif - // - pull-up - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[2].pull_select), .value(1'b1), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[0]); -`ifdef VCS - // TODO(#18988): Drive strength seems to be reported incorrectly by VCS. - `DV_CHECK_STREQ(obs_strength, "St1", "on FLASH_TEST_MODE0") -`else - `DV_CHECK_STREQ(obs_strength, "We1", "on FLASH_TEST_MODE0") -`endif - // - pull disabled - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[2].pull_en), .value(1'b0), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[0]); - `DV_CHECK_STREQ(obs_strength, "HiZ", "on FLASH_TEST_MODE0") - // --------------------------------------------------------------------------------------------- - - // FLASH_TEST_MODE1 ---------------------------------------------------------------------------- - // - pull disabled (post-reset configuration) - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[1]); - `DV_CHECK_STREQ(obs_strength, "HiZ", "on FLASH_TEST_MODE1") - // - pull-down - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[3].pull_select), .value(1'b0), .blocking(1), - .predict(1)); - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[3].pull_en), .value(1'b1), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[1]); -`ifdef VCS - // TODO(#18988): Drive strength seems to be reported incorrectly by VCS. - `DV_CHECK_STREQ(obs_strength, "St0", "on FLASH_TEST_MODE1") -`else - `DV_CHECK_STREQ(obs_strength, "We0", "on FLASH_TEST_MODE1") -`endif - // - pull-up - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[3].pull_select), .value(1'b1), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[1]); -`ifdef VCS - // TODO(#18988): Drive strength seems to be reported incorrectly by VCS. - `DV_CHECK_STREQ(obs_strength, "St1", "on FLASH_TEST_MODE1") -`else - `DV_CHECK_STREQ(obs_strength, "We1", "on FLASH_TEST_MODE1") -`endif - // - pull disabled - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[3].pull_en), .value(1'b0), .blocking(1), - .predict(1)); - #(cfg.pad_pull_delay * 1ns); - obs_strength = $sformatf("%v", cfg.chip_vif.flash_test_mode_if.pins[1]); - `DV_CHECK_STREQ(obs_strength, "HiZ", "on FLASH_TEST_MODE1") - // --------------------------------------------------------------------------------------------- endtask function logic hdl_read_lsb(string path); @@ -790,20 +713,6 @@ class chip_padctrl_attributes_vseq extends chip_stub_cpu_base_vseq; act = hdl_read_lsb("tb.dut.manual_in_cc2"); `DV_CHECK_CASE_EQ(lsb_exp_val, act) - cfg.chip_vif.flash_test_mode_if.drive('1); - cfg.chip_vif.io_div4_clk_rst_if.wait_clks(1); - act = hdl_read_lsb("tb.dut.manual_in_flash_test_mode0"); - `DV_CHECK_CASE_EQ(1'b1, act) - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[2].input_disable), .value(1'b1), .blocking(1), - .predict(1)); - act = hdl_read_lsb("tb.dut.manual_in_flash_test_mode0"); - `DV_CHECK_CASE_EQ(lsb_exp_val, act) - act = hdl_read_lsb("tb.dut.manual_in_flash_test_mode1"); - `DV_CHECK_CASE_EQ(1'b1, act) - csr_wr(.ptr(ral.sensor_ctrl.manual_pad_attr[3].input_disable), .value(1'b1), .blocking(1), - .predict(1)); - act = hdl_read_lsb("tb.dut.manual_in_flash_test_mode1"); - `DV_CHECK_CASE_EQ(lsb_exp_val, act) endtask endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index 7191fe9075cc6..85dcdf1d7e325 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -31,11 +31,7 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; '{"edn0", "", TopEarlgreyAlertIdEdn0FatalAlert}, '{"edn1", "", TopEarlgreyAlertIdEdn1FatalAlert}, '{"entropy_src", "", TopEarlgreyAlertIdEntropySrcFatalAlert}, - '{"flash_ctrl", "", TopEarlgreyAlertIdFlashCtrlFatalStdErr}, '{"rram_ctrl", "", TopEarlgreyAlertIdRramCtrlFatalStdErr}, - // test u_eflash.u_flash alert TopEarlgreyAlertIdFlashCtrlFatalErr is implemented in the - // `chip_sw_flash_host_gnt_err_inj_vseq` sequence. - '{"flash_ctrl*.u_flash", "", TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert}, '{"rram_macro", "", TopEarlgreyAlertIdRramCtrlFatalMacroErr}, '{"gpio", "", TopEarlgreyAlertIdGpioFatalFault}, '{"hmac", "", TopEarlgreyAlertIdHmacFatalFault}, diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_host_gnt_err_inj_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_host_gnt_err_inj_vseq.sv deleted file mode 100644 index c16656df78afd..0000000000000 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_host_gnt_err_inj_vseq.sv +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This sequence waits for a host request from flash_core bank1, -// then force flash_part to 'info_partition' to assert the host_grant error. -class chip_sw_flash_host_gnt_err_inj_vseq extends chip_sw_fault_base_vseq; - `uvm_object_utils(chip_sw_flash_host_gnt_err_inj_vseq) - `uvm_object_new - - function void set_fault_parameters(); - if_path = "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.gen_flash_cores[1].u_core"; - alert_id = TopEarlgreyAlertIdFlashCtrlFatalErr; - endfunction - - task wait_event(); - int polling_timeout_ns = 1_000_000; - `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest) - `DV_SPINWAIT(wait(cfg.chip_vif.flash_core1_host_req == 1);, - "wait for core1_host_req is timed out", - polling_timeout_ns) - `uvm_info(`gfn, "polling is done", UVM_MEDIUM) - endtask -endclass // chip_sw_flash_host_gnt_err_inj_vseq diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv index 9a51cf1ef2dbb..b4188a8dc0afb 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv @@ -91,7 +91,6 @@ `include "chip_sw_exit_test_unlocked_bootstrap_vseq.sv" `include "chip_sw_spi_device_tpm_vseq.sv" `include "chip_sw_aes_masking_off_vseq.sv" -`include "chip_sw_flash_host_gnt_err_inj_vseq.sv" `include "chip_padctrl_attributes_vseq.sv" `include "chip_sw_rom_e2e_base_vseq.sv" `include "chip_sw_rom_e2e_shutdown_exception_c_vseq.sv" diff --git a/hw/top_earlgrey/dv/env/top_earlgrey_error_injection_ifs_bind.sv b/hw/top_earlgrey/dv/env/top_earlgrey_error_injection_ifs_bind.sv index 2df6e60cd592d..8e48895199cae 100644 --- a/hw/top_earlgrey/dv/env/top_earlgrey_error_injection_ifs_bind.sv +++ b/hw/top_earlgrey/dv/env/top_earlgrey_error_injection_ifs_bind.sv @@ -10,8 +10,6 @@ module top_earlgrey_error_injection_ifs_bind; prim_count_if(.*); // This is used to inject reset consistency errors in rstmgr. bind rstmgr_leaf_rst rstmgr_cnsty_fault_if rstmgr_cnsty_fault_if (.*); - // This is used to inject host_gnt error in flash_ctrl. - bind tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.gen_flash_cores[1].u_core - flash_ctrl_host_gnt_fault_if flash_ctrl_host_gnt_fault_if (.*); + `endif endmodule diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index fd6cedd893670..b0cc996cb5d70 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -13,7 +13,6 @@ `define CPU_HIER `PD_MAIN_HIER.u_rv_core_ibex `define CPU_CORE_HIER `CPU_HIER.u_core `define CPU_TL_ADAPT_D_HIER `CPU_HIER.tl_adapter_host_d_ibex -`define EFLASH_HIER `PD_MAIN_HIER.u_flash_ctrl.u_eflash.u_flash `define RRAM_MACRO_HIER `PD_MAIN_HIER.u_rram_macro `define GPIO_HIER `PD_MAIN_HIER.u_gpio `define KEYMGR_DPE_HIER `PD_MAIN_HIER.u_keymgr_dpe @@ -39,16 +38,7 @@ `endif // Memory hierarchies. -// TODO: Temporarily only reference info type0 of the info partitions in flash. In the future, this -// needs to be upgraded to support all info types. `define MEM_ARRAY_SUB mem -`define EFLASH_GENERIC_HIER `EFLASH_HIER -`define FLASH_BANK0_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[0].u_prim_flash_bank -`define FLASH_BANK1_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[1].u_prim_flash_bank -`define FLASH0_DATA_MEM_HIER `FLASH_BANK0_HIER.u_mem.`MEM_ARRAY_SUB -`define FLASH0_INFO_MEM_HIER `FLASH_BANK0_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB -`define FLASH1_DATA_MEM_HIER `FLASH_BANK1_HIER.u_mem.`MEM_ARRAY_SUB -`define FLASH1_INFO_MEM_HIER `FLASH_BANK1_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB `define RRAM_DATA_MEM_HIER `RRAM_MACRO_HIER.u_data_array.`MEM_ARRAY_SUB `define RRAM_INFO_MEM_HIER `RRAM_MACRO_HIER.u_info_array.`MEM_ARRAY_SUB `define ICACHE_WAY0_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[0].gen_scramble_rams diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv index 1d020295a62a4..e4a79c486b02b 100644 --- a/hw/top_earlgrey/dv/tb/tb.sv +++ b/hw/top_earlgrey/dv/tb/tb.sv @@ -13,7 +13,6 @@ module tb; import top_earlgrey_pkg::*; import chip_test_pkg::*; import xbar_test_pkg::*; - import flash_ctrl_bkdr_util_pkg::*; import rram_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import rom_ctrl_bkdr_util_pkg::*; @@ -125,9 +124,6 @@ module tb; .CC1(dut.chip_if.dios[top_earlgrey_pkg::DioPadCc1]), .CC2(dut.chip_if.dios[top_earlgrey_pkg::DioPadCc2]), `endif - .FLASH_TEST_VOLT(dut.chip_if.dios[top_earlgrey_pkg::DioPadFlashTestVolt]), - .FLASH_TEST_MODE0(dut.chip_if.dios[top_earlgrey_pkg::DioPadFlashTestMode0]), - .FLASH_TEST_MODE1(dut.chip_if.dios[top_earlgrey_pkg::DioPadFlashTestMode1]), .SPI_HOST_D0(dut.chip_if.dios[top_earlgrey_pkg::DioPadSpiHostD0]), .SPI_HOST_D1(dut.chip_if.dios[top_earlgrey_pkg::DioPadSpiHostD1]), .SPI_HOST_D2(dut.chip_if.dios[top_earlgrey_pkg::DioPadSpiHostD2]), @@ -573,7 +569,6 @@ module tb; // variables first. rram_ctrl_bkdr_util data, info; rram_ctrl_otp_bkdr_util otp; - flash_ctrl_bkdr_util data0, info0, data1, info1; sram_ctrl_bkdr_util ram_main0, ram_ret0; rom_ctrl_bkdr_util rom; chip_mem_e mem; @@ -604,54 +599,6 @@ module tb; m_mem_bkdr_util[RramInfo] = info; `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RramInfo], `RRAM_INFO_MEM_HIER) - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for flash 0 data", UVM_MEDIUM) - data0 = new( - .name ("mem_bkdr_util[FlashBank0Data]"), - .path (`DV_STRINGIFY(`FLASH0_DATA_MEM_HIER)), - .depth ($size(`FLASH0_DATA_MEM_HIER)), - .n_bits($bits(`FLASH0_DATA_MEM_HIER)), - .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68), - .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR)); - m_mem_bkdr_util[FlashBank0Data] = data0; - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank0Data], `FLASH0_DATA_MEM_HIER) - - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for flash 0 info", UVM_MEDIUM) - info0 = new( - .name ("mem_bkdr_util[FlashBank0Info]"), - .path (`DV_STRINGIFY(`FLASH0_INFO_MEM_HIER)), - .depth ($size(`FLASH0_INFO_MEM_HIER)), - .n_bits($bits(`FLASH0_INFO_MEM_HIER)), - .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68), - .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR)); - m_mem_bkdr_util[FlashBank0Info] = info0; - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank0Info], `FLASH0_INFO_MEM_HIER) - - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for flash 1 data", UVM_MEDIUM) - data1 = new( - .name ("mem_bkdr_util[FlashBank1Data]"), - .path (`DV_STRINGIFY(`FLASH1_DATA_MEM_HIER)), - .depth ($size(`FLASH1_DATA_MEM_HIER)), - .n_bits($bits(`FLASH1_DATA_MEM_HIER)), - .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68), - .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / - flash_ctrl_top_specific_pkg::NumBanks)); - m_mem_bkdr_util[FlashBank1Data] = data1; - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank1Data], `FLASH1_DATA_MEM_HIER) - - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for flash 1 info", UVM_MEDIUM) - info1 = new( - .name ("mem_bkdr_util[FlashBank1Info]"), - .path (`DV_STRINGIFY(`FLASH1_INFO_MEM_HIER)), - .depth ($size(`FLASH1_INFO_MEM_HIER)), - .n_bits($bits(`FLASH1_INFO_MEM_HIER)), - .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68), - .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / - flash_ctrl_top_specific_pkg::NumBanks)); - m_mem_bkdr_util[FlashBank1Info] = info1; - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank1Info], `FLASH1_INFO_MEM_HIER) - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for I cache way 0 tag", UVM_MEDIUM) m_mem_bkdr_util[ICacheWay0Tag] = new( .name ("mem_bkdr_util[ICacheWay0Tag]"), @@ -815,7 +762,6 @@ module tb; // See chip_padctrl_attributes_vseq for more details. forever @dut.chip_if.chip_padctrl_attributes_test_sva_disable begin if (dut.chip_if.chip_padctrl_attributes_test_sva_disable) begin - $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_gpio); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c0); @@ -832,7 +778,6 @@ module tb; $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_uart3); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_usbdev); end else begin - $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_gpio); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c0); diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson index 9add075350dae..ced30edba1988 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson @@ -66,12 +66,6 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" rel_path: "hw/ip/edn/dv/lint/{tool}" }, - { name: flash_ctrl - fusesoc_core: lowrisc:earlgrey_dv:flash_ctrl_sim - import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" - rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/dv/lint/{tool}" - }, { name: gpio fusesoc_core: lowrisc:earlgrey_dv:gpio_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 6677c72579d7c..f6f653d80089f 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -82,12 +82,6 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" rel_path: "hw/ip/edn/lint/{tool}" }, - { name: flash_ctrl - fusesoc_core: lowrisc:earlgrey_ip:flash_ctrl - import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" - rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/lint/{tool}" - }, { name: gpio fusesoc_core: lowrisc:earlgrey_ip:gpio import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] diff --git a/hw/top_earlgrey/rtl/pad_orient_pkg.sv b/hw/top_earlgrey/rtl/pad_orient_pkg.sv index 88cae703331de..e3ef2984a53ed 100644 --- a/hw/top_earlgrey/rtl/pad_orient_pkg.sv +++ b/hw/top_earlgrey/rtl/pad_orient_pkg.sv @@ -27,9 +27,6 @@ package pad_orient_pkg; parameter pad_orient_e DioPadUsbNPadOrient = OrientH; parameter pad_orient_e DioPadCc1PadOrient = OrientH; parameter pad_orient_e DioPadCc2PadOrient = OrientH; - parameter pad_orient_e DioPadFlashTestVoltPadOrient = OrientH; - parameter pad_orient_e DioPadFlashTestMode0PadOrient = OrientH; - parameter pad_orient_e DioPadFlashTestMode1PadOrient = OrientH; parameter pad_orient_e DioPadRramAnalogPadOrient = OrientH; parameter pad_orient_e DioPadIor8PadOrient = OrientV; parameter pad_orient_e DioPadIor9PadOrient = OrientV; diff --git a/hw/top_earlgrey/rtl/scan_role_pkg.sv b/hw/top_earlgrey/rtl/scan_role_pkg.sv index 4f1965e3e3dd3..d8f83d852b85d 100644 --- a/hw/top_earlgrey/rtl/scan_role_pkg.sv +++ b/hw/top_earlgrey/rtl/scan_role_pkg.sv @@ -27,9 +27,6 @@ package scan_role_pkg; parameter scan_role_e DioPadUsbNScanRole = NoScan; parameter scan_role_e DioPadCc1ScanRole = NoScan; parameter scan_role_e DioPadCc2ScanRole = NoScan; - parameter scan_role_e DioPadFlashTestVoltScanRole = NoScan; - parameter scan_role_e DioPadFlashTestMode0ScanRole = NoScan; - parameter scan_role_e DioPadFlashTestMode1ScanRole = NoScan; parameter scan_role_e DioPadRramAnalogScanRole = NoScan; parameter scan_role_e DioPadIor8ScanRole = NoScan; parameter scan_role_e DioPadIor9ScanRole = NoScan; diff --git a/hw/top_earlgrey/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl index e747e12cfc707..9cea2020f0286 100644 --- a/hw/top_earlgrey/templates/chiplevel.sv.tpl +++ b/hw/top_earlgrey/templates/chiplevel.sv.tpl @@ -593,10 +593,13 @@ module chip_${top["name"]}_${target["name"]} #( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; +% if top["name"] == "earlgrey": + assign flash_obs = '0; +% endif // clock bypass req/ack prim_mubi_pkg::mubi4_t io_clk_byp_req; @@ -906,7 +909,7 @@ module chip_${top["name"]}_${target["name"]} #( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -971,6 +974,7 @@ module chip_${top["name"]}_${target["name"]} #( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections % if top["name"] != "englishbreakfast": @@ -990,6 +994,14 @@ module chip_${top["name"]}_${target["name"]} #( .scan_reset_no ( scan_rst_n ) ); +% if top["name"] == "earlgrey": + logic unused_flash_ast_sigs; + assign unused_flash_ast_sigs = ^{ + flash_bist_enable, + flash_power_down_h, + flash_power_ready_h + }; +% endif ################################################################### ## ASIC ## @@ -1008,12 +1020,6 @@ module chip_${top["name"]}_${target["name"]} #( assign manual_out_cc2 = 1'b0; assign manual_oe_cc2 = 1'b0; - assign manual_out_flash_test_mode0 = 1'b0; - assign manual_oe_flash_test_mode0 = 1'b0; - assign manual_out_flash_test_mode1 = 1'b0; - assign manual_oe_flash_test_mode1 = 1'b0; - assign manual_out_flash_test_volt = 1'b0; - assign manual_oe_flash_test_volt = 1'b0; assign manual_out_rram_analog = 1'b0; assign manual_oe_rram_analog = 1'b0; @@ -1025,20 +1031,14 @@ module chip_${top["name"]}_${target["name"]} #( prim_pad_wrapper_pkg::pad_attr_t [3:0] sensor_ctrl_manual_pad_attr; assign manual_attr_cc1 = sensor_ctrl_manual_pad_attr[0]; assign manual_attr_cc2 = sensor_ctrl_manual_pad_attr[1]; - assign manual_attr_flash_test_mode0 = sensor_ctrl_manual_pad_attr[2]; - assign manual_attr_flash_test_mode1 = sensor_ctrl_manual_pad_attr[3]; // These pad attributes are currently tied off permanently (these are supply pads). - assign manual_attr_flash_test_volt = '0; assign manual_attr_rram_analog = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ manual_in_cc2, manual_in_cc1, - manual_in_flash_test_volt, - manual_in_flash_test_mode0, - manual_in_flash_test_mode1, manual_in_rram_analog }; diff --git a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl index fdcd59ef3b1f0..422472f23497c 100644 --- a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl +++ b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl @@ -63,12 +63,6 @@ module ${top["name"]}_pd_${domain.lower()} #( }; % endif % if m.get("name") == "rram_ctrl": - // TODO: remove once flash_ctrl is removed - assign flash_ctrl_otp_rsp.data_ack = flash_ctrl_otp_req.data_req; - assign flash_ctrl_otp_rsp.addr_ack = flash_ctrl_otp_req.addr_req; - assign flash_ctrl_otp_rsp.key = '0; - assign flash_ctrl_otp_rsp.rand_key = '0; - assign flash_ctrl_otp_rsp.seed_valid = 1'b0; % endif % endfor diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 25db569ae9df6..e807e24f2ad94 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -28,7 +28,6 @@ filesets: - lowrisc:ip:kmac - lowrisc:ip:otbn - lowrisc:prim:ram_1p_scr - - lowrisc:prim:flash - lowrisc:ip:rram_ctrl - lowrisc:ip:rram_macro - lowrisc:ip:sram_ctrl @@ -42,7 +41,6 @@ filesets: - lowrisc:top_earlgrey:xbar_peri - lowrisc:earlgrey_ip:alert_handler - lowrisc:earlgrey_ip:clkmgr - - lowrisc:earlgrey_ip:flash_ctrl - lowrisc:earlgrey_ip:gpio - lowrisc:earlgrey_ip:otp_ctrl - lowrisc:earlgrey_ip:pinmux @@ -108,7 +106,6 @@ mapping: "lowrisc:virtual_constants:top_pkg": "lowrisc:earlgrey_constants:top_pkg" "lowrisc:virtual_constants:top_racl_pkg": "lowrisc:earlgrey_constants:top_racl_pkg" "lowrisc:systems:ast_pkg": "lowrisc:systems:top_earlgrey_ast_pkg" - "lowrisc:virtual_ip:flash_ctrl_prim_reg_top": "lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top" "lowrisc:virtual_constants:lc_ctrl_token_pkg": "lowrisc:earlgrey_constants:testing_lc_ctrl_token_pkg" "lowrisc:virtual_constants:rnd_cnst_pkg": "lowrisc:earlgrey_constants:testing_rnd_cnst_pkg" From de8a1bb7564bf2e4b78181b183cbcaa6e0f7fe19 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 13:53:54 +0200 Subject: [PATCH 04/24] [rtl,top_earlgrey] autogen changes for flash ctrl removal Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/autogen/defs.bzl | 7 - .../data/autogen/top_earlgrey.gen.hjson | 1612 +----- .../top_earlgrey.secrets.testing.gen.hjson | 213 +- .../data/otp/otp_ctrl_img_owner_sw_cfg.hjson | 13 +- hw/top_earlgrey/doc/design/README.md | 141 +- hw/top_earlgrey/doc/memory_map.md | 3 - .../dv/autogen/tb__alert_handler_connect.sv | 67 +- .../dv/autogen/tb__xbar_connect.sv | 6 - .../dv/autogen/xbar_env_pkg__params.sv | 16 - hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg | 9 - .../dv/env/autogen/chip_env_pkg__params.sv | 7 +- .../data/autogen/xbar_main.gen.hjson | 112 - .../ip/xbar_main/data/autogen/xbar_main.hjson | 18 - .../xbar_main/dv/autogen/tb__xbar_connect.sv | 3 - .../ip/xbar_main/dv/autogen/xbar_cover.cfg | 9 - .../dv/autogen/xbar_env_pkg__params.sv | 16 - .../ip/xbar_main/dv/autogen/xbar_main_bind.sv | 18 - .../ip/xbar_main/rtl/autogen/tl_main_pkg.sv | 47 +- .../ip/xbar_main/rtl/autogen/xbar_main.sv | 1291 +++-- .../alert_handler/data/alert_handler.hjson | 12 +- .../top_earlgrey_alert_handler.ipconfig.hjson | 12 +- .../alert_handler/doc/theory_of_operation.md | 2 +- .../rtl/alert_handler_reg_pkg.sv | 1202 +++-- .../rtl/alert_handler_reg_top.sv | 3590 +++++-------- .../data/top_earlgrey_clkmgr.ipconfig.hjson | 2 +- .../ip_autogen/pinmux/data/pinmux.hjson | 4 +- .../data/top_earlgrey_pinmux.ipconfig.hjson | 4 +- .../ip_autogen/pinmux/doc/pinout_asic.md | 145 +- .../ip_autogen/pinmux/doc/pinout_cw340.md | 4 - .../ip_autogen/pinmux/doc/pinout_verilator.md | 145 +- .../ip_autogen/pinmux/doc/registers.md | 2052 ++++---- .../ip_autogen/pinmux/doc/targets.md | 4 +- .../ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv | 2070 ++++---- .../ip_autogen/pinmux/rtl/pinmux_reg_top.sv | 4523 ++++++++--------- .../ip_autogen/rv_plic/data/rv_plic.hjson | 2 +- .../data/top_earlgrey_rv_plic.ipconfig.hjson | 2 +- .../ip_autogen/rv_plic/rtl/rv_plic.sv | 10 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv | 62 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv | 742 +-- .../rtl/autogen/chip_earlgrey_asic.sv | 78 +- .../rtl/autogen/chip_earlgrey_cw340.sv | 20 +- .../rtl/autogen/chip_earlgrey_verilator.sv | 18 +- .../rtl/autogen/earlgrey_pd_main.sv | 356 +- .../testing/top_earlgrey_rnd_cnst_pkg.sv | 272 +- .../top_earlgrey_testing_rnd_cnst_pkg.core | 1 - hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 19 - .../rtl/autogen/top_earlgrey_pkg.sv | 282 +- .../sw/autogen/chip/top_earlgrey.rs | 512 +- hw/top_earlgrey/sw/autogen/tests/BUILD | 2 - hw/top_earlgrey/sw/autogen/tests/alert_test.c | 20 - .../sw/autogen/tests/plic_all_irqs_test.c | 406 +- hw/top_earlgrey/sw/autogen/top_earlgrey.c | 15 +- hw/top_earlgrey/sw/autogen/top_earlgrey.h | 299 +- .../sw/autogen/top_earlgrey_memory.h | 48 +- .../sw/autogen/top_earlgrey_memory.ld | 1 - hw/top_earlgrey/templates/chiplevel.sv.tpl | 8 + .../autogen/chip_englishbreakfast_cw305.sv | 5 +- .../chip_englishbreakfast_verilator.sv | 5 +- sw/host/ot_hal/src/top/autogen/earlgrey.rs | 60 +- 59 files changed, 8056 insertions(+), 12568 deletions(-) diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index c0582f3933090..55ca56f45dda7 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -16,7 +16,6 @@ load("//hw/top_earlgrey/ip_autogen/clkmgr:defs.bzl", "CLKMGR") load("//hw/ip/csrng:defs.bzl", "CSRNG") load("//hw/ip/edn:defs.bzl", "EDN") load("//hw/ip/entropy_src:defs.bzl", "ENTROPY_SRC") -load("//hw/top_earlgrey/ip_autogen/flash_ctrl:defs.bzl", "FLASH_CTRL") load("//hw/top_earlgrey/ip_autogen/gpio:defs.bzl", "GPIO") load("//hw/ip/hmac:defs.bzl", "HMAC") load("//hw/ip/i2c:defs.bzl", "I2C") @@ -53,7 +52,6 @@ EARLGREY_IPS = [ CSRNG, EDN, ENTROPY_SRC, - FLASH_CTRL, GPIO, HMAC, I2C, @@ -115,11 +113,6 @@ EARLGREY_ALERTS = [ "sensor_ctrl_recov_alert", "sensor_ctrl_fatal_alert", "sram_ctrl_ret_fatal_error", - "flash_ctrl_recov_err", - "flash_ctrl_fatal_std_err", - "flash_ctrl_fatal_err", - "flash_ctrl_fatal_prim_flash_alert", - "flash_ctrl_recov_prim_flash_alert", "rram_ctrl_recov_err", "rram_ctrl_fatal_std_err", "rram_ctrl_fatal_err", diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index d011bd2a03b63..592a4c0577b50 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -561,7 +561,7 @@ desc: ''' MMIO region excludes any memory that is separate from the module configuration - space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device + space, i.e. ROM, main SRAM, and RRAM are excluded but retention SRAM, spi_device memory, or usbdev memory are included. ''' nodes: @@ -592,8 +592,6 @@ ast sensor_ctrl sram_ctrl_ret - flash_ctrl.core - flash_ctrl.prim rram_ctrl.core rram_macro.prim rv_plic @@ -5727,410 +5725,6 @@ ] generate_dif: true } - { - name: flash_ctrl - type: flash_ctrl - template_type: flash_ctrl - clock_srcs: - { - clk_i: main - clk_otp_i: io_div4 - } - clock_group: infra - reset_connections: - { - rst_ni: - { - name: lc - domain: Main - } - rst_otp_ni: - { - name: lc_io_div4 - domain: Main - } - } - base_addrs: - { - core: - { - hart: 0x41000000 - } - prim: - { - hart: 0x41008000 - } - mem: - { - hart: 0x20000000 - } - } - param_decl: - { - ProgFifoDepth: "4" - } - memory: - { - mem: - { - label: eflash - swaccess: ro - data_intg_passthru: "true" - exec: True - byte_write: False - config: - { - banks: 2 - pages_per_bank: 256 - program_resolution: 8 - pgm_resolution_bytes: 64 - bytes_per_page: 2048 - bytes_per_bank: 524288 - size: 0x100000 - } - size: 0x100000 - } - } - attr: ipgen - clock_connections: - { - clk_i: clkmgr_clocks_i.clk_main_infra - clk_otp_i: clkmgr_clocks_i.clk_io_div4_infra - } - param_list: - [ - { - name: SecScrambleEn - desc: Compile-time option to enable flash scrambling - type: bit - default: "1" - local: "false" - expose: "true" - name_top: SecFlashCtrlScrambleEn - } - { - name: ProgFifoDepth - desc: Depth of program fifo - type: int - default: "4" - local: "false" - expose: "true" - name_top: FlashCtrlProgFifoDepth - } - { - name: RdFifoDepth - desc: Depth of read fifo - type: int - default: "16" - local: "false" - expose: "true" - name_top: FlashCtrlRdFifoDepth - } - ] - inter_signal_list: - [ - { - name: otp - struct: nvm_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - inst_name: flash_ctrl - default: "" - top_signame: flash_ctrl_otp - index: -1 - } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_debug_en - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - conn_type: false - index: -1 - top_signame: flash_bist_enable - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_power_down_h - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_power_ready_h - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_test_mode_a - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_test_voltage_h - } - { - name: lc_creator_seed_sw_rw_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_creator_seed_sw_rw_en - index: -1 - } - { - name: lc_owner_seed_sw_rw_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_owner_seed_sw_rw_en - index: -1 - } - { - name: lc_iso_part_sw_rd_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_iso_part_sw_rd_en - index: -1 - } - { - name: lc_iso_part_sw_wr_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_iso_part_sw_wr_en - index: -1 - } - { - name: lc_seed_hw_rd_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_seed_hw_rd_en - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: rma_req - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_rma_req - index: -1 - } - { - name: rma_ack - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: rma_seed - struct: lc_nvm_rma_seed - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_rma_seed - index: -1 - } - { - name: pwrmgr - struct: pwr_nvm - package: pwrmgr_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: keymgr - struct: keymgr_flash - package: flash_ctrl_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: ast_obs_ctrl - index: -1 - } - { - name: fla_obs - struct: logic - type: uni - act: req - width: 8 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_obs - } - { - name: core_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_core_tl - index: -1 - } - { - name: prim_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_prim_tl - index: -1 - } - { - name: mem_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_mem_tl - index: -1 - } - ] - generate_dif: true - domain: Main - } { name: rram_ctrl type: rram_ctrl @@ -10405,7 +9999,6 @@ { ast.obs_ctrl: [ - flash_ctrl.obs_ctrl rram_macro.obs_ctrl ] alert_handler.crashdump: @@ -10445,7 +10038,6 @@ ] lc_ctrl.lc_nvm_rma_seed: [ - flash_ctrl.rma_seed rram_ctrl.rma_seed ] otp_ctrl.sram_otp_key: @@ -10498,7 +10090,6 @@ ] lc_ctrl.lc_nvm_rma_req: [ - flash_ctrl.rma_req otbn.lc_rma_req rram_ctrl.rma_req ] @@ -10629,7 +10220,6 @@ ] lc_ctrl.lc_nvm_debug_en: [ - flash_ctrl.lc_nvm_debug_en rram_macro.lc_nvm_debug_en ] lc_ctrl.lc_hw_debug_clr: @@ -10669,7 +10259,6 @@ sram_ctrl_sec.lc_escalate_en sram_ctrl_ret.lc_escalate_en aon_timer.lc_escalate_en - flash_ctrl.lc_escalate_en rram_ctrl.lc_escalate_en pinmux.lc_escalate_en ] @@ -10689,28 +10278,23 @@ lc_ctrl.lc_creator_seed_sw_rw_en: [ otp_ctrl.lc_creator_seed_sw_rw_en - flash_ctrl.lc_creator_seed_sw_rw_en rram_ctrl.lc_creator_seed_sw_rw_en ] lc_ctrl.lc_owner_seed_sw_rw_en: [ - flash_ctrl.lc_owner_seed_sw_rw_en rram_ctrl.lc_owner_seed_sw_rw_en ] lc_ctrl.lc_iso_part_sw_rd_en: [ - flash_ctrl.lc_iso_part_sw_rd_en rram_ctrl.lc_iso_part_sw_rd_en ] lc_ctrl.lc_iso_part_sw_wr_en: [ - flash_ctrl.lc_iso_part_sw_wr_en rram_ctrl.lc_iso_part_sw_wr_en ] lc_ctrl.lc_seed_hw_rd_en: [ otp_ctrl.lc_seed_hw_rd_en - flash_ctrl.lc_seed_hw_rd_en rram_ctrl.lc_seed_hw_rd_en ] lc_ctrl.lc_rma_state: @@ -10815,18 +10399,6 @@ [ main.tl_usbdev ] - flash_ctrl.core_tl: - [ - main.tl_flash_ctrl__core - ] - flash_ctrl.prim_tl: - [ - main.tl_flash_ctrl__prim - ] - flash_ctrl.mem_tl: - [ - main.tl_flash_ctrl__mem - ] rram_ctrl.core_tl: [ main.tl_rram_ctrl__core @@ -11001,7 +10573,6 @@ rv_core_ibex.irq_timer rv_core_ibex.hart_id rv_core_ibex.boot_addr - flash_ctrl.otp pinmux.dft_jtag otp_ctrl.otp_broadcast csrng.otp_en_csrng_sw_app_read @@ -11047,12 +10618,6 @@ clkmgr.hi_speed_sel: hi_speed_sel clkmgr.div_step_down_req: div_step_down_req clkmgr.calib_rdy: calib_rdy - flash_ctrl.flash_bist_enable: flash_bist_enable - flash_ctrl.flash_power_down_h: flash_power_down_h - flash_ctrl.flash_power_ready_h: flash_power_ready_h - flash_ctrl.flash_test_mode_a: flash_test_mode_a - flash_ctrl.flash_test_voltage_h: flash_test_voltage_h - flash_ctrl.fla_obs: flash_obs entropy_src.entropy_src_rng_enable: es_rng_enable entropy_src.entropy_src_rng_valid: es_rng_valid entropy_src.entropy_src_rng_bits: es_rng_bit @@ -11142,7 +10707,6 @@ rv_dm.mem sram_ctrl_main.ram sram_ctrl_sec.ram - flash_ctrl.mem rram_ctrl.host ] rv_core_ibex.cored: @@ -11157,9 +10721,6 @@ spi_host0 spi_host1 usbdev - flash_ctrl.core - flash_ctrl.prim - flash_ctrl.mem rram_ctrl.core rram_ctrl.host rram_macro.prim @@ -11189,9 +10750,6 @@ spi_host0 spi_host1 usbdev - flash_ctrl.core - flash_ctrl.prim - flash_ctrl.mem rram_ctrl.core rram_ctrl.host rram_macro.prim @@ -11434,72 +10992,6 @@ stub: false pipeline: true } - { - name: flash_ctrl.core - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x41000000 - } - size_byte: 0x200 - } - ] - xbar: false - stub: false - pipeline: true - } - { - name: flash_ctrl.prim - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x41008000 - } - size_byte: 0x80 - } - ] - xbar: false - stub: false - pipeline: true - } - { - name: flash_ctrl.mem - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x20000000 - } - size_byte: 0x100000 - } - ] - xbar: false - stub: false - pipeline: true - } { name: rram_ctrl.core type: device @@ -12050,45 +11542,6 @@ top_signame: usbdev_tl index: -1 } - { - name: tl_flash_ctrl__core - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_core_tl - index: -1 - } - { - name: tl_flash_ctrl__prim - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_prim_tl - index: -1 - } - { - name: tl_flash_ctrl__mem - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_mem_tl - index: -1 - } { name: tl_rram_ctrl__core struct: tl @@ -13307,40 +12760,13 @@ port_type: `INOUT_AI idx: 4 } - { - name: FLASH_TEST_VOLT - type: AnalogIn0 - bank: VCC - connection: manual - desc: Flash test voltage input - idx: 5 - port_type: inout - } - { - name: FLASH_TEST_MODE0 - type: InputStd - bank: VCC - connection: manual - desc: Flash test mode signal - idx: 6 - port_type: inout - } - { - name: FLASH_TEST_MODE1 - type: InputStd - bank: VCC - connection: manual - desc: Flash test mode signal - idx: 7 - port_type: inout - } { name: RRAM_ANALOG type: AnalogIn0 bank: VCC connection: manual desc: RRAM analog test signal - idx: 8 + idx: 5 port_type: inout } { @@ -13349,7 +12775,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 9 + idx: 6 port_type: inout } { @@ -13358,7 +12784,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 10 + idx: 7 port_type: inout } { @@ -13367,7 +12793,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 11 + idx: 8 port_type: inout } { @@ -13376,7 +12802,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 12 + idx: 9 port_type: inout } { @@ -13385,7 +12811,7 @@ bank: VIOA connection: direct desc: SPI host clock - idx: 13 + idx: 10 port_type: inout } { @@ -13394,7 +12820,7 @@ bank: VIOA connection: direct desc: SPI host chip select - idx: 14 + idx: 11 port_type: inout } { @@ -13403,7 +12829,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 15 + idx: 12 port_type: inout } { @@ -13412,7 +12838,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 16 + idx: 13 port_type: inout } { @@ -13421,7 +12847,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 17 + idx: 14 port_type: inout } { @@ -13430,7 +12856,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 18 + idx: 15 port_type: inout } { @@ -13439,7 +12865,7 @@ bank: VIOA connection: direct desc: SPI device clock - idx: 19 + idx: 16 port_type: inout } { @@ -13448,7 +12874,7 @@ bank: VIOA connection: direct desc: SPI device chip select - idx: 20 + idx: 17 port_type: inout } { @@ -13844,7 +13270,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (ec_rst_l) - idx: 21 + idx: 18 port_type: inout } { @@ -13853,7 +13279,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (flash_wp_l)) - idx: 22 + idx: 19 port_type: inout } { @@ -14090,14 +13516,6 @@ desc: "" attr: "" } - { - instance: flash_ctrl - port: "" - connection: muxed - pad: "" - desc: "" - attr: "" - } { instance: rram_macro port: "" @@ -14973,42 +14391,6 @@ domain: Main glob_idx: 46 } - { - name: flash_ctrl_tck - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - domain: Main - glob_idx: 47 - } - { - name: flash_ctrl_tms - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - domain: Main - glob_idx: 48 - } - { - name: flash_ctrl_tdi - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - domain: Main - glob_idx: 49 - } { name: rram_macro_tck width: 1 @@ -15019,7 +14401,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 50 + glob_idx: 47 } { name: rram_macro_tms @@ -15031,7 +14413,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 51 + glob_idx: 48 } { name: rram_macro_tdi @@ -15043,7 +14425,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 52 + glob_idx: 49 } { name: sysrst_ctrl_ac_present @@ -15055,7 +14437,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 53 + glob_idx: 50 } { name: sysrst_ctrl_key0_in @@ -15067,7 +14449,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 54 + glob_idx: 51 } { name: sysrst_ctrl_key1_in @@ -15079,7 +14461,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 55 + glob_idx: 52 } { name: sysrst_ctrl_key2_in @@ -15091,7 +14473,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 56 + glob_idx: 53 } { name: sysrst_ctrl_pwrb_in @@ -15103,7 +14485,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 57 + glob_idx: 54 } { name: sysrst_ctrl_lid_open @@ -15115,7 +14497,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 58 + glob_idx: 55 } { name: usbdev_sense @@ -15127,7 +14509,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 59 + glob_idx: 56 } { name: spi_host0_sck @@ -15225,18 +14607,6 @@ domain: Main glob_idx: 47 } - { - name: flash_ctrl_tdo - width: 1 - type: output - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - domain: Main - glob_idx: 48 - } { name: rram_macro_tdo width: 1 @@ -15247,7 +14617,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 49 + glob_idx: 48 } { name: sensor_ctrl_ast_debug_out @@ -15259,7 +14629,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 50 + glob_idx: 49 } { name: sensor_ctrl_ast_debug_out @@ -15271,7 +14641,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 51 + glob_idx: 50 } { name: sensor_ctrl_ast_debug_out @@ -15283,7 +14653,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 52 + glob_idx: 51 } { name: sensor_ctrl_ast_debug_out @@ -15295,7 +14665,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 53 + glob_idx: 52 } { name: sensor_ctrl_ast_debug_out @@ -15307,7 +14677,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 54 + glob_idx: 53 } { name: sensor_ctrl_ast_debug_out @@ -15319,7 +14689,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 55 + glob_idx: 54 } { name: sensor_ctrl_ast_debug_out @@ -15331,7 +14701,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 56 + glob_idx: 55 } { name: sensor_ctrl_ast_debug_out @@ -15343,7 +14713,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 57 + glob_idx: 56 } { name: sensor_ctrl_ast_debug_out @@ -15355,7 +14725,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 58 + glob_idx: 57 } { name: sysrst_ctrl_bat_disable @@ -15367,7 +14737,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 59 + glob_idx: 58 } { name: sysrst_ctrl_key0_out @@ -15379,7 +14749,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 60 + glob_idx: 59 } { name: sysrst_ctrl_key1_out @@ -15391,7 +14761,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 61 + glob_idx: 60 } { name: sysrst_ctrl_key2_out @@ -15403,7 +14773,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 62 + glob_idx: 61 } { name: sysrst_ctrl_pwrb_out @@ -15415,7 +14785,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 63 + glob_idx: 62 } { name: sysrst_ctrl_z3_wakeup @@ -15427,7 +14797,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 64 + glob_idx: 63 } ] io_counts: @@ -15437,13 +14807,13 @@ inouts: 12 inputs: 2 outputs: 2 - pads: 23 + pads: 20 } muxed: { inouts: 42 - inputs: 18 - outputs: 23 + inputs: 15 + outputs: 22 pads: 47 } } @@ -15472,14 +14842,6 @@ { unused: true } - flash_ctrl.flash_test_mode_a: - { - signal: "{FLASH_TEST_MODE1, FLASH_TEST_MODE0}" - } - flash_ctrl.flash_test_voltage_h: - { - signal: FLASH_TEST_VOLT - } rram_macro.rram_test_analog: { signal: RRAM_ANALOG @@ -15627,16 +14989,6 @@ { unused: true } - flash_ctrl.flash_test_mode_a: - { - unused: true - tie_value: "" - } - flash_ctrl.flash_test_voltage_h: - { - unused: true - tie_value: "" - } rram_macro.rram_test_analog: { unused: true @@ -15853,23 +15205,6 @@ { unused: true } - flash_ctrl.flash_test_mode_a: - { - unused: true - } - flash_ctrl.flash_test_voltage_h: - { - unused: true - } - flash_ctrl.flash_power_down_h: - { - unused: true - } - flash_ctrl.flash_power_ready_h: - { - unused: true - tie_value: 1'b1 - } } } pinout: @@ -15879,10 +15214,7 @@ [ CC1 CC2 - FLASH_TEST_VOLT RRAM_ANALOG - FLASH_TEST_MODE0 - FLASH_TEST_MODE1 USB_P USB_N ] @@ -16451,61 +15783,6 @@ lpg_name: infra_lc_io_div4_Aon lpg_idx: 16 } - { - name: flash_ctrl_recov_err - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: flash_ctrl - desc: flash_ctrl recov_err alert - lpg_name: infra_lc_Main - lpg_idx: 17 - } - { - name: flash_ctrl_fatal_std_err - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: flash_ctrl - desc: flash_ctrl fatal_std_err alert - lpg_name: infra_lc_Main - lpg_idx: 17 - } - { - name: flash_ctrl_fatal_err - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: flash_ctrl - desc: flash_ctrl fatal_err alert - lpg_name: infra_lc_Main - lpg_idx: 17 - } - { - name: flash_ctrl_fatal_prim_flash_alert - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: flash_ctrl - desc: flash_ctrl fatal_prim_flash_alert alert - lpg_name: infra_lc_Main - lpg_idx: 17 - } - { - name: flash_ctrl_recov_prim_flash_alert - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: flash_ctrl - desc: flash_ctrl recov_prim_flash_alert alert - lpg_name: infra_lc_Main - lpg_idx: 17 - } { name: rram_ctrl_recov_err width: 1 @@ -18489,84 +17766,6 @@ plic: rv_plic outgoing: false } - { - name: flash_ctrl_prog_empty - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl prog_empty interrupt - intr_type: IntrType.Status - default_val: true - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } - { - name: flash_ctrl_prog_lvl - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl prog_lvl interrupt - intr_type: IntrType.Status - default_val: true - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } - { - name: flash_ctrl_rd_full - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl rd_full interrupt - intr_type: IntrType.Status - default_val: false - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } - { - name: flash_ctrl_rd_lvl - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl rd_lvl interrupt - intr_type: IntrType.Status - default_val: false - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } - { - name: flash_ctrl_op_done - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl op_done interrupt - intr_type: IntrType.Event - default_val: false - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } - { - name: flash_ctrl_corr_err - width: 1 - type: interrupt - module_name: flash_ctrl - desc: flash_ctrl corr_err interrupt - intr_type: IntrType.Event - default_val: false - incoming: false - domain: Main - plic: rv_plic - outgoing: false - } { name: rram_ctrl_wr_empty width: 1 @@ -18912,11 +18111,11 @@ rv_plic: { domain: Main - count_tot: 190 + count_tot: 184 count_pd: { Aon: 7 - Main: 182 + Main: 176 } } } @@ -19819,7 +19018,6 @@ aon_timer sensor_ctrl sram_ctrl_ret - flash_ctrl rram_ctrl rv_dm rv_plic @@ -20088,7 +19286,7 @@ alert_handler[32]: fatal_error ] } - module_flash_ctrl: + module_rram_ctrl: { tx_expr: alert_tx[37:33] rx_expr: alert_rx[37:33] @@ -20098,183 +19296,169 @@ alert_handler[33]: recov_err alert_handler[34]: fatal_std_err alert_handler[35]: fatal_err - alert_handler[36]: fatal_prim_flash_alert - alert_handler[37]: recov_prim_flash_alert - ] - } - module_rram_ctrl: - { - tx_expr: alert_tx[42:38] - rx_expr: alert_rx[42:38] - async_expr: alert_handler_reg_pkg::AsyncOn[42:38] - comments: - [ - alert_handler[38]: recov_err - alert_handler[39]: fatal_std_err - alert_handler[40]: fatal_err - alert_handler[41]: fatal_macro_err - alert_handler[42]: recov_macro_err + alert_handler[36]: fatal_macro_err + alert_handler[37]: recov_macro_err ] } module_rv_dm: { - tx_expr: alert_tx[43] - rx_expr: alert_rx[43] - async_expr: alert_handler_reg_pkg::AsyncOn[43] + tx_expr: alert_tx[38] + rx_expr: alert_rx[38] + async_expr: alert_handler_reg_pkg::AsyncOn[38] comments: [ - alert_handler[43]: fatal_fault + alert_handler[38]: fatal_fault ] } module_rv_plic: { - tx_expr: alert_tx[44] - rx_expr: alert_rx[44] - async_expr: alert_handler_reg_pkg::AsyncOn[44] + tx_expr: alert_tx[39] + rx_expr: alert_rx[39] + async_expr: alert_handler_reg_pkg::AsyncOn[39] comments: [ - alert_handler[44]: fatal_fault + alert_handler[39]: fatal_fault ] } module_aes: { - tx_expr: alert_tx[46:45] - rx_expr: alert_rx[46:45] - async_expr: alert_handler_reg_pkg::AsyncOn[46:45] + tx_expr: alert_tx[41:40] + rx_expr: alert_rx[41:40] + async_expr: alert_handler_reg_pkg::AsyncOn[41:40] comments: [ - alert_handler[45]: recov_ctrl_update_err - alert_handler[46]: fatal_fault + alert_handler[40]: recov_ctrl_update_err + alert_handler[41]: fatal_fault ] } module_hmac: { - tx_expr: alert_tx[47] - rx_expr: alert_rx[47] - async_expr: alert_handler_reg_pkg::AsyncOn[47] + tx_expr: alert_tx[42] + rx_expr: alert_rx[42] + async_expr: alert_handler_reg_pkg::AsyncOn[42] comments: [ - alert_handler[47]: fatal_fault + alert_handler[42]: fatal_fault ] } module_kmac: { - tx_expr: alert_tx[49:48] - rx_expr: alert_rx[49:48] - async_expr: alert_handler_reg_pkg::AsyncOn[49:48] + tx_expr: alert_tx[44:43] + rx_expr: alert_rx[44:43] + async_expr: alert_handler_reg_pkg::AsyncOn[44:43] comments: [ - alert_handler[48]: recov_operation_err - alert_handler[49]: fatal_fault_err + alert_handler[43]: recov_operation_err + alert_handler[44]: fatal_fault_err ] } module_otbn: { - tx_expr: alert_tx[51:50] - rx_expr: alert_rx[51:50] - async_expr: alert_handler_reg_pkg::AsyncOn[51:50] + tx_expr: alert_tx[46:45] + rx_expr: alert_rx[46:45] + async_expr: alert_handler_reg_pkg::AsyncOn[46:45] comments: [ - alert_handler[50]: fatal - alert_handler[51]: recov + alert_handler[45]: fatal + alert_handler[46]: recov ] } module_keymgr_dpe: { - tx_expr: alert_tx[53:52] - rx_expr: alert_rx[53:52] - async_expr: alert_handler_reg_pkg::AsyncOn[53:52] + tx_expr: alert_tx[48:47] + rx_expr: alert_rx[48:47] + async_expr: alert_handler_reg_pkg::AsyncOn[48:47] comments: [ - alert_handler[52]: recov_operation_err - alert_handler[53]: fatal_fault_err + alert_handler[47]: recov_operation_err + alert_handler[48]: fatal_fault_err ] } module_csrng: { - tx_expr: alert_tx[55:54] - rx_expr: alert_rx[55:54] - async_expr: alert_handler_reg_pkg::AsyncOn[55:54] + tx_expr: alert_tx[50:49] + rx_expr: alert_rx[50:49] + async_expr: alert_handler_reg_pkg::AsyncOn[50:49] comments: [ - alert_handler[54]: recov_alert - alert_handler[55]: fatal_alert + alert_handler[49]: recov_alert + alert_handler[50]: fatal_alert ] } module_entropy_src: { - tx_expr: alert_tx[57:56] - rx_expr: alert_rx[57:56] - async_expr: alert_handler_reg_pkg::AsyncOn[57:56] + tx_expr: alert_tx[52:51] + rx_expr: alert_rx[52:51] + async_expr: alert_handler_reg_pkg::AsyncOn[52:51] comments: [ - alert_handler[56]: recov_alert - alert_handler[57]: fatal_alert + alert_handler[51]: recov_alert + alert_handler[52]: fatal_alert ] } module_edn0: { - tx_expr: alert_tx[59:58] - rx_expr: alert_rx[59:58] - async_expr: alert_handler_reg_pkg::AsyncOn[59:58] + tx_expr: alert_tx[54:53] + rx_expr: alert_rx[54:53] + async_expr: alert_handler_reg_pkg::AsyncOn[54:53] comments: [ - alert_handler[58]: recov_alert - alert_handler[59]: fatal_alert + alert_handler[53]: recov_alert + alert_handler[54]: fatal_alert ] } module_edn1: { - tx_expr: alert_tx[61:60] - rx_expr: alert_rx[61:60] - async_expr: alert_handler_reg_pkg::AsyncOn[61:60] + tx_expr: alert_tx[56:55] + rx_expr: alert_rx[56:55] + async_expr: alert_handler_reg_pkg::AsyncOn[56:55] comments: [ - alert_handler[60]: recov_alert - alert_handler[61]: fatal_alert + alert_handler[55]: recov_alert + alert_handler[56]: fatal_alert ] } module_sram_ctrl_main: { - tx_expr: alert_tx[62] - rx_expr: alert_rx[62] - async_expr: alert_handler_reg_pkg::AsyncOn[62] + tx_expr: alert_tx[57] + rx_expr: alert_rx[57] + async_expr: alert_handler_reg_pkg::AsyncOn[57] comments: [ - alert_handler[62]: fatal_error + alert_handler[57]: fatal_error ] } module_sram_ctrl_sec: { - tx_expr: alert_tx[63] - rx_expr: alert_rx[63] - async_expr: alert_handler_reg_pkg::AsyncOn[63] + tx_expr: alert_tx[58] + rx_expr: alert_rx[58] + async_expr: alert_handler_reg_pkg::AsyncOn[58] comments: [ - alert_handler[63]: fatal_error + alert_handler[58]: fatal_error ] } module_rom_ctrl: { - tx_expr: alert_tx[64] - rx_expr: alert_rx[64] - async_expr: alert_handler_reg_pkg::AsyncOn[64] + tx_expr: alert_tx[59] + rx_expr: alert_rx[59] + async_expr: alert_handler_reg_pkg::AsyncOn[59] comments: [ - alert_handler[64]: fatal + alert_handler[59]: fatal ] } module_rv_core_ibex: { - tx_expr: alert_tx[68:65] - rx_expr: alert_rx[68:65] - async_expr: alert_handler_reg_pkg::AsyncOn[68:65] + tx_expr: alert_tx[63:60] + rx_expr: alert_rx[63:60] + async_expr: alert_handler_reg_pkg::AsyncOn[63:60] comments: [ - alert_handler[65]: fatal_sw_err - alert_handler[66]: recov_sw_err - alert_handler[67]: fatal_hw_err - alert_handler[68]: recov_hw_err + alert_handler[60]: fatal_sw_err + alert_handler[61]: recov_sw_err + alert_handler[62]: fatal_hw_err + alert_handler[63]: recov_hw_err ] } } @@ -20283,11 +19467,11 @@ alert_handler: { domain: Main - count_tot: 69 + count_tot: 64 count_pd: { Aon: 11 - Main: 58 + Main: 53 } connect_pd: { @@ -20371,7 +19555,6 @@ adc_ctrl aon_timer sensor_ctrl - flash_ctrl rram_ctrl hmac kmac @@ -24467,304 +23650,6 @@ external: true conn_type: false } - { - name: otp - struct: nvm_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - inst_name: flash_ctrl - default: "" - top_signame: flash_ctrl_otp - index: -1 - } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_debug_en - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - conn_type: false - index: -1 - top_signame: flash_bist_enable - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_power_down_h - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_power_ready_h - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_test_mode_a - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_test_voltage_h - } - { - name: lc_creator_seed_sw_rw_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_creator_seed_sw_rw_en - index: -1 - } - { - name: lc_owner_seed_sw_rw_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_owner_seed_sw_rw_en - index: -1 - } - { - name: lc_iso_part_sw_rd_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_iso_part_sw_rd_en - index: -1 - } - { - name: lc_iso_part_sw_wr_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_iso_part_sw_wr_en - index: -1 - } - { - name: lc_seed_hw_rd_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_seed_hw_rd_en - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: rma_req - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_rma_req - index: -1 - } - { - name: rma_ack - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: rma_seed - struct: lc_nvm_rma_seed - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: lc_ctrl_lc_nvm_rma_seed - index: -1 - } - { - name: pwrmgr - struct: pwr_nvm - package: pwrmgr_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: keymgr - struct: keymgr_flash - package: flash_ctrl_pkg - type: uni - act: req - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - domain: Main - top_signame: ast_obs_ctrl - index: -1 - } - { - name: fla_obs - struct: logic - type: uni - act: req - width: 8 - inst_name: flash_ctrl - default: "" - package: "" - external: true - conn_type: false - index: -1 - top_signame: flash_obs - } - { - name: core_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_core_tl - index: -1 - } - { - name: prim_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_prim_tl - index: -1 - } - { - name: mem_tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: flash_ctrl - default: "" - end_idx: -1 - top_type: one-to-one - top_signame: flash_ctrl_mem_tl - index: -1 - } { name: rram_macro struct: rram_macro @@ -27248,45 +26133,6 @@ top_signame: usbdev_tl index: -1 } - { - name: tl_flash_ctrl__core - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_core_tl - index: -1 - } - { - name: tl_flash_ctrl__prim - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_prim_tl - index: -1 - } - { - name: tl_flash_ctrl__mem - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_mem_tl - index: -1 - } { name: tl_rram_ctrl__core struct: tl @@ -30622,126 +29468,6 @@ index: -1 netname: calib_rdy } - { - package: prim_mubi_pkg - struct: mubi4 - domain: Main - inter_pd: false - signame: flash_bist_enable_i - signame_chip: - { - asic: flash_bist_enable - verilator: flash_bist_enable - cw340: flash_bist_enable - } - width: 1 - type: uni - default: "" - direction: in - conn_type: false - index: -1 - netname: flash_bist_enable - } - { - package: "" - struct: logic - domain: Main - inter_pd: false - signame: flash_power_down_h_i - signame_chip: - { - asic: flash_power_down_h - verilator: flash_power_down_h - cw340: 1'b0 - } - width: 1 - type: uni - default: "" - direction: in - conn_type: false - index: -1 - netname: flash_power_down_h - } - { - package: "" - struct: logic - domain: Main - inter_pd: false - signame: flash_power_ready_h_i - signame_chip: - { - asic: flash_power_ready_h - verilator: flash_power_ready_h - cw340: 1'b1 - } - width: 1 - type: uni - default: "" - direction: in - conn_type: false - index: -1 - netname: flash_power_ready_h - } - { - package: "" - struct: "" - domain: Main - inter_pd: false - signame: flash_test_mode_a_io - signame_chip: - { - asic: "{FLASH_TEST_MODE1, FLASH_TEST_MODE0}" - verilator: "" - cw340: "'0" - } - width: 2 - type: io - default: "" - direction: inout - conn_type: false - index: -1 - netname: flash_test_mode_a - } - { - package: "" - struct: "" - domain: Main - inter_pd: false - signame: flash_test_voltage_h_io - signame_chip: - { - asic: FLASH_TEST_VOLT - verilator: "" - cw340: 1'b0 - } - width: 1 - type: io - default: "" - direction: inout - conn_type: false - index: -1 - netname: flash_test_voltage_h - } - { - package: "" - struct: logic - domain: Main - inter_pd: false - signame: flash_obs_o - signame_chip: - { - asic: flash_obs - verilator: flash_obs - cw340: flash_obs - } - width: 8 - type: uni - default: "" - direction: out - conn_type: false - index: -1 - netname: flash_obs - } { package: "" struct: logic @@ -33680,78 +32406,6 @@ suffix: rsp default: "" } - { - package: tlul_pkg - struct: tl_h2d - domain: Main - signame: flash_ctrl_core_tl_req - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: req - default: tlul_pkg::TL_H2D_DEFAULT - } - { - package: tlul_pkg - struct: tl_d2h - domain: Main - signame: flash_ctrl_core_tl_rsp - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: rsp - default: "" - } - { - package: tlul_pkg - struct: tl_h2d - domain: Main - signame: flash_ctrl_prim_tl_req - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: req - default: tlul_pkg::TL_H2D_DEFAULT - } - { - package: tlul_pkg - struct: tl_d2h - domain: Main - signame: flash_ctrl_prim_tl_rsp - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: rsp - default: "" - } - { - package: tlul_pkg - struct: tl_h2d - domain: Main - signame: flash_ctrl_mem_tl_req - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: req - default: tlul_pkg::TL_H2D_DEFAULT - } - { - package: tlul_pkg - struct: tl_d2h - domain: Main - signame: flash_ctrl_mem_tl_rsp - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: rsp - default: "" - } { package: tlul_pkg struct: tl_h2d @@ -34590,26 +33244,6 @@ end_idx: -1 default: "" } - { - package: otp_ctrl_pkg - struct: nvm_otp_key_req - domain: Main - signame: flash_ctrl_otp_req - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } - { - package: otp_ctrl_pkg - struct: nvm_otp_key_rsp - domain: Main - signame: flash_ctrl_otp_rsp - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } { package: jtag_pkg struct: jtag_req diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson index 0908c6253a8d3..e2ca01eb00649 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson @@ -47,7 +47,7 @@ randcount: 40 randtype: data name_top: RndCnstOtpCtrlLfsrSeed - default: 0xb87118af11 + default: 0xdaf5141df1 randwidth: 40 } { @@ -57,7 +57,7 @@ randcount: 40 randtype: perm name_top: RndCnstOtpCtrlLfsrPerm - default: 0x3da38428d1d72c69c98e242030155f6e44619940856534800dd21695871e + default: 0x2d140549d5cf11f0cd25b04c94e1e16086640a37a09d54c601459a70a8a6 randwidth: 240 } { @@ -67,7 +67,7 @@ randcount: 256 randtype: data name_top: RndCnstOtpCtrlScrmblKeyInit - default: 0x85bd9a56ea088d33ffaa6a1155afb0169ab2de3973d027ee30b8f901f644ec7c + default: 0xd8577834ccc6caaa63a8e6604338151b9a23c08f9eed04ca1ebb0bdd305ffb6 randwidth: 256 } { @@ -2935,7 +2935,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivInvalid - default: 0xd3e56c8ed1ec38739f1d0deb7c774199 + default: 0xc4818054e0e0edb0acd0b040fc629ea7 randwidth: 128 } { @@ -2945,7 +2945,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked - default: 0xcf6dd057f44c13e25c7a5877bc5242e6 + default: 0xf8b17fa88fee02e3f0864223a2e23a8c randwidth: 128 } { @@ -2955,7 +2955,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivDev - default: 0xee63ecdf458ae6596e87f9f973db98aa + default: 0xc31e2de5e578d43d2dce49e360cfb594 randwidth: 128 } { @@ -2965,7 +2965,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivProduction - default: 0xa293568fd1f31a0165939d819d151869 + default: 0xacddf170684f6ead2b7febfe895523d7 randwidth: 128 } { @@ -2975,7 +2975,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivRma - default: 0xe6473cdb2479391635057ca1045b9e1 + default: 0xbc4846a485956c7f904b9eded09b89a7 randwidth: 128 } { @@ -2985,7 +2985,7 @@ randcount: 1024 randtype: data name_top: RndCnstLcCtrlInvalidTokens - default: 0x917e1ff0189b04a4f7fba960fe098a4fb9d469171b950e364b0dac5469568e661498fd89197ccae8ea08ff43efc2bfb1c6ab5cc63e6f4741e80f777cb7fc05041a1b896350c9636d6814d23e2f5ff1275ef19959aaa8b6a004d5574984ded1cc79bd6787d6663aa5e622682a6525e083ccddbd2a1b008057c22c884ed49d87a5 + default: 0x5433566f4963d9dc27f3ecb11ce3b87aaa7abc85920b1881083aff7bde18eacff85679453da77d92a176b87118af11cdbe78d67060615a20b9c0740f07969ccd2d10a1a6e7988fa528ac032e0a6138cb8316ff95c65cd7a1a768b06e0106d60eda0f1bc67adf85bd9a56ea088d33ffaa6a1155afb0169ab2de3973d027ee30b8 randwidth: 1024 } ] @@ -3010,7 +3010,7 @@ randcount: 32 randtype: data name_top: RndCnstAlertHandlerLfsrSeed - default: 0xb56ba735 + default: 0xf901f644 randwidth: 32 } { @@ -3020,7 +3020,7 @@ randcount: 32 randtype: perm name_top: RndCnstAlertHandlerLfsrPerm - default: 0x48b6f5ccd4f0c25bca307379faeb36c758041147 + default: 0x903e6ba6c282d992d49456d18f047371e2de69fd randwidth: 160 } ] @@ -3061,7 +3061,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetSramKey - default: 0xedecf7b17682d2ce3db9b12e1af4339e + default: 0x87f9f973db98aaa293568fd1f31a0165 randwidth: 128 } { @@ -3071,7 +3071,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetSramNonce - default: 0x1f45164a418ebc52210d58dc65508e86 + default: 0x939d819d1518690e6473cdb247939163 randwidth: 128 } { @@ -3081,7 +3081,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlRetLfsrSeed - default: 0x9af565c1b87d687e + default: 0x5057ca1045b9e191 randwidth: 64 } { @@ -3091,106 +3091,11 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlRetLfsrPerm - default: 0xeedf1f3234b462ae144607abf6e0dafb5dcba6c847a3f9953806d92135dd2b140290914fcc1e761a2c3295cbd69c437a + default: 0x92130429c46b27bbe752cd2000f3bae48b7e6cba1e597ddd436ff0d71663e3257348d0e5f456ae4e2098aa90661bc1df randwidth: 384 } ] } - { - name: flash_ctrl - type: flash_ctrl - base_addrs: - { - core: - { - hart: 0x41000000 - } - prim: - { - hart: 0x41008000 - } - mem: - { - hart: 0x20000000 - } - } - memory: - { - mem: - { - label: eflash - swaccess: ro - data_intg_passthru: "true" - exec: True - byte_write: False - config: - { - banks: 2 - pages_per_bank: 256 - program_resolution: 8 - pgm_resolution_bytes: 64 - bytes_per_page: 2048 - bytes_per_bank: 524288 - size: 0x100000 - } - size: 0x100000 - } - } - param_list: - [ - { - name: RndCnstAddrKey - desc: Compile-time random bits for default address key - type: flash_ctrl_pkg::flash_key_t - randcount: 128 - randtype: data - name_top: RndCnstFlashCtrlAddrKey - default: 0x378405dbcb5508cd6cd2ce715e7cceb1 - randwidth: 128 - } - { - name: RndCnstDataKey - desc: Compile-time random bits for default data key - type: flash_ctrl_pkg::flash_key_t - randcount: 128 - randtype: data - name_top: RndCnstFlashCtrlDataKey - default: 0xbc1c61b3d27bb8e8398e880ecd252956 - randwidth: 128 - } - { - name: RndCnstAllSeeds - desc: Compile-time random bits for default seeds - type: flash_ctrl_top_specific_pkg::all_seeds_t - randcount: 512 - randtype: data - name_top: RndCnstFlashCtrlAllSeeds - default: 0xba81616362b27eafb903ec79bddf0a4f7dff07db05de63910e4ee4d8a2c7d4022f16ed8a24f80eebcf8299839c103eae3c2f18b4666b5e59d16c252f9db7f094 - randwidth: 512 - } - { - name: RndCnstLfsrSeed - desc: Compile-time random bits for initial LFSR seed - type: flash_ctrl_top_specific_pkg::lfsr_seed_t - randcount: 64 - randtype: data - name_top: RndCnstFlashCtrlLfsrSeed - default: 0x161d818dc161fe26 - randwidth: 64 - } - { - name: RndCnstLfsrPerm - desc: Compile-time random permutation for LFSR output - type: flash_ctrl_top_specific_pkg::lfsr_perm_t - randcount: 64 - randtype: perm - name_top: RndCnstFlashCtrlLfsrPerm - default: 0x853ec21a35348b2331141f4ec07b1167998d5aaade24abc8f9fdd70dc82d6bc61297afe8ba9d4b10fce76d0936755e00 - randwidth: 384 - } - ] - template_type: flash_ctrl - } { name: rram_ctrl type: rram_ctrl @@ -3226,7 +3131,7 @@ randcount: 128 randtype: data name_top: RndCnstRramCtrlAddrKey - default: 0x816510c535a8164939d97df7421ad4d2 + default: 0xf19959aaa8b6a004d5574984ded1cc79 randwidth: 128 } { @@ -3236,7 +3141,7 @@ randcount: 128 randtype: data name_top: RndCnstRramCtrlDataKey - default: 0xc18b270d422ec39c41f727d130ed9b18 + default: 0xbd6787d6663aa5e622682a6525e083cc randwidth: 128 } { @@ -3246,7 +3151,7 @@ randcount: 512 randtype: data name_top: RndCnstRramCtrlAllSeeds - default: 0xb90e42e4287f60ad57d6a551e78f940b8ae9f2bb40621f43f3abd8d737f8d12d8f43fd1619fb83e1a607dcc172099339ef142e028325714513bfdc2a062c2eb4 + default: 0xddbd2a1b008057c22c884ed49d87a5b56ba7353c532142f50667e220c5b724c3fdb6d060653b42a96f88b574e4d3814f5116b3e6f3e331da1182dbc29c894f18 randwidth: 512 } { @@ -3256,7 +3161,7 @@ randcount: 64 randtype: data name_top: RndCnstRramCtrlLfsrSeed - default: 0xecdc716a92861ff7 + default: 0xedecf7b17682d2 randwidth: 64 } { @@ -3266,7 +3171,7 @@ randcount: 64 randtype: perm name_top: RndCnstRramCtrlLfsrPerm - default: 0x359634cc6af8fe654c8e44bb1c1e8b3cea43821b768825fcdf1bd015f7a528071d5bdfaa214a11d6e9ec4f227911a6f0 + default: 0x2bbfab6ea4e027aa55ff9797d65c419220b700e77dd98e3472d10da1a7fc9a1cb06560c852f8d04854479cc18bb2e3f3 randwidth: 384 } ] @@ -3291,7 +3196,7 @@ randcount: 64 randtype: data name_top: RndCnstAesClearingLfsrSeed - default: 0x8c893a6cb3fd30a8 + default: 0x1e9ee420d5b523f randwidth: 64 } { @@ -3301,7 +3206,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingLfsrPerm - default: 0xa9b75048ad734645e2ad9c133c26a197f0777b1b74a209e9c95b9cd98f8c014f071b9343f78b09eafecb9a310558839f + default: 0x83b8a60fc508664aad97d2e77714cc439144a2f4698cfff46307d771b09507636b87339e1d2fba5aeb3824ad771b201a randwidth: 384 } { @@ -3311,7 +3216,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingSharePerm - default: 0x51edce57f6fa0d1ec8a0f27e0501b57e994c9c7b6bf4a90bd05ca0f335aec3812f853e5c8ac363d806b199849709976a + default: 0x7d75e550eecc237ea729932954dc285334848e2babcc611f07e2df9b5976991bfbab3c49f49a0cc326214b035c68db9 randwidth: 384 } { @@ -3321,7 +3226,7 @@ randcount: 288 randtype: data name_top: RndCnstAesMaskingLfsrSeed - default: 0x108133b38a7167f82d4b5453ca0293579000103032eed900bb073d9519792faecdf66777 + default: 0xd7fe6c45d1534fd390c7b068cfe8968794de88e8ff4adc3d02ebfa0a1d5faa5ee00ca534 randwidth: 288 } { @@ -3331,7 +3236,7 @@ randcount: 160 randtype: perm name_top: RndCnstAesMaskingLfsrPerm - default: 0x9248987356407d765d641f23453f69420b041c808f5f226f3b139f849534634e5b2766759a9b0f5086584f538c2b5e65196a60413c0500037f773991595128787b208a445a326b4b062f6e0e4610476c37621a54253a3e07081b7c29122c559d1826610a82174a4d8d0989797e97942a578b01167a3d5c431167359e338385933170361d96740c52141e888130498e6d689071212d38029c728724994c2e0d15 + default: 0x78867a544b3e445059196d6a5c759b466e2469628f26809c488c512b11025f843a2f85991d4e4f565b4d3d6600072d9f583c8a4c71779a3364326f3f791f1e251476633b2c7e3796299d88130834367c4361955a5e7097150922381267019e0a1c930492980353890c0b727b94681b826c55210f31205d7445054a477383526b57607f288e0e18308d412e900d278b1a427d394916351065812a408706231791 randwidth: 1280 } ] @@ -3356,7 +3261,7 @@ randcount: 288 randtype: data name_top: RndCnstKmacLfsrSeed - default: 0x84d95ca06120352218c90dfab74299e7882f53f007a8ac1bc2fdebbdb82764e00b66018 + default: 0x50b10232a8b3c33a6017b97036561aa26231042404e5ef74645be00ea5b567dbb5dabac0 randwidth: 288 } { @@ -3366,7 +3271,7 @@ randcount: 800 randtype: perm name_top: RndCnstKmacLfsrPerm - default: 0x4cee8bec251404612580ea97bfcc67feaea09b2a9cac4ad901bc79c15ba36869177092c56855872356de28c4b869cd47d6b7861330f16a6dd1672c5421df86eef62f1a4fa75285ed5d502bca7e9eef52614983a04aa9da0613db9a4713a00280423d8616deb8002c092406be4b5b830c0a989190d0589d06980f4cd970dcc1c385e5ba050c9f27651507558a3e2d05ed34782f844f7c0a46a00d6232773fe27a60e7a12405c8553a52521906c0ce6034af25c9293ae74d43bb96f69a1606f86e8f2a91e9aaa76da4a5c87e88311c847295297ed88791060d669bc0814635b49f796c05622677f17a3be15a42fead4c23c2572ce7951a321519a3d699af9f12e5731acca931387d2940fe3f2a11967e28439ef75c6336da4880c5b1d612059510e50c2e21066b2a052d240fca81c1180e8748776065a41151a6a2483401008d9bf1ce9957e52c0bc46258aa6490dd821dfb9cdac2f67a24ea2195932ecea77aad915867accc2e942198bca20cf256ed2445cc3ebd42a564d85b7890c5915fc753a264a6535a00f56f6310f03ac8149b56fea5c547da387579594160a41c05712231bba33805cf94dc237036a78214b0688e48e7a82ea59707768d53aa64aa0fa57144b9d5b2dcba2ab9b2aa4a8e1c4f29f0d50511a29520e08b81c63ce4a49999d2dd7923a058b8719af80d965f214b8e2b1e1237d8c85d9c50cc2834eb7ac55bab1b878062859161a8344c2197e155114f49c6fd12921970eb4bcf3450f2aaed98b0d85507438f10295a58c1db49ccb29c9c1da910b226c22d5140252a918842365e1325d08f9c2862da1fbe0d199a4fbe8c7c7ee85a5c37d41f82717b071371db10830a3e99b6886d9641e956c362ab446dccb890d949827b08ba0c7355e1727d17bac4cafd8522030389e793623c12bb54ee40b6cea15314011a2faa1168941066b301f998de635cb2324262ad6782a7fc1d50c3453259a75959da1d115def38626c0ac4f6ae22c495981c717a1bd44dfe374f182e065fe8b686088dedb052389f2e919df3a33197263e0e563482cd3fa69c7011bc45f3eed77501a644238313f0e0d29e0cd288b097ae18497d26dbc5e50b1349e4ecec6d141c04f95b66a1eea8634850a4ed5797bb3180a714a9ca1d1268950260bb19e3111c63ad01647c9888d92de31b171b52b661c0c4a009c79220f126268de8d15a3515c80b1b74ca96c144c62f0abeea7c09d921ee04903911349f63b2b80a974e5056cf2d26eacdb9405c404044945fd1014cc188053d929b512426c95a9479dafb3e0b709c7e1fda81595db12425b1a920a54091a36ed244e5c050dd63f48a06e612fed101dae6b489b182237edf8f5e9772f40c5376daf70f8ce660ad41ebcb58e1907006cc0392a93b72b0ae91d + default: 0x7c88fa95bd35adfaa50f8c257ae05f4f47bc2dfd52c77bc11dbb97129c52ac510c0ee6766d81556f5a245b55b39fe08b5b066a275c42437e544a5a9087e4c1bc2c74e618622148c7453109a88d44f26d5f7143c89327dfb5e44b781c04c668301bc6dce2b7003a480592ea70951760d02a0de2b8e198d0c3760149c88b41cd27c4eeb44cdab157bd6bc635053f8f1430d561a5a276157b1fe7a020375e184e637a6ba006775c97f28d559484435d7306ca193d7b99e8a6d2b4260859c1b5191dea01437fc290f0665b196a7e04803028a95b5486b841e492678362a4849f77b5df6febb5e997be4e722430bedae5acfa25120019c11b9cf05e7e73b17942b694e5d07111a2582838de450d06164192300c300e6b580ab5929ae94b90b63050d72af79edc61ca653d0caa209a76e9a7123519d451c45cba2bf9f2dd7691f6687e01eab009cc1a0043c0091302f70ea13a2241898cacdb8888b4998ae8154f2591549dd22e14d5d70436e6c0a2a3500e6242560f8ea65178806c5832de9816504535b4099b6912b32e162167b06e5489a937e829569b5180b38cf82308d85caa7c0e9770ed1f71d2def6a4549c79a310d1e4ef1c0ea208eb01371c2498137d95a4d02db808016b18575fc8f5ee031182e97057841baa444feb7c3dfa06104aa9017746d78c324de9361251b4cc2b197490a3351ebd26e739ea0fbcc503127dc5625bd3094aa020d4ad2c1eba9a86c59f89396d1f02e2e6d936497b8a3f63a11541b6c7da73fcb108d87bf8b2bb57c587137261a3f4e57d016990a6aa2fd666d7919d64725c3ddbe15ac70c58109af88283f4b9aa8a091a3c4742b0a3cd778e5a28de23640da421c8c1ece58991b08ecbae1cbc627b26312cdd43452cac2d4210c64023c59a5f8fab2a56fab001eb209e735a58b4ccb10a44e878a66db2ad1a3d4fb9c4835581d324a057d933208ab0e5b18c5d1b2a02b28e0dceb8d89c09eaf13a2e7ceb5054769d21621a26b3ecb419ef690701ff1b4e6fc07c606c2ff114005646ab9ef280d295a5426c58f40c2a629132a71991de602a382a11b1264a33f0e4b62c9aae916db91a659af8381610b592584658ba3558091b2a10191e5ba3862f3914175caf43954528571781208b0d86dbb18538824bf7a8fc82e7974232520484d8398ad2f0f42b48481570a2c48467469c682ef3e43b222545f9e5834590d26945b08878a5a15951cc361d482a05334a12b7d6d22557631f052f66e129ab5bab903f11239af670c5022cd0cc511ea064923b6865e71c8738130874924c8bba5c54674be194f6bb0cb1031a935512d59f8a4ce108bc03698aba87a7a14041639d99b3bd535805334e07a31899884f72d3e716ca699ac9bd25085d56781a5aa9d9028b539e713598 randwidth: 8000 } { @@ -3376,7 +3281,7 @@ randcount: 800 randtype: data name_top: RndCnstKmacBufferLfsrSeed - default: 0x6289edd5f001dcd4095890a290a9b632f0395d11cac7f7e9e764add7ede232a4e00dabf1d1d2ad2e2a5133f6a12ff2ec1569bef1f0b924c470ac5a99809985dc415ba1eaced382d54c9e378d030ea5d37665d43a035f4ea1e463032a3a8e24b4547f8b0d + default: 0xe0895d76f862ef81f419e3c6cdc8662c71eac141666e443c6492d9bcf7a82420750e5dfc5e3ed4f2907532e179ebec7ed7d3a5ef4982f73ed91c4b1cd0c85ec5e548b40184a69eb1e54396460e36c55c459efe9e43836fe878e464337ebcae3238dcdf7d randwidth: 800 } { @@ -3386,7 +3291,7 @@ randcount: 64 randtype: perm name_top: RndCnstKmacMsgPerm - default: 0xf26d18fc86ef733e0574e4467bd8d0b7306ea649ef974e850588bb5061a2af9e51d6adc3a9238d40ab007f74991fc6c + default: 0xb325f95b999abb791af95301b78da7294e114832e8033c759061db34f6803f5f62cdcbe927f04c523b5bcae01b558ba randwidth: 384 } ] @@ -3411,7 +3316,7 @@ randcount: 288 randtype: data name_top: RndCnstOtbnUrndPrngSeed - default: 0xa69f03f5a88525a587cedea90913bbce814e6794df2bdd99e66d07801b027bd4e9bf578b + default: 0x5a54ff19343cb32040b3490768889d27e0ba8588d34c05bcf127dae58b65d6a251088099 randwidth: 288 } { @@ -3421,7 +3326,7 @@ randcount: 256 randtype: perm name_top: RndCnstOtbnBnMacUrndPerm - default: 0x4f22173c8f0bd8bb254be88d77c0ec4522fe26c27cb1e12a13bfa0fa0a33cdb4f6d8f4abcd0c2c6ed295c91dd00a20278153a3369f5d6103ffcda5d90ee9963fdd5e49559ab6e25390942c1d2f196c0acc9b606cfe85a9a1bdcde1116b708f774fe9cd88e34c3ec26d420eb1f8d7e5fb0eae1b1d3184035984c5176e30592032bfbb8b58987ae37f624cd8a0a720b53f456f9ff67137f5564ce851df33e1cafb39386e63d419ddfc54b0157bb62842d941971e730d14ecc7b8070bf4d17d91a5ba6c78c9eba66ca387de583a5f86a2eaa7981977a22b9482aad2c9ba407a7505832280de0774323efa9319f4765b47545a84936e90c68445e4682606b616f14 + default: 0xc115938cd4a11dc9f317b8b072122379f24d6c4ec52d82637327fdd0da53e7a0d764f513ad4610213c20889939eb09bba6a4b9e8a39b140ae66dd95a8ff6ddc245327fb51c702c757bee312668dbd561ca57bdc436e4cb9f418d34ea16ba8e1eb23fe36ba9f07698e08719ffbc80664b8bed4233d690f7a53e187400dc11355bc006963d022f240fd22bef776037e22a04b4be928558a7f8014ce90cc80b9ae55469aa2852c38a1fae486f407c4fabc7255d3afed12e945efc05fbac1b6259afd367296a0e55a86544869eec22430d08dfd8a2898197b7f1f43b7e7dcd38ce565c6e3091c67a9d4a7851fa49e1509cb683bf4784f9de035f951acfccb10771b3 randwidth: 2048 } { @@ -3431,7 +3336,7 @@ randcount: 128 randtype: data name_top: RndCnstOtbnOtbnKey - default: 0xcacaea4e16ef75a4823ee1bf100b50c3 + default: 0xa4d3d73871fdaf5ad0c1dd1e95f99d71 randwidth: 128 } { @@ -3441,7 +3346,7 @@ randcount: 64 randtype: data name_top: RndCnstOtbnOtbnNonce - default: 0xa2c1ba79a60bd0d9 + default: 0x29ca6861a4425b9c randwidth: 64 } ] @@ -3466,7 +3371,7 @@ randcount: 64 randtype: data name_top: RndCnstKeymgrDpeLfsrSeed - default: 0x47c26d8d3c3874c6 + default: 0xc42edba88a15b752 randwidth: 64 } { @@ -3476,7 +3381,7 @@ randcount: 64 randtype: perm name_top: RndCnstKeymgrDpeLfsrPerm - default: 0xf901836e0753a55cc7f7c8b1798288351dd932ac3b58fd7fb09d1a7eba027259f2bcbd84040b7a9941633b95e4852e2e + default: 0xb63956d31ac318f23c2c7edada2e28cb781e5ec055cd943f26100ea9cf9117d29f0b548d4faa5b11d60cbf0926e6e9d4 randwidth: 384 } { @@ -3486,7 +3391,7 @@ randcount: 32 randtype: perm name_top: RndCnstKeymgrDpeRandPerm - default: 0x38cca5a1c161125e4333f5df1ec9bbd7e9800ad5 + default: 0x85e8b7fa3bfa8a310247d131c9e596722a93742d randwidth: 160 } { @@ -3496,7 +3401,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeRevisionSeed - default: 0x650a85c30237536dc3e35040de9ac1a6f2b35c99fb71e1aaab3c208383adf503 + default: 0x227a978179aa2e6adc5ea5fd83777d387766ba9e8c77a65b1aad174dd41aca70 randwidth: 256 } { @@ -3506,7 +3411,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeSoftOutputSeed - default: 0x11ff71fd46921923a8cd8c6ff98f9bdfc2b205d8690dd35500e5a51bba34a71d + default: 0xd3807ba54e793023fa711994ccf5d2f42daffa84621ab157014b70509da8413d randwidth: 256 } { @@ -3516,7 +3421,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeHardOutputSeed - default: 0x81e9eb876b6f1996b2be4b58dfcfb830b9e25bdaa3e1affa91806d01a89bdf50 + default: 0xda43fecdd6c1a58693232d1c3e361d856ab2d1dc6455d87f13c9a4671446bea8 randwidth: 256 } { @@ -3526,7 +3431,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeAesSeed - default: 0x84c3f043fe74b4ff850b4a6dea97774b63ef1e13ca69b8bb7dae3157b7279a2b + default: 0x56d5fbb54bb5b253a70bc372cfc9bb0ab38a5edabee7d224d1a668378437dd24 randwidth: 256 } { @@ -3536,7 +3441,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeKmacSeed - default: 0xd0f45178add4099b463a9bfadeb0a249e67a25feea95e50b27dedc6815c375b4 + default: 0x797b602b068c0a1aeca298c96a8130ab336462cee1bf8c653fde5a40a24df78e randwidth: 256 } { @@ -3546,7 +3451,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeOtbnSeed - default: 0xbd85e84aeb69c3f4db751585b16ed45d55a6c1ffd5c92099cdeea949dc968ac7 + default: 0x146916dc55f8ce6dbfaad08910fbe1822c22a17a376fa1315c0cb3c29cf4d10a randwidth: 256 } { @@ -3556,7 +3461,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeNoneSeed - default: 0x991c5514057a6a15faa577395193cde4a6705bd11203330a927a8ce1ac88224 + default: 0xe5c8f0c7b034bf23c9068e307d8513b7734aa78cc36f947a2737bbc0acd1447b randwidth: 256 } ] @@ -3581,7 +3486,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivNonProduction - default: 0xa441c4192abe1dc426feee2c9b1c8b34b1a821afe522e11c4049d9b85f9dc3c99a37868579b46a84095ea981140ff7f0 + default: 0xaa83c3fc818bb3b4a840ad3214ceb3f354ca2e089302c3ee1d695aa616283205db05cd6c18888ad01fe046eafd8bf298 randwidth: 384 } { @@ -3591,7 +3496,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivProduction - default: 0xc4ad73d59726774a37e33560266d52a2d9c4901261c19f480238c0197cfa2c9010eefdd66d4b91725b5e1a95a1411451 + default: 0xdb7d5fe0fd32a29689a0c1549c28c210c01ff7e6e6d20e0404e7b51d020aa3695df42597cacaea4e16ef75a4823ee1bf randwidth: 384 } ] @@ -3631,7 +3536,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramKey - default: 0xc3da5967f2cc89f1b0eca3388f277ffa + default: 0x100b50c3a2c1ba79a60bd0d947c26d8d randwidth: 128 } { @@ -3641,7 +3546,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramNonce - default: 0xe4319b4144b76b7c902a9c89f6f8f885 + default: 0x3c3874c6b8e34a85925ce73b8f155098 randwidth: 128 } { @@ -3651,7 +3556,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMainLfsrSeed - default: 0x6d8b76b9b8ec2f4f + default: 0x5eb503e8e4071315 randwidth: 64 } { @@ -3661,7 +3566,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMainLfsrPerm - default: 0x706fb310ee91c18db25cd085feca6164c79d007408e6ef4f4ca977d7c0662f46a28d4b784a856abd6824edfc499dbac3 + default: 0x548bb3ca4d68806b6f35d30e5bcc0749103b85714f8a64eb07461441b8f8a99c43eac7a92be27769ff7909cda59ff10b randwidth: 384 } ] @@ -3701,7 +3606,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlSecSramKey - default: 0xd474657b77f7eda1a07047f937051a05 + default: 0x25ec69547062345c400f5ef1b06a119 randwidth: 128 } { @@ -3711,7 +3616,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlSecSramNonce - default: 0x7461414b8b3587c6de71b922084ec4ea + default: 0x650a85c30237536dc3e35040de9ac1a6 randwidth: 128 } { @@ -3721,7 +3626,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlSecLfsrSeed - default: 0x31a97e0acb1acb48 + default: 0xf2b35c99fb71e1aa randwidth: 64 } { @@ -3731,7 +3636,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlSecLfsrPerm - default: 0xe2bab79b975a58a183a4527ef0bc6ef6507b87f733d53b5560e780d2c5e7314202d916528ef12440f7cdc1b822e87a32 + default: 0x158ded08e4f2a76f9e9783332a8b907d4be2d5d64b2575929f0ea1ec7374e550da06c9b16e3ffd1a445c100afc8083ea randwidth: 384 } ] @@ -3771,7 +3676,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrlScrNonce - default: 0x29ee296da1850be6 + default: 0xca69b8bb7dae3157 randwidth: 64 } { @@ -3781,7 +3686,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrlScrKey - default: 0xbed073f6ee870f58b89fabfe08c82783 + default: 0xb7279a2bd0f45178add4099b463a9bfa randwidth: 128 } ] @@ -3806,7 +3711,7 @@ randcount: 32 randtype: data name_top: RndCnstRvCoreIbexLfsrSeed - default: 0x7c7867ee + default: 0xdeb0a249 randwidth: 32 } { @@ -3816,7 +3721,7 @@ randcount: 32 randtype: perm name_top: RndCnstRvCoreIbexLfsrPerm - default: 0xd1bc70db288506ae7c5db826f2912c936abdba38 + default: 0x1fb7401d1fd454c2cccbae2f94c2ce137a1911fc randwidth: 160 } { @@ -3826,7 +3731,7 @@ randcount: 128 randtype: data name_top: RndCnstRvCoreIbexIbexKeyDefault - default: 0xe90caeae11cb84b65fdc5c702578f9f8 + default: 0x57a6a15faa577395193cde4a6705bd11 randwidth: 128 } { @@ -3836,7 +3741,7 @@ randcount: 64 randtype: data name_top: RndCnstRvCoreIbexIbexNonceDefault - default: 0x93c20a2865ef55e0 + default: 0x203330a927a8ce1a randwidth: 64 } ] diff --git a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson index 6801195138b66..4f5a11908a6e7 100644 --- a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson +++ b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson @@ -113,11 +113,6 @@ "0x94949494", "0x94949494", "0x94949494", - "0x94949494", - "0x94949494", - "0x94949494", - "0x94949494", - "0x94949494", ], }, { @@ -168,19 +163,19 @@ }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", - value: "0x363b8f75", + value: "0x18cbd487", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", - value: "0x5893a89a", + value: "0x7663f368", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", - value: "0xacd84c1f", + value: "0x822817ed", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", - value: "0xf2ed003e", + value: "0xdc1d5bcc", }, { name: "OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG", diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index 6bb988e4287f1..50227ed1025b7 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -427,78 +427,75 @@ The first EDN instance, `u_edn0` is intended to be configured to deliver entropy ### Pinout -| ID | Name | Bank | Type | Connection Type | Description | -|:-----|:-----------------|:-------|:-------------|:------------------|:-------------------------------------------| -| 0 | POR_N | VCC | InputStd | manual | System reset | -| 1 | USB_P | VCC | DualBidirTol | manual | USB P signal | -| 2 | USB_N | VCC | DualBidirTol | manual | USB N signal | -| 3 | CC1 | AVCC | BidirTol | manual | ADC input 1 | -| 4 | CC2 | AVCC | BidirTol | manual | ADC input 2 | -| 5 | FLASH_TEST_VOLT | VCC | AnalogIn0 | manual | Flash test voltage input | -| 6 | FLASH_TEST_MODE0 | VCC | InputStd | manual | Flash test mode signal | -| 7 | FLASH_TEST_MODE1 | VCC | InputStd | manual | Flash test mode signal | -| 8 | RRAM_ANALOG | VCC | AnalogIn0 | manual | RRAM analog test signal | -| 9 | SPI_HOST_D0 | VIOA | BidirStd | direct | SPI host data | -| 10 | SPI_HOST_D1 | VIOA | BidirStd | direct | SPI host data | -| 11 | SPI_HOST_D2 | VIOA | BidirStd | direct | SPI host data | -| 12 | SPI_HOST_D3 | VIOA | BidirStd | direct | SPI host data | -| 13 | SPI_HOST_CLK | VIOA | BidirStd | direct | SPI host clock | -| 14 | SPI_HOST_CS_L | VIOA | BidirStd | direct | SPI host chip select | -| 15 | SPI_DEV_D0 | VIOA | BidirStd | direct | SPI device data | -| 16 | SPI_DEV_D1 | VIOA | BidirStd | direct | SPI device data | -| 17 | SPI_DEV_D2 | VIOA | BidirStd | direct | SPI device data | -| 18 | SPI_DEV_D3 | VIOA | BidirStd | direct | SPI device data | -| 19 | SPI_DEV_CLK | VIOA | InputStd | direct | SPI device clock | -| 20 | SPI_DEV_CS_L | VIOA | InputStd | direct | SPI device chip select | -| 0 | IOA0 | VIOA | BidirStd | muxed | Muxed IO pad | -| 1 | IOA1 | VIOA | BidirStd | muxed | Muxed IO pad | -| 2 | IOA2 | VIOA | BidirStd | muxed | Muxed IO pad | -| 3 | IOA3 | VIOA | BidirStd | muxed | Muxed IO pad | -| 4 | IOA4 | VIOA | BidirStd | muxed | Muxed IO pad | -| 5 | IOA5 | VIOA | BidirStd | muxed | Muxed IO pad | -| 6 | IOA6 | VIOA | BidirOd | muxed | Muxed IO pad | -| 7 | IOA7 | VIOA | BidirOd | muxed | Muxed IO pad | -| 8 | IOA8 | VIOA | BidirOd | muxed | Muxed IO pad | -| 9 | IOB0 | VIOB | BidirStd | muxed | Muxed IO pad | -| 10 | IOB1 | VIOB | BidirStd | muxed | Muxed IO pad | -| 11 | IOB2 | VIOB | BidirStd | muxed | Muxed IO pad | -| 12 | IOB3 | VIOB | BidirStd | muxed | Muxed IO pad | -| 13 | IOB4 | VIOB | BidirStd | muxed | Muxed IO pad | -| 14 | IOB5 | VIOB | BidirStd | muxed | Muxed IO pad | -| 15 | IOB6 | VIOB | BidirStd | muxed | Muxed IO pad | -| 16 | IOB7 | VIOB | BidirStd | muxed | Muxed IO pad | -| 17 | IOB8 | VIOB | BidirStd | muxed | Muxed IO pad | -| 18 | IOB9 | VIOB | BidirOd | muxed | Muxed IO pad | -| 19 | IOB10 | VIOB | BidirOd | muxed | Muxed IO pad | -| 20 | IOB11 | VIOB | BidirOd | muxed | Muxed IO pad | -| 21 | IOB12 | VIOB | BidirOd | muxed | Muxed IO pad | -| 22 | IOC0 | VCC | BidirStd | muxed | Muxed IO pad | -| 23 | IOC1 | VCC | BidirStd | muxed | Muxed IO pad | -| 24 | IOC2 | VCC | BidirStd | muxed | Muxed IO pad | -| 25 | IOC3 | VCC | BidirStd | muxed | Muxed IO pad | -| 26 | IOC4 | VCC | BidirStd | muxed | Muxed IO pad | -| 27 | IOC5 | VCC | BidirStd | muxed | Muxed IO pad | -| 28 | IOC6 | VCC | BidirStd | muxed | Muxed IO pad | -| 29 | IOC7 | VCC | BidirStd | muxed | Muxed IO pad | -| 30 | IOC8 | VCC | BidirStd | muxed | Muxed IO pad | -| 31 | IOC9 | VCC | BidirStd | muxed | Muxed IO pad | -| 32 | IOC10 | VCC | BidirOd | muxed | Muxed IO pad | -| 33 | IOC11 | VCC | BidirOd | muxed | Muxed IO pad | -| 34 | IOC12 | VCC | BidirOd | muxed | Muxed IO pad | -| 35 | IOR0 | VCC | BidirStd | muxed | Muxed IO pad | -| 36 | IOR1 | VCC | BidirStd | muxed | Muxed IO pad | -| 37 | IOR2 | VCC | BidirStd | muxed | Muxed IO pad | -| 38 | IOR3 | VCC | BidirStd | muxed | Muxed IO pad | -| 39 | IOR4 | VCC | BidirStd | muxed | Muxed IO pad | -| 40 | IOR5 | VCC | BidirStd | muxed | Muxed IO pad | -| 41 | IOR6 | VCC | BidirStd | muxed | Muxed IO pad | -| 42 | IOR7 | VCC | BidirStd | muxed | Muxed IO pad | -| 21 | IOR8 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (ec_rst_l) | -| 22 | IOR9 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (flash_wp_l)) | -| 43 | IOR10 | VCC | BidirOd | muxed | Muxed IO pad | -| 44 | IOR11 | VCC | BidirOd | muxed | Muxed IO pad | -| 45 | IOR12 | VCC | BidirOd | muxed | Muxed IO pad | -| 46 | IOR13 | VCC | BidirOd | muxed | Muxed IO pad | +| ID | Name | Bank | Type | Connection Type | Description | +|:-----|:--------------|:-------|:-------------|:------------------|:-------------------------------------------| +| 0 | POR_N | VCC | InputStd | manual | System reset | +| 1 | USB_P | VCC | DualBidirTol | manual | USB P signal | +| 2 | USB_N | VCC | DualBidirTol | manual | USB N signal | +| 3 | CC1 | AVCC | BidirTol | manual | ADC input 1 | +| 4 | CC2 | AVCC | BidirTol | manual | ADC input 2 | +| 5 | RRAM_ANALOG | VCC | AnalogIn0 | manual | RRAM analog test signal | +| 6 | SPI_HOST_D0 | VIOA | BidirStd | direct | SPI host data | +| 7 | SPI_HOST_D1 | VIOA | BidirStd | direct | SPI host data | +| 8 | SPI_HOST_D2 | VIOA | BidirStd | direct | SPI host data | +| 9 | SPI_HOST_D3 | VIOA | BidirStd | direct | SPI host data | +| 10 | SPI_HOST_CLK | VIOA | BidirStd | direct | SPI host clock | +| 11 | SPI_HOST_CS_L | VIOA | BidirStd | direct | SPI host chip select | +| 12 | SPI_DEV_D0 | VIOA | BidirStd | direct | SPI device data | +| 13 | SPI_DEV_D1 | VIOA | BidirStd | direct | SPI device data | +| 14 | SPI_DEV_D2 | VIOA | BidirStd | direct | SPI device data | +| 15 | SPI_DEV_D3 | VIOA | BidirStd | direct | SPI device data | +| 16 | SPI_DEV_CLK | VIOA | InputStd | direct | SPI device clock | +| 17 | SPI_DEV_CS_L | VIOA | InputStd | direct | SPI device chip select | +| 0 | IOA0 | VIOA | BidirStd | muxed | Muxed IO pad | +| 1 | IOA1 | VIOA | BidirStd | muxed | Muxed IO pad | +| 2 | IOA2 | VIOA | BidirStd | muxed | Muxed IO pad | +| 3 | IOA3 | VIOA | BidirStd | muxed | Muxed IO pad | +| 4 | IOA4 | VIOA | BidirStd | muxed | Muxed IO pad | +| 5 | IOA5 | VIOA | BidirStd | muxed | Muxed IO pad | +| 6 | IOA6 | VIOA | BidirOd | muxed | Muxed IO pad | +| 7 | IOA7 | VIOA | BidirOd | muxed | Muxed IO pad | +| 8 | IOA8 | VIOA | BidirOd | muxed | Muxed IO pad | +| 9 | IOB0 | VIOB | BidirStd | muxed | Muxed IO pad | +| 10 | IOB1 | VIOB | BidirStd | muxed | Muxed IO pad | +| 11 | IOB2 | VIOB | BidirStd | muxed | Muxed IO pad | +| 12 | IOB3 | VIOB | BidirStd | muxed | Muxed IO pad | +| 13 | IOB4 | VIOB | BidirStd | muxed | Muxed IO pad | +| 14 | IOB5 | VIOB | BidirStd | muxed | Muxed IO pad | +| 15 | IOB6 | VIOB | BidirStd | muxed | Muxed IO pad | +| 16 | IOB7 | VIOB | BidirStd | muxed | Muxed IO pad | +| 17 | IOB8 | VIOB | BidirStd | muxed | Muxed IO pad | +| 18 | IOB9 | VIOB | BidirOd | muxed | Muxed IO pad | +| 19 | IOB10 | VIOB | BidirOd | muxed | Muxed IO pad | +| 20 | IOB11 | VIOB | BidirOd | muxed | Muxed IO pad | +| 21 | IOB12 | VIOB | BidirOd | muxed | Muxed IO pad | +| 22 | IOC0 | VCC | BidirStd | muxed | Muxed IO pad | +| 23 | IOC1 | VCC | BidirStd | muxed | Muxed IO pad | +| 24 | IOC2 | VCC | BidirStd | muxed | Muxed IO pad | +| 25 | IOC3 | VCC | BidirStd | muxed | Muxed IO pad | +| 26 | IOC4 | VCC | BidirStd | muxed | Muxed IO pad | +| 27 | IOC5 | VCC | BidirStd | muxed | Muxed IO pad | +| 28 | IOC6 | VCC | BidirStd | muxed | Muxed IO pad | +| 29 | IOC7 | VCC | BidirStd | muxed | Muxed IO pad | +| 30 | IOC8 | VCC | BidirStd | muxed | Muxed IO pad | +| 31 | IOC9 | VCC | BidirStd | muxed | Muxed IO pad | +| 32 | IOC10 | VCC | BidirOd | muxed | Muxed IO pad | +| 33 | IOC11 | VCC | BidirOd | muxed | Muxed IO pad | +| 34 | IOC12 | VCC | BidirOd | muxed | Muxed IO pad | +| 35 | IOR0 | VCC | BidirStd | muxed | Muxed IO pad | +| 36 | IOR1 | VCC | BidirStd | muxed | Muxed IO pad | +| 37 | IOR2 | VCC | BidirStd | muxed | Muxed IO pad | +| 38 | IOR3 | VCC | BidirStd | muxed | Muxed IO pad | +| 39 | IOR4 | VCC | BidirStd | muxed | Muxed IO pad | +| 40 | IOR5 | VCC | BidirStd | muxed | Muxed IO pad | +| 41 | IOR6 | VCC | BidirStd | muxed | Muxed IO pad | +| 42 | IOR7 | VCC | BidirStd | muxed | Muxed IO pad | +| 18 | IOR8 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (ec_rst_l) | +| 19 | IOR9 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (flash_wp_l)) | +| 43 | IOR10 | VCC | BidirOd | muxed | Muxed IO pad | +| 44 | IOR11 | VCC | BidirOd | muxed | Muxed IO pad | +| 45 | IOR12 | VCC | BidirOd | muxed | Muxed IO pad | +| 46 | IOR13 | VCC | BidirOd | muxed | Muxed IO pad | diff --git a/hw/top_earlgrey/doc/memory_map.md b/hw/top_earlgrey/doc/memory_map.md index 2c4b2b50fd7bb..1ea572e06bf98 100644 --- a/hw/top_earlgrey/doc/memory_map.md +++ b/hw/top_earlgrey/doc/memory_map.md @@ -40,8 +40,6 @@ The main address space, shared between the CPU and DM | ast | default | `0x40480000` | `0x400` | `0x100` | ast | | sensor_ctrl | default | `0x40490000` | `0x80` | `0x20` | sensor_ctrl | | sram_ctrl_ret | regs | `0x40500000` | `0x40` | `0x10` | regs device on sram_ctrl_ret | -| flash_ctrl | core | `0x41000000` | `0x200` | `0x80` | core device on flash_ctrl | -| flash_ctrl | prim | `0x41008000` | `0x80` | `0x20` | prim device on flash_ctrl | | rram_ctrl | core | `0x41010000` | `0x200` | `0x80` | core device on rram_ctrl | | rram_macro | prim | `0x41018000` | `0x10` | `0x4` | prim device on rram_macro | | rv_dm | regs | `0x41200000` | `0x10` | `0x4` | regs device on rv_dm | @@ -66,7 +64,6 @@ The main address space, shared between the CPU and DM | Memory | Interface | Base Address | Size (bytes) | Size (words) | |----------------|-------------|----------------|----------------|----------------| | sram_ctrl_ret | ram | `0x40600000` | `0x1000` | `0x400` | -| flash_ctrl | mem | `0x20000000` | `0x100000` | `0x40000` | | rram_ctrl | host | `0x30000000` | `0x200000` | `0x80000` | | sram_ctrl_main | ram | `0x10000000` | `0x20000` | `0x8000` | | sram_ctrl_sec | ram | `0x10020000` | `0x10000` | `0x4000` | diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index ef7be56e5ea27..e0c9b685bb319 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv @@ -37,39 +37,34 @@ assign alert_if[29].alert_tx = `PD_AON_HIER.u_aon_timer.alert_tx_o[0]; assign alert_if[30].alert_tx = `PD_AON_HIER.u_sensor_ctrl.alert_tx_o[0]; assign alert_if[31].alert_tx = `PD_AON_HIER.u_sensor_ctrl.alert_tx_o[1]; assign alert_if[32].alert_tx = `PD_AON_HIER.u_sram_ctrl_ret.alert_tx_o[0]; -assign alert_if[33].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[0]; -assign alert_if[34].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[1]; -assign alert_if[35].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[2]; -assign alert_if[36].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[3]; -assign alert_if[37].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[4]; -assign alert_if[38].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[0]; -assign alert_if[39].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[1]; -assign alert_if[40].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[2]; -assign alert_if[41].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[3]; -assign alert_if[42].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[4]; -assign alert_if[43].alert_tx = `PD_MAIN_HIER.u_rv_dm.alert_tx_o[0]; -assign alert_if[44].alert_tx = `PD_MAIN_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[45].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[0]; -assign alert_if[46].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[1]; -assign alert_if[47].alert_tx = `PD_MAIN_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[48].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[49].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[1]; -assign alert_if[50].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[51].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[52].alert_tx = `PD_MAIN_HIER.u_keymgr_dpe.alert_tx_o[0]; -assign alert_if[53].alert_tx = `PD_MAIN_HIER.u_keymgr_dpe.alert_tx_o[1]; -assign alert_if[54].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[55].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[1]; -assign alert_if[56].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[57].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[58].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[59].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[1]; -assign alert_if[60].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[61].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[1]; -assign alert_if[62].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[63].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_sec.alert_tx_o[0]; -assign alert_if[64].alert_tx = `PD_MAIN_HIER.u_rom_ctrl.alert_tx_o[0]; -assign alert_if[65].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[0]; -assign alert_if[66].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[1]; -assign alert_if[67].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[2]; -assign alert_if[68].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[3]; +assign alert_if[33].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[0]; +assign alert_if[34].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[1]; +assign alert_if[35].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[2]; +assign alert_if[36].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[3]; +assign alert_if[37].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[4]; +assign alert_if[38].alert_tx = `PD_MAIN_HIER.u_rv_dm.alert_tx_o[0]; +assign alert_if[39].alert_tx = `PD_MAIN_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[40].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[0]; +assign alert_if[41].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[1]; +assign alert_if[42].alert_tx = `PD_MAIN_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[43].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[44].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[1]; +assign alert_if[45].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[46].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[47].alert_tx = `PD_MAIN_HIER.u_keymgr_dpe.alert_tx_o[0]; +assign alert_if[48].alert_tx = `PD_MAIN_HIER.u_keymgr_dpe.alert_tx_o[1]; +assign alert_if[49].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[50].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[1]; +assign alert_if[51].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[52].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[53].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[54].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[1]; +assign alert_if[55].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[56].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[1]; +assign alert_if[57].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[58].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_sec.alert_tx_o[0]; +assign alert_if[59].alert_tx = `PD_MAIN_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[60].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[0]; +assign alert_if[61].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[1]; +assign alert_if[62].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[2]; +assign alert_if[63].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[3]; diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 243ceb779a4fd..0d6afe3d82c62 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -48,9 +48,6 @@ tl_if rom_ctrl__regs_tl_if(clk_main, rst_n); tl_if spi_host0_tl_if(clk_io, rst_n); tl_if spi_host1_tl_if(clk_io_div2, rst_n); tl_if usbdev_tl_if(clk_usb, rst_n); -tl_if flash_ctrl__core_tl_if(clk_main, rst_n); -tl_if flash_ctrl__prim_tl_if(clk_main, rst_n); -tl_if flash_ctrl__mem_tl_if(clk_main, rst_n); tl_if rram_ctrl__core_tl_if(clk_main, rst_n); tl_if rram_macro__prim_tl_if(clk_main, rst_n); tl_if rram_ctrl__host_tl_if(clk_main, rst_n); @@ -132,9 +129,6 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl, main) `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl, main) `DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl, main) - `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl, main) - `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl, main) - `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(rram_ctrl__core, rram_ctrl, core_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(rram_macro__prim, rram_macro, prim_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(rram_ctrl__host, rram_ctrl, host_tl, main) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 04aaa2ba55a60..e188ea8c5655b 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -28,15 +28,6 @@ tl_device_t xbar_devices[$] = '{ '{"usbdev", '{ '{32'h40320000, 32'h40320fff} }}, - '{"flash_ctrl__core", '{ - '{32'h41000000, 32'h410001ff} - }}, - '{"flash_ctrl__prim", '{ - '{32'h41008000, 32'h4100807f} - }}, - '{"flash_ctrl__mem", '{ - '{32'h20000000, 32'h200fffff} - }}, '{"rram_ctrl__core", '{ '{32'h41010000, 32'h410101ff} }}, @@ -171,7 +162,6 @@ tl_host_t xbar_hosts[$] = '{ "rv_dm__mem", "sram_ctrl_main__ram", "sram_ctrl_sec__ram", - "flash_ctrl__mem", "rram_ctrl__host"}} , '{"rv_core_ibex__cored", 1, '{ @@ -208,9 +198,6 @@ tl_host_t xbar_hosts[$] = '{ "spi_host0", "spi_host1", "usbdev", - "flash_ctrl__core", - "flash_ctrl__prim", - "flash_ctrl__mem", "rram_ctrl__core", "rram_ctrl__host", "rram_macro__prim", @@ -262,9 +249,6 @@ tl_host_t xbar_hosts[$] = '{ "spi_host0", "spi_host1", "usbdev", - "flash_ctrl__core", - "flash_ctrl__prim", - "flash_ctrl__mem", "rram_ctrl__core", "rram_ctrl__host", "rram_macro__prim", diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 6c82abdb8ae0a..43111c6f93f5f 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -46,15 +46,6 @@ -node tb.dut*.u_usbdev tl_*i.a_address[19:18] -node tb.dut*.u_usbdev tl_*i.a_address[29:22] -node tb.dut*.u_usbdev tl_*i.a_address[31:31] --node tb.dut*.u_flash_ctrl core_tl_*i.a_address[23:9] --node tb.dut*.u_flash_ctrl core_tl_*i.a_address[29:25] --node tb.dut*.u_flash_ctrl core_tl_*i.a_address[31:31] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[14:7] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[23:16] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[29:25] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[31:31] --node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[28:20] --node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[31:30] -node tb.dut*.u_rram_ctrl core_tl_*i.a_address[15:9] -node tb.dut*.u_rram_ctrl core_tl_*i.a_address[23:17] -node tb.dut*.u_rram_ctrl core_tl_*i.a_address[29:25] diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 4ef7141e64efa..bc70d578d2480 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv @@ -4,7 +4,7 @@ // Generated by topgen.py -parameter uint NUM_ALERTS = 69; +parameter uint NUM_ALERTS = 64; parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "uart0_fatal_fault", "uart1_fatal_fault", @@ -39,11 +39,6 @@ parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "sensor_ctrl_recov_alert", "sensor_ctrl_fatal_alert", "sram_ctrl_ret_fatal_error", - "flash_ctrl_recov_err", - "flash_ctrl_fatal_std_err", - "flash_ctrl_fatal_err", - "flash_ctrl_fatal_prim_flash_alert", - "flash_ctrl_recov_prim_flash_alert", "rram_ctrl_recov_err", "rram_ctrl_fatal_std_err", "rram_ctrl_fatal_err", diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index d6a01c4fe69c3..7f710c37f64a5 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -63,7 +63,6 @@ rv_dm.mem sram_ctrl_main.ram sram_ctrl_sec.ram - flash_ctrl.mem rram_ctrl.host ] rv_core_ibex.cored: @@ -78,9 +77,6 @@ spi_host0 spi_host1 usbdev - flash_ctrl.core - flash_ctrl.prim - flash_ctrl.mem rram_ctrl.core rram_ctrl.host rram_macro.prim @@ -110,9 +106,6 @@ spi_host0 spi_host1 usbdev - flash_ctrl.core - flash_ctrl.prim - flash_ctrl.mem rram_ctrl.core rram_ctrl.host rram_macro.prim @@ -355,72 +348,6 @@ stub: false pipeline: true } - { - name: flash_ctrl.core - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x41000000 - } - size_byte: 0x200 - } - ] - xbar: false - stub: false - pipeline: true - } - { - name: flash_ctrl.prim - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x41008000 - } - size_byte: 0x80 - } - ] - xbar: false - stub: false - pipeline: true - } - { - name: flash_ctrl.mem - type: device - clock: clk_main_i - reset: rst_main_ni - req_fifo_pass: false - rsp_fifo_pass: false - inst_type: flash_ctrl - addr_range: - [ - { - base_addrs: - { - hart: 0x20000000 - } - size_byte: 0x100000 - } - ] - xbar: false - stub: false - pipeline: true - } { name: rram_ctrl.core type: device @@ -971,45 +898,6 @@ top_signame: usbdev_tl index: -1 } - { - name: tl_flash_ctrl__core - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_core_tl - index: -1 - } - { - name: tl_flash_ctrl__prim - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_prim_tl - index: -1 - } - { - name: tl_flash_ctrl__mem - struct: tl - package: tlul_pkg - type: req_rsp - act: req - inst_name: main - width: 1 - default: "" - domain: Main - top_signame: flash_ctrl_mem_tl - index: -1 - } { name: tl_rram_ctrl__core struct: tl diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 05d4d4acde367..9703b23da28e0 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson @@ -79,24 +79,6 @@ act: "req" package: "tlul_pkg" } - { struct: "tl" - type: "req_rsp" - name: "tl_flash_ctrl__core" - act: "req" - package: "tlul_pkg" - } - { struct: "tl" - type: "req_rsp" - name: "tl_flash_ctrl__prim" - act: "req" - package: "tlul_pkg" - } - { struct: "tl" - type: "req_rsp" - name: "tl_flash_ctrl__mem" - act: "req" - package: "tlul_pkg" - } { struct: "tl" type: "req_rsp" name: "tl_rram_ctrl__core" diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index d9a7c3b44e40b..74ede25bbc660 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -39,9 +39,6 @@ initial force dut.rst_spi_host1_ni = rst_n; `CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_spi_host0_i, rst_n) `CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_spi_host1_i, rst_n) `CONNECT_TL_DEVICE_IF(usbdev, dut, clk_usb_i, rst_n) -`CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rram_ctrl__core, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rram_macro__prim, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rram_ctrl__host, dut, clk_main_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index 854ad899853ea..65a5cac002acf 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -44,15 +44,6 @@ -node tb.dut tl_usbdev_o.a_address[19:18] -node tb.dut tl_usbdev_o.a_address[29:22] -node tb.dut tl_usbdev_o.a_address[31:31] --node tb.dut tl_flash_ctrl__core_o.a_address[23:9] --node tb.dut tl_flash_ctrl__core_o.a_address[29:25] --node tb.dut tl_flash_ctrl__core_o.a_address[31:31] --node tb.dut tl_flash_ctrl__prim_o.a_address[14:7] --node tb.dut tl_flash_ctrl__prim_o.a_address[23:16] --node tb.dut tl_flash_ctrl__prim_o.a_address[29:25] --node tb.dut tl_flash_ctrl__prim_o.a_address[31:31] --node tb.dut tl_flash_ctrl__mem_o.a_address[28:20] --node tb.dut tl_flash_ctrl__mem_o.a_address[31:30] -node tb.dut tl_rram_ctrl__core_o.a_address[15:9] -node tb.dut tl_rram_ctrl__core_o.a_address[23:17] -node tb.dut tl_rram_ctrl__core_o.a_address[29:25] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 32a8c87c5a58f..2cf7e23883ebb 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -32,15 +32,6 @@ tl_device_t xbar_devices[$] = '{ '{"usbdev", '{ '{32'h40320000, 32'h40320fff} }}, - '{"flash_ctrl__core", '{ - '{32'h41000000, 32'h410001ff} - }}, - '{"flash_ctrl__prim", '{ - '{32'h41008000, 32'h4100807f} - }}, - '{"flash_ctrl__mem", '{ - '{32'h20000000, 32'h200fffff} - }}, '{"rram_ctrl__core", '{ '{32'h41010000, 32'h410101ff} }}, @@ -103,7 +94,6 @@ tl_host_t xbar_hosts[$] = '{ "rv_dm__mem", "sram_ctrl_main__ram", "sram_ctrl_sec__ram", - "flash_ctrl__mem", "rram_ctrl__host"}} , '{"rv_core_ibex__cored", 1, '{ @@ -117,9 +107,6 @@ tl_host_t xbar_hosts[$] = '{ "spi_host0", "spi_host1", "usbdev", - "flash_ctrl__core", - "flash_ctrl__prim", - "flash_ctrl__mem", "rram_ctrl__core", "rram_ctrl__host", "rram_macro__prim", @@ -148,9 +135,6 @@ tl_host_t xbar_hosts[$] = '{ "spi_host0", "spi_host1", "usbdev", - "flash_ctrl__core", - "flash_ctrl__prim", - "flash_ctrl__mem", "rram_ctrl__core", "rram_ctrl__host", "rram_macro__prim", diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 18a7537677006..339f4a86d0c00 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -74,24 +74,6 @@ module xbar_main_bind; .h2d (tl_usbdev_o), .d2h (tl_usbdev_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__core ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .h2d (tl_flash_ctrl__core_o), - .d2h (tl_flash_ctrl__core_i) - ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__prim ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .h2d (tl_flash_ctrl__prim_o), - .d2h (tl_flash_ctrl__prim_i) - ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__mem ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .h2d (tl_flash_ctrl__mem_o), - .d2h (tl_flash_ctrl__mem_i) - ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rram_ctrl__core ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 00a21b3580cae..8117c07595611 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -17,9 +17,6 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 40300000; localparam logic [31:0] ADDR_SPACE_SPI_HOST1 = 32'h 40310000; localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40320000; - localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000; - localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000; - localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000; localparam logic [31:0] ADDR_SPACE_RRAM_CTRL__CORE = 32'h 41010000; localparam logic [31:0] ADDR_SPACE_RRAM_MACRO__PRIM = 32'h 41018000; localparam logic [31:0] ADDR_SPACE_RRAM_CTRL__HOST = 32'h 30000000; @@ -50,9 +47,6 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_SPI_HOST1 = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 000001ff; - localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 0000007f; - localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 000fffff; localparam logic [31:0] ADDR_MASK_RRAM_CTRL__CORE = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_RRAM_MACRO__PRIM = 32'h 0000000f; localparam logic [31:0] ADDR_MASK_RRAM_CTRL__HOST = 32'h 001fffff; @@ -73,7 +67,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_SEC__RAM = 32'h 0000ffff; localparam int N_HOST = 3; - localparam int N_DEVICE = 29; + localparam int N_DEVICE = 26; typedef enum int { TlRvDmRegs = 0, @@ -84,27 +78,24 @@ package tl_main_pkg; TlSpiHost0 = 5, TlSpiHost1 = 6, TlUsbdev = 7, - TlFlashCtrlCore = 8, - TlFlashCtrlPrim = 9, - TlFlashCtrlMem = 10, - TlRramCtrlCore = 11, - TlRramMacroPrim = 12, - TlRramCtrlHost = 13, - TlHmac = 14, - TlKmac = 15, - TlAes = 16, - TlEntropySrc = 17, - TlCsrng = 18, - TlEdn0 = 19, - TlEdn1 = 20, - TlRvPlic = 21, - TlOtbn = 22, - TlKeymgrDpe = 23, - TlRvCoreIbexCfg = 24, - TlSramCtrlMainRegs = 25, - TlSramCtrlMainRam = 26, - TlSramCtrlSecRegs = 27, - TlSramCtrlSecRam = 28 + TlRramCtrlCore = 8, + TlRramMacroPrim = 9, + TlRramCtrlHost = 10, + TlHmac = 11, + TlKmac = 12, + TlAes = 13, + TlEntropySrc = 14, + TlCsrng = 15, + TlEdn0 = 16, + TlEdn1 = 17, + TlRvPlic = 18, + TlOtbn = 19, + TlKeymgrDpe = 20, + TlRvCoreIbexCfg = 21, + TlSramCtrlMainRegs = 22, + TlSramCtrlMainRam = 23, + TlSramCtrlSecRegs = 24, + TlSramCtrlSecRam = 25 } tl_device_e; typedef enum int { diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index 2a4f444d56213..15f6f2351fdf3 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -7,146 +7,132 @@ // // Interconnect // rv_core_ibex.corei -// -> s1n_32 -// -> sm1_33 +// -> s1n_29 +// -> sm1_30 // -> rom_ctrl.rom -// -> sm1_34 +// -> sm1_31 // -> rv_dm.mem -// -> sm1_35 +// -> sm1_32 // -> sram_ctrl_main.ram -// -> sm1_36 +// -> sm1_33 // -> sram_ctrl_sec.ram -// -> sm1_37 -// -> flash_ctrl.mem -// -> sm1_38 +// -> sm1_34 // -> rram_ctrl.host // rv_core_ibex.cored -// -> s1n_39 -// -> sm1_33 +// -> s1n_35 +// -> sm1_30 // -> rom_ctrl.rom -// -> sm1_40 +// -> sm1_36 // -> rom_ctrl.regs -// -> sm1_34 +// -> sm1_31 // -> rv_dm.mem -// -> sm1_41 +// -> sm1_37 // -> rv_dm.regs -// -> sm1_35 +// -> sm1_32 // -> sram_ctrl_main.ram -// -> sm1_36 +// -> sm1_33 // -> sram_ctrl_sec.ram +// -> sm1_39 +// -> asf_38 +// -> peri +// -> sm1_41 +// -> asf_40 +// -> spi_host0 // -> sm1_43 // -> asf_42 -// -> peri +// -> spi_host1 // -> sm1_45 // -> asf_44 -// -> spi_host0 -// -> sm1_47 -// -> asf_46 -// -> spi_host1 -// -> sm1_49 -// -> asf_48 // -> usbdev -// -> sm1_50 -// -> flash_ctrl.core -// -> sm1_51 -// -> flash_ctrl.prim -// -> sm1_37 -// -> flash_ctrl.mem -// -> sm1_52 +// -> sm1_46 // -> rram_ctrl.core -// -> sm1_38 +// -> sm1_34 // -> rram_ctrl.host -// -> sm1_53 +// -> sm1_47 // -> rram_macro.prim -// -> sm1_54 +// -> sm1_48 // -> aes -// -> sm1_55 +// -> sm1_49 // -> entropy_src -// -> sm1_56 +// -> sm1_50 // -> csrng -// -> sm1_57 +// -> sm1_51 // -> edn0 -// -> sm1_58 +// -> sm1_52 // -> edn1 -// -> sm1_59 +// -> sm1_53 // -> hmac -// -> sm1_60 +// -> sm1_54 // -> rv_plic -// -> sm1_61 +// -> sm1_55 // -> otbn -// -> sm1_62 +// -> sm1_56 // -> keymgr_dpe -// -> sm1_63 +// -> sm1_57 // -> kmac -// -> sm1_64 +// -> sm1_58 // -> sram_ctrl_main.regs -// -> sm1_65 +// -> sm1_59 // -> sram_ctrl_sec.regs -// -> sm1_66 +// -> sm1_60 // -> rv_core_ibex.cfg // rv_dm.sba -// -> s1n_67 -// -> sm1_33 +// -> s1n_61 +// -> sm1_30 // -> rom_ctrl.rom -// -> sm1_40 +// -> sm1_36 // -> rom_ctrl.regs -// -> sm1_34 +// -> sm1_31 // -> rv_dm.mem -// -> sm1_41 +// -> sm1_37 // -> rv_dm.regs -// -> sm1_35 +// -> sm1_32 // -> sram_ctrl_main.ram -// -> sm1_36 +// -> sm1_33 // -> sram_ctrl_sec.ram +// -> sm1_39 +// -> asf_38 +// -> peri +// -> sm1_41 +// -> asf_40 +// -> spi_host0 // -> sm1_43 // -> asf_42 -// -> peri +// -> spi_host1 // -> sm1_45 // -> asf_44 -// -> spi_host0 -// -> sm1_47 -// -> asf_46 -// -> spi_host1 -// -> sm1_49 -// -> asf_48 // -> usbdev -// -> sm1_50 -// -> flash_ctrl.core -// -> sm1_51 -// -> flash_ctrl.prim -// -> sm1_37 -// -> flash_ctrl.mem -// -> sm1_52 +// -> sm1_46 // -> rram_ctrl.core -// -> sm1_38 +// -> sm1_34 // -> rram_ctrl.host -// -> sm1_53 +// -> sm1_47 // -> rram_macro.prim -// -> sm1_54 +// -> sm1_48 // -> aes -// -> sm1_55 +// -> sm1_49 // -> entropy_src -// -> sm1_56 +// -> sm1_50 // -> csrng -// -> sm1_57 +// -> sm1_51 // -> edn0 -// -> sm1_58 +// -> sm1_52 // -> edn1 -// -> sm1_59 +// -> sm1_53 // -> hmac -// -> sm1_60 +// -> sm1_54 // -> rv_plic -// -> sm1_61 +// -> sm1_55 // -> otbn -// -> sm1_62 +// -> sm1_56 // -> keymgr_dpe -// -> sm1_63 +// -> sm1_57 // -> kmac -// -> sm1_64 +// -> sm1_58 // -> sram_ctrl_main.regs -// -> sm1_65 +// -> sm1_59 // -> sram_ctrl_sec.regs -// -> sm1_66 +// -> sm1_60 // -> rv_core_ibex.cfg module xbar_main ( @@ -186,12 +172,6 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_spi_host1_i, output tlul_pkg::tl_h2d_t tl_usbdev_o, input tlul_pkg::tl_d2h_t tl_usbdev_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl__core_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl__core_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl__prim_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl__prim_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl__mem_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl__mem_i, output tlul_pkg::tl_h2d_t tl_rram_ctrl__core_o, input tlul_pkg::tl_d2h_t tl_rram_ctrl__core_i, output tlul_pkg::tl_h2d_t tl_rram_macro__prim_o, @@ -240,15 +220,36 @@ module xbar_main ( logic unused_scanmode; assign unused_scanmode = ^scanmode_i; - tl_h2d_t tl_s1n_32_us_h2d ; - tl_d2h_t tl_s1n_32_us_d2h ; + tl_h2d_t tl_s1n_29_us_h2d ; + tl_d2h_t tl_s1n_29_us_d2h ; - tl_h2d_t tl_s1n_32_ds_h2d [6]; - tl_d2h_t tl_s1n_32_ds_d2h [6]; + tl_h2d_t tl_s1n_29_ds_h2d [5]; + tl_d2h_t tl_s1n_29_ds_d2h [5]; // Create steering signal - logic [2:0] dev_sel_s1n_32; + logic [2:0] dev_sel_s1n_29; + + + tl_h2d_t tl_sm1_30_us_h2d [3]; + tl_d2h_t tl_sm1_30_us_d2h [3]; + + tl_h2d_t tl_sm1_30_ds_h2d ; + tl_d2h_t tl_sm1_30_ds_d2h ; + + + tl_h2d_t tl_sm1_31_us_h2d [3]; + tl_d2h_t tl_sm1_31_us_d2h [3]; + + tl_h2d_t tl_sm1_31_ds_h2d ; + tl_d2h_t tl_sm1_31_ds_d2h ; + + + tl_h2d_t tl_sm1_32_us_h2d [3]; + tl_d2h_t tl_sm1_32_us_d2h [3]; + + tl_h2d_t tl_sm1_32_ds_h2d ; + tl_d2h_t tl_sm1_32_ds_d2h ; tl_h2d_t tl_sm1_33_us_h2d [3]; @@ -264,50 +265,46 @@ module xbar_main ( tl_h2d_t tl_sm1_34_ds_h2d ; tl_d2h_t tl_sm1_34_ds_d2h ; + tl_h2d_t tl_s1n_35_us_h2d ; + tl_d2h_t tl_s1n_35_us_d2h ; - tl_h2d_t tl_sm1_35_us_h2d [3]; - tl_d2h_t tl_sm1_35_us_d2h [3]; - tl_h2d_t tl_sm1_35_ds_h2d ; - tl_d2h_t tl_sm1_35_ds_d2h ; + tl_h2d_t tl_s1n_35_ds_h2d [26]; + tl_d2h_t tl_s1n_35_ds_d2h [26]; + + // Create steering signal + logic [4:0] dev_sel_s1n_35; - tl_h2d_t tl_sm1_36_us_h2d [3]; - tl_d2h_t tl_sm1_36_us_d2h [3]; + tl_h2d_t tl_sm1_36_us_h2d [2]; + tl_d2h_t tl_sm1_36_us_d2h [2]; tl_h2d_t tl_sm1_36_ds_h2d ; tl_d2h_t tl_sm1_36_ds_d2h ; - tl_h2d_t tl_sm1_37_us_h2d [3]; - tl_d2h_t tl_sm1_37_us_d2h [3]; + tl_h2d_t tl_sm1_37_us_h2d [2]; + tl_d2h_t tl_sm1_37_us_d2h [2]; tl_h2d_t tl_sm1_37_ds_h2d ; tl_d2h_t tl_sm1_37_ds_d2h ; + tl_h2d_t tl_asf_38_us_h2d ; + tl_d2h_t tl_asf_38_us_d2h ; + tl_h2d_t tl_asf_38_ds_h2d ; + tl_d2h_t tl_asf_38_ds_d2h ; - tl_h2d_t tl_sm1_38_us_h2d [3]; - tl_d2h_t tl_sm1_38_us_d2h [3]; - - tl_h2d_t tl_sm1_38_ds_h2d ; - tl_d2h_t tl_sm1_38_ds_d2h ; - tl_h2d_t tl_s1n_39_us_h2d ; - tl_d2h_t tl_s1n_39_us_d2h ; + tl_h2d_t tl_sm1_39_us_h2d [2]; + tl_d2h_t tl_sm1_39_us_d2h [2]; + tl_h2d_t tl_sm1_39_ds_h2d ; + tl_d2h_t tl_sm1_39_ds_d2h ; - tl_h2d_t tl_s1n_39_ds_h2d [29]; - tl_d2h_t tl_s1n_39_ds_d2h [29]; - - // Create steering signal - logic [4:0] dev_sel_s1n_39; - - - tl_h2d_t tl_sm1_40_us_h2d [2]; - tl_d2h_t tl_sm1_40_us_d2h [2]; - - tl_h2d_t tl_sm1_40_ds_h2d ; - tl_d2h_t tl_sm1_40_ds_d2h ; + tl_h2d_t tl_asf_40_us_h2d ; + tl_d2h_t tl_asf_40_us_d2h ; + tl_h2d_t tl_asf_40_ds_h2d ; + tl_d2h_t tl_asf_40_ds_d2h ; tl_h2d_t tl_sm1_41_us_h2d [2]; @@ -340,10 +337,12 @@ module xbar_main ( tl_h2d_t tl_sm1_45_ds_h2d ; tl_d2h_t tl_sm1_45_ds_d2h ; - tl_h2d_t tl_asf_46_us_h2d ; - tl_d2h_t tl_asf_46_us_d2h ; - tl_h2d_t tl_asf_46_ds_h2d ; - tl_d2h_t tl_asf_46_ds_d2h ; + + tl_h2d_t tl_sm1_46_us_h2d [2]; + tl_d2h_t tl_sm1_46_us_d2h [2]; + + tl_h2d_t tl_sm1_46_ds_h2d ; + tl_d2h_t tl_sm1_46_ds_d2h ; tl_h2d_t tl_sm1_47_us_h2d [2]; @@ -352,10 +351,12 @@ module xbar_main ( tl_h2d_t tl_sm1_47_ds_h2d ; tl_d2h_t tl_sm1_47_ds_d2h ; - tl_h2d_t tl_asf_48_us_h2d ; - tl_d2h_t tl_asf_48_us_d2h ; - tl_h2d_t tl_asf_48_ds_h2d ; - tl_d2h_t tl_asf_48_ds_d2h ; + + tl_h2d_t tl_sm1_48_us_h2d [2]; + tl_d2h_t tl_sm1_48_us_d2h [2]; + + tl_h2d_t tl_sm1_48_ds_h2d ; + tl_d2h_t tl_sm1_48_ds_d2h ; tl_h2d_t tl_sm1_49_us_h2d [2]; @@ -441,632 +442,532 @@ module xbar_main ( tl_h2d_t tl_sm1_60_ds_h2d ; tl_d2h_t tl_sm1_60_ds_d2h ; + tl_h2d_t tl_s1n_61_us_h2d ; + tl_d2h_t tl_s1n_61_us_d2h ; - tl_h2d_t tl_sm1_61_us_h2d [2]; - tl_d2h_t tl_sm1_61_us_d2h [2]; - - tl_h2d_t tl_sm1_61_ds_h2d ; - tl_d2h_t tl_sm1_61_ds_d2h ; - - - tl_h2d_t tl_sm1_62_us_h2d [2]; - tl_d2h_t tl_sm1_62_us_d2h [2]; - - tl_h2d_t tl_sm1_62_ds_h2d ; - tl_d2h_t tl_sm1_62_ds_d2h ; - - - tl_h2d_t tl_sm1_63_us_h2d [2]; - tl_d2h_t tl_sm1_63_us_d2h [2]; - - tl_h2d_t tl_sm1_63_ds_h2d ; - tl_d2h_t tl_sm1_63_ds_d2h ; - - - tl_h2d_t tl_sm1_64_us_h2d [2]; - tl_d2h_t tl_sm1_64_us_d2h [2]; - - tl_h2d_t tl_sm1_64_ds_h2d ; - tl_d2h_t tl_sm1_64_ds_d2h ; - - - tl_h2d_t tl_sm1_65_us_h2d [2]; - tl_d2h_t tl_sm1_65_us_d2h [2]; - - tl_h2d_t tl_sm1_65_ds_h2d ; - tl_d2h_t tl_sm1_65_ds_d2h ; - - tl_h2d_t tl_sm1_66_us_h2d [2]; - tl_d2h_t tl_sm1_66_us_d2h [2]; - - tl_h2d_t tl_sm1_66_ds_h2d ; - tl_d2h_t tl_sm1_66_ds_d2h ; - - tl_h2d_t tl_s1n_67_us_h2d ; - tl_d2h_t tl_s1n_67_us_d2h ; - - - tl_h2d_t tl_s1n_67_ds_h2d [29]; - tl_d2h_t tl_s1n_67_ds_d2h [29]; + tl_h2d_t tl_s1n_61_ds_h2d [26]; + tl_d2h_t tl_s1n_61_ds_d2h [26]; // Create steering signal - logic [4:0] dev_sel_s1n_67; - + logic [4:0] dev_sel_s1n_61; - assign tl_sm1_33_us_h2d[0] = tl_s1n_32_ds_h2d[0]; - assign tl_s1n_32_ds_d2h[0] = tl_sm1_33_us_d2h[0]; - assign tl_sm1_34_us_h2d[0] = tl_s1n_32_ds_h2d[1]; - assign tl_s1n_32_ds_d2h[1] = tl_sm1_34_us_d2h[0]; + assign tl_sm1_30_us_h2d[0] = tl_s1n_29_ds_h2d[0]; + assign tl_s1n_29_ds_d2h[0] = tl_sm1_30_us_d2h[0]; - assign tl_sm1_35_us_h2d[0] = tl_s1n_32_ds_h2d[2]; - assign tl_s1n_32_ds_d2h[2] = tl_sm1_35_us_d2h[0]; + assign tl_sm1_31_us_h2d[0] = tl_s1n_29_ds_h2d[1]; + assign tl_s1n_29_ds_d2h[1] = tl_sm1_31_us_d2h[0]; - assign tl_sm1_36_us_h2d[0] = tl_s1n_32_ds_h2d[3]; - assign tl_s1n_32_ds_d2h[3] = tl_sm1_36_us_d2h[0]; + assign tl_sm1_32_us_h2d[0] = tl_s1n_29_ds_h2d[2]; + assign tl_s1n_29_ds_d2h[2] = tl_sm1_32_us_d2h[0]; - assign tl_sm1_37_us_h2d[0] = tl_s1n_32_ds_h2d[4]; - assign tl_s1n_32_ds_d2h[4] = tl_sm1_37_us_d2h[0]; + assign tl_sm1_33_us_h2d[0] = tl_s1n_29_ds_h2d[3]; + assign tl_s1n_29_ds_d2h[3] = tl_sm1_33_us_d2h[0]; - assign tl_sm1_38_us_h2d[0] = tl_s1n_32_ds_h2d[5]; - assign tl_s1n_32_ds_d2h[5] = tl_sm1_38_us_d2h[0]; + assign tl_sm1_34_us_h2d[0] = tl_s1n_29_ds_h2d[4]; + assign tl_s1n_29_ds_d2h[4] = tl_sm1_34_us_d2h[0]; - assign tl_sm1_33_us_h2d[1] = tl_s1n_39_ds_h2d[0]; - assign tl_s1n_39_ds_d2h[0] = tl_sm1_33_us_d2h[1]; + assign tl_sm1_30_us_h2d[1] = tl_s1n_35_ds_h2d[0]; + assign tl_s1n_35_ds_d2h[0] = tl_sm1_30_us_d2h[1]; - assign tl_sm1_40_us_h2d[0] = tl_s1n_39_ds_h2d[1]; - assign tl_s1n_39_ds_d2h[1] = tl_sm1_40_us_d2h[0]; + assign tl_sm1_36_us_h2d[0] = tl_s1n_35_ds_h2d[1]; + assign tl_s1n_35_ds_d2h[1] = tl_sm1_36_us_d2h[0]; - assign tl_sm1_34_us_h2d[1] = tl_s1n_39_ds_h2d[2]; - assign tl_s1n_39_ds_d2h[2] = tl_sm1_34_us_d2h[1]; + assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[2]; + assign tl_s1n_35_ds_d2h[2] = tl_sm1_31_us_d2h[1]; - assign tl_sm1_41_us_h2d[0] = tl_s1n_39_ds_h2d[3]; - assign tl_s1n_39_ds_d2h[3] = tl_sm1_41_us_d2h[0]; + assign tl_sm1_37_us_h2d[0] = tl_s1n_35_ds_h2d[3]; + assign tl_s1n_35_ds_d2h[3] = tl_sm1_37_us_d2h[0]; - assign tl_sm1_35_us_h2d[1] = tl_s1n_39_ds_h2d[4]; - assign tl_s1n_39_ds_d2h[4] = tl_sm1_35_us_d2h[1]; + assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[4]; + assign tl_s1n_35_ds_d2h[4] = tl_sm1_32_us_d2h[1]; - assign tl_sm1_36_us_h2d[1] = tl_s1n_39_ds_h2d[5]; - assign tl_s1n_39_ds_d2h[5] = tl_sm1_36_us_d2h[1]; + assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[5]; + assign tl_s1n_35_ds_d2h[5] = tl_sm1_33_us_d2h[1]; - assign tl_sm1_43_us_h2d[0] = tl_s1n_39_ds_h2d[6]; - assign tl_s1n_39_ds_d2h[6] = tl_sm1_43_us_d2h[0]; + assign tl_sm1_39_us_h2d[0] = tl_s1n_35_ds_h2d[6]; + assign tl_s1n_35_ds_d2h[6] = tl_sm1_39_us_d2h[0]; - assign tl_sm1_45_us_h2d[0] = tl_s1n_39_ds_h2d[7]; - assign tl_s1n_39_ds_d2h[7] = tl_sm1_45_us_d2h[0]; + assign tl_sm1_41_us_h2d[0] = tl_s1n_35_ds_h2d[7]; + assign tl_s1n_35_ds_d2h[7] = tl_sm1_41_us_d2h[0]; - assign tl_sm1_47_us_h2d[0] = tl_s1n_39_ds_h2d[8]; - assign tl_s1n_39_ds_d2h[8] = tl_sm1_47_us_d2h[0]; + assign tl_sm1_43_us_h2d[0] = tl_s1n_35_ds_h2d[8]; + assign tl_s1n_35_ds_d2h[8] = tl_sm1_43_us_d2h[0]; - assign tl_sm1_49_us_h2d[0] = tl_s1n_39_ds_h2d[9]; - assign tl_s1n_39_ds_d2h[9] = tl_sm1_49_us_d2h[0]; + assign tl_sm1_45_us_h2d[0] = tl_s1n_35_ds_h2d[9]; + assign tl_s1n_35_ds_d2h[9] = tl_sm1_45_us_d2h[0]; - assign tl_sm1_50_us_h2d[0] = tl_s1n_39_ds_h2d[10]; - assign tl_s1n_39_ds_d2h[10] = tl_sm1_50_us_d2h[0]; + assign tl_sm1_46_us_h2d[0] = tl_s1n_35_ds_h2d[10]; + assign tl_s1n_35_ds_d2h[10] = tl_sm1_46_us_d2h[0]; - assign tl_sm1_51_us_h2d[0] = tl_s1n_39_ds_h2d[11]; - assign tl_s1n_39_ds_d2h[11] = tl_sm1_51_us_d2h[0]; + assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[11]; + assign tl_s1n_35_ds_d2h[11] = tl_sm1_34_us_d2h[1]; - assign tl_sm1_37_us_h2d[1] = tl_s1n_39_ds_h2d[12]; - assign tl_s1n_39_ds_d2h[12] = tl_sm1_37_us_d2h[1]; + assign tl_sm1_47_us_h2d[0] = tl_s1n_35_ds_h2d[12]; + assign tl_s1n_35_ds_d2h[12] = tl_sm1_47_us_d2h[0]; - assign tl_sm1_52_us_h2d[0] = tl_s1n_39_ds_h2d[13]; - assign tl_s1n_39_ds_d2h[13] = tl_sm1_52_us_d2h[0]; + assign tl_sm1_48_us_h2d[0] = tl_s1n_35_ds_h2d[13]; + assign tl_s1n_35_ds_d2h[13] = tl_sm1_48_us_d2h[0]; - assign tl_sm1_38_us_h2d[1] = tl_s1n_39_ds_h2d[14]; - assign tl_s1n_39_ds_d2h[14] = tl_sm1_38_us_d2h[1]; + assign tl_sm1_49_us_h2d[0] = tl_s1n_35_ds_h2d[14]; + assign tl_s1n_35_ds_d2h[14] = tl_sm1_49_us_d2h[0]; - assign tl_sm1_53_us_h2d[0] = tl_s1n_39_ds_h2d[15]; - assign tl_s1n_39_ds_d2h[15] = tl_sm1_53_us_d2h[0]; + assign tl_sm1_50_us_h2d[0] = tl_s1n_35_ds_h2d[15]; + assign tl_s1n_35_ds_d2h[15] = tl_sm1_50_us_d2h[0]; - assign tl_sm1_54_us_h2d[0] = tl_s1n_39_ds_h2d[16]; - assign tl_s1n_39_ds_d2h[16] = tl_sm1_54_us_d2h[0]; + assign tl_sm1_51_us_h2d[0] = tl_s1n_35_ds_h2d[16]; + assign tl_s1n_35_ds_d2h[16] = tl_sm1_51_us_d2h[0]; - assign tl_sm1_55_us_h2d[0] = tl_s1n_39_ds_h2d[17]; - assign tl_s1n_39_ds_d2h[17] = tl_sm1_55_us_d2h[0]; + assign tl_sm1_52_us_h2d[0] = tl_s1n_35_ds_h2d[17]; + assign tl_s1n_35_ds_d2h[17] = tl_sm1_52_us_d2h[0]; - assign tl_sm1_56_us_h2d[0] = tl_s1n_39_ds_h2d[18]; - assign tl_s1n_39_ds_d2h[18] = tl_sm1_56_us_d2h[0]; + assign tl_sm1_53_us_h2d[0] = tl_s1n_35_ds_h2d[18]; + assign tl_s1n_35_ds_d2h[18] = tl_sm1_53_us_d2h[0]; - assign tl_sm1_57_us_h2d[0] = tl_s1n_39_ds_h2d[19]; - assign tl_s1n_39_ds_d2h[19] = tl_sm1_57_us_d2h[0]; + assign tl_sm1_54_us_h2d[0] = tl_s1n_35_ds_h2d[19]; + assign tl_s1n_35_ds_d2h[19] = tl_sm1_54_us_d2h[0]; - assign tl_sm1_58_us_h2d[0] = tl_s1n_39_ds_h2d[20]; - assign tl_s1n_39_ds_d2h[20] = tl_sm1_58_us_d2h[0]; + assign tl_sm1_55_us_h2d[0] = tl_s1n_35_ds_h2d[20]; + assign tl_s1n_35_ds_d2h[20] = tl_sm1_55_us_d2h[0]; - assign tl_sm1_59_us_h2d[0] = tl_s1n_39_ds_h2d[21]; - assign tl_s1n_39_ds_d2h[21] = tl_sm1_59_us_d2h[0]; + assign tl_sm1_56_us_h2d[0] = tl_s1n_35_ds_h2d[21]; + assign tl_s1n_35_ds_d2h[21] = tl_sm1_56_us_d2h[0]; - assign tl_sm1_60_us_h2d[0] = tl_s1n_39_ds_h2d[22]; - assign tl_s1n_39_ds_d2h[22] = tl_sm1_60_us_d2h[0]; + assign tl_sm1_57_us_h2d[0] = tl_s1n_35_ds_h2d[22]; + assign tl_s1n_35_ds_d2h[22] = tl_sm1_57_us_d2h[0]; - assign tl_sm1_61_us_h2d[0] = tl_s1n_39_ds_h2d[23]; - assign tl_s1n_39_ds_d2h[23] = tl_sm1_61_us_d2h[0]; + assign tl_sm1_58_us_h2d[0] = tl_s1n_35_ds_h2d[23]; + assign tl_s1n_35_ds_d2h[23] = tl_sm1_58_us_d2h[0]; - assign tl_sm1_62_us_h2d[0] = tl_s1n_39_ds_h2d[24]; - assign tl_s1n_39_ds_d2h[24] = tl_sm1_62_us_d2h[0]; + assign tl_sm1_59_us_h2d[0] = tl_s1n_35_ds_h2d[24]; + assign tl_s1n_35_ds_d2h[24] = tl_sm1_59_us_d2h[0]; - assign tl_sm1_63_us_h2d[0] = tl_s1n_39_ds_h2d[25]; - assign tl_s1n_39_ds_d2h[25] = tl_sm1_63_us_d2h[0]; + assign tl_sm1_60_us_h2d[0] = tl_s1n_35_ds_h2d[25]; + assign tl_s1n_35_ds_d2h[25] = tl_sm1_60_us_d2h[0]; - assign tl_sm1_64_us_h2d[0] = tl_s1n_39_ds_h2d[26]; - assign tl_s1n_39_ds_d2h[26] = tl_sm1_64_us_d2h[0]; + assign tl_sm1_30_us_h2d[2] = tl_s1n_61_ds_h2d[0]; + assign tl_s1n_61_ds_d2h[0] = tl_sm1_30_us_d2h[2]; - assign tl_sm1_65_us_h2d[0] = tl_s1n_39_ds_h2d[27]; - assign tl_s1n_39_ds_d2h[27] = tl_sm1_65_us_d2h[0]; + assign tl_sm1_36_us_h2d[1] = tl_s1n_61_ds_h2d[1]; + assign tl_s1n_61_ds_d2h[1] = tl_sm1_36_us_d2h[1]; - assign tl_sm1_66_us_h2d[0] = tl_s1n_39_ds_h2d[28]; - assign tl_s1n_39_ds_d2h[28] = tl_sm1_66_us_d2h[0]; + assign tl_sm1_31_us_h2d[2] = tl_s1n_61_ds_h2d[2]; + assign tl_s1n_61_ds_d2h[2] = tl_sm1_31_us_d2h[2]; - assign tl_sm1_33_us_h2d[2] = tl_s1n_67_ds_h2d[0]; - assign tl_s1n_67_ds_d2h[0] = tl_sm1_33_us_d2h[2]; + assign tl_sm1_37_us_h2d[1] = tl_s1n_61_ds_h2d[3]; + assign tl_s1n_61_ds_d2h[3] = tl_sm1_37_us_d2h[1]; - assign tl_sm1_40_us_h2d[1] = tl_s1n_67_ds_h2d[1]; - assign tl_s1n_67_ds_d2h[1] = tl_sm1_40_us_d2h[1]; + assign tl_sm1_32_us_h2d[2] = tl_s1n_61_ds_h2d[4]; + assign tl_s1n_61_ds_d2h[4] = tl_sm1_32_us_d2h[2]; - assign tl_sm1_34_us_h2d[2] = tl_s1n_67_ds_h2d[2]; - assign tl_s1n_67_ds_d2h[2] = tl_sm1_34_us_d2h[2]; + assign tl_sm1_33_us_h2d[2] = tl_s1n_61_ds_h2d[5]; + assign tl_s1n_61_ds_d2h[5] = tl_sm1_33_us_d2h[2]; - assign tl_sm1_41_us_h2d[1] = tl_s1n_67_ds_h2d[3]; - assign tl_s1n_67_ds_d2h[3] = tl_sm1_41_us_d2h[1]; + assign tl_sm1_39_us_h2d[1] = tl_s1n_61_ds_h2d[6]; + assign tl_s1n_61_ds_d2h[6] = tl_sm1_39_us_d2h[1]; - assign tl_sm1_35_us_h2d[2] = tl_s1n_67_ds_h2d[4]; - assign tl_s1n_67_ds_d2h[4] = tl_sm1_35_us_d2h[2]; + assign tl_sm1_41_us_h2d[1] = tl_s1n_61_ds_h2d[7]; + assign tl_s1n_61_ds_d2h[7] = tl_sm1_41_us_d2h[1]; - assign tl_sm1_36_us_h2d[2] = tl_s1n_67_ds_h2d[5]; - assign tl_s1n_67_ds_d2h[5] = tl_sm1_36_us_d2h[2]; + assign tl_sm1_43_us_h2d[1] = tl_s1n_61_ds_h2d[8]; + assign tl_s1n_61_ds_d2h[8] = tl_sm1_43_us_d2h[1]; - assign tl_sm1_43_us_h2d[1] = tl_s1n_67_ds_h2d[6]; - assign tl_s1n_67_ds_d2h[6] = tl_sm1_43_us_d2h[1]; + assign tl_sm1_45_us_h2d[1] = tl_s1n_61_ds_h2d[9]; + assign tl_s1n_61_ds_d2h[9] = tl_sm1_45_us_d2h[1]; - assign tl_sm1_45_us_h2d[1] = tl_s1n_67_ds_h2d[7]; - assign tl_s1n_67_ds_d2h[7] = tl_sm1_45_us_d2h[1]; + assign tl_sm1_46_us_h2d[1] = tl_s1n_61_ds_h2d[10]; + assign tl_s1n_61_ds_d2h[10] = tl_sm1_46_us_d2h[1]; - assign tl_sm1_47_us_h2d[1] = tl_s1n_67_ds_h2d[8]; - assign tl_s1n_67_ds_d2h[8] = tl_sm1_47_us_d2h[1]; + assign tl_sm1_34_us_h2d[2] = tl_s1n_61_ds_h2d[11]; + assign tl_s1n_61_ds_d2h[11] = tl_sm1_34_us_d2h[2]; - assign tl_sm1_49_us_h2d[1] = tl_s1n_67_ds_h2d[9]; - assign tl_s1n_67_ds_d2h[9] = tl_sm1_49_us_d2h[1]; + assign tl_sm1_47_us_h2d[1] = tl_s1n_61_ds_h2d[12]; + assign tl_s1n_61_ds_d2h[12] = tl_sm1_47_us_d2h[1]; - assign tl_sm1_50_us_h2d[1] = tl_s1n_67_ds_h2d[10]; - assign tl_s1n_67_ds_d2h[10] = tl_sm1_50_us_d2h[1]; + assign tl_sm1_48_us_h2d[1] = tl_s1n_61_ds_h2d[13]; + assign tl_s1n_61_ds_d2h[13] = tl_sm1_48_us_d2h[1]; - assign tl_sm1_51_us_h2d[1] = tl_s1n_67_ds_h2d[11]; - assign tl_s1n_67_ds_d2h[11] = tl_sm1_51_us_d2h[1]; + assign tl_sm1_49_us_h2d[1] = tl_s1n_61_ds_h2d[14]; + assign tl_s1n_61_ds_d2h[14] = tl_sm1_49_us_d2h[1]; - assign tl_sm1_37_us_h2d[2] = tl_s1n_67_ds_h2d[12]; - assign tl_s1n_67_ds_d2h[12] = tl_sm1_37_us_d2h[2]; + assign tl_sm1_50_us_h2d[1] = tl_s1n_61_ds_h2d[15]; + assign tl_s1n_61_ds_d2h[15] = tl_sm1_50_us_d2h[1]; - assign tl_sm1_52_us_h2d[1] = tl_s1n_67_ds_h2d[13]; - assign tl_s1n_67_ds_d2h[13] = tl_sm1_52_us_d2h[1]; + assign tl_sm1_51_us_h2d[1] = tl_s1n_61_ds_h2d[16]; + assign tl_s1n_61_ds_d2h[16] = tl_sm1_51_us_d2h[1]; - assign tl_sm1_38_us_h2d[2] = tl_s1n_67_ds_h2d[14]; - assign tl_s1n_67_ds_d2h[14] = tl_sm1_38_us_d2h[2]; + assign tl_sm1_52_us_h2d[1] = tl_s1n_61_ds_h2d[17]; + assign tl_s1n_61_ds_d2h[17] = tl_sm1_52_us_d2h[1]; - assign tl_sm1_53_us_h2d[1] = tl_s1n_67_ds_h2d[15]; - assign tl_s1n_67_ds_d2h[15] = tl_sm1_53_us_d2h[1]; + assign tl_sm1_53_us_h2d[1] = tl_s1n_61_ds_h2d[18]; + assign tl_s1n_61_ds_d2h[18] = tl_sm1_53_us_d2h[1]; - assign tl_sm1_54_us_h2d[1] = tl_s1n_67_ds_h2d[16]; - assign tl_s1n_67_ds_d2h[16] = tl_sm1_54_us_d2h[1]; + assign tl_sm1_54_us_h2d[1] = tl_s1n_61_ds_h2d[19]; + assign tl_s1n_61_ds_d2h[19] = tl_sm1_54_us_d2h[1]; - assign tl_sm1_55_us_h2d[1] = tl_s1n_67_ds_h2d[17]; - assign tl_s1n_67_ds_d2h[17] = tl_sm1_55_us_d2h[1]; + assign tl_sm1_55_us_h2d[1] = tl_s1n_61_ds_h2d[20]; + assign tl_s1n_61_ds_d2h[20] = tl_sm1_55_us_d2h[1]; - assign tl_sm1_56_us_h2d[1] = tl_s1n_67_ds_h2d[18]; - assign tl_s1n_67_ds_d2h[18] = tl_sm1_56_us_d2h[1]; + assign tl_sm1_56_us_h2d[1] = tl_s1n_61_ds_h2d[21]; + assign tl_s1n_61_ds_d2h[21] = tl_sm1_56_us_d2h[1]; - assign tl_sm1_57_us_h2d[1] = tl_s1n_67_ds_h2d[19]; - assign tl_s1n_67_ds_d2h[19] = tl_sm1_57_us_d2h[1]; + assign tl_sm1_57_us_h2d[1] = tl_s1n_61_ds_h2d[22]; + assign tl_s1n_61_ds_d2h[22] = tl_sm1_57_us_d2h[1]; - assign tl_sm1_58_us_h2d[1] = tl_s1n_67_ds_h2d[20]; - assign tl_s1n_67_ds_d2h[20] = tl_sm1_58_us_d2h[1]; + assign tl_sm1_58_us_h2d[1] = tl_s1n_61_ds_h2d[23]; + assign tl_s1n_61_ds_d2h[23] = tl_sm1_58_us_d2h[1]; - assign tl_sm1_59_us_h2d[1] = tl_s1n_67_ds_h2d[21]; - assign tl_s1n_67_ds_d2h[21] = tl_sm1_59_us_d2h[1]; + assign tl_sm1_59_us_h2d[1] = tl_s1n_61_ds_h2d[24]; + assign tl_s1n_61_ds_d2h[24] = tl_sm1_59_us_d2h[1]; - assign tl_sm1_60_us_h2d[1] = tl_s1n_67_ds_h2d[22]; - assign tl_s1n_67_ds_d2h[22] = tl_sm1_60_us_d2h[1]; + assign tl_sm1_60_us_h2d[1] = tl_s1n_61_ds_h2d[25]; + assign tl_s1n_61_ds_d2h[25] = tl_sm1_60_us_d2h[1]; - assign tl_sm1_61_us_h2d[1] = tl_s1n_67_ds_h2d[23]; - assign tl_s1n_67_ds_d2h[23] = tl_sm1_61_us_d2h[1]; + assign tl_s1n_29_us_h2d = tl_rv_core_ibex__corei_i; + assign tl_rv_core_ibex__corei_o = tl_s1n_29_us_d2h; - assign tl_sm1_62_us_h2d[1] = tl_s1n_67_ds_h2d[24]; - assign tl_s1n_67_ds_d2h[24] = tl_sm1_62_us_d2h[1]; + assign tl_rom_ctrl__rom_o = tl_sm1_30_ds_h2d; + assign tl_sm1_30_ds_d2h = tl_rom_ctrl__rom_i; - assign tl_sm1_63_us_h2d[1] = tl_s1n_67_ds_h2d[25]; - assign tl_s1n_67_ds_d2h[25] = tl_sm1_63_us_d2h[1]; + assign tl_rv_dm__mem_o = tl_sm1_31_ds_h2d; + assign tl_sm1_31_ds_d2h = tl_rv_dm__mem_i; - assign tl_sm1_64_us_h2d[1] = tl_s1n_67_ds_h2d[26]; - assign tl_s1n_67_ds_d2h[26] = tl_sm1_64_us_d2h[1]; + assign tl_sram_ctrl_main__ram_o = tl_sm1_32_ds_h2d; + assign tl_sm1_32_ds_d2h = tl_sram_ctrl_main__ram_i; - assign tl_sm1_65_us_h2d[1] = tl_s1n_67_ds_h2d[27]; - assign tl_s1n_67_ds_d2h[27] = tl_sm1_65_us_d2h[1]; + assign tl_sram_ctrl_sec__ram_o = tl_sm1_33_ds_h2d; + assign tl_sm1_33_ds_d2h = tl_sram_ctrl_sec__ram_i; - assign tl_sm1_66_us_h2d[1] = tl_s1n_67_ds_h2d[28]; - assign tl_s1n_67_ds_d2h[28] = tl_sm1_66_us_d2h[1]; + assign tl_rram_ctrl__host_o = tl_sm1_34_ds_h2d; + assign tl_sm1_34_ds_d2h = tl_rram_ctrl__host_i; - assign tl_s1n_32_us_h2d = tl_rv_core_ibex__corei_i; - assign tl_rv_core_ibex__corei_o = tl_s1n_32_us_d2h; + assign tl_s1n_35_us_h2d = tl_rv_core_ibex__cored_i; + assign tl_rv_core_ibex__cored_o = tl_s1n_35_us_d2h; - assign tl_rom_ctrl__rom_o = tl_sm1_33_ds_h2d; - assign tl_sm1_33_ds_d2h = tl_rom_ctrl__rom_i; + assign tl_rom_ctrl__regs_o = tl_sm1_36_ds_h2d; + assign tl_sm1_36_ds_d2h = tl_rom_ctrl__regs_i; - assign tl_rv_dm__mem_o = tl_sm1_34_ds_h2d; - assign tl_sm1_34_ds_d2h = tl_rv_dm__mem_i; + assign tl_rv_dm__regs_o = tl_sm1_37_ds_h2d; + assign tl_sm1_37_ds_d2h = tl_rv_dm__regs_i; - assign tl_sram_ctrl_main__ram_o = tl_sm1_35_ds_h2d; - assign tl_sm1_35_ds_d2h = tl_sram_ctrl_main__ram_i; + assign tl_peri_o = tl_asf_38_ds_h2d; + assign tl_asf_38_ds_d2h = tl_peri_i; - assign tl_sram_ctrl_sec__ram_o = tl_sm1_36_ds_h2d; - assign tl_sm1_36_ds_d2h = tl_sram_ctrl_sec__ram_i; + assign tl_asf_38_us_h2d = tl_sm1_39_ds_h2d; + assign tl_sm1_39_ds_d2h = tl_asf_38_us_d2h; - assign tl_flash_ctrl__mem_o = tl_sm1_37_ds_h2d; - assign tl_sm1_37_ds_d2h = tl_flash_ctrl__mem_i; + assign tl_spi_host0_o = tl_asf_40_ds_h2d; + assign tl_asf_40_ds_d2h = tl_spi_host0_i; - assign tl_rram_ctrl__host_o = tl_sm1_38_ds_h2d; - assign tl_sm1_38_ds_d2h = tl_rram_ctrl__host_i; + assign tl_asf_40_us_h2d = tl_sm1_41_ds_h2d; + assign tl_sm1_41_ds_d2h = tl_asf_40_us_d2h; - assign tl_s1n_39_us_h2d = tl_rv_core_ibex__cored_i; - assign tl_rv_core_ibex__cored_o = tl_s1n_39_us_d2h; - - assign tl_rom_ctrl__regs_o = tl_sm1_40_ds_h2d; - assign tl_sm1_40_ds_d2h = tl_rom_ctrl__regs_i; - - assign tl_rv_dm__regs_o = tl_sm1_41_ds_h2d; - assign tl_sm1_41_ds_d2h = tl_rv_dm__regs_i; - - assign tl_peri_o = tl_asf_42_ds_h2d; - assign tl_asf_42_ds_d2h = tl_peri_i; + assign tl_spi_host1_o = tl_asf_42_ds_h2d; + assign tl_asf_42_ds_d2h = tl_spi_host1_i; assign tl_asf_42_us_h2d = tl_sm1_43_ds_h2d; assign tl_sm1_43_ds_d2h = tl_asf_42_us_d2h; - assign tl_spi_host0_o = tl_asf_44_ds_h2d; - assign tl_asf_44_ds_d2h = tl_spi_host0_i; + assign tl_usbdev_o = tl_asf_44_ds_h2d; + assign tl_asf_44_ds_d2h = tl_usbdev_i; assign tl_asf_44_us_h2d = tl_sm1_45_ds_h2d; assign tl_sm1_45_ds_d2h = tl_asf_44_us_d2h; - assign tl_spi_host1_o = tl_asf_46_ds_h2d; - assign tl_asf_46_ds_d2h = tl_spi_host1_i; - - assign tl_asf_46_us_h2d = tl_sm1_47_ds_h2d; - assign tl_sm1_47_ds_d2h = tl_asf_46_us_d2h; - - assign tl_usbdev_o = tl_asf_48_ds_h2d; - assign tl_asf_48_ds_d2h = tl_usbdev_i; + assign tl_rram_ctrl__core_o = tl_sm1_46_ds_h2d; + assign tl_sm1_46_ds_d2h = tl_rram_ctrl__core_i; - assign tl_asf_48_us_h2d = tl_sm1_49_ds_h2d; - assign tl_sm1_49_ds_d2h = tl_asf_48_us_d2h; + assign tl_rram_macro__prim_o = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_rram_macro__prim_i; - assign tl_flash_ctrl__core_o = tl_sm1_50_ds_h2d; - assign tl_sm1_50_ds_d2h = tl_flash_ctrl__core_i; + assign tl_aes_o = tl_sm1_48_ds_h2d; + assign tl_sm1_48_ds_d2h = tl_aes_i; - assign tl_flash_ctrl__prim_o = tl_sm1_51_ds_h2d; - assign tl_sm1_51_ds_d2h = tl_flash_ctrl__prim_i; + assign tl_entropy_src_o = tl_sm1_49_ds_h2d; + assign tl_sm1_49_ds_d2h = tl_entropy_src_i; - assign tl_rram_ctrl__core_o = tl_sm1_52_ds_h2d; - assign tl_sm1_52_ds_d2h = tl_rram_ctrl__core_i; + assign tl_csrng_o = tl_sm1_50_ds_h2d; + assign tl_sm1_50_ds_d2h = tl_csrng_i; - assign tl_rram_macro__prim_o = tl_sm1_53_ds_h2d; - assign tl_sm1_53_ds_d2h = tl_rram_macro__prim_i; + assign tl_edn0_o = tl_sm1_51_ds_h2d; + assign tl_sm1_51_ds_d2h = tl_edn0_i; - assign tl_aes_o = tl_sm1_54_ds_h2d; - assign tl_sm1_54_ds_d2h = tl_aes_i; + assign tl_edn1_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_edn1_i; - assign tl_entropy_src_o = tl_sm1_55_ds_h2d; - assign tl_sm1_55_ds_d2h = tl_entropy_src_i; + assign tl_hmac_o = tl_sm1_53_ds_h2d; + assign tl_sm1_53_ds_d2h = tl_hmac_i; - assign tl_csrng_o = tl_sm1_56_ds_h2d; - assign tl_sm1_56_ds_d2h = tl_csrng_i; + assign tl_rv_plic_o = tl_sm1_54_ds_h2d; + assign tl_sm1_54_ds_d2h = tl_rv_plic_i; - assign tl_edn0_o = tl_sm1_57_ds_h2d; - assign tl_sm1_57_ds_d2h = tl_edn0_i; + assign tl_otbn_o = tl_sm1_55_ds_h2d; + assign tl_sm1_55_ds_d2h = tl_otbn_i; - assign tl_edn1_o = tl_sm1_58_ds_h2d; - assign tl_sm1_58_ds_d2h = tl_edn1_i; + assign tl_keymgr_dpe_o = tl_sm1_56_ds_h2d; + assign tl_sm1_56_ds_d2h = tl_keymgr_dpe_i; - assign tl_hmac_o = tl_sm1_59_ds_h2d; - assign tl_sm1_59_ds_d2h = tl_hmac_i; + assign tl_kmac_o = tl_sm1_57_ds_h2d; + assign tl_sm1_57_ds_d2h = tl_kmac_i; - assign tl_rv_plic_o = tl_sm1_60_ds_h2d; - assign tl_sm1_60_ds_d2h = tl_rv_plic_i; + assign tl_sram_ctrl_main__regs_o = tl_sm1_58_ds_h2d; + assign tl_sm1_58_ds_d2h = tl_sram_ctrl_main__regs_i; - assign tl_otbn_o = tl_sm1_61_ds_h2d; - assign tl_sm1_61_ds_d2h = tl_otbn_i; + assign tl_sram_ctrl_sec__regs_o = tl_sm1_59_ds_h2d; + assign tl_sm1_59_ds_d2h = tl_sram_ctrl_sec__regs_i; - assign tl_keymgr_dpe_o = tl_sm1_62_ds_h2d; - assign tl_sm1_62_ds_d2h = tl_keymgr_dpe_i; + assign tl_rv_core_ibex__cfg_o = tl_sm1_60_ds_h2d; + assign tl_sm1_60_ds_d2h = tl_rv_core_ibex__cfg_i; - assign tl_kmac_o = tl_sm1_63_ds_h2d; - assign tl_sm1_63_ds_d2h = tl_kmac_i; - - assign tl_sram_ctrl_main__regs_o = tl_sm1_64_ds_h2d; - assign tl_sm1_64_ds_d2h = tl_sram_ctrl_main__regs_i; - - assign tl_sram_ctrl_sec__regs_o = tl_sm1_65_ds_h2d; - assign tl_sm1_65_ds_d2h = tl_sram_ctrl_sec__regs_i; - - assign tl_rv_core_ibex__cfg_o = tl_sm1_66_ds_h2d; - assign tl_sm1_66_ds_d2h = tl_rv_core_ibex__cfg_i; - - assign tl_s1n_67_us_h2d = tl_rv_dm__sba_i; - assign tl_rv_dm__sba_o = tl_s1n_67_us_d2h; + assign tl_s1n_61_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_61_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_32 = 3'd6; - if (((tl_s1n_32_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_32 = 3'd0; + dev_sel_s1n_29 = 3'd5; + if (((tl_s1n_29_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_29_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_29 = 3'd0; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_32 = 3'd1; + dev_sel_s1n_29 = 3'd1; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_32 = 3'd2; + dev_sel_s1n_29 = 3'd2; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_32 = 3'd3; - - end else if ((tl_s1n_32_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_32 = 3'd4; + dev_sel_s1n_29 = 3'd3; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin - dev_sel_s1n_32 = 3'd5; + dev_sel_s1n_29 = 3'd4; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_39 = 5'd29; - if (((tl_s1n_39_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_39_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_39 = 5'd0; + dev_sel_s1n_35 = 5'd26; + if (((tl_s1n_35_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_35 = 5'd0; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_39 = 5'd1; + dev_sel_s1n_35 = 5'd1; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_39 = 5'd2; + dev_sel_s1n_35 = 5'd2; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_39 = 5'd3; + dev_sel_s1n_35 = 5'd3; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_39 = 5'd4; + dev_sel_s1n_35 = 5'd4; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_39 = 5'd5; + dev_sel_s1n_35 = 5'd5; end else if ( - ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_39 = 5'd6; + dev_sel_s1n_35 = 5'd6; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_39 = 5'd7; + dev_sel_s1n_35 = 5'd7; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_39 = 5'd8; + dev_sel_s1n_35 = 5'd8; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_39 = 5'd9; + dev_sel_s1n_35 = 5'd9; - end else if ((tl_s1n_39_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_39 = 5'd10; - - end else if ((tl_s1n_39_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_39 = 5'd11; - - end else if ((tl_s1n_39_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_39 = 5'd12; - - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RRAM_CTRL__CORE)) == ADDR_SPACE_RRAM_CTRL__CORE) begin - dev_sel_s1n_39 = 5'd13; + dev_sel_s1n_35 = 5'd10; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin - dev_sel_s1n_39 = 5'd14; + dev_sel_s1n_35 = 5'd11; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RRAM_MACRO__PRIM)) == ADDR_SPACE_RRAM_MACRO__PRIM) begin - dev_sel_s1n_39 = 5'd15; + dev_sel_s1n_35 = 5'd12; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_39 = 5'd16; + dev_sel_s1n_35 = 5'd13; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_39 = 5'd17; + dev_sel_s1n_35 = 5'd14; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_39 = 5'd18; + dev_sel_s1n_35 = 5'd15; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_39 = 5'd19; + dev_sel_s1n_35 = 5'd16; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_39 = 5'd20; + dev_sel_s1n_35 = 5'd17; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_39 = 5'd21; + dev_sel_s1n_35 = 5'd18; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_39 = 5'd22; + dev_sel_s1n_35 = 5'd19; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_39 = 5'd23; + dev_sel_s1n_35 = 5'd20; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin - dev_sel_s1n_39 = 5'd24; + dev_sel_s1n_35 = 5'd21; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_39 = 5'd25; + dev_sel_s1n_35 = 5'd22; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_39 = 5'd26; + dev_sel_s1n_35 = 5'd23; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__REGS)) == ADDR_SPACE_SRAM_CTRL_SEC__REGS) begin - dev_sel_s1n_39 = 5'd27; + dev_sel_s1n_35 = 5'd24; - end else if ((tl_s1n_39_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_39 = 5'd28; + dev_sel_s1n_35 = 5'd25; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_67 = 5'd29; - if (((tl_s1n_67_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_67_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_67 = 5'd0; + dev_sel_s1n_61 = 5'd26; + if (((tl_s1n_61_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_61_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_61 = 5'd0; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_67 = 5'd1; + dev_sel_s1n_61 = 5'd1; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_67 = 5'd2; + dev_sel_s1n_61 = 5'd2; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_67 = 5'd3; + dev_sel_s1n_61 = 5'd3; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_67 = 5'd4; + dev_sel_s1n_61 = 5'd4; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_67 = 5'd5; + dev_sel_s1n_61 = 5'd5; end else if ( - ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_67 = 5'd6; + dev_sel_s1n_61 = 5'd6; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_67 = 5'd7; + dev_sel_s1n_61 = 5'd7; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_67 = 5'd8; + dev_sel_s1n_61 = 5'd8; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_67 = 5'd9; - - end else if ((tl_s1n_67_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_67 = 5'd10; - - end else if ((tl_s1n_67_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_67 = 5'd11; + dev_sel_s1n_61 = 5'd9; - end else if ((tl_s1n_67_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_67 = 5'd12; - - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RRAM_CTRL__CORE)) == ADDR_SPACE_RRAM_CTRL__CORE) begin - dev_sel_s1n_67 = 5'd13; + dev_sel_s1n_61 = 5'd10; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin - dev_sel_s1n_67 = 5'd14; + dev_sel_s1n_61 = 5'd11; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RRAM_MACRO__PRIM)) == ADDR_SPACE_RRAM_MACRO__PRIM) begin - dev_sel_s1n_67 = 5'd15; + dev_sel_s1n_61 = 5'd12; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_67 = 5'd16; + dev_sel_s1n_61 = 5'd13; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_67 = 5'd17; + dev_sel_s1n_61 = 5'd14; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_67 = 5'd18; + dev_sel_s1n_61 = 5'd15; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_67 = 5'd19; + dev_sel_s1n_61 = 5'd16; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_67 = 5'd20; + dev_sel_s1n_61 = 5'd17; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_67 = 5'd21; + dev_sel_s1n_61 = 5'd18; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_67 = 5'd22; + dev_sel_s1n_61 = 5'd19; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_67 = 5'd23; + dev_sel_s1n_61 = 5'd20; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin - dev_sel_s1n_67 = 5'd24; + dev_sel_s1n_61 = 5'd21; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_67 = 5'd25; + dev_sel_s1n_61 = 5'd22; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_67 = 5'd26; + dev_sel_s1n_61 = 5'd23; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__REGS)) == ADDR_SPACE_SRAM_CTRL_SEC__REGS) begin - dev_sel_s1n_67 = 5'd27; + dev_sel_s1n_61 = 5'd24; - end else if ((tl_s1n_67_us_h2d.a_address & + end else if ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_67 = 5'd28; + dev_sel_s1n_61 = 5'd25; end end @@ -1075,30 +976,30 @@ end tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (24'h0), - .DRspDepth (24'h0), - .N (6) - ) u_s1n_32 ( + .DReqDepth (20'h0), + .DRspDepth (20'h0), + .N (5) + ) u_s1n_29 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_32_us_h2d), - .tl_h_o (tl_s1n_32_us_d2h), - .tl_d_o (tl_s1n_32_ds_h2d), - .tl_d_i (tl_s1n_32_ds_d2h), - .dev_select_i (dev_sel_s1n_32) + .tl_h_i (tl_s1n_29_us_h2d), + .tl_h_o (tl_s1n_29_us_d2h), + .tl_d_o (tl_s1n_29_ds_h2d), + .tl_d_i (tl_s1n_29_ds_d2h), + .dev_select_i (dev_sel_s1n_29) ); tlul_socket_m1 #( .HReqDepth (12'h0), .HRspDepth (12'h0), .DRspPass (1'b0), .M (3) - ) u_sm1_33 ( + ) u_sm1_30 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_33_us_h2d), - .tl_h_o (tl_sm1_33_us_d2h), - .tl_d_o (tl_sm1_33_ds_h2d), - .tl_d_i (tl_sm1_33_ds_d2h) + .tl_h_i (tl_sm1_30_us_h2d), + .tl_h_o (tl_sm1_30_us_d2h), + .tl_d_o (tl_sm1_30_ds_h2d), + .tl_d_i (tl_sm1_30_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1106,13 +1007,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_34 ( + ) u_sm1_31 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_34_us_h2d), - .tl_h_o (tl_sm1_34_us_d2h), - .tl_d_o (tl_sm1_34_ds_h2d), - .tl_d_i (tl_sm1_34_ds_d2h) + .tl_h_i (tl_sm1_31_us_h2d), + .tl_h_o (tl_sm1_31_us_d2h), + .tl_d_o (tl_sm1_31_ds_h2d), + .tl_d_i (tl_sm1_31_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1120,13 +1021,13 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_35 ( + ) u_sm1_32 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_35_us_h2d), - .tl_h_o (tl_sm1_35_us_d2h), - .tl_d_o (tl_sm1_35_ds_h2d), - .tl_d_i (tl_sm1_35_ds_d2h) + .tl_h_i (tl_sm1_32_us_h2d), + .tl_h_o (tl_sm1_32_us_d2h), + .tl_d_o (tl_sm1_32_ds_h2d), + .tl_d_i (tl_sm1_32_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1134,27 +1035,13 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_36 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_36_us_h2d), - .tl_h_o (tl_sm1_36_us_d2h), - .tl_d_o (tl_sm1_36_ds_h2d), - .tl_d_i (tl_sm1_36_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (12'h0), - .HRspDepth (12'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (3) - ) u_sm1_37 ( + ) u_sm1_33 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_37_us_h2d), - .tl_h_o (tl_sm1_37_us_d2h), - .tl_d_o (tl_sm1_37_ds_h2d), - .tl_d_i (tl_sm1_37_ds_d2h) + .tl_h_i (tl_sm1_33_us_h2d), + .tl_h_o (tl_sm1_33_us_d2h), + .tl_d_o (tl_sm1_33_ds_h2d), + .tl_d_i (tl_sm1_33_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1162,28 +1049,28 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_38 ( + ) u_sm1_34 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_38_us_h2d), - .tl_h_o (tl_sm1_38_us_d2h), - .tl_d_o (tl_sm1_38_ds_h2d), - .tl_d_i (tl_sm1_38_ds_d2h) + .tl_h_i (tl_sm1_34_us_h2d), + .tl_h_o (tl_sm1_34_us_d2h), + .tl_d_o (tl_sm1_34_ds_h2d), + .tl_d_i (tl_sm1_34_ds_d2h) ); tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (116'h0), - .DRspDepth (116'h0), - .N (29) - ) u_s1n_39 ( + .DReqDepth (104'h0), + .DRspDepth (104'h0), + .N (26) + ) u_s1n_35 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_39_us_h2d), - .tl_h_o (tl_s1n_39_us_d2h), - .tl_d_o (tl_s1n_39_ds_h2d), - .tl_d_i (tl_s1n_39_ds_d2h), - .dev_select_i (dev_sel_s1n_39) + .tl_h_i (tl_s1n_35_us_h2d), + .tl_h_o (tl_s1n_35_us_d2h), + .tl_d_o (tl_s1n_35_ds_h2d), + .tl_d_i (tl_s1n_35_ds_d2h), + .dev_select_i (dev_sel_s1n_35) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1191,13 +1078,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) - ) u_sm1_40 ( + ) u_sm1_36 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_40_us_h2d), - .tl_h_o (tl_sm1_40_us_d2h), - .tl_d_o (tl_sm1_40_ds_h2d), - .tl_d_i (tl_sm1_40_ds_d2h) + .tl_h_i (tl_sm1_36_us_h2d), + .tl_h_o (tl_sm1_36_us_d2h), + .tl_d_o (tl_sm1_36_ds_h2d), + .tl_d_i (tl_sm1_36_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1205,6 +1092,60 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) + ) u_sm1_37 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_37_us_h2d), + .tl_h_o (tl_sm1_37_us_d2h), + .tl_d_o (tl_sm1_37_ds_h2d), + .tl_d_i (tl_sm1_37_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_38 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_38_us_h2d), + .tl_h_o (tl_asf_38_us_d2h), + .tl_d_o (tl_asf_38_ds_h2d), + .tl_d_i (tl_asf_38_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_39 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_39_us_h2d), + .tl_h_o (tl_sm1_39_us_d2h), + .tl_d_o (tl_sm1_39_ds_h2d), + .tl_d_i (tl_sm1_39_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_40 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_spi_host0_i), + .rst_d_ni (rst_spi_host0_ni), + .tl_h_i (tl_asf_40_us_h2d), + .tl_h_o (tl_asf_40_us_d2h), + .tl_d_o (tl_asf_40_ds_h2d), + .tl_d_i (tl_asf_40_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) ) u_sm1_41 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -1219,8 +1160,8 @@ end ) u_asf_42 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), + .clk_d_i (clk_spi_host1_i), + .rst_d_ni (rst_spi_host1_ni), .tl_h_i (tl_asf_42_us_h2d), .tl_h_o (tl_asf_42_us_d2h), .tl_d_o (tl_asf_42_ds_h2d), @@ -1246,8 +1187,8 @@ end ) u_asf_44 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), - .clk_d_i (clk_spi_host0_i), - .rst_d_ni (rst_spi_host0_ni), + .clk_d_i (clk_usb_i), + .rst_d_ni (rst_usb_ni), .tl_h_i (tl_asf_44_us_h2d), .tl_h_o (tl_asf_44_us_d2h), .tl_d_o (tl_asf_44_ds_h2d), @@ -1267,24 +1208,25 @@ end .tl_d_o (tl_sm1_45_ds_h2d), .tl_d_i (tl_sm1_45_ds_d2h) ); - tlul_fifo_async #( - .ReqDepth (1), - .RspDepth (1) - ) u_asf_46 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_spi_host1_i), - .rst_d_ni (rst_spi_host1_ni), - .tl_h_i (tl_asf_46_us_h2d), - .tl_h_o (tl_asf_46_us_d2h), - .tl_d_o (tl_asf_46_ds_h2d), - .tl_d_i (tl_asf_46_ds_d2h) + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_46 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_46_us_h2d), + .tl_h_o (tl_sm1_46_us_d2h), + .tl_d_o (tl_sm1_46_ds_h2d), + .tl_d_i (tl_sm1_46_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), .M (2) ) u_sm1_47 ( .clk_i (clk_main_i), @@ -1294,24 +1236,25 @@ end .tl_d_o (tl_sm1_47_ds_h2d), .tl_d_i (tl_sm1_47_ds_d2h) ); - tlul_fifo_async #( - .ReqDepth (1), - .RspDepth (1) - ) u_asf_48 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_usb_i), - .rst_d_ni (rst_usb_ni), - .tl_h_i (tl_asf_48_us_h2d), - .tl_h_o (tl_asf_48_us_d2h), - .tl_d_o (tl_asf_48_ds_h2d), - .tl_d_i (tl_asf_48_ds_d2h) + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_48 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_48_us_h2d), + .tl_h_o (tl_sm1_48_us_d2h), + .tl_d_o (tl_sm1_48_ds_h2d), + .tl_d_i (tl_sm1_48_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), .M (2) ) u_sm1_49 ( .clk_i (clk_main_i), @@ -1475,104 +1418,20 @@ end .tl_d_o (tl_sm1_60_ds_h2d), .tl_d_i (tl_sm1_60_ds_d2h) ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_61 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_61_us_h2d), - .tl_h_o (tl_sm1_61_us_d2h), - .tl_d_o (tl_sm1_61_ds_h2d), - .tl_d_i (tl_sm1_61_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_62 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_62_us_h2d), - .tl_h_o (tl_sm1_62_us_d2h), - .tl_d_o (tl_sm1_62_ds_h2d), - .tl_d_i (tl_sm1_62_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_63 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_63_us_h2d), - .tl_h_o (tl_sm1_63_us_d2h), - .tl_d_o (tl_sm1_63_ds_h2d), - .tl_d_i (tl_sm1_63_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_64 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_64_us_h2d), - .tl_h_o (tl_sm1_64_us_d2h), - .tl_d_o (tl_sm1_64_ds_h2d), - .tl_d_i (tl_sm1_64_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_65 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_65_us_h2d), - .tl_h_o (tl_sm1_65_us_d2h), - .tl_d_o (tl_sm1_65_ds_h2d), - .tl_d_i (tl_sm1_65_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_66 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_66_us_h2d), - .tl_h_o (tl_sm1_66_us_d2h), - .tl_d_o (tl_sm1_66_ds_h2d), - .tl_d_i (tl_sm1_66_ds_d2h) - ); tlul_socket_1n #( .HReqPass (1'b0), .HRspPass (1'b0), - .DReqDepth (116'h0), - .DRspDepth (116'h0), - .N (29) - ) u_s1n_67 ( + .DReqDepth (104'h0), + .DRspDepth (104'h0), + .N (26) + ) u_s1n_61 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_67_us_h2d), - .tl_h_o (tl_s1n_67_us_d2h), - .tl_d_o (tl_s1n_67_ds_h2d), - .tl_d_i (tl_s1n_67_ds_d2h), - .dev_select_i (dev_sel_s1n_67) + .tl_h_i (tl_s1n_61_us_h2d), + .tl_h_o (tl_s1n_61_us_d2h), + .tl_d_o (tl_s1n_61_ds_h2d), + .tl_d_i (tl_s1n_61_ds_d2h), + .dev_select_i (dev_sel_s1n_61) ); endmodule diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson index 933592cfdc7c3..91e13451558c2 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson @@ -49,7 +49,7 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "69", + default: "64", local: "true" }, { name: "NLpg", @@ -102,11 +102,6 @@ 5'd17, 5'd17, 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, 5'd16, 5'd12, 5'd12, @@ -227,11 +222,6 @@ 1'b1, 1'b1, 1'b1, - 1'b1, - 1'b1, - 1'b1, - 1'b1, - 1'b1, 1'b1 } ''' diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index 94f9480afb3dd..e8794e3a35322 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -6,7 +6,7 @@ param_values: { module_instance_name: alert_handler - n_alerts: 69 + n_alerts: 64 esc_cnt_dw: 32 accu_cnt_dw: 16 async_on: @@ -75,11 +75,6 @@ 1'b1 1'b1 1'b1 - 1'b1 - 1'b1 - 1'b1 - 1'b1 - 1'b1 ] n_classes: 4 n_esc_sev: 4 @@ -125,11 +120,6 @@ 5'd17 5'd17 5'd17 - 5'd17 - 5'd17 - 5'd17 - 5'd17 - 5'd17 5'd18 5'd19 5'd20 diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md index d00ba1166d01f..cba96ec13df43 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -24,7 +24,7 @@ The parameterization rules are explained in more detail in the architectural des Localparam | Default (Max) | This Core | Description ---------------|-----------------------|----------------|--------------- -`NAlerts` | 8 (248) | 69 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NAlerts` | 8 (248) | 64 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. `NLpg` | 1 | 24 | Number of unique low-power groups as determined by topgen. `LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. `EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index 18d5276b5d15a..8f751fde35a80 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -7,7 +7,7 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 69; + parameter int NAlerts = 64; parameter int NLpg = 24; parameter int NLpgWidth = 5; parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { @@ -42,11 +42,6 @@ package alert_handler_reg_pkg; 5'd17, 5'd17, 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, - 5'd17, 5'd16, 5'd12, 5'd12, @@ -147,11 +142,6 @@ package alert_handler_reg_pkg; 1'b1, 1'b1, 1'b1, - 1'b1, - 1'b1, - 1'b1, - 1'b1, - 1'b1, 1'b1 }; parameter int N_CLASSES = 4; @@ -174,7 +164,7 @@ package alert_handler_reg_pkg; parameter int BlockAw = 11; // Number of registers for every interface - parameter int NumRegs = 366; + parameter int NumRegs = 346; //////////////////////////// // Typedefs for registers // @@ -628,15 +618,15 @@ package alert_handler_reg_pkg; // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1181:1178] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1177:1174] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1173:1166] - alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1165:1150] - alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1149:1149] - alert_handler_reg2hw_alert_regwen_mreg_t [68:0] alert_regwen; // [1148:1080] - alert_handler_reg2hw_alert_en_shadowed_mreg_t [68:0] alert_en_shadowed; // [1079:1011] - alert_handler_reg2hw_alert_class_shadowed_mreg_t [68:0] alert_class_shadowed; // [1010:873] - alert_handler_reg2hw_alert_cause_mreg_t [68:0] alert_cause; // [872:804] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1156:1153] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1152:1149] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1148:1141] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1140:1125] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1124:1124] + alert_handler_reg2hw_alert_regwen_mreg_t [63:0] alert_regwen; // [1123:1060] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [63:0] alert_en_shadowed; // [1059:996] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [63:0] alert_class_shadowed; // [995:868] + alert_handler_reg2hw_alert_cause_mreg_t [63:0] alert_cause; // [867:804] alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] loc_alert_class_shadowed; // [796:783] @@ -689,8 +679,8 @@ package alert_handler_reg_pkg; // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [371:364] - alert_handler_hw2reg_alert_cause_mreg_t [68:0] alert_cause; // [363:226] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [361:354] + alert_handler_hw2reg_alert_cause_mreg_t [63:0] alert_cause; // [353:226] alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -781,302 +771,282 @@ package alert_handler_reg_pkg; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_68_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_68_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 554; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 558; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 55c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 560; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 564; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 568; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 56c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 570; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 574; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 578; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 57c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 580; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 584; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 588; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 58c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 590; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 594; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 598; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 59c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 5a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 5a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 5a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 5ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 5b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 564; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -1169,11 +1139,6 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_REGWEN_61, ALERT_HANDLER_ALERT_REGWEN_62, ALERT_HANDLER_ALERT_REGWEN_63, - ALERT_HANDLER_ALERT_REGWEN_64, - ALERT_HANDLER_ALERT_REGWEN_65, - ALERT_HANDLER_ALERT_REGWEN_66, - ALERT_HANDLER_ALERT_REGWEN_67, - ALERT_HANDLER_ALERT_REGWEN_68, ALERT_HANDLER_ALERT_EN_SHADOWED_0, ALERT_HANDLER_ALERT_EN_SHADOWED_1, ALERT_HANDLER_ALERT_EN_SHADOWED_2, @@ -1238,11 +1203,6 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_EN_SHADOWED_61, ALERT_HANDLER_ALERT_EN_SHADOWED_62, ALERT_HANDLER_ALERT_EN_SHADOWED_63, - ALERT_HANDLER_ALERT_EN_SHADOWED_64, - ALERT_HANDLER_ALERT_EN_SHADOWED_65, - ALERT_HANDLER_ALERT_EN_SHADOWED_66, - ALERT_HANDLER_ALERT_EN_SHADOWED_67, - ALERT_HANDLER_ALERT_EN_SHADOWED_68, ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, @@ -1307,11 +1267,6 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, - ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, - ALERT_HANDLER_ALERT_CLASS_SHADOWED_65, - ALERT_HANDLER_ALERT_CLASS_SHADOWED_66, - ALERT_HANDLER_ALERT_CLASS_SHADOWED_67, - ALERT_HANDLER_ALERT_CLASS_SHADOWED_68, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1376,11 +1331,6 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CAUSE_61, ALERT_HANDLER_ALERT_CAUSE_62, ALERT_HANDLER_ALERT_CAUSE_63, - ALERT_HANDLER_ALERT_CAUSE_64, - ALERT_HANDLER_ALERT_CAUSE_65, - ALERT_HANDLER_ALERT_CAUSE_66, - ALERT_HANDLER_ALERT_CAUSE_67, - ALERT_HANDLER_ALERT_CAUSE_68, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1468,7 +1418,7 @@ package alert_handler_reg_pkg; } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [366] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [346] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1539,302 +1489,282 @@ package alert_handler_reg_pkg; 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 - 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 - 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_REGWEN_68 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_7 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_8 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_9 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_10 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_11 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_12 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_13 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_14 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_15 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_16 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_17 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_18 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_19 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_20 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_21 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_22 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_23 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_24 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_25 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_26 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_27 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_28 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_29 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_30 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_31 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_32 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_33 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_34 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_35 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_36 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_37 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_38 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_39 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_40 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_41 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_42 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_43 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_44 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_45 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_46 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_47 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_48 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_49 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_50 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_51 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_52 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_53 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_54 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_55 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_56 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_57 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_58 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_59 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_60 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_61 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_62 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_SHADOWED_63 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_SHADOWED_64 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_SHADOWED_65 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_SHADOWED_66 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_EN_SHADOWED_67 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_EN_SHADOWED_68 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CAUSE_63 - 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CAUSE_64 - 4'b 0001, // index[278] ALERT_HANDLER_ALERT_CAUSE_65 - 4'b 0001, // index[279] ALERT_HANDLER_ALERT_CAUSE_66 - 4'b 0001, // index[280] ALERT_HANDLER_ALERT_CAUSE_67 - 4'b 0001, // index[281] ALERT_HANDLER_ALERT_CAUSE_68 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_REGWEN_5 - 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_REGWEN_6 - 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[294] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[295] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[296] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[297] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[298] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[299] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[300] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[301] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[302] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[303] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[304] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[305] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[306] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[307] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[308] ALERT_HANDLER_LOC_ALERT_CAUSE_5 - 4'b 0001, // index[309] ALERT_HANDLER_LOC_ALERT_CAUSE_6 - 4'b 0001, // index[310] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[311] ALERT_HANDLER_CLASSA_CTRL_SHADOWED - 4'b 0001, // index[312] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[313] ALERT_HANDLER_CLASSA_CLR_SHADOWED - 4'b 0011, // index[314] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[315] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[316] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[317] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[318] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED - 4'b 1111, // index[319] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED - 4'b 1111, // index[320] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED - 4'b 1111, // index[321] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED - 4'b 1111, // index[322] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[323] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[324] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[325] ALERT_HANDLER_CLASSB_CTRL_SHADOWED - 4'b 0001, // index[326] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[327] ALERT_HANDLER_CLASSB_CLR_SHADOWED - 4'b 0011, // index[328] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[329] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[330] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[331] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[332] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED - 4'b 1111, // index[333] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED - 4'b 1111, // index[334] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED - 4'b 1111, // index[335] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED - 4'b 1111, // index[336] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[337] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[338] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[339] ALERT_HANDLER_CLASSC_CTRL_SHADOWED - 4'b 0001, // index[340] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[341] ALERT_HANDLER_CLASSC_CLR_SHADOWED - 4'b 0011, // index[342] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[343] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[344] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[345] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[346] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED - 4'b 1111, // index[347] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED - 4'b 1111, // index[348] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED - 4'b 1111, // index[349] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED - 4'b 1111, // index[350] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[351] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[352] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[353] ALERT_HANDLER_CLASSD_CTRL_SHADOWED - 4'b 0001, // index[354] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[355] ALERT_HANDLER_CLASSD_CLR_SHADOWED - 4'b 0011, // index[356] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[357] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[358] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[359] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[360] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED - 4'b 1111, // index[361] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED - 4'b 1111, // index[362] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED - 4'b 1111, // index[363] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED - 4'b 1111, // index[364] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[365] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[290] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[291] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[292] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[293] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[294] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[296] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[298] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[299] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[301] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[303] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[304] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[305] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[306] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[307] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[308] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[309] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[310] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[312] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[313] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[315] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[317] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[318] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[319] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[320] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[321] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[322] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[323] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[324] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[327] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[329] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[331] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[332] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[333] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[334] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[336] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[338] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[341] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[343] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[345] ALERT_HANDLER_CLASSD_STATE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv index f2f17212870b7..c40fe370f5de3 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -56,9 +56,9 @@ module alert_handler_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [365:0] reg_we_check; + logic [345:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(366) + .OneHotWidth(346) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -355,21 +355,6 @@ module alert_handler_reg_top ( logic alert_regwen_63_we; logic alert_regwen_63_qs; logic alert_regwen_63_wd; - logic alert_regwen_64_we; - logic alert_regwen_64_qs; - logic alert_regwen_64_wd; - logic alert_regwen_65_we; - logic alert_regwen_65_qs; - logic alert_regwen_65_wd; - logic alert_regwen_66_we; - logic alert_regwen_66_qs; - logic alert_regwen_66_wd; - logic alert_regwen_67_we; - logic alert_regwen_67_qs; - logic alert_regwen_67_wd; - logic alert_regwen_68_we; - logic alert_regwen_68_qs; - logic alert_regwen_68_wd; logic alert_en_shadowed_0_re; logic alert_en_shadowed_0_we; logic alert_en_shadowed_0_qs; @@ -754,36 +739,6 @@ module alert_handler_reg_top ( logic alert_en_shadowed_63_wd; logic alert_en_shadowed_63_storage_err; logic alert_en_shadowed_63_update_err; - logic alert_en_shadowed_64_re; - logic alert_en_shadowed_64_we; - logic alert_en_shadowed_64_qs; - logic alert_en_shadowed_64_wd; - logic alert_en_shadowed_64_storage_err; - logic alert_en_shadowed_64_update_err; - logic alert_en_shadowed_65_re; - logic alert_en_shadowed_65_we; - logic alert_en_shadowed_65_qs; - logic alert_en_shadowed_65_wd; - logic alert_en_shadowed_65_storage_err; - logic alert_en_shadowed_65_update_err; - logic alert_en_shadowed_66_re; - logic alert_en_shadowed_66_we; - logic alert_en_shadowed_66_qs; - logic alert_en_shadowed_66_wd; - logic alert_en_shadowed_66_storage_err; - logic alert_en_shadowed_66_update_err; - logic alert_en_shadowed_67_re; - logic alert_en_shadowed_67_we; - logic alert_en_shadowed_67_qs; - logic alert_en_shadowed_67_wd; - logic alert_en_shadowed_67_storage_err; - logic alert_en_shadowed_67_update_err; - logic alert_en_shadowed_68_re; - logic alert_en_shadowed_68_we; - logic alert_en_shadowed_68_qs; - logic alert_en_shadowed_68_wd; - logic alert_en_shadowed_68_storage_err; - logic alert_en_shadowed_68_update_err; logic alert_class_shadowed_0_re; logic alert_class_shadowed_0_we; logic [1:0] alert_class_shadowed_0_qs; @@ -1168,36 +1123,6 @@ module alert_handler_reg_top ( logic [1:0] alert_class_shadowed_63_wd; logic alert_class_shadowed_63_storage_err; logic alert_class_shadowed_63_update_err; - logic alert_class_shadowed_64_re; - logic alert_class_shadowed_64_we; - logic [1:0] alert_class_shadowed_64_qs; - logic [1:0] alert_class_shadowed_64_wd; - logic alert_class_shadowed_64_storage_err; - logic alert_class_shadowed_64_update_err; - logic alert_class_shadowed_65_re; - logic alert_class_shadowed_65_we; - logic [1:0] alert_class_shadowed_65_qs; - logic [1:0] alert_class_shadowed_65_wd; - logic alert_class_shadowed_65_storage_err; - logic alert_class_shadowed_65_update_err; - logic alert_class_shadowed_66_re; - logic alert_class_shadowed_66_we; - logic [1:0] alert_class_shadowed_66_qs; - logic [1:0] alert_class_shadowed_66_wd; - logic alert_class_shadowed_66_storage_err; - logic alert_class_shadowed_66_update_err; - logic alert_class_shadowed_67_re; - logic alert_class_shadowed_67_we; - logic [1:0] alert_class_shadowed_67_qs; - logic [1:0] alert_class_shadowed_67_wd; - logic alert_class_shadowed_67_storage_err; - logic alert_class_shadowed_67_update_err; - logic alert_class_shadowed_68_re; - logic alert_class_shadowed_68_we; - logic [1:0] alert_class_shadowed_68_qs; - logic [1:0] alert_class_shadowed_68_wd; - logic alert_class_shadowed_68_storage_err; - logic alert_class_shadowed_68_update_err; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -1390,21 +1315,6 @@ module alert_handler_reg_top ( logic alert_cause_63_we; logic alert_cause_63_qs; logic alert_cause_63_wd; - logic alert_cause_64_we; - logic alert_cause_64_qs; - logic alert_cause_64_wd; - logic alert_cause_65_we; - logic alert_cause_65_qs; - logic alert_cause_65_wd; - logic alert_cause_66_we; - logic alert_cause_66_qs; - logic alert_cause_66_wd; - logic alert_cause_67_we; - logic alert_cause_67_qs; - logic alert_cause_67_wd; - logic alert_cause_68_we; - logic alert_cause_68_qs; - logic alert_cause_68_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -4194,151 +4104,6 @@ module alert_handler_reg_top ( ); - // Subregister 64 of Multireg alert_regwen - // R[alert_regwen_64]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen_64 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_64_we), - .wd (alert_regwen_64_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_regwen[64].q), - .ds (), - - // to register interface (read) - .qs (alert_regwen_64_qs) - ); - - - // Subregister 65 of Multireg alert_regwen - // R[alert_regwen_65]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen_65 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_65_we), - .wd (alert_regwen_65_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_regwen[65].q), - .ds (), - - // to register interface (read) - .qs (alert_regwen_65_qs) - ); - - - // Subregister 66 of Multireg alert_regwen - // R[alert_regwen_66]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen_66 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_66_we), - .wd (alert_regwen_66_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_regwen[66].q), - .ds (), - - // to register interface (read) - .qs (alert_regwen_66_qs) - ); - - - // Subregister 67 of Multireg alert_regwen - // R[alert_regwen_67]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen_67 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_67_we), - .wd (alert_regwen_67_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_regwen[67].q), - .ds (), - - // to register interface (read) - .qs (alert_regwen_67_qs) - ); - - - // Subregister 68 of Multireg alert_regwen - // R[alert_regwen_68]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen_68 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_68_we), - .wd (alert_regwen_68_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_regwen[68].q), - .ds (), - - // to register interface (read) - .qs (alert_regwen_68_qs) - ); - - // Subregister 0 of Multireg alert_en_shadowed // R[alert_en_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -6963,211 +6728,6 @@ module alert_handler_reg_top ( ); - // Subregister 64 of Multireg alert_en_shadowed - // R[alert_en_shadowed_64]: V(False) - // Create REGWEN-gated WE signal - logic alert_en_shadowed_64_gated_we; - assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs; - prim_subreg_shadow #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_en_shadowed_64 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_en_shadowed_64_re), - .we (alert_en_shadowed_64_gated_we), - .wd (alert_en_shadowed_64_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_en_shadowed[64].q), - .ds (), - - // to register interface (read) - .qs (alert_en_shadowed_64_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_en_shadowed_64_update_err), - .err_storage (alert_en_shadowed_64_storage_err) - ); - - - // Subregister 65 of Multireg alert_en_shadowed - // R[alert_en_shadowed_65]: V(False) - // Create REGWEN-gated WE signal - logic alert_en_shadowed_65_gated_we; - assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs; - prim_subreg_shadow #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_en_shadowed_65 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_en_shadowed_65_re), - .we (alert_en_shadowed_65_gated_we), - .wd (alert_en_shadowed_65_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_en_shadowed[65].q), - .ds (), - - // to register interface (read) - .qs (alert_en_shadowed_65_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_en_shadowed_65_update_err), - .err_storage (alert_en_shadowed_65_storage_err) - ); - - - // Subregister 66 of Multireg alert_en_shadowed - // R[alert_en_shadowed_66]: V(False) - // Create REGWEN-gated WE signal - logic alert_en_shadowed_66_gated_we; - assign alert_en_shadowed_66_gated_we = alert_en_shadowed_66_we & alert_regwen_66_qs; - prim_subreg_shadow #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_en_shadowed_66 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_en_shadowed_66_re), - .we (alert_en_shadowed_66_gated_we), - .wd (alert_en_shadowed_66_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_en_shadowed[66].q), - .ds (), - - // to register interface (read) - .qs (alert_en_shadowed_66_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_en_shadowed_66_update_err), - .err_storage (alert_en_shadowed_66_storage_err) - ); - - - // Subregister 67 of Multireg alert_en_shadowed - // R[alert_en_shadowed_67]: V(False) - // Create REGWEN-gated WE signal - logic alert_en_shadowed_67_gated_we; - assign alert_en_shadowed_67_gated_we = alert_en_shadowed_67_we & alert_regwen_67_qs; - prim_subreg_shadow #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_en_shadowed_67 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_en_shadowed_67_re), - .we (alert_en_shadowed_67_gated_we), - .wd (alert_en_shadowed_67_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_en_shadowed[67].q), - .ds (), - - // to register interface (read) - .qs (alert_en_shadowed_67_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_en_shadowed_67_update_err), - .err_storage (alert_en_shadowed_67_storage_err) - ); - - - // Subregister 68 of Multireg alert_en_shadowed - // R[alert_en_shadowed_68]: V(False) - // Create REGWEN-gated WE signal - logic alert_en_shadowed_68_gated_we; - assign alert_en_shadowed_68_gated_we = alert_en_shadowed_68_we & alert_regwen_68_qs; - prim_subreg_shadow #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_en_shadowed_68 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_en_shadowed_68_re), - .we (alert_en_shadowed_68_gated_we), - .wd (alert_en_shadowed_68_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_en_shadowed[68].q), - .ds (), - - // to register interface (read) - .qs (alert_en_shadowed_68_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_en_shadowed_68_update_err), - .err_storage (alert_en_shadowed_68_storage_err) - ); - - // Subregister 0 of Multireg alert_class_shadowed // R[alert_class_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -9792,211 +9352,6 @@ module alert_handler_reg_top ( ); - // Subregister 64 of Multireg alert_class_shadowed - // R[alert_class_shadowed_64]: V(False) - // Create REGWEN-gated WE signal - logic alert_class_shadowed_64_gated_we; - assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs; - prim_subreg_shadow #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_alert_class_shadowed_64 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_class_shadowed_64_re), - .we (alert_class_shadowed_64_gated_we), - .wd (alert_class_shadowed_64_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_class_shadowed[64].q), - .ds (), - - // to register interface (read) - .qs (alert_class_shadowed_64_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_class_shadowed_64_update_err), - .err_storage (alert_class_shadowed_64_storage_err) - ); - - - // Subregister 65 of Multireg alert_class_shadowed - // R[alert_class_shadowed_65]: V(False) - // Create REGWEN-gated WE signal - logic alert_class_shadowed_65_gated_we; - assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs; - prim_subreg_shadow #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_alert_class_shadowed_65 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_class_shadowed_65_re), - .we (alert_class_shadowed_65_gated_we), - .wd (alert_class_shadowed_65_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_class_shadowed[65].q), - .ds (), - - // to register interface (read) - .qs (alert_class_shadowed_65_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_class_shadowed_65_update_err), - .err_storage (alert_class_shadowed_65_storage_err) - ); - - - // Subregister 66 of Multireg alert_class_shadowed - // R[alert_class_shadowed_66]: V(False) - // Create REGWEN-gated WE signal - logic alert_class_shadowed_66_gated_we; - assign alert_class_shadowed_66_gated_we = alert_class_shadowed_66_we & alert_regwen_66_qs; - prim_subreg_shadow #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_alert_class_shadowed_66 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_class_shadowed_66_re), - .we (alert_class_shadowed_66_gated_we), - .wd (alert_class_shadowed_66_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_class_shadowed[66].q), - .ds (), - - // to register interface (read) - .qs (alert_class_shadowed_66_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_class_shadowed_66_update_err), - .err_storage (alert_class_shadowed_66_storage_err) - ); - - - // Subregister 67 of Multireg alert_class_shadowed - // R[alert_class_shadowed_67]: V(False) - // Create REGWEN-gated WE signal - logic alert_class_shadowed_67_gated_we; - assign alert_class_shadowed_67_gated_we = alert_class_shadowed_67_we & alert_regwen_67_qs; - prim_subreg_shadow #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_alert_class_shadowed_67 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_class_shadowed_67_re), - .we (alert_class_shadowed_67_gated_we), - .wd (alert_class_shadowed_67_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_class_shadowed[67].q), - .ds (), - - // to register interface (read) - .qs (alert_class_shadowed_67_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_class_shadowed_67_update_err), - .err_storage (alert_class_shadowed_67_storage_err) - ); - - - // Subregister 68 of Multireg alert_class_shadowed - // R[alert_class_shadowed_68]: V(False) - // Create REGWEN-gated WE signal - logic alert_class_shadowed_68_gated_we; - assign alert_class_shadowed_68_gated_we = alert_class_shadowed_68_we & alert_regwen_68_qs; - prim_subreg_shadow #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_alert_class_shadowed_68 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .rst_shadowed_ni (rst_shadowed_ni), - - // from register interface - .re (alert_class_shadowed_68_re), - .we (alert_class_shadowed_68_gated_we), - .wd (alert_class_shadowed_68_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_class_shadowed[68].q), - .ds (), - - // to register interface (read) - .qs (alert_class_shadowed_68_qs), - - // Shadow register phase. Relevant for hwext only. - .phase (), - - // Shadow register error conditions - .err_update (alert_class_shadowed_68_update_err), - .err_storage (alert_class_shadowed_68_storage_err) - ); - - // Subregister 0 of Multireg alert_cause // R[alert_cause_0]: V(False) prim_subreg #( @@ -11853,151 +11208,6 @@ module alert_handler_reg_top ( ); - // Subregister 64 of Multireg alert_cause - // R[alert_cause_64]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_cause_64 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_cause_64_we), - .wd (alert_cause_64_wd), - - // from internal hardware - .de (hw2reg.alert_cause[64].de), - .d (hw2reg.alert_cause[64].d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_cause[64].q), - .ds (), - - // to register interface (read) - .qs (alert_cause_64_qs) - ); - - - // Subregister 65 of Multireg alert_cause - // R[alert_cause_65]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_cause_65 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_cause_65_we), - .wd (alert_cause_65_wd), - - // from internal hardware - .de (hw2reg.alert_cause[65].de), - .d (hw2reg.alert_cause[65].d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_cause[65].q), - .ds (), - - // to register interface (read) - .qs (alert_cause_65_qs) - ); - - - // Subregister 66 of Multireg alert_cause - // R[alert_cause_66]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_cause_66 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_cause_66_we), - .wd (alert_cause_66_wd), - - // from internal hardware - .de (hw2reg.alert_cause[66].de), - .d (hw2reg.alert_cause[66].d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_cause[66].q), - .ds (), - - // to register interface (read) - .qs (alert_cause_66_qs) - ); - - - // Subregister 67 of Multireg alert_cause - // R[alert_cause_67]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_cause_67 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_cause_67_we), - .wd (alert_cause_67_wd), - - // from internal hardware - .de (hw2reg.alert_cause[67].de), - .d (hw2reg.alert_cause[67].d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_cause[67].q), - .ds (), - - // to register interface (read) - .qs (alert_cause_67_qs) - ); - - - // Subregister 68 of Multireg alert_cause - // R[alert_cause_68]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_cause_68 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_cause_68_we), - .wd (alert_cause_68_wd), - - // from internal hardware - .de (hw2reg.alert_cause[68].de), - .d (hw2reg.alert_cause[68].d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_cause[68].q), - .ds (), - - // to register interface (read) - .qs (alert_cause_68_qs) - ); - - // Subregister 0 of Multireg loc_alert_regwen // R[loc_alert_regwen_0]: V(False) prim_subreg #( @@ -16194,7 +15404,7 @@ module alert_handler_reg_top ( - logic [365:0] addr_hit; + logic [345:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET); @@ -16266,302 +15476,282 @@ module alert_handler_reg_top ( addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET); addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); - addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); - addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_68_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_68_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); - addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[350] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[351] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[352] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[353] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); - addr_hit[354] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[355] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); - addr_hit[356] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[357] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[358] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[359] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[360] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[361] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[362] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[363] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[364] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[365] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -16914,27 +16104,7 @@ module alert_handler_reg_top ( (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | - (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) | - (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | - (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | - (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | - (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))) | - (addr_hit[350] & (|(ALERT_HANDLER_PERMIT[350] & ~reg_be))) | - (addr_hit[351] & (|(ALERT_HANDLER_PERMIT[351] & ~reg_be))) | - (addr_hit[352] & (|(ALERT_HANDLER_PERMIT[352] & ~reg_be))) | - (addr_hit[353] & (|(ALERT_HANDLER_PERMIT[353] & ~reg_be))) | - (addr_hit[354] & (|(ALERT_HANDLER_PERMIT[354] & ~reg_be))) | - (addr_hit[355] & (|(ALERT_HANDLER_PERMIT[355] & ~reg_be))) | - (addr_hit[356] & (|(ALERT_HANDLER_PERMIT[356] & ~reg_be))) | - (addr_hit[357] & (|(ALERT_HANDLER_PERMIT[357] & ~reg_be))) | - (addr_hit[358] & (|(ALERT_HANDLER_PERMIT[358] & ~reg_be))) | - (addr_hit[359] & (|(ALERT_HANDLER_PERMIT[359] & ~reg_be))) | - (addr_hit[360] & (|(ALERT_HANDLER_PERMIT[360] & ~reg_be))) | - (addr_hit[361] & (|(ALERT_HANDLER_PERMIT[361] & ~reg_be))) | - (addr_hit[362] & (|(ALERT_HANDLER_PERMIT[362] & ~reg_be))) | - (addr_hit[363] & (|(ALERT_HANDLER_PERMIT[363] & ~reg_be))) | - (addr_hit[364] & (|(ALERT_HANDLER_PERMIT[364] & ~reg_be))) | - (addr_hit[365] & (|(ALERT_HANDLER_PERMIT[365] & ~reg_be))))); + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))))); end // Generate write-enables @@ -17168,883 +16338,813 @@ module alert_handler_reg_top ( assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error; assign alert_regwen_63_wd = reg_wdata[0]; - assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; - - assign alert_regwen_64_wd = reg_wdata[0]; - assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; - - assign alert_regwen_65_wd = reg_wdata[0]; - assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; - - assign alert_regwen_66_wd = reg_wdata[0]; - assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error; - - assign alert_regwen_67_wd = reg_wdata[0]; - assign alert_regwen_68_we = addr_hit[74] & reg_we & !reg_error; - - assign alert_regwen_68_wd = reg_wdata[0]; - assign alert_en_shadowed_0_re = addr_hit[75] & reg_re & !reg_error; - assign alert_en_shadowed_0_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_shadowed_0_re = addr_hit[70] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[70] & reg_we & !reg_error; assign alert_en_shadowed_0_wd = reg_wdata[0]; - assign alert_en_shadowed_1_re = addr_hit[76] & reg_re & !reg_error; - assign alert_en_shadowed_1_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_shadowed_1_re = addr_hit[71] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[71] & reg_we & !reg_error; assign alert_en_shadowed_1_wd = reg_wdata[0]; - assign alert_en_shadowed_2_re = addr_hit[77] & reg_re & !reg_error; - assign alert_en_shadowed_2_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_shadowed_2_re = addr_hit[72] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[72] & reg_we & !reg_error; assign alert_en_shadowed_2_wd = reg_wdata[0]; - assign alert_en_shadowed_3_re = addr_hit[78] & reg_re & !reg_error; - assign alert_en_shadowed_3_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_shadowed_3_re = addr_hit[73] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[73] & reg_we & !reg_error; assign alert_en_shadowed_3_wd = reg_wdata[0]; - assign alert_en_shadowed_4_re = addr_hit[79] & reg_re & !reg_error; - assign alert_en_shadowed_4_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_shadowed_4_re = addr_hit[74] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[74] & reg_we & !reg_error; assign alert_en_shadowed_4_wd = reg_wdata[0]; - assign alert_en_shadowed_5_re = addr_hit[80] & reg_re & !reg_error; - assign alert_en_shadowed_5_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_shadowed_5_re = addr_hit[75] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_shadowed_5_wd = reg_wdata[0]; - assign alert_en_shadowed_6_re = addr_hit[81] & reg_re & !reg_error; - assign alert_en_shadowed_6_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_shadowed_6_re = addr_hit[76] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_shadowed_6_wd = reg_wdata[0]; - assign alert_en_shadowed_7_re = addr_hit[82] & reg_re & !reg_error; - assign alert_en_shadowed_7_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_shadowed_7_re = addr_hit[77] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_shadowed_7_wd = reg_wdata[0]; - assign alert_en_shadowed_8_re = addr_hit[83] & reg_re & !reg_error; - assign alert_en_shadowed_8_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_shadowed_8_re = addr_hit[78] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_shadowed_8_wd = reg_wdata[0]; - assign alert_en_shadowed_9_re = addr_hit[84] & reg_re & !reg_error; - assign alert_en_shadowed_9_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_shadowed_9_re = addr_hit[79] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_shadowed_9_wd = reg_wdata[0]; - assign alert_en_shadowed_10_re = addr_hit[85] & reg_re & !reg_error; - assign alert_en_shadowed_10_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_shadowed_10_re = addr_hit[80] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_shadowed_10_wd = reg_wdata[0]; - assign alert_en_shadowed_11_re = addr_hit[86] & reg_re & !reg_error; - assign alert_en_shadowed_11_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_shadowed_11_re = addr_hit[81] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_shadowed_11_wd = reg_wdata[0]; - assign alert_en_shadowed_12_re = addr_hit[87] & reg_re & !reg_error; - assign alert_en_shadowed_12_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_shadowed_12_re = addr_hit[82] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_shadowed_12_wd = reg_wdata[0]; - assign alert_en_shadowed_13_re = addr_hit[88] & reg_re & !reg_error; - assign alert_en_shadowed_13_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_shadowed_13_re = addr_hit[83] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_shadowed_13_wd = reg_wdata[0]; - assign alert_en_shadowed_14_re = addr_hit[89] & reg_re & !reg_error; - assign alert_en_shadowed_14_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_shadowed_14_re = addr_hit[84] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_shadowed_14_wd = reg_wdata[0]; - assign alert_en_shadowed_15_re = addr_hit[90] & reg_re & !reg_error; - assign alert_en_shadowed_15_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_shadowed_15_re = addr_hit[85] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_shadowed_15_wd = reg_wdata[0]; - assign alert_en_shadowed_16_re = addr_hit[91] & reg_re & !reg_error; - assign alert_en_shadowed_16_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_shadowed_16_re = addr_hit[86] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_shadowed_16_wd = reg_wdata[0]; - assign alert_en_shadowed_17_re = addr_hit[92] & reg_re & !reg_error; - assign alert_en_shadowed_17_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_shadowed_17_re = addr_hit[87] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_shadowed_17_wd = reg_wdata[0]; - assign alert_en_shadowed_18_re = addr_hit[93] & reg_re & !reg_error; - assign alert_en_shadowed_18_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_shadowed_18_re = addr_hit[88] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_shadowed_18_wd = reg_wdata[0]; - assign alert_en_shadowed_19_re = addr_hit[94] & reg_re & !reg_error; - assign alert_en_shadowed_19_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_shadowed_19_re = addr_hit[89] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_shadowed_19_wd = reg_wdata[0]; - assign alert_en_shadowed_20_re = addr_hit[95] & reg_re & !reg_error; - assign alert_en_shadowed_20_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_shadowed_20_re = addr_hit[90] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_shadowed_20_wd = reg_wdata[0]; - assign alert_en_shadowed_21_re = addr_hit[96] & reg_re & !reg_error; - assign alert_en_shadowed_21_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_shadowed_21_re = addr_hit[91] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_shadowed_21_wd = reg_wdata[0]; - assign alert_en_shadowed_22_re = addr_hit[97] & reg_re & !reg_error; - assign alert_en_shadowed_22_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_shadowed_22_re = addr_hit[92] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_shadowed_22_wd = reg_wdata[0]; - assign alert_en_shadowed_23_re = addr_hit[98] & reg_re & !reg_error; - assign alert_en_shadowed_23_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_shadowed_23_re = addr_hit[93] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_shadowed_23_wd = reg_wdata[0]; - assign alert_en_shadowed_24_re = addr_hit[99] & reg_re & !reg_error; - assign alert_en_shadowed_24_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_shadowed_24_re = addr_hit[94] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_shadowed_24_wd = reg_wdata[0]; - assign alert_en_shadowed_25_re = addr_hit[100] & reg_re & !reg_error; - assign alert_en_shadowed_25_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_shadowed_25_re = addr_hit[95] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_shadowed_25_wd = reg_wdata[0]; - assign alert_en_shadowed_26_re = addr_hit[101] & reg_re & !reg_error; - assign alert_en_shadowed_26_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_shadowed_26_re = addr_hit[96] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_shadowed_26_wd = reg_wdata[0]; - assign alert_en_shadowed_27_re = addr_hit[102] & reg_re & !reg_error; - assign alert_en_shadowed_27_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_shadowed_27_re = addr_hit[97] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_shadowed_27_wd = reg_wdata[0]; - assign alert_en_shadowed_28_re = addr_hit[103] & reg_re & !reg_error; - assign alert_en_shadowed_28_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_shadowed_28_re = addr_hit[98] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_shadowed_28_wd = reg_wdata[0]; - assign alert_en_shadowed_29_re = addr_hit[104] & reg_re & !reg_error; - assign alert_en_shadowed_29_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_shadowed_29_re = addr_hit[99] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_shadowed_29_wd = reg_wdata[0]; - assign alert_en_shadowed_30_re = addr_hit[105] & reg_re & !reg_error; - assign alert_en_shadowed_30_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_shadowed_30_re = addr_hit[100] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_shadowed_30_wd = reg_wdata[0]; - assign alert_en_shadowed_31_re = addr_hit[106] & reg_re & !reg_error; - assign alert_en_shadowed_31_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_shadowed_31_re = addr_hit[101] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_shadowed_31_wd = reg_wdata[0]; - assign alert_en_shadowed_32_re = addr_hit[107] & reg_re & !reg_error; - assign alert_en_shadowed_32_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_shadowed_32_re = addr_hit[102] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_shadowed_32_wd = reg_wdata[0]; - assign alert_en_shadowed_33_re = addr_hit[108] & reg_re & !reg_error; - assign alert_en_shadowed_33_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_shadowed_33_re = addr_hit[103] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_shadowed_33_wd = reg_wdata[0]; - assign alert_en_shadowed_34_re = addr_hit[109] & reg_re & !reg_error; - assign alert_en_shadowed_34_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_shadowed_34_re = addr_hit[104] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_shadowed_34_wd = reg_wdata[0]; - assign alert_en_shadowed_35_re = addr_hit[110] & reg_re & !reg_error; - assign alert_en_shadowed_35_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_shadowed_35_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_shadowed_35_wd = reg_wdata[0]; - assign alert_en_shadowed_36_re = addr_hit[111] & reg_re & !reg_error; - assign alert_en_shadowed_36_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_shadowed_36_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_shadowed_36_wd = reg_wdata[0]; - assign alert_en_shadowed_37_re = addr_hit[112] & reg_re & !reg_error; - assign alert_en_shadowed_37_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_shadowed_37_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_shadowed_37_wd = reg_wdata[0]; - assign alert_en_shadowed_38_re = addr_hit[113] & reg_re & !reg_error; - assign alert_en_shadowed_38_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_shadowed_38_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_shadowed_38_wd = reg_wdata[0]; - assign alert_en_shadowed_39_re = addr_hit[114] & reg_re & !reg_error; - assign alert_en_shadowed_39_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_shadowed_39_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_shadowed_39_wd = reg_wdata[0]; - assign alert_en_shadowed_40_re = addr_hit[115] & reg_re & !reg_error; - assign alert_en_shadowed_40_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_shadowed_40_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_shadowed_40_wd = reg_wdata[0]; - assign alert_en_shadowed_41_re = addr_hit[116] & reg_re & !reg_error; - assign alert_en_shadowed_41_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_shadowed_41_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_shadowed_41_wd = reg_wdata[0]; - assign alert_en_shadowed_42_re = addr_hit[117] & reg_re & !reg_error; - assign alert_en_shadowed_42_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_shadowed_42_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_shadowed_42_wd = reg_wdata[0]; - assign alert_en_shadowed_43_re = addr_hit[118] & reg_re & !reg_error; - assign alert_en_shadowed_43_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_shadowed_43_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_shadowed_43_wd = reg_wdata[0]; - assign alert_en_shadowed_44_re = addr_hit[119] & reg_re & !reg_error; - assign alert_en_shadowed_44_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_shadowed_44_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_shadowed_44_wd = reg_wdata[0]; - assign alert_en_shadowed_45_re = addr_hit[120] & reg_re & !reg_error; - assign alert_en_shadowed_45_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_shadowed_45_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_shadowed_45_wd = reg_wdata[0]; - assign alert_en_shadowed_46_re = addr_hit[121] & reg_re & !reg_error; - assign alert_en_shadowed_46_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_shadowed_46_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_shadowed_46_wd = reg_wdata[0]; - assign alert_en_shadowed_47_re = addr_hit[122] & reg_re & !reg_error; - assign alert_en_shadowed_47_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_shadowed_47_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_shadowed_47_wd = reg_wdata[0]; - assign alert_en_shadowed_48_re = addr_hit[123] & reg_re & !reg_error; - assign alert_en_shadowed_48_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_shadowed_48_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_shadowed_48_wd = reg_wdata[0]; - assign alert_en_shadowed_49_re = addr_hit[124] & reg_re & !reg_error; - assign alert_en_shadowed_49_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_shadowed_49_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_shadowed_49_wd = reg_wdata[0]; - assign alert_en_shadowed_50_re = addr_hit[125] & reg_re & !reg_error; - assign alert_en_shadowed_50_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_shadowed_50_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_shadowed_50_wd = reg_wdata[0]; - assign alert_en_shadowed_51_re = addr_hit[126] & reg_re & !reg_error; - assign alert_en_shadowed_51_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_shadowed_51_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_shadowed_51_wd = reg_wdata[0]; - assign alert_en_shadowed_52_re = addr_hit[127] & reg_re & !reg_error; - assign alert_en_shadowed_52_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_shadowed_52_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_shadowed_52_wd = reg_wdata[0]; - assign alert_en_shadowed_53_re = addr_hit[128] & reg_re & !reg_error; - assign alert_en_shadowed_53_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_shadowed_53_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_shadowed_53_wd = reg_wdata[0]; - assign alert_en_shadowed_54_re = addr_hit[129] & reg_re & !reg_error; - assign alert_en_shadowed_54_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_shadowed_54_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_shadowed_54_wd = reg_wdata[0]; - assign alert_en_shadowed_55_re = addr_hit[130] & reg_re & !reg_error; - assign alert_en_shadowed_55_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_shadowed_55_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_shadowed_55_wd = reg_wdata[0]; - assign alert_en_shadowed_56_re = addr_hit[131] & reg_re & !reg_error; - assign alert_en_shadowed_56_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_shadowed_56_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_shadowed_56_wd = reg_wdata[0]; - assign alert_en_shadowed_57_re = addr_hit[132] & reg_re & !reg_error; - assign alert_en_shadowed_57_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_shadowed_57_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_shadowed_57_wd = reg_wdata[0]; - assign alert_en_shadowed_58_re = addr_hit[133] & reg_re & !reg_error; - assign alert_en_shadowed_58_we = addr_hit[133] & reg_we & !reg_error; + assign alert_en_shadowed_58_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_shadowed_58_wd = reg_wdata[0]; - assign alert_en_shadowed_59_re = addr_hit[134] & reg_re & !reg_error; - assign alert_en_shadowed_59_we = addr_hit[134] & reg_we & !reg_error; + assign alert_en_shadowed_59_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_shadowed_59_wd = reg_wdata[0]; - assign alert_en_shadowed_60_re = addr_hit[135] & reg_re & !reg_error; - assign alert_en_shadowed_60_we = addr_hit[135] & reg_we & !reg_error; + assign alert_en_shadowed_60_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_shadowed_60_wd = reg_wdata[0]; - assign alert_en_shadowed_61_re = addr_hit[136] & reg_re & !reg_error; - assign alert_en_shadowed_61_we = addr_hit[136] & reg_we & !reg_error; + assign alert_en_shadowed_61_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_shadowed_61_wd = reg_wdata[0]; - assign alert_en_shadowed_62_re = addr_hit[137] & reg_re & !reg_error; - assign alert_en_shadowed_62_we = addr_hit[137] & reg_we & !reg_error; + assign alert_en_shadowed_62_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_shadowed_62_wd = reg_wdata[0]; - assign alert_en_shadowed_63_re = addr_hit[138] & reg_re & !reg_error; - assign alert_en_shadowed_63_we = addr_hit[138] & reg_we & !reg_error; + assign alert_en_shadowed_63_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_shadowed_63_wd = reg_wdata[0]; - assign alert_en_shadowed_64_re = addr_hit[139] & reg_re & !reg_error; - assign alert_en_shadowed_64_we = addr_hit[139] & reg_we & !reg_error; - - assign alert_en_shadowed_64_wd = reg_wdata[0]; - assign alert_en_shadowed_65_re = addr_hit[140] & reg_re & !reg_error; - assign alert_en_shadowed_65_we = addr_hit[140] & reg_we & !reg_error; - - assign alert_en_shadowed_65_wd = reg_wdata[0]; - assign alert_en_shadowed_66_re = addr_hit[141] & reg_re & !reg_error; - assign alert_en_shadowed_66_we = addr_hit[141] & reg_we & !reg_error; - - assign alert_en_shadowed_66_wd = reg_wdata[0]; - assign alert_en_shadowed_67_re = addr_hit[142] & reg_re & !reg_error; - assign alert_en_shadowed_67_we = addr_hit[142] & reg_we & !reg_error; - - assign alert_en_shadowed_67_wd = reg_wdata[0]; - assign alert_en_shadowed_68_re = addr_hit[143] & reg_re & !reg_error; - assign alert_en_shadowed_68_we = addr_hit[143] & reg_we & !reg_error; - - assign alert_en_shadowed_68_wd = reg_wdata[0]; - assign alert_class_shadowed_0_re = addr_hit[144] & reg_re & !reg_error; - assign alert_class_shadowed_0_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_shadowed_0_re = addr_hit[134] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[134] & reg_we & !reg_error; assign alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign alert_class_shadowed_1_re = addr_hit[145] & reg_re & !reg_error; - assign alert_class_shadowed_1_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_shadowed_1_re = addr_hit[135] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[135] & reg_we & !reg_error; assign alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign alert_class_shadowed_2_re = addr_hit[146] & reg_re & !reg_error; - assign alert_class_shadowed_2_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_shadowed_2_re = addr_hit[136] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[136] & reg_we & !reg_error; assign alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign alert_class_shadowed_3_re = addr_hit[147] & reg_re & !reg_error; - assign alert_class_shadowed_3_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_shadowed_3_re = addr_hit[137] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[137] & reg_we & !reg_error; assign alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign alert_class_shadowed_4_re = addr_hit[148] & reg_re & !reg_error; - assign alert_class_shadowed_4_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_shadowed_4_re = addr_hit[138] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[138] & reg_we & !reg_error; assign alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign alert_class_shadowed_5_re = addr_hit[149] & reg_re & !reg_error; - assign alert_class_shadowed_5_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_shadowed_5_re = addr_hit[139] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[139] & reg_we & !reg_error; assign alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign alert_class_shadowed_6_re = addr_hit[150] & reg_re & !reg_error; - assign alert_class_shadowed_6_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_shadowed_6_re = addr_hit[140] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[140] & reg_we & !reg_error; assign alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign alert_class_shadowed_7_re = addr_hit[151] & reg_re & !reg_error; - assign alert_class_shadowed_7_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_shadowed_7_re = addr_hit[141] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[141] & reg_we & !reg_error; assign alert_class_shadowed_7_wd = reg_wdata[1:0]; - assign alert_class_shadowed_8_re = addr_hit[152] & reg_re & !reg_error; - assign alert_class_shadowed_8_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_shadowed_8_re = addr_hit[142] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[142] & reg_we & !reg_error; assign alert_class_shadowed_8_wd = reg_wdata[1:0]; - assign alert_class_shadowed_9_re = addr_hit[153] & reg_re & !reg_error; - assign alert_class_shadowed_9_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_shadowed_9_re = addr_hit[143] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[143] & reg_we & !reg_error; assign alert_class_shadowed_9_wd = reg_wdata[1:0]; - assign alert_class_shadowed_10_re = addr_hit[154] & reg_re & !reg_error; - assign alert_class_shadowed_10_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_shadowed_10_re = addr_hit[144] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_shadowed_10_wd = reg_wdata[1:0]; - assign alert_class_shadowed_11_re = addr_hit[155] & reg_re & !reg_error; - assign alert_class_shadowed_11_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_shadowed_11_re = addr_hit[145] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_shadowed_11_wd = reg_wdata[1:0]; - assign alert_class_shadowed_12_re = addr_hit[156] & reg_re & !reg_error; - assign alert_class_shadowed_12_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_shadowed_12_re = addr_hit[146] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_shadowed_12_wd = reg_wdata[1:0]; - assign alert_class_shadowed_13_re = addr_hit[157] & reg_re & !reg_error; - assign alert_class_shadowed_13_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_shadowed_13_re = addr_hit[147] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_shadowed_13_wd = reg_wdata[1:0]; - assign alert_class_shadowed_14_re = addr_hit[158] & reg_re & !reg_error; - assign alert_class_shadowed_14_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_shadowed_14_re = addr_hit[148] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_shadowed_14_wd = reg_wdata[1:0]; - assign alert_class_shadowed_15_re = addr_hit[159] & reg_re & !reg_error; - assign alert_class_shadowed_15_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_shadowed_15_re = addr_hit[149] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_shadowed_15_wd = reg_wdata[1:0]; - assign alert_class_shadowed_16_re = addr_hit[160] & reg_re & !reg_error; - assign alert_class_shadowed_16_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_shadowed_16_re = addr_hit[150] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_shadowed_16_wd = reg_wdata[1:0]; - assign alert_class_shadowed_17_re = addr_hit[161] & reg_re & !reg_error; - assign alert_class_shadowed_17_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_shadowed_17_re = addr_hit[151] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_shadowed_17_wd = reg_wdata[1:0]; - assign alert_class_shadowed_18_re = addr_hit[162] & reg_re & !reg_error; - assign alert_class_shadowed_18_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_shadowed_18_re = addr_hit[152] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_shadowed_18_wd = reg_wdata[1:0]; - assign alert_class_shadowed_19_re = addr_hit[163] & reg_re & !reg_error; - assign alert_class_shadowed_19_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_shadowed_19_re = addr_hit[153] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_shadowed_19_wd = reg_wdata[1:0]; - assign alert_class_shadowed_20_re = addr_hit[164] & reg_re & !reg_error; - assign alert_class_shadowed_20_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_shadowed_20_re = addr_hit[154] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_shadowed_20_wd = reg_wdata[1:0]; - assign alert_class_shadowed_21_re = addr_hit[165] & reg_re & !reg_error; - assign alert_class_shadowed_21_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_shadowed_21_re = addr_hit[155] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_shadowed_21_wd = reg_wdata[1:0]; - assign alert_class_shadowed_22_re = addr_hit[166] & reg_re & !reg_error; - assign alert_class_shadowed_22_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_shadowed_22_re = addr_hit[156] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_shadowed_22_wd = reg_wdata[1:0]; - assign alert_class_shadowed_23_re = addr_hit[167] & reg_re & !reg_error; - assign alert_class_shadowed_23_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_shadowed_23_re = addr_hit[157] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_shadowed_23_wd = reg_wdata[1:0]; - assign alert_class_shadowed_24_re = addr_hit[168] & reg_re & !reg_error; - assign alert_class_shadowed_24_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_shadowed_24_re = addr_hit[158] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_shadowed_24_wd = reg_wdata[1:0]; - assign alert_class_shadowed_25_re = addr_hit[169] & reg_re & !reg_error; - assign alert_class_shadowed_25_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_shadowed_25_re = addr_hit[159] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_shadowed_25_wd = reg_wdata[1:0]; - assign alert_class_shadowed_26_re = addr_hit[170] & reg_re & !reg_error; - assign alert_class_shadowed_26_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_shadowed_26_re = addr_hit[160] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_shadowed_26_wd = reg_wdata[1:0]; - assign alert_class_shadowed_27_re = addr_hit[171] & reg_re & !reg_error; - assign alert_class_shadowed_27_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_shadowed_27_re = addr_hit[161] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_shadowed_27_wd = reg_wdata[1:0]; - assign alert_class_shadowed_28_re = addr_hit[172] & reg_re & !reg_error; - assign alert_class_shadowed_28_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_shadowed_28_re = addr_hit[162] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_shadowed_28_wd = reg_wdata[1:0]; - assign alert_class_shadowed_29_re = addr_hit[173] & reg_re & !reg_error; - assign alert_class_shadowed_29_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_shadowed_29_re = addr_hit[163] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_shadowed_29_wd = reg_wdata[1:0]; - assign alert_class_shadowed_30_re = addr_hit[174] & reg_re & !reg_error; - assign alert_class_shadowed_30_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_shadowed_30_re = addr_hit[164] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_shadowed_30_wd = reg_wdata[1:0]; - assign alert_class_shadowed_31_re = addr_hit[175] & reg_re & !reg_error; - assign alert_class_shadowed_31_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_shadowed_31_re = addr_hit[165] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_shadowed_31_wd = reg_wdata[1:0]; - assign alert_class_shadowed_32_re = addr_hit[176] & reg_re & !reg_error; - assign alert_class_shadowed_32_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_shadowed_32_re = addr_hit[166] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_shadowed_32_wd = reg_wdata[1:0]; - assign alert_class_shadowed_33_re = addr_hit[177] & reg_re & !reg_error; - assign alert_class_shadowed_33_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_shadowed_33_re = addr_hit[167] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_shadowed_33_wd = reg_wdata[1:0]; - assign alert_class_shadowed_34_re = addr_hit[178] & reg_re & !reg_error; - assign alert_class_shadowed_34_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_shadowed_34_re = addr_hit[168] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_shadowed_34_wd = reg_wdata[1:0]; - assign alert_class_shadowed_35_re = addr_hit[179] & reg_re & !reg_error; - assign alert_class_shadowed_35_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_shadowed_35_re = addr_hit[169] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_shadowed_35_wd = reg_wdata[1:0]; - assign alert_class_shadowed_36_re = addr_hit[180] & reg_re & !reg_error; - assign alert_class_shadowed_36_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_shadowed_36_re = addr_hit[170] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_shadowed_36_wd = reg_wdata[1:0]; - assign alert_class_shadowed_37_re = addr_hit[181] & reg_re & !reg_error; - assign alert_class_shadowed_37_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_shadowed_37_re = addr_hit[171] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_shadowed_37_wd = reg_wdata[1:0]; - assign alert_class_shadowed_38_re = addr_hit[182] & reg_re & !reg_error; - assign alert_class_shadowed_38_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_shadowed_38_re = addr_hit[172] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_shadowed_38_wd = reg_wdata[1:0]; - assign alert_class_shadowed_39_re = addr_hit[183] & reg_re & !reg_error; - assign alert_class_shadowed_39_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_shadowed_39_re = addr_hit[173] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_shadowed_39_wd = reg_wdata[1:0]; - assign alert_class_shadowed_40_re = addr_hit[184] & reg_re & !reg_error; - assign alert_class_shadowed_40_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_shadowed_40_re = addr_hit[174] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_shadowed_40_wd = reg_wdata[1:0]; - assign alert_class_shadowed_41_re = addr_hit[185] & reg_re & !reg_error; - assign alert_class_shadowed_41_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_shadowed_41_re = addr_hit[175] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_shadowed_41_wd = reg_wdata[1:0]; - assign alert_class_shadowed_42_re = addr_hit[186] & reg_re & !reg_error; - assign alert_class_shadowed_42_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_shadowed_42_re = addr_hit[176] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_shadowed_42_wd = reg_wdata[1:0]; - assign alert_class_shadowed_43_re = addr_hit[187] & reg_re & !reg_error; - assign alert_class_shadowed_43_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_shadowed_43_re = addr_hit[177] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_shadowed_43_wd = reg_wdata[1:0]; - assign alert_class_shadowed_44_re = addr_hit[188] & reg_re & !reg_error; - assign alert_class_shadowed_44_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_shadowed_44_re = addr_hit[178] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_shadowed_44_wd = reg_wdata[1:0]; - assign alert_class_shadowed_45_re = addr_hit[189] & reg_re & !reg_error; - assign alert_class_shadowed_45_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_shadowed_45_re = addr_hit[179] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_shadowed_45_wd = reg_wdata[1:0]; - assign alert_class_shadowed_46_re = addr_hit[190] & reg_re & !reg_error; - assign alert_class_shadowed_46_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_shadowed_46_re = addr_hit[180] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_shadowed_46_wd = reg_wdata[1:0]; - assign alert_class_shadowed_47_re = addr_hit[191] & reg_re & !reg_error; - assign alert_class_shadowed_47_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_shadowed_47_re = addr_hit[181] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_shadowed_47_wd = reg_wdata[1:0]; - assign alert_class_shadowed_48_re = addr_hit[192] & reg_re & !reg_error; - assign alert_class_shadowed_48_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_shadowed_48_re = addr_hit[182] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_shadowed_48_wd = reg_wdata[1:0]; - assign alert_class_shadowed_49_re = addr_hit[193] & reg_re & !reg_error; - assign alert_class_shadowed_49_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_shadowed_49_re = addr_hit[183] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_shadowed_49_wd = reg_wdata[1:0]; - assign alert_class_shadowed_50_re = addr_hit[194] & reg_re & !reg_error; - assign alert_class_shadowed_50_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_shadowed_50_re = addr_hit[184] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_shadowed_50_wd = reg_wdata[1:0]; - assign alert_class_shadowed_51_re = addr_hit[195] & reg_re & !reg_error; - assign alert_class_shadowed_51_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_shadowed_51_re = addr_hit[185] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_shadowed_51_wd = reg_wdata[1:0]; - assign alert_class_shadowed_52_re = addr_hit[196] & reg_re & !reg_error; - assign alert_class_shadowed_52_we = addr_hit[196] & reg_we & !reg_error; + assign alert_class_shadowed_52_re = addr_hit[186] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_shadowed_52_wd = reg_wdata[1:0]; - assign alert_class_shadowed_53_re = addr_hit[197] & reg_re & !reg_error; - assign alert_class_shadowed_53_we = addr_hit[197] & reg_we & !reg_error; + assign alert_class_shadowed_53_re = addr_hit[187] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_shadowed_53_wd = reg_wdata[1:0]; - assign alert_class_shadowed_54_re = addr_hit[198] & reg_re & !reg_error; - assign alert_class_shadowed_54_we = addr_hit[198] & reg_we & !reg_error; + assign alert_class_shadowed_54_re = addr_hit[188] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_shadowed_54_wd = reg_wdata[1:0]; - assign alert_class_shadowed_55_re = addr_hit[199] & reg_re & !reg_error; - assign alert_class_shadowed_55_we = addr_hit[199] & reg_we & !reg_error; + assign alert_class_shadowed_55_re = addr_hit[189] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_shadowed_55_wd = reg_wdata[1:0]; - assign alert_class_shadowed_56_re = addr_hit[200] & reg_re & !reg_error; - assign alert_class_shadowed_56_we = addr_hit[200] & reg_we & !reg_error; + assign alert_class_shadowed_56_re = addr_hit[190] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_shadowed_56_wd = reg_wdata[1:0]; - assign alert_class_shadowed_57_re = addr_hit[201] & reg_re & !reg_error; - assign alert_class_shadowed_57_we = addr_hit[201] & reg_we & !reg_error; + assign alert_class_shadowed_57_re = addr_hit[191] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_shadowed_57_wd = reg_wdata[1:0]; - assign alert_class_shadowed_58_re = addr_hit[202] & reg_re & !reg_error; - assign alert_class_shadowed_58_we = addr_hit[202] & reg_we & !reg_error; + assign alert_class_shadowed_58_re = addr_hit[192] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_shadowed_58_wd = reg_wdata[1:0]; - assign alert_class_shadowed_59_re = addr_hit[203] & reg_re & !reg_error; - assign alert_class_shadowed_59_we = addr_hit[203] & reg_we & !reg_error; + assign alert_class_shadowed_59_re = addr_hit[193] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_shadowed_59_wd = reg_wdata[1:0]; - assign alert_class_shadowed_60_re = addr_hit[204] & reg_re & !reg_error; - assign alert_class_shadowed_60_we = addr_hit[204] & reg_we & !reg_error; + assign alert_class_shadowed_60_re = addr_hit[194] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_shadowed_60_wd = reg_wdata[1:0]; - assign alert_class_shadowed_61_re = addr_hit[205] & reg_re & !reg_error; - assign alert_class_shadowed_61_we = addr_hit[205] & reg_we & !reg_error; + assign alert_class_shadowed_61_re = addr_hit[195] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_shadowed_61_wd = reg_wdata[1:0]; - assign alert_class_shadowed_62_re = addr_hit[206] & reg_re & !reg_error; - assign alert_class_shadowed_62_we = addr_hit[206] & reg_we & !reg_error; + assign alert_class_shadowed_62_re = addr_hit[196] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_shadowed_62_wd = reg_wdata[1:0]; - assign alert_class_shadowed_63_re = addr_hit[207] & reg_re & !reg_error; - assign alert_class_shadowed_63_we = addr_hit[207] & reg_we & !reg_error; + assign alert_class_shadowed_63_re = addr_hit[197] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_shadowed_63_wd = reg_wdata[1:0]; - assign alert_class_shadowed_64_re = addr_hit[208] & reg_re & !reg_error; - assign alert_class_shadowed_64_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_0_we = addr_hit[198] & reg_we & !reg_error; - assign alert_class_shadowed_64_wd = reg_wdata[1:0]; - assign alert_class_shadowed_65_re = addr_hit[209] & reg_re & !reg_error; - assign alert_class_shadowed_65_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_0_wd = reg_wdata[0]; + assign alert_cause_1_we = addr_hit[199] & reg_we & !reg_error; - assign alert_class_shadowed_65_wd = reg_wdata[1:0]; - assign alert_class_shadowed_66_re = addr_hit[210] & reg_re & !reg_error; - assign alert_class_shadowed_66_we = addr_hit[210] & reg_we & !reg_error; - - assign alert_class_shadowed_66_wd = reg_wdata[1:0]; - assign alert_class_shadowed_67_re = addr_hit[211] & reg_re & !reg_error; - assign alert_class_shadowed_67_we = addr_hit[211] & reg_we & !reg_error; - - assign alert_class_shadowed_67_wd = reg_wdata[1:0]; - assign alert_class_shadowed_68_re = addr_hit[212] & reg_re & !reg_error; - assign alert_class_shadowed_68_we = addr_hit[212] & reg_we & !reg_error; - - assign alert_class_shadowed_68_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[213] & reg_we & !reg_error; - - assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[214] & reg_we & !reg_error; - - assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_1_wd = reg_wdata[0]; + assign alert_cause_2_we = addr_hit[200] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[201] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[202] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[203] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[204] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[205] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[206] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[207] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[208] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[209] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[210] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[211] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[212] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[259] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[260] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[261] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[262] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[263] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[264] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[265] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[266] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[267] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[268] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[269] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[270] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[271] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[272] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[273] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[274] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[275] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign alert_cause_63_we = addr_hit[276] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_63_wd = reg_wdata[0]; - assign alert_cause_64_we = addr_hit[277] & reg_we & !reg_error; - - assign alert_cause_64_wd = reg_wdata[0]; - assign alert_cause_65_we = addr_hit[278] & reg_we & !reg_error; - - assign alert_cause_65_wd = reg_wdata[0]; - assign alert_cause_66_we = addr_hit[279] & reg_we & !reg_error; - - assign alert_cause_66_wd = reg_wdata[0]; - assign alert_cause_67_we = addr_hit[280] & reg_we & !reg_error; - - assign alert_cause_67_wd = reg_wdata[0]; - assign alert_cause_68_we = addr_hit[281] & reg_we & !reg_error; - - assign alert_cause_68_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_regwen_0_we = addr_hit[262] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[263] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[264] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[265] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[286] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[266] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_regwen_5_we = addr_hit[287] & reg_we & !reg_error; + assign loc_alert_regwen_5_we = addr_hit[267] & reg_we & !reg_error; assign loc_alert_regwen_5_wd = reg_wdata[0]; - assign loc_alert_regwen_6_we = addr_hit[288] & reg_we & !reg_error; + assign loc_alert_regwen_6_we = addr_hit[268] & reg_we & !reg_error; assign loc_alert_regwen_6_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_0_re = addr_hit[289] & reg_re & !reg_error; - assign loc_alert_en_shadowed_0_we = addr_hit[289] & reg_we & !reg_error; + assign loc_alert_en_shadowed_0_re = addr_hit[269] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[269] & reg_we & !reg_error; assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_1_re = addr_hit[290] & reg_re & !reg_error; - assign loc_alert_en_shadowed_1_we = addr_hit[290] & reg_we & !reg_error; + assign loc_alert_en_shadowed_1_re = addr_hit[270] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[270] & reg_we & !reg_error; assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_2_re = addr_hit[291] & reg_re & !reg_error; - assign loc_alert_en_shadowed_2_we = addr_hit[291] & reg_we & !reg_error; + assign loc_alert_en_shadowed_2_re = addr_hit[271] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[271] & reg_we & !reg_error; assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_3_re = addr_hit[292] & reg_re & !reg_error; - assign loc_alert_en_shadowed_3_we = addr_hit[292] & reg_we & !reg_error; + assign loc_alert_en_shadowed_3_re = addr_hit[272] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[272] & reg_we & !reg_error; assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_4_re = addr_hit[293] & reg_re & !reg_error; - assign loc_alert_en_shadowed_4_we = addr_hit[293] & reg_we & !reg_error; + assign loc_alert_en_shadowed_4_re = addr_hit[273] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[273] & reg_we & !reg_error; assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_5_re = addr_hit[294] & reg_re & !reg_error; - assign loc_alert_en_shadowed_5_we = addr_hit[294] & reg_we & !reg_error; + assign loc_alert_en_shadowed_5_re = addr_hit[274] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[274] & reg_we & !reg_error; assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_6_re = addr_hit[295] & reg_re & !reg_error; - assign loc_alert_en_shadowed_6_we = addr_hit[295] & reg_we & !reg_error; + assign loc_alert_en_shadowed_6_re = addr_hit[275] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[275] & reg_we & !reg_error; assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; - assign loc_alert_class_shadowed_0_re = addr_hit[296] & reg_re & !reg_error; - assign loc_alert_class_shadowed_0_we = addr_hit[296] & reg_we & !reg_error; + assign loc_alert_class_shadowed_0_re = addr_hit[276] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[276] & reg_we & !reg_error; assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_1_re = addr_hit[297] & reg_re & !reg_error; - assign loc_alert_class_shadowed_1_we = addr_hit[297] & reg_we & !reg_error; + assign loc_alert_class_shadowed_1_re = addr_hit[277] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[277] & reg_we & !reg_error; assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_2_re = addr_hit[298] & reg_re & !reg_error; - assign loc_alert_class_shadowed_2_we = addr_hit[298] & reg_we & !reg_error; + assign loc_alert_class_shadowed_2_re = addr_hit[278] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[278] & reg_we & !reg_error; assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_3_re = addr_hit[299] & reg_re & !reg_error; - assign loc_alert_class_shadowed_3_we = addr_hit[299] & reg_we & !reg_error; + assign loc_alert_class_shadowed_3_re = addr_hit[279] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[279] & reg_we & !reg_error; assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_4_re = addr_hit[300] & reg_re & !reg_error; - assign loc_alert_class_shadowed_4_we = addr_hit[300] & reg_we & !reg_error; + assign loc_alert_class_shadowed_4_re = addr_hit[280] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[280] & reg_we & !reg_error; assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_5_re = addr_hit[301] & reg_re & !reg_error; - assign loc_alert_class_shadowed_5_we = addr_hit[301] & reg_we & !reg_error; + assign loc_alert_class_shadowed_5_re = addr_hit[281] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[281] & reg_we & !reg_error; assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_6_re = addr_hit[302] & reg_re & !reg_error; - assign loc_alert_class_shadowed_6_we = addr_hit[302] & reg_we & !reg_error; + assign loc_alert_class_shadowed_6_re = addr_hit[282] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[303] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[304] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[305] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[306] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[307] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign loc_alert_cause_5_we = addr_hit[308] & reg_we & !reg_error; + assign loc_alert_cause_5_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_cause_5_wd = reg_wdata[0]; - assign loc_alert_cause_6_we = addr_hit[309] & reg_we & !reg_error; + assign loc_alert_cause_6_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_cause_6_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[310] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[290] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_shadowed_re = addr_hit[311] & reg_re & !reg_error; - assign classa_ctrl_shadowed_we = addr_hit[311] & reg_we & !reg_error; + assign classa_ctrl_shadowed_re = addr_hit[291] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[291] & reg_we & !reg_error; assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -18065,49 +17165,49 @@ module alert_handler_reg_top ( assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[312] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[292] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_shadowed_re = addr_hit[313] & reg_re & !reg_error; - assign classa_clr_shadowed_we = addr_hit[313] & reg_we & !reg_error; + assign classa_clr_shadowed_re = addr_hit[293] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[293] & reg_we & !reg_error; assign classa_clr_shadowed_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[314] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_re = addr_hit[315] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_we = addr_hit[315] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[294] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[295] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[295] & reg_we & !reg_error; assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error; - assign classa_timeout_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error; + assign classa_timeout_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error; assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_crashdump_trigger_shadowed_re = addr_hit[317] & reg_re & !reg_error; - assign classa_crashdump_trigger_shadowed_we = addr_hit[317] & reg_we & !reg_error; + assign classa_crashdump_trigger_shadowed_re = addr_hit[297] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[297] & reg_we & !reg_error; assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classa_phase0_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error; - assign classa_phase0_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error; + assign classa_phase0_cyc_shadowed_re = addr_hit[298] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[298] & reg_we & !reg_error; assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error; - assign classa_phase1_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error; + assign classa_phase1_cyc_shadowed_re = addr_hit[299] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[299] & reg_we & !reg_error; assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error; - assign classa_phase2_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error; + assign classa_phase2_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error; assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_shadowed_re = addr_hit[321] & reg_re & !reg_error; - assign classa_phase3_cyc_shadowed_we = addr_hit[321] & reg_we & !reg_error; + assign classa_phase3_cyc_shadowed_re = addr_hit[301] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[301] & reg_we & !reg_error; assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[322] & reg_re & !reg_error; - assign classa_state_re = addr_hit[323] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[324] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[302] & reg_re & !reg_error; + assign classa_state_re = addr_hit[303] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[304] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_shadowed_re = addr_hit[325] & reg_re & !reg_error; - assign classb_ctrl_shadowed_we = addr_hit[325] & reg_we & !reg_error; + assign classb_ctrl_shadowed_re = addr_hit[305] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[305] & reg_we & !reg_error; assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -18128,49 +17228,49 @@ module alert_handler_reg_top ( assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[326] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[306] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_shadowed_re = addr_hit[327] & reg_re & !reg_error; - assign classb_clr_shadowed_we = addr_hit[327] & reg_we & !reg_error; + assign classb_clr_shadowed_re = addr_hit[307] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[307] & reg_we & !reg_error; assign classb_clr_shadowed_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[328] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_re = addr_hit[329] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_we = addr_hit[329] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[308] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[309] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[309] & reg_we & !reg_error; assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error; - assign classb_timeout_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error; + assign classb_timeout_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error; assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_crashdump_trigger_shadowed_re = addr_hit[331] & reg_re & !reg_error; - assign classb_crashdump_trigger_shadowed_we = addr_hit[331] & reg_we & !reg_error; + assign classb_crashdump_trigger_shadowed_re = addr_hit[311] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[311] & reg_we & !reg_error; assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classb_phase0_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error; - assign classb_phase0_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error; + assign classb_phase0_cyc_shadowed_re = addr_hit[312] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[312] & reg_we & !reg_error; assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error; - assign classb_phase1_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error; + assign classb_phase1_cyc_shadowed_re = addr_hit[313] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[313] & reg_we & !reg_error; assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_shadowed_re = addr_hit[334] & reg_re & !reg_error; - assign classb_phase2_cyc_shadowed_we = addr_hit[334] & reg_we & !reg_error; + assign classb_phase2_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error; assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_shadowed_re = addr_hit[335] & reg_re & !reg_error; - assign classb_phase3_cyc_shadowed_we = addr_hit[335] & reg_we & !reg_error; + assign classb_phase3_cyc_shadowed_re = addr_hit[315] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[315] & reg_we & !reg_error; assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[336] & reg_re & !reg_error; - assign classb_state_re = addr_hit[337] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[338] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[316] & reg_re & !reg_error; + assign classb_state_re = addr_hit[317] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[318] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_shadowed_re = addr_hit[339] & reg_re & !reg_error; - assign classc_ctrl_shadowed_we = addr_hit[339] & reg_we & !reg_error; + assign classc_ctrl_shadowed_re = addr_hit[319] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[319] & reg_we & !reg_error; assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -18191,49 +17291,49 @@ module alert_handler_reg_top ( assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[340] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[320] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_shadowed_re = addr_hit[341] & reg_re & !reg_error; - assign classc_clr_shadowed_we = addr_hit[341] & reg_we & !reg_error; + assign classc_clr_shadowed_re = addr_hit[321] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[321] & reg_we & !reg_error; assign classc_clr_shadowed_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[342] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_re = addr_hit[343] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_we = addr_hit[343] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[322] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[323] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[323] & reg_we & !reg_error; assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error; - assign classc_timeout_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error; + assign classc_timeout_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error; assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_crashdump_trigger_shadowed_re = addr_hit[345] & reg_re & !reg_error; - assign classc_crashdump_trigger_shadowed_we = addr_hit[345] & reg_we & !reg_error; + assign classc_crashdump_trigger_shadowed_re = addr_hit[325] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[325] & reg_we & !reg_error; assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classc_phase0_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error; - assign classc_phase0_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error; + assign classc_phase0_cyc_shadowed_re = addr_hit[326] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[326] & reg_we & !reg_error; assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error; - assign classc_phase1_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error; + assign classc_phase1_cyc_shadowed_re = addr_hit[327] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[327] & reg_we & !reg_error; assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_shadowed_re = addr_hit[348] & reg_re & !reg_error; - assign classc_phase2_cyc_shadowed_we = addr_hit[348] & reg_we & !reg_error; + assign classc_phase2_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error; assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_shadowed_re = addr_hit[349] & reg_re & !reg_error; - assign classc_phase3_cyc_shadowed_we = addr_hit[349] & reg_we & !reg_error; + assign classc_phase3_cyc_shadowed_re = addr_hit[329] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[329] & reg_we & !reg_error; assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[350] & reg_re & !reg_error; - assign classc_state_re = addr_hit[351] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[352] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[330] & reg_re & !reg_error; + assign classc_state_re = addr_hit[331] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[332] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_shadowed_re = addr_hit[353] & reg_re & !reg_error; - assign classd_ctrl_shadowed_we = addr_hit[353] & reg_we & !reg_error; + assign classd_ctrl_shadowed_re = addr_hit[333] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[333] & reg_we & !reg_error; assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -18254,44 +17354,44 @@ module alert_handler_reg_top ( assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[354] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[334] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_shadowed_re = addr_hit[355] & reg_re & !reg_error; - assign classd_clr_shadowed_we = addr_hit[355] & reg_we & !reg_error; + assign classd_clr_shadowed_re = addr_hit[335] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[335] & reg_we & !reg_error; assign classd_clr_shadowed_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[356] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_re = addr_hit[357] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_we = addr_hit[357] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[336] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[337] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[337] & reg_we & !reg_error; assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_shadowed_re = addr_hit[358] & reg_re & !reg_error; - assign classd_timeout_cyc_shadowed_we = addr_hit[358] & reg_we & !reg_error; + assign classd_timeout_cyc_shadowed_re = addr_hit[338] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[338] & reg_we & !reg_error; assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_crashdump_trigger_shadowed_re = addr_hit[359] & reg_re & !reg_error; - assign classd_crashdump_trigger_shadowed_we = addr_hit[359] & reg_we & !reg_error; + assign classd_crashdump_trigger_shadowed_re = addr_hit[339] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[339] & reg_we & !reg_error; assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classd_phase0_cyc_shadowed_re = addr_hit[360] & reg_re & !reg_error; - assign classd_phase0_cyc_shadowed_we = addr_hit[360] & reg_we & !reg_error; + assign classd_phase0_cyc_shadowed_re = addr_hit[340] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[340] & reg_we & !reg_error; assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_shadowed_re = addr_hit[361] & reg_re & !reg_error; - assign classd_phase1_cyc_shadowed_we = addr_hit[361] & reg_we & !reg_error; + assign classd_phase1_cyc_shadowed_re = addr_hit[341] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[341] & reg_we & !reg_error; assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_shadowed_re = addr_hit[362] & reg_re & !reg_error; - assign classd_phase2_cyc_shadowed_we = addr_hit[362] & reg_we & !reg_error; + assign classd_phase2_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error; assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_shadowed_re = addr_hit[363] & reg_re & !reg_error; - assign classd_phase3_cyc_shadowed_we = addr_hit[363] & reg_we & !reg_error; + assign classd_phase3_cyc_shadowed_re = addr_hit[343] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[343] & reg_we & !reg_error; assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[364] & reg_re & !reg_error; - assign classd_state_re = addr_hit[365] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[344] & reg_re & !reg_error; + assign classd_state_re = addr_hit[345] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -18365,302 +17465,282 @@ module alert_handler_reg_top ( reg_we_check[67] = alert_regwen_61_we; reg_we_check[68] = alert_regwen_62_we; reg_we_check[69] = alert_regwen_63_we; - reg_we_check[70] = alert_regwen_64_we; - reg_we_check[71] = alert_regwen_65_we; - reg_we_check[72] = alert_regwen_66_we; - reg_we_check[73] = alert_regwen_67_we; - reg_we_check[74] = alert_regwen_68_we; - reg_we_check[75] = alert_en_shadowed_0_gated_we; - reg_we_check[76] = alert_en_shadowed_1_gated_we; - reg_we_check[77] = alert_en_shadowed_2_gated_we; - reg_we_check[78] = alert_en_shadowed_3_gated_we; - reg_we_check[79] = alert_en_shadowed_4_gated_we; - reg_we_check[80] = alert_en_shadowed_5_gated_we; - reg_we_check[81] = alert_en_shadowed_6_gated_we; - reg_we_check[82] = alert_en_shadowed_7_gated_we; - reg_we_check[83] = alert_en_shadowed_8_gated_we; - reg_we_check[84] = alert_en_shadowed_9_gated_we; - reg_we_check[85] = alert_en_shadowed_10_gated_we; - reg_we_check[86] = alert_en_shadowed_11_gated_we; - reg_we_check[87] = alert_en_shadowed_12_gated_we; - reg_we_check[88] = alert_en_shadowed_13_gated_we; - reg_we_check[89] = alert_en_shadowed_14_gated_we; - reg_we_check[90] = alert_en_shadowed_15_gated_we; - reg_we_check[91] = alert_en_shadowed_16_gated_we; - reg_we_check[92] = alert_en_shadowed_17_gated_we; - reg_we_check[93] = alert_en_shadowed_18_gated_we; - reg_we_check[94] = alert_en_shadowed_19_gated_we; - reg_we_check[95] = alert_en_shadowed_20_gated_we; - reg_we_check[96] = alert_en_shadowed_21_gated_we; - reg_we_check[97] = alert_en_shadowed_22_gated_we; - reg_we_check[98] = alert_en_shadowed_23_gated_we; - reg_we_check[99] = alert_en_shadowed_24_gated_we; - reg_we_check[100] = alert_en_shadowed_25_gated_we; - reg_we_check[101] = alert_en_shadowed_26_gated_we; - reg_we_check[102] = alert_en_shadowed_27_gated_we; - reg_we_check[103] = alert_en_shadowed_28_gated_we; - reg_we_check[104] = alert_en_shadowed_29_gated_we; - reg_we_check[105] = alert_en_shadowed_30_gated_we; - reg_we_check[106] = alert_en_shadowed_31_gated_we; - reg_we_check[107] = alert_en_shadowed_32_gated_we; - reg_we_check[108] = alert_en_shadowed_33_gated_we; - reg_we_check[109] = alert_en_shadowed_34_gated_we; - reg_we_check[110] = alert_en_shadowed_35_gated_we; - reg_we_check[111] = alert_en_shadowed_36_gated_we; - reg_we_check[112] = alert_en_shadowed_37_gated_we; - reg_we_check[113] = alert_en_shadowed_38_gated_we; - reg_we_check[114] = alert_en_shadowed_39_gated_we; - reg_we_check[115] = alert_en_shadowed_40_gated_we; - reg_we_check[116] = alert_en_shadowed_41_gated_we; - reg_we_check[117] = alert_en_shadowed_42_gated_we; - reg_we_check[118] = alert_en_shadowed_43_gated_we; - reg_we_check[119] = alert_en_shadowed_44_gated_we; - reg_we_check[120] = alert_en_shadowed_45_gated_we; - reg_we_check[121] = alert_en_shadowed_46_gated_we; - reg_we_check[122] = alert_en_shadowed_47_gated_we; - reg_we_check[123] = alert_en_shadowed_48_gated_we; - reg_we_check[124] = alert_en_shadowed_49_gated_we; - reg_we_check[125] = alert_en_shadowed_50_gated_we; - reg_we_check[126] = alert_en_shadowed_51_gated_we; - reg_we_check[127] = alert_en_shadowed_52_gated_we; - reg_we_check[128] = alert_en_shadowed_53_gated_we; - reg_we_check[129] = alert_en_shadowed_54_gated_we; - reg_we_check[130] = alert_en_shadowed_55_gated_we; - reg_we_check[131] = alert_en_shadowed_56_gated_we; - reg_we_check[132] = alert_en_shadowed_57_gated_we; - reg_we_check[133] = alert_en_shadowed_58_gated_we; - reg_we_check[134] = alert_en_shadowed_59_gated_we; - reg_we_check[135] = alert_en_shadowed_60_gated_we; - reg_we_check[136] = alert_en_shadowed_61_gated_we; - reg_we_check[137] = alert_en_shadowed_62_gated_we; - reg_we_check[138] = alert_en_shadowed_63_gated_we; - reg_we_check[139] = alert_en_shadowed_64_gated_we; - reg_we_check[140] = alert_en_shadowed_65_gated_we; - reg_we_check[141] = alert_en_shadowed_66_gated_we; - reg_we_check[142] = alert_en_shadowed_67_gated_we; - reg_we_check[143] = alert_en_shadowed_68_gated_we; - reg_we_check[144] = alert_class_shadowed_0_gated_we; - reg_we_check[145] = alert_class_shadowed_1_gated_we; - reg_we_check[146] = alert_class_shadowed_2_gated_we; - reg_we_check[147] = alert_class_shadowed_3_gated_we; - reg_we_check[148] = alert_class_shadowed_4_gated_we; - reg_we_check[149] = alert_class_shadowed_5_gated_we; - reg_we_check[150] = alert_class_shadowed_6_gated_we; - reg_we_check[151] = alert_class_shadowed_7_gated_we; - reg_we_check[152] = alert_class_shadowed_8_gated_we; - reg_we_check[153] = alert_class_shadowed_9_gated_we; - reg_we_check[154] = alert_class_shadowed_10_gated_we; - reg_we_check[155] = alert_class_shadowed_11_gated_we; - reg_we_check[156] = alert_class_shadowed_12_gated_we; - reg_we_check[157] = alert_class_shadowed_13_gated_we; - reg_we_check[158] = alert_class_shadowed_14_gated_we; - reg_we_check[159] = alert_class_shadowed_15_gated_we; - reg_we_check[160] = alert_class_shadowed_16_gated_we; - reg_we_check[161] = alert_class_shadowed_17_gated_we; - reg_we_check[162] = alert_class_shadowed_18_gated_we; - reg_we_check[163] = alert_class_shadowed_19_gated_we; - reg_we_check[164] = alert_class_shadowed_20_gated_we; - reg_we_check[165] = alert_class_shadowed_21_gated_we; - reg_we_check[166] = alert_class_shadowed_22_gated_we; - reg_we_check[167] = alert_class_shadowed_23_gated_we; - reg_we_check[168] = alert_class_shadowed_24_gated_we; - reg_we_check[169] = alert_class_shadowed_25_gated_we; - reg_we_check[170] = alert_class_shadowed_26_gated_we; - reg_we_check[171] = alert_class_shadowed_27_gated_we; - reg_we_check[172] = alert_class_shadowed_28_gated_we; - reg_we_check[173] = alert_class_shadowed_29_gated_we; - reg_we_check[174] = alert_class_shadowed_30_gated_we; - reg_we_check[175] = alert_class_shadowed_31_gated_we; - reg_we_check[176] = alert_class_shadowed_32_gated_we; - reg_we_check[177] = alert_class_shadowed_33_gated_we; - reg_we_check[178] = alert_class_shadowed_34_gated_we; - reg_we_check[179] = alert_class_shadowed_35_gated_we; - reg_we_check[180] = alert_class_shadowed_36_gated_we; - reg_we_check[181] = alert_class_shadowed_37_gated_we; - reg_we_check[182] = alert_class_shadowed_38_gated_we; - reg_we_check[183] = alert_class_shadowed_39_gated_we; - reg_we_check[184] = alert_class_shadowed_40_gated_we; - reg_we_check[185] = alert_class_shadowed_41_gated_we; - reg_we_check[186] = alert_class_shadowed_42_gated_we; - reg_we_check[187] = alert_class_shadowed_43_gated_we; - reg_we_check[188] = alert_class_shadowed_44_gated_we; - reg_we_check[189] = alert_class_shadowed_45_gated_we; - reg_we_check[190] = alert_class_shadowed_46_gated_we; - reg_we_check[191] = alert_class_shadowed_47_gated_we; - reg_we_check[192] = alert_class_shadowed_48_gated_we; - reg_we_check[193] = alert_class_shadowed_49_gated_we; - reg_we_check[194] = alert_class_shadowed_50_gated_we; - reg_we_check[195] = alert_class_shadowed_51_gated_we; - reg_we_check[196] = alert_class_shadowed_52_gated_we; - reg_we_check[197] = alert_class_shadowed_53_gated_we; - reg_we_check[198] = alert_class_shadowed_54_gated_we; - reg_we_check[199] = alert_class_shadowed_55_gated_we; - reg_we_check[200] = alert_class_shadowed_56_gated_we; - reg_we_check[201] = alert_class_shadowed_57_gated_we; - reg_we_check[202] = alert_class_shadowed_58_gated_we; - reg_we_check[203] = alert_class_shadowed_59_gated_we; - reg_we_check[204] = alert_class_shadowed_60_gated_we; - reg_we_check[205] = alert_class_shadowed_61_gated_we; - reg_we_check[206] = alert_class_shadowed_62_gated_we; - reg_we_check[207] = alert_class_shadowed_63_gated_we; - reg_we_check[208] = alert_class_shadowed_64_gated_we; - reg_we_check[209] = alert_class_shadowed_65_gated_we; - reg_we_check[210] = alert_class_shadowed_66_gated_we; - reg_we_check[211] = alert_class_shadowed_67_gated_we; - reg_we_check[212] = alert_class_shadowed_68_gated_we; - reg_we_check[213] = alert_cause_0_we; - reg_we_check[214] = alert_cause_1_we; - reg_we_check[215] = alert_cause_2_we; - reg_we_check[216] = alert_cause_3_we; - reg_we_check[217] = alert_cause_4_we; - reg_we_check[218] = alert_cause_5_we; - reg_we_check[219] = alert_cause_6_we; - reg_we_check[220] = alert_cause_7_we; - reg_we_check[221] = alert_cause_8_we; - reg_we_check[222] = alert_cause_9_we; - reg_we_check[223] = alert_cause_10_we; - reg_we_check[224] = alert_cause_11_we; - reg_we_check[225] = alert_cause_12_we; - reg_we_check[226] = alert_cause_13_we; - reg_we_check[227] = alert_cause_14_we; - reg_we_check[228] = alert_cause_15_we; - reg_we_check[229] = alert_cause_16_we; - reg_we_check[230] = alert_cause_17_we; - reg_we_check[231] = alert_cause_18_we; - reg_we_check[232] = alert_cause_19_we; - reg_we_check[233] = alert_cause_20_we; - reg_we_check[234] = alert_cause_21_we; - reg_we_check[235] = alert_cause_22_we; - reg_we_check[236] = alert_cause_23_we; - reg_we_check[237] = alert_cause_24_we; - reg_we_check[238] = alert_cause_25_we; - reg_we_check[239] = alert_cause_26_we; - reg_we_check[240] = alert_cause_27_we; - reg_we_check[241] = alert_cause_28_we; - reg_we_check[242] = alert_cause_29_we; - reg_we_check[243] = alert_cause_30_we; - reg_we_check[244] = alert_cause_31_we; - reg_we_check[245] = alert_cause_32_we; - reg_we_check[246] = alert_cause_33_we; - reg_we_check[247] = alert_cause_34_we; - reg_we_check[248] = alert_cause_35_we; - reg_we_check[249] = alert_cause_36_we; - reg_we_check[250] = alert_cause_37_we; - reg_we_check[251] = alert_cause_38_we; - reg_we_check[252] = alert_cause_39_we; - reg_we_check[253] = alert_cause_40_we; - reg_we_check[254] = alert_cause_41_we; - reg_we_check[255] = alert_cause_42_we; - reg_we_check[256] = alert_cause_43_we; - reg_we_check[257] = alert_cause_44_we; - reg_we_check[258] = alert_cause_45_we; - reg_we_check[259] = alert_cause_46_we; - reg_we_check[260] = alert_cause_47_we; - reg_we_check[261] = alert_cause_48_we; - reg_we_check[262] = alert_cause_49_we; - reg_we_check[263] = alert_cause_50_we; - reg_we_check[264] = alert_cause_51_we; - reg_we_check[265] = alert_cause_52_we; - reg_we_check[266] = alert_cause_53_we; - reg_we_check[267] = alert_cause_54_we; - reg_we_check[268] = alert_cause_55_we; - reg_we_check[269] = alert_cause_56_we; - reg_we_check[270] = alert_cause_57_we; - reg_we_check[271] = alert_cause_58_we; - reg_we_check[272] = alert_cause_59_we; - reg_we_check[273] = alert_cause_60_we; - reg_we_check[274] = alert_cause_61_we; - reg_we_check[275] = alert_cause_62_we; - reg_we_check[276] = alert_cause_63_we; - reg_we_check[277] = alert_cause_64_we; - reg_we_check[278] = alert_cause_65_we; - reg_we_check[279] = alert_cause_66_we; - reg_we_check[280] = alert_cause_67_we; - reg_we_check[281] = alert_cause_68_we; - reg_we_check[282] = loc_alert_regwen_0_we; - reg_we_check[283] = loc_alert_regwen_1_we; - reg_we_check[284] = loc_alert_regwen_2_we; - reg_we_check[285] = loc_alert_regwen_3_we; - reg_we_check[286] = loc_alert_regwen_4_we; - reg_we_check[287] = loc_alert_regwen_5_we; - reg_we_check[288] = loc_alert_regwen_6_we; - reg_we_check[289] = loc_alert_en_shadowed_0_gated_we; - reg_we_check[290] = loc_alert_en_shadowed_1_gated_we; - reg_we_check[291] = loc_alert_en_shadowed_2_gated_we; - reg_we_check[292] = loc_alert_en_shadowed_3_gated_we; - reg_we_check[293] = loc_alert_en_shadowed_4_gated_we; - reg_we_check[294] = loc_alert_en_shadowed_5_gated_we; - reg_we_check[295] = loc_alert_en_shadowed_6_gated_we; - reg_we_check[296] = loc_alert_class_shadowed_0_gated_we; - reg_we_check[297] = loc_alert_class_shadowed_1_gated_we; - reg_we_check[298] = loc_alert_class_shadowed_2_gated_we; - reg_we_check[299] = loc_alert_class_shadowed_3_gated_we; - reg_we_check[300] = loc_alert_class_shadowed_4_gated_we; - reg_we_check[301] = loc_alert_class_shadowed_5_gated_we; - reg_we_check[302] = loc_alert_class_shadowed_6_gated_we; - reg_we_check[303] = loc_alert_cause_0_we; - reg_we_check[304] = loc_alert_cause_1_we; - reg_we_check[305] = loc_alert_cause_2_we; - reg_we_check[306] = loc_alert_cause_3_we; - reg_we_check[307] = loc_alert_cause_4_we; - reg_we_check[308] = loc_alert_cause_5_we; - reg_we_check[309] = loc_alert_cause_6_we; - reg_we_check[310] = classa_regwen_we; - reg_we_check[311] = classa_ctrl_shadowed_gated_we; - reg_we_check[312] = classa_clr_regwen_we; - reg_we_check[313] = classa_clr_shadowed_gated_we; - reg_we_check[314] = 1'b0; - reg_we_check[315] = classa_accum_thresh_shadowed_gated_we; - reg_we_check[316] = classa_timeout_cyc_shadowed_gated_we; - reg_we_check[317] = classa_crashdump_trigger_shadowed_gated_we; - reg_we_check[318] = classa_phase0_cyc_shadowed_gated_we; - reg_we_check[319] = classa_phase1_cyc_shadowed_gated_we; - reg_we_check[320] = classa_phase2_cyc_shadowed_gated_we; - reg_we_check[321] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[70] = alert_en_shadowed_0_gated_we; + reg_we_check[71] = alert_en_shadowed_1_gated_we; + reg_we_check[72] = alert_en_shadowed_2_gated_we; + reg_we_check[73] = alert_en_shadowed_3_gated_we; + reg_we_check[74] = alert_en_shadowed_4_gated_we; + reg_we_check[75] = alert_en_shadowed_5_gated_we; + reg_we_check[76] = alert_en_shadowed_6_gated_we; + reg_we_check[77] = alert_en_shadowed_7_gated_we; + reg_we_check[78] = alert_en_shadowed_8_gated_we; + reg_we_check[79] = alert_en_shadowed_9_gated_we; + reg_we_check[80] = alert_en_shadowed_10_gated_we; + reg_we_check[81] = alert_en_shadowed_11_gated_we; + reg_we_check[82] = alert_en_shadowed_12_gated_we; + reg_we_check[83] = alert_en_shadowed_13_gated_we; + reg_we_check[84] = alert_en_shadowed_14_gated_we; + reg_we_check[85] = alert_en_shadowed_15_gated_we; + reg_we_check[86] = alert_en_shadowed_16_gated_we; + reg_we_check[87] = alert_en_shadowed_17_gated_we; + reg_we_check[88] = alert_en_shadowed_18_gated_we; + reg_we_check[89] = alert_en_shadowed_19_gated_we; + reg_we_check[90] = alert_en_shadowed_20_gated_we; + reg_we_check[91] = alert_en_shadowed_21_gated_we; + reg_we_check[92] = alert_en_shadowed_22_gated_we; + reg_we_check[93] = alert_en_shadowed_23_gated_we; + reg_we_check[94] = alert_en_shadowed_24_gated_we; + reg_we_check[95] = alert_en_shadowed_25_gated_we; + reg_we_check[96] = alert_en_shadowed_26_gated_we; + reg_we_check[97] = alert_en_shadowed_27_gated_we; + reg_we_check[98] = alert_en_shadowed_28_gated_we; + reg_we_check[99] = alert_en_shadowed_29_gated_we; + reg_we_check[100] = alert_en_shadowed_30_gated_we; + reg_we_check[101] = alert_en_shadowed_31_gated_we; + reg_we_check[102] = alert_en_shadowed_32_gated_we; + reg_we_check[103] = alert_en_shadowed_33_gated_we; + reg_we_check[104] = alert_en_shadowed_34_gated_we; + reg_we_check[105] = alert_en_shadowed_35_gated_we; + reg_we_check[106] = alert_en_shadowed_36_gated_we; + reg_we_check[107] = alert_en_shadowed_37_gated_we; + reg_we_check[108] = alert_en_shadowed_38_gated_we; + reg_we_check[109] = alert_en_shadowed_39_gated_we; + reg_we_check[110] = alert_en_shadowed_40_gated_we; + reg_we_check[111] = alert_en_shadowed_41_gated_we; + reg_we_check[112] = alert_en_shadowed_42_gated_we; + reg_we_check[113] = alert_en_shadowed_43_gated_we; + reg_we_check[114] = alert_en_shadowed_44_gated_we; + reg_we_check[115] = alert_en_shadowed_45_gated_we; + reg_we_check[116] = alert_en_shadowed_46_gated_we; + reg_we_check[117] = alert_en_shadowed_47_gated_we; + reg_we_check[118] = alert_en_shadowed_48_gated_we; + reg_we_check[119] = alert_en_shadowed_49_gated_we; + reg_we_check[120] = alert_en_shadowed_50_gated_we; + reg_we_check[121] = alert_en_shadowed_51_gated_we; + reg_we_check[122] = alert_en_shadowed_52_gated_we; + reg_we_check[123] = alert_en_shadowed_53_gated_we; + reg_we_check[124] = alert_en_shadowed_54_gated_we; + reg_we_check[125] = alert_en_shadowed_55_gated_we; + reg_we_check[126] = alert_en_shadowed_56_gated_we; + reg_we_check[127] = alert_en_shadowed_57_gated_we; + reg_we_check[128] = alert_en_shadowed_58_gated_we; + reg_we_check[129] = alert_en_shadowed_59_gated_we; + reg_we_check[130] = alert_en_shadowed_60_gated_we; + reg_we_check[131] = alert_en_shadowed_61_gated_we; + reg_we_check[132] = alert_en_shadowed_62_gated_we; + reg_we_check[133] = alert_en_shadowed_63_gated_we; + reg_we_check[134] = alert_class_shadowed_0_gated_we; + reg_we_check[135] = alert_class_shadowed_1_gated_we; + reg_we_check[136] = alert_class_shadowed_2_gated_we; + reg_we_check[137] = alert_class_shadowed_3_gated_we; + reg_we_check[138] = alert_class_shadowed_4_gated_we; + reg_we_check[139] = alert_class_shadowed_5_gated_we; + reg_we_check[140] = alert_class_shadowed_6_gated_we; + reg_we_check[141] = alert_class_shadowed_7_gated_we; + reg_we_check[142] = alert_class_shadowed_8_gated_we; + reg_we_check[143] = alert_class_shadowed_9_gated_we; + reg_we_check[144] = alert_class_shadowed_10_gated_we; + reg_we_check[145] = alert_class_shadowed_11_gated_we; + reg_we_check[146] = alert_class_shadowed_12_gated_we; + reg_we_check[147] = alert_class_shadowed_13_gated_we; + reg_we_check[148] = alert_class_shadowed_14_gated_we; + reg_we_check[149] = alert_class_shadowed_15_gated_we; + reg_we_check[150] = alert_class_shadowed_16_gated_we; + reg_we_check[151] = alert_class_shadowed_17_gated_we; + reg_we_check[152] = alert_class_shadowed_18_gated_we; + reg_we_check[153] = alert_class_shadowed_19_gated_we; + reg_we_check[154] = alert_class_shadowed_20_gated_we; + reg_we_check[155] = alert_class_shadowed_21_gated_we; + reg_we_check[156] = alert_class_shadowed_22_gated_we; + reg_we_check[157] = alert_class_shadowed_23_gated_we; + reg_we_check[158] = alert_class_shadowed_24_gated_we; + reg_we_check[159] = alert_class_shadowed_25_gated_we; + reg_we_check[160] = alert_class_shadowed_26_gated_we; + reg_we_check[161] = alert_class_shadowed_27_gated_we; + reg_we_check[162] = alert_class_shadowed_28_gated_we; + reg_we_check[163] = alert_class_shadowed_29_gated_we; + reg_we_check[164] = alert_class_shadowed_30_gated_we; + reg_we_check[165] = alert_class_shadowed_31_gated_we; + reg_we_check[166] = alert_class_shadowed_32_gated_we; + reg_we_check[167] = alert_class_shadowed_33_gated_we; + reg_we_check[168] = alert_class_shadowed_34_gated_we; + reg_we_check[169] = alert_class_shadowed_35_gated_we; + reg_we_check[170] = alert_class_shadowed_36_gated_we; + reg_we_check[171] = alert_class_shadowed_37_gated_we; + reg_we_check[172] = alert_class_shadowed_38_gated_we; + reg_we_check[173] = alert_class_shadowed_39_gated_we; + reg_we_check[174] = alert_class_shadowed_40_gated_we; + reg_we_check[175] = alert_class_shadowed_41_gated_we; + reg_we_check[176] = alert_class_shadowed_42_gated_we; + reg_we_check[177] = alert_class_shadowed_43_gated_we; + reg_we_check[178] = alert_class_shadowed_44_gated_we; + reg_we_check[179] = alert_class_shadowed_45_gated_we; + reg_we_check[180] = alert_class_shadowed_46_gated_we; + reg_we_check[181] = alert_class_shadowed_47_gated_we; + reg_we_check[182] = alert_class_shadowed_48_gated_we; + reg_we_check[183] = alert_class_shadowed_49_gated_we; + reg_we_check[184] = alert_class_shadowed_50_gated_we; + reg_we_check[185] = alert_class_shadowed_51_gated_we; + reg_we_check[186] = alert_class_shadowed_52_gated_we; + reg_we_check[187] = alert_class_shadowed_53_gated_we; + reg_we_check[188] = alert_class_shadowed_54_gated_we; + reg_we_check[189] = alert_class_shadowed_55_gated_we; + reg_we_check[190] = alert_class_shadowed_56_gated_we; + reg_we_check[191] = alert_class_shadowed_57_gated_we; + reg_we_check[192] = alert_class_shadowed_58_gated_we; + reg_we_check[193] = alert_class_shadowed_59_gated_we; + reg_we_check[194] = alert_class_shadowed_60_gated_we; + reg_we_check[195] = alert_class_shadowed_61_gated_we; + reg_we_check[196] = alert_class_shadowed_62_gated_we; + reg_we_check[197] = alert_class_shadowed_63_gated_we; + reg_we_check[198] = alert_cause_0_we; + reg_we_check[199] = alert_cause_1_we; + reg_we_check[200] = alert_cause_2_we; + reg_we_check[201] = alert_cause_3_we; + reg_we_check[202] = alert_cause_4_we; + reg_we_check[203] = alert_cause_5_we; + reg_we_check[204] = alert_cause_6_we; + reg_we_check[205] = alert_cause_7_we; + reg_we_check[206] = alert_cause_8_we; + reg_we_check[207] = alert_cause_9_we; + reg_we_check[208] = alert_cause_10_we; + reg_we_check[209] = alert_cause_11_we; + reg_we_check[210] = alert_cause_12_we; + reg_we_check[211] = alert_cause_13_we; + reg_we_check[212] = alert_cause_14_we; + reg_we_check[213] = alert_cause_15_we; + reg_we_check[214] = alert_cause_16_we; + reg_we_check[215] = alert_cause_17_we; + reg_we_check[216] = alert_cause_18_we; + reg_we_check[217] = alert_cause_19_we; + reg_we_check[218] = alert_cause_20_we; + reg_we_check[219] = alert_cause_21_we; + reg_we_check[220] = alert_cause_22_we; + reg_we_check[221] = alert_cause_23_we; + reg_we_check[222] = alert_cause_24_we; + reg_we_check[223] = alert_cause_25_we; + reg_we_check[224] = alert_cause_26_we; + reg_we_check[225] = alert_cause_27_we; + reg_we_check[226] = alert_cause_28_we; + reg_we_check[227] = alert_cause_29_we; + reg_we_check[228] = alert_cause_30_we; + reg_we_check[229] = alert_cause_31_we; + reg_we_check[230] = alert_cause_32_we; + reg_we_check[231] = alert_cause_33_we; + reg_we_check[232] = alert_cause_34_we; + reg_we_check[233] = alert_cause_35_we; + reg_we_check[234] = alert_cause_36_we; + reg_we_check[235] = alert_cause_37_we; + reg_we_check[236] = alert_cause_38_we; + reg_we_check[237] = alert_cause_39_we; + reg_we_check[238] = alert_cause_40_we; + reg_we_check[239] = alert_cause_41_we; + reg_we_check[240] = alert_cause_42_we; + reg_we_check[241] = alert_cause_43_we; + reg_we_check[242] = alert_cause_44_we; + reg_we_check[243] = alert_cause_45_we; + reg_we_check[244] = alert_cause_46_we; + reg_we_check[245] = alert_cause_47_we; + reg_we_check[246] = alert_cause_48_we; + reg_we_check[247] = alert_cause_49_we; + reg_we_check[248] = alert_cause_50_we; + reg_we_check[249] = alert_cause_51_we; + reg_we_check[250] = alert_cause_52_we; + reg_we_check[251] = alert_cause_53_we; + reg_we_check[252] = alert_cause_54_we; + reg_we_check[253] = alert_cause_55_we; + reg_we_check[254] = alert_cause_56_we; + reg_we_check[255] = alert_cause_57_we; + reg_we_check[256] = alert_cause_58_we; + reg_we_check[257] = alert_cause_59_we; + reg_we_check[258] = alert_cause_60_we; + reg_we_check[259] = alert_cause_61_we; + reg_we_check[260] = alert_cause_62_we; + reg_we_check[261] = alert_cause_63_we; + reg_we_check[262] = loc_alert_regwen_0_we; + reg_we_check[263] = loc_alert_regwen_1_we; + reg_we_check[264] = loc_alert_regwen_2_we; + reg_we_check[265] = loc_alert_regwen_3_we; + reg_we_check[266] = loc_alert_regwen_4_we; + reg_we_check[267] = loc_alert_regwen_5_we; + reg_we_check[268] = loc_alert_regwen_6_we; + reg_we_check[269] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[270] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[271] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[272] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[273] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[274] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[275] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[276] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[277] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[278] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[279] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[280] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[281] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[282] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[283] = loc_alert_cause_0_we; + reg_we_check[284] = loc_alert_cause_1_we; + reg_we_check[285] = loc_alert_cause_2_we; + reg_we_check[286] = loc_alert_cause_3_we; + reg_we_check[287] = loc_alert_cause_4_we; + reg_we_check[288] = loc_alert_cause_5_we; + reg_we_check[289] = loc_alert_cause_6_we; + reg_we_check[290] = classa_regwen_we; + reg_we_check[291] = classa_ctrl_shadowed_gated_we; + reg_we_check[292] = classa_clr_regwen_we; + reg_we_check[293] = classa_clr_shadowed_gated_we; + reg_we_check[294] = 1'b0; + reg_we_check[295] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[296] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[297] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[298] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[299] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[300] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[301] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[302] = 1'b0; + reg_we_check[303] = 1'b0; + reg_we_check[304] = classb_regwen_we; + reg_we_check[305] = classb_ctrl_shadowed_gated_we; + reg_we_check[306] = classb_clr_regwen_we; + reg_we_check[307] = classb_clr_shadowed_gated_we; + reg_we_check[308] = 1'b0; + reg_we_check[309] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[310] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[311] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[312] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[313] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[314] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[315] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[316] = 1'b0; + reg_we_check[317] = 1'b0; + reg_we_check[318] = classc_regwen_we; + reg_we_check[319] = classc_ctrl_shadowed_gated_we; + reg_we_check[320] = classc_clr_regwen_we; + reg_we_check[321] = classc_clr_shadowed_gated_we; reg_we_check[322] = 1'b0; - reg_we_check[323] = 1'b0; - reg_we_check[324] = classb_regwen_we; - reg_we_check[325] = classb_ctrl_shadowed_gated_we; - reg_we_check[326] = classb_clr_regwen_we; - reg_we_check[327] = classb_clr_shadowed_gated_we; - reg_we_check[328] = 1'b0; - reg_we_check[329] = classb_accum_thresh_shadowed_gated_we; - reg_we_check[330] = classb_timeout_cyc_shadowed_gated_we; - reg_we_check[331] = classb_crashdump_trigger_shadowed_gated_we; - reg_we_check[332] = classb_phase0_cyc_shadowed_gated_we; - reg_we_check[333] = classb_phase1_cyc_shadowed_gated_we; - reg_we_check[334] = classb_phase2_cyc_shadowed_gated_we; - reg_we_check[335] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[323] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[324] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[325] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[326] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[327] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[328] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[329] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[330] = 1'b0; + reg_we_check[331] = 1'b0; + reg_we_check[332] = classd_regwen_we; + reg_we_check[333] = classd_ctrl_shadowed_gated_we; + reg_we_check[334] = classd_clr_regwen_we; + reg_we_check[335] = classd_clr_shadowed_gated_we; reg_we_check[336] = 1'b0; - reg_we_check[337] = 1'b0; - reg_we_check[338] = classc_regwen_we; - reg_we_check[339] = classc_ctrl_shadowed_gated_we; - reg_we_check[340] = classc_clr_regwen_we; - reg_we_check[341] = classc_clr_shadowed_gated_we; - reg_we_check[342] = 1'b0; - reg_we_check[343] = classc_accum_thresh_shadowed_gated_we; - reg_we_check[344] = classc_timeout_cyc_shadowed_gated_we; - reg_we_check[345] = classc_crashdump_trigger_shadowed_gated_we; - reg_we_check[346] = classc_phase0_cyc_shadowed_gated_we; - reg_we_check[347] = classc_phase1_cyc_shadowed_gated_we; - reg_we_check[348] = classc_phase2_cyc_shadowed_gated_we; - reg_we_check[349] = classc_phase3_cyc_shadowed_gated_we; - reg_we_check[350] = 1'b0; - reg_we_check[351] = 1'b0; - reg_we_check[352] = classd_regwen_we; - reg_we_check[353] = classd_ctrl_shadowed_gated_we; - reg_we_check[354] = classd_clr_regwen_we; - reg_we_check[355] = classd_clr_shadowed_gated_we; - reg_we_check[356] = 1'b0; - reg_we_check[357] = classd_accum_thresh_shadowed_gated_we; - reg_we_check[358] = classd_timeout_cyc_shadowed_gated_we; - reg_we_check[359] = classd_crashdump_trigger_shadowed_gated_we; - reg_we_check[360] = classd_phase0_cyc_shadowed_gated_we; - reg_we_check[361] = classd_phase1_cyc_shadowed_gated_we; - reg_we_check[362] = classd_phase2_cyc_shadowed_gated_we; - reg_we_check[363] = classd_phase3_cyc_shadowed_gated_we; - reg_we_check[364] = 1'b0; - reg_we_check[365] = 1'b0; + reg_we_check[337] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[338] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[339] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[340] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[341] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[342] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[343] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[344] = 1'b0; + reg_we_check[345] = 1'b0; end // Read data return @@ -18957,970 +18037,890 @@ module alert_handler_reg_top ( end addr_hit[70]: begin - reg_rdata_next[0] = alert_regwen_64_qs; + reg_rdata_next[0] = alert_en_shadowed_0_qs; end addr_hit[71]: begin - reg_rdata_next[0] = alert_regwen_65_qs; + reg_rdata_next[0] = alert_en_shadowed_1_qs; end addr_hit[72]: begin - reg_rdata_next[0] = alert_regwen_66_qs; + reg_rdata_next[0] = alert_en_shadowed_2_qs; end addr_hit[73]: begin - reg_rdata_next[0] = alert_regwen_67_qs; + reg_rdata_next[0] = alert_en_shadowed_3_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_regwen_68_qs; + reg_rdata_next[0] = alert_en_shadowed_4_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_en_shadowed_5_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_shadowed_1_qs; + reg_rdata_next[0] = alert_en_shadowed_6_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_shadowed_2_qs; + reg_rdata_next[0] = alert_en_shadowed_7_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_shadowed_3_qs; + reg_rdata_next[0] = alert_en_shadowed_8_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_shadowed_4_qs; + reg_rdata_next[0] = alert_en_shadowed_9_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_shadowed_5_qs; + reg_rdata_next[0] = alert_en_shadowed_10_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_shadowed_6_qs; + reg_rdata_next[0] = alert_en_shadowed_11_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_shadowed_7_qs; + reg_rdata_next[0] = alert_en_shadowed_12_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_shadowed_8_qs; + reg_rdata_next[0] = alert_en_shadowed_13_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_shadowed_9_qs; + reg_rdata_next[0] = alert_en_shadowed_14_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_shadowed_10_qs; + reg_rdata_next[0] = alert_en_shadowed_15_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_shadowed_11_qs; + reg_rdata_next[0] = alert_en_shadowed_16_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_shadowed_12_qs; + reg_rdata_next[0] = alert_en_shadowed_17_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_shadowed_13_qs; + reg_rdata_next[0] = alert_en_shadowed_18_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_shadowed_14_qs; + reg_rdata_next[0] = alert_en_shadowed_19_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_shadowed_15_qs; + reg_rdata_next[0] = alert_en_shadowed_20_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_shadowed_16_qs; + reg_rdata_next[0] = alert_en_shadowed_21_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_shadowed_17_qs; + reg_rdata_next[0] = alert_en_shadowed_22_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_shadowed_18_qs; + reg_rdata_next[0] = alert_en_shadowed_23_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_shadowed_19_qs; + reg_rdata_next[0] = alert_en_shadowed_24_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_shadowed_20_qs; + reg_rdata_next[0] = alert_en_shadowed_25_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_shadowed_21_qs; + reg_rdata_next[0] = alert_en_shadowed_26_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_shadowed_22_qs; + reg_rdata_next[0] = alert_en_shadowed_27_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_shadowed_23_qs; + reg_rdata_next[0] = alert_en_shadowed_28_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_shadowed_24_qs; + reg_rdata_next[0] = alert_en_shadowed_29_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_shadowed_25_qs; + reg_rdata_next[0] = alert_en_shadowed_30_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_shadowed_26_qs; + reg_rdata_next[0] = alert_en_shadowed_31_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_shadowed_27_qs; + reg_rdata_next[0] = alert_en_shadowed_32_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_shadowed_28_qs; + reg_rdata_next[0] = alert_en_shadowed_33_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_shadowed_29_qs; + reg_rdata_next[0] = alert_en_shadowed_34_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_shadowed_30_qs; + reg_rdata_next[0] = alert_en_shadowed_35_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_shadowed_31_qs; + reg_rdata_next[0] = alert_en_shadowed_36_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_shadowed_32_qs; + reg_rdata_next[0] = alert_en_shadowed_37_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_shadowed_33_qs; + reg_rdata_next[0] = alert_en_shadowed_38_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_shadowed_34_qs; + reg_rdata_next[0] = alert_en_shadowed_39_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_shadowed_35_qs; + reg_rdata_next[0] = alert_en_shadowed_40_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_shadowed_36_qs; + reg_rdata_next[0] = alert_en_shadowed_41_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_shadowed_37_qs; + reg_rdata_next[0] = alert_en_shadowed_42_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_shadowed_38_qs; + reg_rdata_next[0] = alert_en_shadowed_43_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_shadowed_39_qs; + reg_rdata_next[0] = alert_en_shadowed_44_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_shadowed_40_qs; + reg_rdata_next[0] = alert_en_shadowed_45_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_shadowed_41_qs; + reg_rdata_next[0] = alert_en_shadowed_46_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_shadowed_42_qs; + reg_rdata_next[0] = alert_en_shadowed_47_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_shadowed_43_qs; + reg_rdata_next[0] = alert_en_shadowed_48_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_shadowed_44_qs; + reg_rdata_next[0] = alert_en_shadowed_49_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_shadowed_45_qs; + reg_rdata_next[0] = alert_en_shadowed_50_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_shadowed_46_qs; + reg_rdata_next[0] = alert_en_shadowed_51_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_shadowed_47_qs; + reg_rdata_next[0] = alert_en_shadowed_52_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_shadowed_48_qs; + reg_rdata_next[0] = alert_en_shadowed_53_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_shadowed_49_qs; + reg_rdata_next[0] = alert_en_shadowed_54_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_shadowed_50_qs; + reg_rdata_next[0] = alert_en_shadowed_55_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_shadowed_51_qs; + reg_rdata_next[0] = alert_en_shadowed_56_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_shadowed_52_qs; + reg_rdata_next[0] = alert_en_shadowed_57_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_shadowed_53_qs; + reg_rdata_next[0] = alert_en_shadowed_58_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_shadowed_54_qs; + reg_rdata_next[0] = alert_en_shadowed_59_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_shadowed_55_qs; + reg_rdata_next[0] = alert_en_shadowed_60_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_shadowed_56_qs; + reg_rdata_next[0] = alert_en_shadowed_61_qs; end addr_hit[132]: begin - reg_rdata_next[0] = alert_en_shadowed_57_qs; + reg_rdata_next[0] = alert_en_shadowed_62_qs; end addr_hit[133]: begin - reg_rdata_next[0] = alert_en_shadowed_58_qs; + reg_rdata_next[0] = alert_en_shadowed_63_qs; end addr_hit[134]: begin - reg_rdata_next[0] = alert_en_shadowed_59_qs; + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; end addr_hit[135]: begin - reg_rdata_next[0] = alert_en_shadowed_60_qs; + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; end addr_hit[136]: begin - reg_rdata_next[0] = alert_en_shadowed_61_qs; + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; end addr_hit[137]: begin - reg_rdata_next[0] = alert_en_shadowed_62_qs; + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; end addr_hit[138]: begin - reg_rdata_next[0] = alert_en_shadowed_63_qs; + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; end addr_hit[139]: begin - reg_rdata_next[0] = alert_en_shadowed_64_qs; + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; end addr_hit[140]: begin - reg_rdata_next[0] = alert_en_shadowed_65_qs; + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; end addr_hit[141]: begin - reg_rdata_next[0] = alert_en_shadowed_66_qs; + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; end addr_hit[142]: begin - reg_rdata_next[0] = alert_en_shadowed_67_qs; + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; end addr_hit[143]: begin - reg_rdata_next[0] = alert_en_shadowed_68_qs; + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = alert_class_shadowed_53_qs; - end - - addr_hit[198]: begin - reg_rdata_next[1:0] = alert_class_shadowed_54_qs; - end - - addr_hit[199]: begin - reg_rdata_next[1:0] = alert_class_shadowed_55_qs; - end - - addr_hit[200]: begin - reg_rdata_next[1:0] = alert_class_shadowed_56_qs; - end - - addr_hit[201]: begin - reg_rdata_next[1:0] = alert_class_shadowed_57_qs; - end - - addr_hit[202]: begin - reg_rdata_next[1:0] = alert_class_shadowed_58_qs; - end - - addr_hit[203]: begin - reg_rdata_next[1:0] = alert_class_shadowed_59_qs; - end - - addr_hit[204]: begin - reg_rdata_next[1:0] = alert_class_shadowed_60_qs; - end - - addr_hit[205]: begin - reg_rdata_next[1:0] = alert_class_shadowed_61_qs; - end - - addr_hit[206]: begin - reg_rdata_next[1:0] = alert_class_shadowed_62_qs; - end - - addr_hit[207]: begin reg_rdata_next[1:0] = alert_class_shadowed_63_qs; end - addr_hit[208]: begin - reg_rdata_next[1:0] = alert_class_shadowed_64_qs; - end - - addr_hit[209]: begin - reg_rdata_next[1:0] = alert_class_shadowed_65_qs; - end - - addr_hit[210]: begin - reg_rdata_next[1:0] = alert_class_shadowed_66_qs; - end - - addr_hit[211]: begin - reg_rdata_next[1:0] = alert_class_shadowed_67_qs; - end - - addr_hit[212]: begin - reg_rdata_next[1:0] = alert_class_shadowed_68_qs; - end - - addr_hit[213]: begin + addr_hit[198]: begin reg_rdata_next[0] = alert_cause_0_qs; end - addr_hit[214]: begin + addr_hit[199]: begin reg_rdata_next[0] = alert_cause_1_qs; end - addr_hit[215]: begin + addr_hit[200]: begin reg_rdata_next[0] = alert_cause_2_qs; end - addr_hit[216]: begin + addr_hit[201]: begin reg_rdata_next[0] = alert_cause_3_qs; end - addr_hit[217]: begin + addr_hit[202]: begin reg_rdata_next[0] = alert_cause_4_qs; end - addr_hit[218]: begin + addr_hit[203]: begin reg_rdata_next[0] = alert_cause_5_qs; end - addr_hit[219]: begin + addr_hit[204]: begin reg_rdata_next[0] = alert_cause_6_qs; end - addr_hit[220]: begin + addr_hit[205]: begin reg_rdata_next[0] = alert_cause_7_qs; end - addr_hit[221]: begin + addr_hit[206]: begin reg_rdata_next[0] = alert_cause_8_qs; end - addr_hit[222]: begin + addr_hit[207]: begin reg_rdata_next[0] = alert_cause_9_qs; end - addr_hit[223]: begin + addr_hit[208]: begin reg_rdata_next[0] = alert_cause_10_qs; end - addr_hit[224]: begin + addr_hit[209]: begin reg_rdata_next[0] = alert_cause_11_qs; end - addr_hit[225]: begin + addr_hit[210]: begin reg_rdata_next[0] = alert_cause_12_qs; end - addr_hit[226]: begin + addr_hit[211]: begin reg_rdata_next[0] = alert_cause_13_qs; end - addr_hit[227]: begin + addr_hit[212]: begin reg_rdata_next[0] = alert_cause_14_qs; end - addr_hit[228]: begin + addr_hit[213]: begin reg_rdata_next[0] = alert_cause_15_qs; end - addr_hit[229]: begin + addr_hit[214]: begin reg_rdata_next[0] = alert_cause_16_qs; end - addr_hit[230]: begin + addr_hit[215]: begin reg_rdata_next[0] = alert_cause_17_qs; end - addr_hit[231]: begin + addr_hit[216]: begin reg_rdata_next[0] = alert_cause_18_qs; end - addr_hit[232]: begin + addr_hit[217]: begin reg_rdata_next[0] = alert_cause_19_qs; end - addr_hit[233]: begin + addr_hit[218]: begin reg_rdata_next[0] = alert_cause_20_qs; end - addr_hit[234]: begin + addr_hit[219]: begin reg_rdata_next[0] = alert_cause_21_qs; end - addr_hit[235]: begin + addr_hit[220]: begin reg_rdata_next[0] = alert_cause_22_qs; end - addr_hit[236]: begin + addr_hit[221]: begin reg_rdata_next[0] = alert_cause_23_qs; end - addr_hit[237]: begin + addr_hit[222]: begin reg_rdata_next[0] = alert_cause_24_qs; end - addr_hit[238]: begin + addr_hit[223]: begin reg_rdata_next[0] = alert_cause_25_qs; end - addr_hit[239]: begin + addr_hit[224]: begin reg_rdata_next[0] = alert_cause_26_qs; end - addr_hit[240]: begin + addr_hit[225]: begin reg_rdata_next[0] = alert_cause_27_qs; end - addr_hit[241]: begin + addr_hit[226]: begin reg_rdata_next[0] = alert_cause_28_qs; end - addr_hit[242]: begin + addr_hit[227]: begin reg_rdata_next[0] = alert_cause_29_qs; end - addr_hit[243]: begin + addr_hit[228]: begin reg_rdata_next[0] = alert_cause_30_qs; end - addr_hit[244]: begin + addr_hit[229]: begin reg_rdata_next[0] = alert_cause_31_qs; end - addr_hit[245]: begin + addr_hit[230]: begin reg_rdata_next[0] = alert_cause_32_qs; end - addr_hit[246]: begin + addr_hit[231]: begin reg_rdata_next[0] = alert_cause_33_qs; end - addr_hit[247]: begin + addr_hit[232]: begin reg_rdata_next[0] = alert_cause_34_qs; end - addr_hit[248]: begin + addr_hit[233]: begin reg_rdata_next[0] = alert_cause_35_qs; end - addr_hit[249]: begin + addr_hit[234]: begin reg_rdata_next[0] = alert_cause_36_qs; end - addr_hit[250]: begin + addr_hit[235]: begin reg_rdata_next[0] = alert_cause_37_qs; end - addr_hit[251]: begin + addr_hit[236]: begin reg_rdata_next[0] = alert_cause_38_qs; end - addr_hit[252]: begin + addr_hit[237]: begin reg_rdata_next[0] = alert_cause_39_qs; end - addr_hit[253]: begin + addr_hit[238]: begin reg_rdata_next[0] = alert_cause_40_qs; end - addr_hit[254]: begin + addr_hit[239]: begin reg_rdata_next[0] = alert_cause_41_qs; end - addr_hit[255]: begin + addr_hit[240]: begin reg_rdata_next[0] = alert_cause_42_qs; end - addr_hit[256]: begin + addr_hit[241]: begin reg_rdata_next[0] = alert_cause_43_qs; end - addr_hit[257]: begin + addr_hit[242]: begin reg_rdata_next[0] = alert_cause_44_qs; end - addr_hit[258]: begin + addr_hit[243]: begin reg_rdata_next[0] = alert_cause_45_qs; end - addr_hit[259]: begin + addr_hit[244]: begin reg_rdata_next[0] = alert_cause_46_qs; end - addr_hit[260]: begin + addr_hit[245]: begin reg_rdata_next[0] = alert_cause_47_qs; end - addr_hit[261]: begin + addr_hit[246]: begin reg_rdata_next[0] = alert_cause_48_qs; end - addr_hit[262]: begin + addr_hit[247]: begin reg_rdata_next[0] = alert_cause_49_qs; end - addr_hit[263]: begin + addr_hit[248]: begin reg_rdata_next[0] = alert_cause_50_qs; end - addr_hit[264]: begin + addr_hit[249]: begin reg_rdata_next[0] = alert_cause_51_qs; end - addr_hit[265]: begin + addr_hit[250]: begin reg_rdata_next[0] = alert_cause_52_qs; end - addr_hit[266]: begin + addr_hit[251]: begin reg_rdata_next[0] = alert_cause_53_qs; end - addr_hit[267]: begin + addr_hit[252]: begin reg_rdata_next[0] = alert_cause_54_qs; end - addr_hit[268]: begin + addr_hit[253]: begin reg_rdata_next[0] = alert_cause_55_qs; end - addr_hit[269]: begin + addr_hit[254]: begin reg_rdata_next[0] = alert_cause_56_qs; end - addr_hit[270]: begin + addr_hit[255]: begin reg_rdata_next[0] = alert_cause_57_qs; end - addr_hit[271]: begin + addr_hit[256]: begin reg_rdata_next[0] = alert_cause_58_qs; end - addr_hit[272]: begin + addr_hit[257]: begin reg_rdata_next[0] = alert_cause_59_qs; end - addr_hit[273]: begin + addr_hit[258]: begin reg_rdata_next[0] = alert_cause_60_qs; end - addr_hit[274]: begin + addr_hit[259]: begin reg_rdata_next[0] = alert_cause_61_qs; end - addr_hit[275]: begin + addr_hit[260]: begin reg_rdata_next[0] = alert_cause_62_qs; end - addr_hit[276]: begin + addr_hit[261]: begin reg_rdata_next[0] = alert_cause_63_qs; end - addr_hit[277]: begin - reg_rdata_next[0] = alert_cause_64_qs; - end - - addr_hit[278]: begin - reg_rdata_next[0] = alert_cause_65_qs; - end - - addr_hit[279]: begin - reg_rdata_next[0] = alert_cause_66_qs; - end - - addr_hit[280]: begin - reg_rdata_next[0] = alert_cause_67_qs; - end - - addr_hit[281]: begin - reg_rdata_next[0] = alert_cause_68_qs; - end - - addr_hit[282]: begin + addr_hit[262]: begin reg_rdata_next[0] = loc_alert_regwen_0_qs; end - addr_hit[283]: begin + addr_hit[263]: begin reg_rdata_next[0] = loc_alert_regwen_1_qs; end - addr_hit[284]: begin + addr_hit[264]: begin reg_rdata_next[0] = loc_alert_regwen_2_qs; end - addr_hit[285]: begin + addr_hit[265]: begin reg_rdata_next[0] = loc_alert_regwen_3_qs; end - addr_hit[286]: begin + addr_hit[266]: begin reg_rdata_next[0] = loc_alert_regwen_4_qs; end - addr_hit[287]: begin + addr_hit[267]: begin reg_rdata_next[0] = loc_alert_regwen_5_qs; end - addr_hit[288]: begin + addr_hit[268]: begin reg_rdata_next[0] = loc_alert_regwen_6_qs; end - addr_hit[289]: begin + addr_hit[269]: begin reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; end - addr_hit[290]: begin + addr_hit[270]: begin reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; end - addr_hit[291]: begin + addr_hit[271]: begin reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; end - addr_hit[292]: begin + addr_hit[272]: begin reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; end - addr_hit[293]: begin + addr_hit[273]: begin reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; end - addr_hit[294]: begin + addr_hit[274]: begin reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; end - addr_hit[295]: begin + addr_hit[275]: begin reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; end - addr_hit[296]: begin + addr_hit[276]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; end - addr_hit[297]: begin + addr_hit[277]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; end - addr_hit[298]: begin + addr_hit[278]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; end - addr_hit[299]: begin + addr_hit[279]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; end - addr_hit[300]: begin + addr_hit[280]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; end - addr_hit[301]: begin + addr_hit[281]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; end - addr_hit[302]: begin + addr_hit[282]: begin reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; end - addr_hit[303]: begin + addr_hit[283]: begin reg_rdata_next[0] = loc_alert_cause_0_qs; end - addr_hit[304]: begin + addr_hit[284]: begin reg_rdata_next[0] = loc_alert_cause_1_qs; end - addr_hit[305]: begin + addr_hit[285]: begin reg_rdata_next[0] = loc_alert_cause_2_qs; end - addr_hit[306]: begin + addr_hit[286]: begin reg_rdata_next[0] = loc_alert_cause_3_qs; end - addr_hit[307]: begin + addr_hit[287]: begin reg_rdata_next[0] = loc_alert_cause_4_qs; end - addr_hit[308]: begin + addr_hit[288]: begin reg_rdata_next[0] = loc_alert_cause_5_qs; end - addr_hit[309]: begin + addr_hit[289]: begin reg_rdata_next[0] = loc_alert_cause_6_qs; end - addr_hit[310]: begin + addr_hit[290]: begin reg_rdata_next[0] = classa_regwen_qs; end - addr_hit[311]: begin + addr_hit[291]: begin reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; @@ -19933,59 +18933,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; end - addr_hit[312]: begin + addr_hit[292]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[313]: begin + addr_hit[293]: begin reg_rdata_next[0] = classa_clr_shadowed_qs; end - addr_hit[314]: begin + addr_hit[294]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[315]: begin + addr_hit[295]: begin reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; end - addr_hit[316]: begin + addr_hit[296]: begin reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; end - addr_hit[317]: begin + addr_hit[297]: begin reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; end - addr_hit[318]: begin + addr_hit[298]: begin reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; end - addr_hit[319]: begin + addr_hit[299]: begin reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; end - addr_hit[320]: begin + addr_hit[300]: begin reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; end - addr_hit[321]: begin + addr_hit[301]: begin reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; end - addr_hit[322]: begin + addr_hit[302]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[323]: begin + addr_hit[303]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[324]: begin + addr_hit[304]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[325]: begin + addr_hit[305]: begin reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; @@ -19998,59 +18998,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; end - addr_hit[326]: begin + addr_hit[306]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[327]: begin + addr_hit[307]: begin reg_rdata_next[0] = classb_clr_shadowed_qs; end - addr_hit[328]: begin + addr_hit[308]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[329]: begin + addr_hit[309]: begin reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; end - addr_hit[330]: begin + addr_hit[310]: begin reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; end - addr_hit[331]: begin + addr_hit[311]: begin reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; end - addr_hit[332]: begin + addr_hit[312]: begin reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; end - addr_hit[333]: begin + addr_hit[313]: begin reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; end - addr_hit[334]: begin + addr_hit[314]: begin reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; end - addr_hit[335]: begin + addr_hit[315]: begin reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; end - addr_hit[336]: begin + addr_hit[316]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[337]: begin + addr_hit[317]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[338]: begin + addr_hit[318]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[339]: begin + addr_hit[319]: begin reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; @@ -20063,59 +19063,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; end - addr_hit[340]: begin + addr_hit[320]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[341]: begin + addr_hit[321]: begin reg_rdata_next[0] = classc_clr_shadowed_qs; end - addr_hit[342]: begin + addr_hit[322]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[343]: begin + addr_hit[323]: begin reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; end - addr_hit[344]: begin + addr_hit[324]: begin reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; end - addr_hit[345]: begin + addr_hit[325]: begin reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; end - addr_hit[346]: begin + addr_hit[326]: begin reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; end - addr_hit[347]: begin + addr_hit[327]: begin reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; end - addr_hit[348]: begin + addr_hit[328]: begin reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; end - addr_hit[349]: begin + addr_hit[329]: begin reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; end - addr_hit[350]: begin + addr_hit[330]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[351]: begin + addr_hit[331]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[352]: begin + addr_hit[332]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[353]: begin + addr_hit[333]: begin reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; @@ -20128,51 +19128,51 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; end - addr_hit[354]: begin + addr_hit[334]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[355]: begin + addr_hit[335]: begin reg_rdata_next[0] = classd_clr_shadowed_qs; end - addr_hit[356]: begin + addr_hit[336]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[357]: begin + addr_hit[337]: begin reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; end - addr_hit[358]: begin + addr_hit[338]: begin reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; end - addr_hit[359]: begin + addr_hit[339]: begin reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; end - addr_hit[360]: begin + addr_hit[340]: begin reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; end - addr_hit[361]: begin + addr_hit[341]: begin reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; end - addr_hit[362]: begin + addr_hit[342]: begin reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; end - addr_hit[363]: begin + addr_hit[343]: begin reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; end - addr_hit[364]: begin + addr_hit[344]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[365]: begin + addr_hit[345]: begin reg_rdata_next[2:0] = classd_state_qs; end @@ -20273,11 +19273,6 @@ module alert_handler_reg_top ( alert_en_shadowed_61_storage_err, alert_en_shadowed_62_storage_err, alert_en_shadowed_63_storage_err, - alert_en_shadowed_64_storage_err, - alert_en_shadowed_65_storage_err, - alert_en_shadowed_66_storage_err, - alert_en_shadowed_67_storage_err, - alert_en_shadowed_68_storage_err, alert_class_shadowed_0_storage_err, alert_class_shadowed_1_storage_err, alert_class_shadowed_2_storage_err, @@ -20342,11 +19337,6 @@ module alert_handler_reg_top ( alert_class_shadowed_61_storage_err, alert_class_shadowed_62_storage_err, alert_class_shadowed_63_storage_err, - alert_class_shadowed_64_storage_err, - alert_class_shadowed_65_storage_err, - alert_class_shadowed_66_storage_err, - alert_class_shadowed_67_storage_err, - alert_class_shadowed_68_storage_err, loc_alert_en_shadowed_0_storage_err, loc_alert_en_shadowed_1_storage_err, loc_alert_en_shadowed_2_storage_err, @@ -20501,11 +19491,6 @@ module alert_handler_reg_top ( alert_en_shadowed_61_update_err, alert_en_shadowed_62_update_err, alert_en_shadowed_63_update_err, - alert_en_shadowed_64_update_err, - alert_en_shadowed_65_update_err, - alert_en_shadowed_66_update_err, - alert_en_shadowed_67_update_err, - alert_en_shadowed_68_update_err, alert_class_shadowed_0_update_err, alert_class_shadowed_1_update_err, alert_class_shadowed_2_update_err, @@ -20570,11 +19555,6 @@ module alert_handler_reg_top ( alert_class_shadowed_61_update_err, alert_class_shadowed_62_update_err, alert_class_shadowed_63_update_err, - alert_class_shadowed_64_update_err, - alert_class_shadowed_65_update_err, - alert_class_shadowed_66_update_err, - alert_class_shadowed_67_update_err, - alert_class_shadowed_68_update_err, loc_alert_en_shadowed_0_update_err, loc_alert_en_shadowed_1_update_err, loc_alert_en_shadowed_2_update_err, diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson index fc0b577b97d3a..4e4041d3e2140 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson @@ -152,7 +152,7 @@ clk_main_infra: { src_name: main - endpoint_ip: flash_ctrl + endpoint_ip: rram_ctrl } clk_usb_infra: { diff --git a/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson b/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson index c2f7dd5fba9a7..33e870c6094bc 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson +++ b/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson @@ -349,13 +349,13 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "60", + default: "57", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "65", + default: "64", local: "true" }, { name: "NMioPads", diff --git a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson index 50b6a461ead5e..40d45cb3a64fb 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson @@ -8,8 +8,8 @@ n_wkup_detect: 8 wkup_cnt_width: 8 n_mio_pads: 47 - n_mio_periph_in: 60 - n_mio_periph_out: 65 + n_mio_periph_in: 57 + n_mio_periph_out: 64 n_dio_pads: 16 n_dio_periph_in: 14 n_dio_periph_out: 14 diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md index 66b9147d5ea7b..3c1efaec9c35a 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md @@ -6,78 +6,75 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ --> ## Pinout Table -|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| -|:-------------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:---------------------------------------------------------------------------------------------:|:---------------------------------------------------------------------------:| -|

POR_N

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

System reset

| -|

USB_P

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB P signal

| -|

USB_N

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB N signal

| -|

CC1

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 1

| -|

CC2

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 2

| -|

FLASH_TEST_VOLT

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

Flash test voltage input

| -|

FLASH_TEST_MODE0

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| -|

FLASH_TEST_MODE1

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| -|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| -|

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_CLK

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host clock

| -|

SPI_HOST_CS_L

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host chip select

| -|

SPI_DEV_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_CLK

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device clock

| -|

SPI_DEV_CS_L

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device chip select

| -|

IOA0

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa0 / kTopEarlgreyPinmuxMioOutIoa0

|

Muxed IO pad

| -|

IOA1

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa1 / kTopEarlgreyPinmuxMioOutIoa1

|

Muxed IO pad

| -|

IOA2

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa2 / kTopEarlgreyPinmuxMioOutIoa2

|

Muxed IO pad

| -|

IOA3

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa3 / kTopEarlgreyPinmuxMioOutIoa3

|

Muxed IO pad

| -|

IOA4

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa4 / kTopEarlgreyPinmuxMioOutIoa4

|

Muxed IO pad

| -|

IOA5

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa5 / kTopEarlgreyPinmuxMioOutIoa5

|

Muxed IO pad

| -|

IOA6

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa6 / kTopEarlgreyPinmuxMioOutIoa6

|

Muxed IO pad

| -|

IOA7

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa7 / kTopEarlgreyPinmuxMioOutIoa7

|

Muxed IO pad

| -|

IOA8

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa8 / kTopEarlgreyPinmuxMioOutIoa8

|

Muxed IO pad

| -|

IOB0

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob0 / kTopEarlgreyPinmuxMioOutIob0

|

Muxed IO pad

| -|

IOB1

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob1 / kTopEarlgreyPinmuxMioOutIob1

|

Muxed IO pad

| -|

IOB2

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob2 / kTopEarlgreyPinmuxMioOutIob2

|

Muxed IO pad

| -|

IOB3

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob3 / kTopEarlgreyPinmuxMioOutIob3

|

Muxed IO pad

| -|

IOB4

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob4 / kTopEarlgreyPinmuxMioOutIob4

|

Muxed IO pad

| -|

IOB5

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob5 / kTopEarlgreyPinmuxMioOutIob5

|

Muxed IO pad

| -|

IOB6

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob6 / kTopEarlgreyPinmuxMioOutIob6

|

Muxed IO pad

| -|

IOB7

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob7 / kTopEarlgreyPinmuxMioOutIob7

|

Muxed IO pad

| -|

IOB8

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob8 / kTopEarlgreyPinmuxMioOutIob8

|

Muxed IO pad

| -|

IOB9

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob9 / kTopEarlgreyPinmuxMioOutIob9

|

Muxed IO pad

| -|

IOB10

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob10 / kTopEarlgreyPinmuxMioOutIob10

|

Muxed IO pad

| -|

IOB11

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob11 / kTopEarlgreyPinmuxMioOutIob11

|

Muxed IO pad

| -|

IOB12

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob12 / kTopEarlgreyPinmuxMioOutIob12

|

Muxed IO pad

| -|

IOC0

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc0 / kTopEarlgreyPinmuxMioOutIoc0

|

Muxed IO pad

| -|

IOC1

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc1 / kTopEarlgreyPinmuxMioOutIoc1

|

Muxed IO pad

| -|

IOC2

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc2 / kTopEarlgreyPinmuxMioOutIoc2

|

Muxed IO pad

| -|

IOC3

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3

|

Muxed IO pad

| -|

IOC4

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4

|

Muxed IO pad

| -|

IOC5

|

BidirStd

|

VCC

|

muxed

|

tap1

|

kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5

|

Muxed IO pad / TAP strap signal.

| -|

IOC6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc6 / kTopEarlgreyPinmuxMioOutIoc6

|

Muxed IO pad

| -|

IOC7

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc7 / kTopEarlgreyPinmuxMioOutIoc7

|

Muxed IO pad

| -|

IOC8

|

BidirStd

|

VCC

|

muxed

|

tap0

|

kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8

|

Muxed IO pad / TAP strap signal.

| -|

IOC9

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc9 / kTopEarlgreyPinmuxMioOutIoc9

|

Muxed IO pad

| -|

IOC10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc10 / kTopEarlgreyPinmuxMioOutIoc10

|

Muxed IO pad

| -|

IOC11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc11 / kTopEarlgreyPinmuxMioOutIoc11

|

Muxed IO pad

| -|

IOC12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc12 / kTopEarlgreyPinmuxMioOutIoc12

|

Muxed IO pad

| -|

IOR0

|

BidirStd

|

VCC

|

muxed

|

tms

|

kTopEarlgreyPinmuxInselIor0 / kTopEarlgreyPinmuxMioOutIor0

|

Muxed IO pad / JTAG tms signal.

| -|

IOR1

|

BidirStd

|

VCC

|

muxed

|

tdo

|

kTopEarlgreyPinmuxInselIor1 / kTopEarlgreyPinmuxMioOutIor1

|

Muxed IO pad / JTAG tdo signal.

| -|

IOR2

|

BidirStd

|

VCC

|

muxed

|

tdi

|

kTopEarlgreyPinmuxInselIor2 / kTopEarlgreyPinmuxMioOutIor2

|

Muxed IO pad / JTAG tdi signal.

| -|

IOR3

|

BidirStd

|

VCC

|

muxed

|

tck

|

kTopEarlgreyPinmuxInselIor3 / kTopEarlgreyPinmuxMioOutIor3

|

Muxed IO pad / JTAG tck signal.

| -|

IOR4

|

BidirStd

|

VCC

|

muxed

|

trst_n

|

kTopEarlgreyPinmuxInselIor4 / kTopEarlgreyPinmuxMioOutIor4

|

Muxed IO pad / JTAG trst_n signal.

| -|

IOR5

|

BidirStd

|

VCC

|

muxed

|

dft0

|

kTopEarlgreyPinmuxInselIor5 / kTopEarlgreyPinmuxMioOutIor5

|

Muxed IO pad / DFT strap signal.

| -|

IOR6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor6 / kTopEarlgreyPinmuxMioOutIor6

|

Muxed IO pad

| -|

IOR7

|

BidirStd

|

VCC

|

muxed

|

dft1

|

kTopEarlgreyPinmuxInselIor7 / kTopEarlgreyPinmuxMioOutIor7

|

Muxed IO pad / DFT strap signal.

| -|

IOR8

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (ec_rst_l)

| -|

IOR9

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (flash_wp_l))

| -|

IOR10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor10 / kTopEarlgreyPinmuxMioOutIor10

|

Muxed IO pad

| -|

IOR11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor11 / kTopEarlgreyPinmuxMioOutIor11

|

Muxed IO pad

| -|

IOR12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor12 / kTopEarlgreyPinmuxMioOutIor12

|

Muxed IO pad

| -|

IOR13

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor13 / kTopEarlgreyPinmuxMioOutIor13

|

Muxed IO pad

| +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:----------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:---------------------------------------------------------------------------------------------:|:---------------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

System reset

| +|

USB_P

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB P signal

| +|

USB_N

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB N signal

| +|

CC1

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 1

| +|

CC2

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 2

| +|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| +|

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

IOA0

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa0 / kTopEarlgreyPinmuxMioOutIoa0

|

Muxed IO pad

| +|

IOA1

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa1 / kTopEarlgreyPinmuxMioOutIoa1

|

Muxed IO pad

| +|

IOA2

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa2 / kTopEarlgreyPinmuxMioOutIoa2

|

Muxed IO pad

| +|

IOA3

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa3 / kTopEarlgreyPinmuxMioOutIoa3

|

Muxed IO pad

| +|

IOA4

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa4 / kTopEarlgreyPinmuxMioOutIoa4

|

Muxed IO pad

| +|

IOA5

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa5 / kTopEarlgreyPinmuxMioOutIoa5

|

Muxed IO pad

| +|

IOA6

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa6 / kTopEarlgreyPinmuxMioOutIoa6

|

Muxed IO pad

| +|

IOA7

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa7 / kTopEarlgreyPinmuxMioOutIoa7

|

Muxed IO pad

| +|

IOA8

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa8 / kTopEarlgreyPinmuxMioOutIoa8

|

Muxed IO pad

| +|

IOB0

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob0 / kTopEarlgreyPinmuxMioOutIob0

|

Muxed IO pad

| +|

IOB1

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob1 / kTopEarlgreyPinmuxMioOutIob1

|

Muxed IO pad

| +|

IOB2

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob2 / kTopEarlgreyPinmuxMioOutIob2

|

Muxed IO pad

| +|

IOB3

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob3 / kTopEarlgreyPinmuxMioOutIob3

|

Muxed IO pad

| +|

IOB4

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob4 / kTopEarlgreyPinmuxMioOutIob4

|

Muxed IO pad

| +|

IOB5

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob5 / kTopEarlgreyPinmuxMioOutIob5

|

Muxed IO pad

| +|

IOB6

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob6 / kTopEarlgreyPinmuxMioOutIob6

|

Muxed IO pad

| +|

IOB7

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob7 / kTopEarlgreyPinmuxMioOutIob7

|

Muxed IO pad

| +|

IOB8

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob8 / kTopEarlgreyPinmuxMioOutIob8

|

Muxed IO pad

| +|

IOB9

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob9 / kTopEarlgreyPinmuxMioOutIob9

|

Muxed IO pad

| +|

IOB10

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob10 / kTopEarlgreyPinmuxMioOutIob10

|

Muxed IO pad

| +|

IOB11

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob11 / kTopEarlgreyPinmuxMioOutIob11

|

Muxed IO pad

| +|

IOB12

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob12 / kTopEarlgreyPinmuxMioOutIob12

|

Muxed IO pad

| +|

IOC0

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc0 / kTopEarlgreyPinmuxMioOutIoc0

|

Muxed IO pad

| +|

IOC1

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc1 / kTopEarlgreyPinmuxMioOutIoc1

|

Muxed IO pad

| +|

IOC2

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc2 / kTopEarlgreyPinmuxMioOutIoc2

|

Muxed IO pad

| +|

IOC3

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3

|

Muxed IO pad

| +|

IOC4

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4

|

Muxed IO pad

| +|

IOC5

|

BidirStd

|

VCC

|

muxed

|

tap1

|

kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5

|

Muxed IO pad / TAP strap signal.

| +|

IOC6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc6 / kTopEarlgreyPinmuxMioOutIoc6

|

Muxed IO pad

| +|

IOC7

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc7 / kTopEarlgreyPinmuxMioOutIoc7

|

Muxed IO pad

| +|

IOC8

|

BidirStd

|

VCC

|

muxed

|

tap0

|

kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8

|

Muxed IO pad / TAP strap signal.

| +|

IOC9

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc9 / kTopEarlgreyPinmuxMioOutIoc9

|

Muxed IO pad

| +|

IOC10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc10 / kTopEarlgreyPinmuxMioOutIoc10

|

Muxed IO pad

| +|

IOC11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc11 / kTopEarlgreyPinmuxMioOutIoc11

|

Muxed IO pad

| +|

IOC12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc12 / kTopEarlgreyPinmuxMioOutIoc12

|

Muxed IO pad

| +|

IOR0

|

BidirStd

|

VCC

|

muxed

|

tms

|

kTopEarlgreyPinmuxInselIor0 / kTopEarlgreyPinmuxMioOutIor0

|

Muxed IO pad / JTAG tms signal.

| +|

IOR1

|

BidirStd

|

VCC

|

muxed

|

tdo

|

kTopEarlgreyPinmuxInselIor1 / kTopEarlgreyPinmuxMioOutIor1

|

Muxed IO pad / JTAG tdo signal.

| +|

IOR2

|

BidirStd

|

VCC

|

muxed

|

tdi

|

kTopEarlgreyPinmuxInselIor2 / kTopEarlgreyPinmuxMioOutIor2

|

Muxed IO pad / JTAG tdi signal.

| +|

IOR3

|

BidirStd

|

VCC

|

muxed

|

tck

|

kTopEarlgreyPinmuxInselIor3 / kTopEarlgreyPinmuxMioOutIor3

|

Muxed IO pad / JTAG tck signal.

| +|

IOR4

|

BidirStd

|

VCC

|

muxed

|

trst_n

|

kTopEarlgreyPinmuxInselIor4 / kTopEarlgreyPinmuxMioOutIor4

|

Muxed IO pad / JTAG trst_n signal.

| +|

IOR5

|

BidirStd

|

VCC

|

muxed

|

dft0

|

kTopEarlgreyPinmuxInselIor5 / kTopEarlgreyPinmuxMioOutIor5

|

Muxed IO pad / DFT strap signal.

| +|

IOR6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor6 / kTopEarlgreyPinmuxMioOutIor6

|

Muxed IO pad

| +|

IOR7

|

BidirStd

|

VCC

|

muxed

|

dft1

|

kTopEarlgreyPinmuxInselIor7 / kTopEarlgreyPinmuxMioOutIor7

|

Muxed IO pad / DFT strap signal.

| +|

IOR8

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (ec_rst_l)

| +|

IOR9

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (flash_wp_l))

| +|

IOR10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor10 / kTopEarlgreyPinmuxMioOutIor10

|

Muxed IO pad

| +|

IOR11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor11 / kTopEarlgreyPinmuxMioOutIor11

|

Muxed IO pad

| +|

IOR12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor12 / kTopEarlgreyPinmuxMioOutIor12

|

Muxed IO pad

| +|

IOR13

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor13 / kTopEarlgreyPinmuxMioOutIor13

|

Muxed IO pad

| ## Pinmux Connectivity |

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| @@ -143,9 +140,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart2_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart2Rx

|

| |

uart3_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart3Rx

|

| |

spi_device_tpm_csb

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb

|

| -|

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| -|

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| -|

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| |

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| |

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| |

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| @@ -164,7 +158,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart3_tx

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselUart3Tx / -

|

| |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| -|

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| |

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md index 6de93458443b1..84681d4063ca1 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md @@ -147,9 +147,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart2_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart2Rx

|

| |

uart3_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart3Rx

|

| |

spi_device_tpm_csb

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb

|

| -|

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| -|

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| -|

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| |

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| |

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| |

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| @@ -168,7 +165,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart3_tx

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselUart3Tx / -

|

| |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| -|

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| |

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md index 9592edddf5b0c..75ea6cbe9aabb 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md @@ -6,78 +6,75 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ --> ## Pinout Table -|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| -|:-------------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:---------------------------------------------------------------------------------------------:|:---------------------------------------------------------------------------:| -|

POR_N

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

System reset

| -|

USB_P

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB P signal

| -|

USB_N

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB N signal

| -|

CC1

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 1

| -|

CC2

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 2

| -|

FLASH_TEST_VOLT

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

Flash test voltage input

| -|

FLASH_TEST_MODE0

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| -|

FLASH_TEST_MODE1

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| -|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| -|

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| -|

SPI_HOST_CLK

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host clock

| -|

SPI_HOST_CS_L

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host chip select

| -|

SPI_DEV_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| -|

SPI_DEV_CLK

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device clock

| -|

SPI_DEV_CS_L

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device chip select

| -|

IOA0

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa0 / kTopEarlgreyPinmuxMioOutIoa0

|

Muxed IO pad

| -|

IOA1

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa1 / kTopEarlgreyPinmuxMioOutIoa1

|

Muxed IO pad

| -|

IOA2

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa2 / kTopEarlgreyPinmuxMioOutIoa2

|

Muxed IO pad

| -|

IOA3

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa3 / kTopEarlgreyPinmuxMioOutIoa3

|

Muxed IO pad

| -|

IOA4

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa4 / kTopEarlgreyPinmuxMioOutIoa4

|

Muxed IO pad

| -|

IOA5

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa5 / kTopEarlgreyPinmuxMioOutIoa5

|

Muxed IO pad

| -|

IOA6

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa6 / kTopEarlgreyPinmuxMioOutIoa6

|

Muxed IO pad

| -|

IOA7

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa7 / kTopEarlgreyPinmuxMioOutIoa7

|

Muxed IO pad

| -|

IOA8

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa8 / kTopEarlgreyPinmuxMioOutIoa8

|

Muxed IO pad

| -|

IOB0

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob0 / kTopEarlgreyPinmuxMioOutIob0

|

Muxed IO pad

| -|

IOB1

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob1 / kTopEarlgreyPinmuxMioOutIob1

|

Muxed IO pad

| -|

IOB2

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob2 / kTopEarlgreyPinmuxMioOutIob2

|

Muxed IO pad

| -|

IOB3

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob3 / kTopEarlgreyPinmuxMioOutIob3

|

Muxed IO pad

| -|

IOB4

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob4 / kTopEarlgreyPinmuxMioOutIob4

|

Muxed IO pad

| -|

IOB5

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob5 / kTopEarlgreyPinmuxMioOutIob5

|

Muxed IO pad

| -|

IOB6

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob6 / kTopEarlgreyPinmuxMioOutIob6

|

Muxed IO pad

| -|

IOB7

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob7 / kTopEarlgreyPinmuxMioOutIob7

|

Muxed IO pad

| -|

IOB8

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob8 / kTopEarlgreyPinmuxMioOutIob8

|

Muxed IO pad

| -|

IOB9

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob9 / kTopEarlgreyPinmuxMioOutIob9

|

Muxed IO pad

| -|

IOB10

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob10 / kTopEarlgreyPinmuxMioOutIob10

|

Muxed IO pad

| -|

IOB11

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob11 / kTopEarlgreyPinmuxMioOutIob11

|

Muxed IO pad

| -|

IOB12

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob12 / kTopEarlgreyPinmuxMioOutIob12

|

Muxed IO pad

| -|

IOC0

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc0 / kTopEarlgreyPinmuxMioOutIoc0

|

Muxed IO pad

| -|

IOC1

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc1 / kTopEarlgreyPinmuxMioOutIoc1

|

Muxed IO pad

| -|

IOC2

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc2 / kTopEarlgreyPinmuxMioOutIoc2

|

Muxed IO pad

| -|

IOC3

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3

|

Muxed IO pad

| -|

IOC4

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4

|

Muxed IO pad

| -|

IOC5

|

BidirStd

|

VCC

|

muxed

|

tap1

|

kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5

|

Muxed IO pad / TAP strap signal.

| -|

IOC6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc6 / kTopEarlgreyPinmuxMioOutIoc6

|

Muxed IO pad

| -|

IOC7

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc7 / kTopEarlgreyPinmuxMioOutIoc7

|

Muxed IO pad

| -|

IOC8

|

BidirStd

|

VCC

|

muxed

|

tap0

|

kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8

|

Muxed IO pad / TAP strap signal.

| -|

IOC9

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc9 / kTopEarlgreyPinmuxMioOutIoc9

|

Muxed IO pad

| -|

IOC10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc10 / kTopEarlgreyPinmuxMioOutIoc10

|

Muxed IO pad

| -|

IOC11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc11 / kTopEarlgreyPinmuxMioOutIoc11

|

Muxed IO pad

| -|

IOC12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc12 / kTopEarlgreyPinmuxMioOutIoc12

|

Muxed IO pad

| -|

IOR0

|

BidirStd

|

VCC

|

muxed

|

tms

|

kTopEarlgreyPinmuxInselIor0 / kTopEarlgreyPinmuxMioOutIor0

|

Muxed IO pad / JTAG tms signal.

| -|

IOR1

|

BidirStd

|

VCC

|

muxed

|

tdo

|

kTopEarlgreyPinmuxInselIor1 / kTopEarlgreyPinmuxMioOutIor1

|

Muxed IO pad / JTAG tdo signal.

| -|

IOR2

|

BidirStd

|

VCC

|

muxed

|

tdi

|

kTopEarlgreyPinmuxInselIor2 / kTopEarlgreyPinmuxMioOutIor2

|

Muxed IO pad / JTAG tdi signal.

| -|

IOR3

|

BidirStd

|

VCC

|

muxed

|

tck

|

kTopEarlgreyPinmuxInselIor3 / kTopEarlgreyPinmuxMioOutIor3

|

Muxed IO pad / JTAG tck signal.

| -|

IOR4

|

BidirStd

|

VCC

|

muxed

|

trst_n

|

kTopEarlgreyPinmuxInselIor4 / kTopEarlgreyPinmuxMioOutIor4

|

Muxed IO pad / JTAG trst_n signal.

| -|

IOR5

|

BidirStd

|

VCC

|

muxed

|

dft0

|

kTopEarlgreyPinmuxInselIor5 / kTopEarlgreyPinmuxMioOutIor5

|

Muxed IO pad / DFT strap signal.

| -|

IOR6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor6 / kTopEarlgreyPinmuxMioOutIor6

|

Muxed IO pad

| -|

IOR7

|

BidirStd

|

VCC

|

muxed

|

dft1

|

kTopEarlgreyPinmuxInselIor7 / kTopEarlgreyPinmuxMioOutIor7

|

Muxed IO pad / DFT strap signal.

| -|

IOR8

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (ec_rst_l)

| -|

IOR9

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (flash_wp_l))

| -|

IOR10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor10 / kTopEarlgreyPinmuxMioOutIor10

|

Muxed IO pad

| -|

IOR11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor11 / kTopEarlgreyPinmuxMioOutIor11

|

Muxed IO pad

| -|

IOR12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor12 / kTopEarlgreyPinmuxMioOutIor12

|

Muxed IO pad

| -|

IOR13

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor13 / kTopEarlgreyPinmuxMioOutIor13

|

Muxed IO pad

| +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:----------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:---------------------------------------------------------------------------------------------:|:---------------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

System reset

| +|

USB_P

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB P signal

| +|

USB_N

|

DualBidirTol

|

VCC

|

manual

|

-

|

- / -

|

USB N signal

| +|

CC1

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 1

| +|

CC2

|

BidirTol

|

AVCC

|

manual

|

-

|

- / -

|

ADC input 2

| +|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| +|

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

IOA0

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa0 / kTopEarlgreyPinmuxMioOutIoa0

|

Muxed IO pad

| +|

IOA1

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa1 / kTopEarlgreyPinmuxMioOutIoa1

|

Muxed IO pad

| +|

IOA2

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa2 / kTopEarlgreyPinmuxMioOutIoa2

|

Muxed IO pad

| +|

IOA3

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa3 / kTopEarlgreyPinmuxMioOutIoa3

|

Muxed IO pad

| +|

IOA4

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa4 / kTopEarlgreyPinmuxMioOutIoa4

|

Muxed IO pad

| +|

IOA5

|

BidirStd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa5 / kTopEarlgreyPinmuxMioOutIoa5

|

Muxed IO pad

| +|

IOA6

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa6 / kTopEarlgreyPinmuxMioOutIoa6

|

Muxed IO pad

| +|

IOA7

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa7 / kTopEarlgreyPinmuxMioOutIoa7

|

Muxed IO pad

| +|

IOA8

|

BidirOd

|

VIOA

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoa8 / kTopEarlgreyPinmuxMioOutIoa8

|

Muxed IO pad

| +|

IOB0

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob0 / kTopEarlgreyPinmuxMioOutIob0

|

Muxed IO pad

| +|

IOB1

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob1 / kTopEarlgreyPinmuxMioOutIob1

|

Muxed IO pad

| +|

IOB2

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob2 / kTopEarlgreyPinmuxMioOutIob2

|

Muxed IO pad

| +|

IOB3

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob3 / kTopEarlgreyPinmuxMioOutIob3

|

Muxed IO pad

| +|

IOB4

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob4 / kTopEarlgreyPinmuxMioOutIob4

|

Muxed IO pad

| +|

IOB5

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob5 / kTopEarlgreyPinmuxMioOutIob5

|

Muxed IO pad

| +|

IOB6

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob6 / kTopEarlgreyPinmuxMioOutIob6

|

Muxed IO pad

| +|

IOB7

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob7 / kTopEarlgreyPinmuxMioOutIob7

|

Muxed IO pad

| +|

IOB8

|

BidirStd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob8 / kTopEarlgreyPinmuxMioOutIob8

|

Muxed IO pad

| +|

IOB9

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob9 / kTopEarlgreyPinmuxMioOutIob9

|

Muxed IO pad

| +|

IOB10

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob10 / kTopEarlgreyPinmuxMioOutIob10

|

Muxed IO pad

| +|

IOB11

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob11 / kTopEarlgreyPinmuxMioOutIob11

|

Muxed IO pad

| +|

IOB12

|

BidirOd

|

VIOB

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIob12 / kTopEarlgreyPinmuxMioOutIob12

|

Muxed IO pad

| +|

IOC0

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc0 / kTopEarlgreyPinmuxMioOutIoc0

|

Muxed IO pad

| +|

IOC1

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc1 / kTopEarlgreyPinmuxMioOutIoc1

|

Muxed IO pad

| +|

IOC2

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc2 / kTopEarlgreyPinmuxMioOutIoc2

|

Muxed IO pad

| +|

IOC3

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3

|

Muxed IO pad

| +|

IOC4

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4

|

Muxed IO pad

| +|

IOC5

|

BidirStd

|

VCC

|

muxed

|

tap1

|

kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5

|

Muxed IO pad / TAP strap signal.

| +|

IOC6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc6 / kTopEarlgreyPinmuxMioOutIoc6

|

Muxed IO pad

| +|

IOC7

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc7 / kTopEarlgreyPinmuxMioOutIoc7

|

Muxed IO pad

| +|

IOC8

|

BidirStd

|

VCC

|

muxed

|

tap0

|

kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8

|

Muxed IO pad / TAP strap signal.

| +|

IOC9

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc9 / kTopEarlgreyPinmuxMioOutIoc9

|

Muxed IO pad

| +|

IOC10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc10 / kTopEarlgreyPinmuxMioOutIoc10

|

Muxed IO pad

| +|

IOC11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc11 / kTopEarlgreyPinmuxMioOutIoc11

|

Muxed IO pad

| +|

IOC12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIoc12 / kTopEarlgreyPinmuxMioOutIoc12

|

Muxed IO pad

| +|

IOR0

|

BidirStd

|

VCC

|

muxed

|

tms

|

kTopEarlgreyPinmuxInselIor0 / kTopEarlgreyPinmuxMioOutIor0

|

Muxed IO pad / JTAG tms signal.

| +|

IOR1

|

BidirStd

|

VCC

|

muxed

|

tdo

|

kTopEarlgreyPinmuxInselIor1 / kTopEarlgreyPinmuxMioOutIor1

|

Muxed IO pad / JTAG tdo signal.

| +|

IOR2

|

BidirStd

|

VCC

|

muxed

|

tdi

|

kTopEarlgreyPinmuxInselIor2 / kTopEarlgreyPinmuxMioOutIor2

|

Muxed IO pad / JTAG tdi signal.

| +|

IOR3

|

BidirStd

|

VCC

|

muxed

|

tck

|

kTopEarlgreyPinmuxInselIor3 / kTopEarlgreyPinmuxMioOutIor3

|

Muxed IO pad / JTAG tck signal.

| +|

IOR4

|

BidirStd

|

VCC

|

muxed

|

trst_n

|

kTopEarlgreyPinmuxInselIor4 / kTopEarlgreyPinmuxMioOutIor4

|

Muxed IO pad / JTAG trst_n signal.

| +|

IOR5

|

BidirStd

|

VCC

|

muxed

|

dft0

|

kTopEarlgreyPinmuxInselIor5 / kTopEarlgreyPinmuxMioOutIor5

|

Muxed IO pad / DFT strap signal.

| +|

IOR6

|

BidirStd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor6 / kTopEarlgreyPinmuxMioOutIor6

|

Muxed IO pad

| +|

IOR7

|

BidirStd

|

VCC

|

muxed

|

dft1

|

kTopEarlgreyPinmuxInselIor7 / kTopEarlgreyPinmuxMioOutIor7

|

Muxed IO pad / DFT strap signal.

| +|

IOR8

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (ec_rst_l)

| +|

IOR9

|

BidirOd

|

VCC

|

direct

|

-

|

- / -

|

Dedicated sysrst_ctrl output (flash_wp_l))

| +|

IOR10

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor10 / kTopEarlgreyPinmuxMioOutIor10

|

Muxed IO pad

| +|

IOR11

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor11 / kTopEarlgreyPinmuxMioOutIor11

|

Muxed IO pad

| +|

IOR12

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor12 / kTopEarlgreyPinmuxMioOutIor12

|

Muxed IO pad

| +|

IOR13

|

BidirOd

|

VCC

|

muxed

|

-

|

kTopEarlgreyPinmuxInselIor13 / kTopEarlgreyPinmuxMioOutIor13

|

Muxed IO pad

| ## Pinmux Connectivity |

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| @@ -143,9 +140,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart2_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart2Rx

|

| |

uart3_rx

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInUart3Rx

|

| |

spi_device_tpm_csb

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb

|

| -|

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| -|

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| -|

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| |

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| |

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| |

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| @@ -164,7 +158,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart3_tx

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselUart3Tx / -

|

| |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| -|

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| |

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md index f2781465dabab..ec01c4628b2c1 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md @@ -63,522 +63,516 @@ | pinmux.[`MIO_PERIPH_INSEL_REGWEN_54`](#mio_periph_insel_regwen) | 0xdc | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_55`](#mio_periph_insel_regwen) | 0xe0 | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_56`](#mio_periph_insel_regwen) | 0xe4 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_57`](#mio_periph_insel_regwen) | 0xe8 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_58`](#mio_periph_insel_regwen) | 0xec | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_59`](#mio_periph_insel_regwen) | 0xf0 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1cc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1d0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1d4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_57`](#mio_periph_insel) | 0x1d8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_58`](#mio_periph_insel) | 0x1dc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_59`](#mio_periph_insel) | 0x1e0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x288 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x28c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x290 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x294 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x298 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x29c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x344 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x348 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x34c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x350 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x354 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x358 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x400 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x404 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x408 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x40c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x410 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x414 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4bc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4c0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4c4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4c8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4cc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4d0 | 4 | Muxed pad attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4fc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x500 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x504 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x508 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x50c | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x510 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x53c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x540 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x544 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x548 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x54c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x550 | 4 | Dedicated pad attributes. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x554 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x558 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x600 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x604 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x608 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x60c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x610 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x614 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6bc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6c0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6c4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6c8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6cc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6d0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x778 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x77c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x780 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x784 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x788 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x78c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x790 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7bc | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7c0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7c4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7c8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7cc | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7d0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x800 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x804 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x808 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x80c | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x810 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x83c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x840 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x844 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x848 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x84c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x850 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x85c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x860 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x864 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x868 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x86c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x870 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x87c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x880 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x884 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x888 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x88c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x890 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x89c | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x8a0 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x8a4 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x8a8 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x8ac | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x8b0 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8bc | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8c0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8c4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8c8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8cc | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8d0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8dc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8e0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8e4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8e8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8ec | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8f0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x8f4 | 4 | Cause registers for wakeup detectors. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xe8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xec | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1cc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1d0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1d4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1d8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1dc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1e0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x288 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x28c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x290 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x294 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x298 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x29c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x344 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x348 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x34c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x350 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x354 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x358 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x400 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x404 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x408 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x40c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x410 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x414 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4bc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4c0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4c4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4c8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4cc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4d0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x4fc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x500 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x504 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x508 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x50c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x510 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x53c | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x540 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x544 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x548 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x54c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x550 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x554 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x558 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x614 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x778 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x77c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x780 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x784 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x788 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x78c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x790 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7bc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7c0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7c4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7c8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x7fc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x800 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x804 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x808 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x80c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x810 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x83c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x840 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x844 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x848 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x84c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x850 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x85c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x860 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x864 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x868 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x86c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x870 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x87c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x880 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x884 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x888 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x88c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x890 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x89c | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8a0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8a4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8a8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8ac | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8b0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8bc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8c0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8c4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8c8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8cc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8d0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x8dc | 4 | Cause registers for wakeup detectors. | ## ALERT_TEST Alert Test Register @@ -663,9 +657,6 @@ Register write enable for MIO peripheral input selects. | MIO_PERIPH_INSEL_REGWEN_54 | 0xdc | | MIO_PERIPH_INSEL_REGWEN_55 | 0xe0 | | MIO_PERIPH_INSEL_REGWEN_56 | 0xe4 | -| MIO_PERIPH_INSEL_REGWEN_57 | 0xe8 | -| MIO_PERIPH_INSEL_REGWEN_58 | 0xec | -| MIO_PERIPH_INSEL_REGWEN_59 | 0xf0 | ### Fields @@ -689,66 +680,63 @@ For each peripheral input, this selects the muxable pad input. | Name | Offset | |:--------------------|:---------| -| MIO_PERIPH_INSEL_0 | 0xf4 | -| MIO_PERIPH_INSEL_1 | 0xf8 | -| MIO_PERIPH_INSEL_2 | 0xfc | -| MIO_PERIPH_INSEL_3 | 0x100 | -| MIO_PERIPH_INSEL_4 | 0x104 | -| MIO_PERIPH_INSEL_5 | 0x108 | -| MIO_PERIPH_INSEL_6 | 0x10c | -| MIO_PERIPH_INSEL_7 | 0x110 | -| MIO_PERIPH_INSEL_8 | 0x114 | -| MIO_PERIPH_INSEL_9 | 0x118 | -| MIO_PERIPH_INSEL_10 | 0x11c | -| MIO_PERIPH_INSEL_11 | 0x120 | -| MIO_PERIPH_INSEL_12 | 0x124 | -| MIO_PERIPH_INSEL_13 | 0x128 | -| MIO_PERIPH_INSEL_14 | 0x12c | -| MIO_PERIPH_INSEL_15 | 0x130 | -| MIO_PERIPH_INSEL_16 | 0x134 | -| MIO_PERIPH_INSEL_17 | 0x138 | -| MIO_PERIPH_INSEL_18 | 0x13c | -| MIO_PERIPH_INSEL_19 | 0x140 | -| MIO_PERIPH_INSEL_20 | 0x144 | -| MIO_PERIPH_INSEL_21 | 0x148 | -| MIO_PERIPH_INSEL_22 | 0x14c | -| MIO_PERIPH_INSEL_23 | 0x150 | -| MIO_PERIPH_INSEL_24 | 0x154 | -| MIO_PERIPH_INSEL_25 | 0x158 | -| MIO_PERIPH_INSEL_26 | 0x15c | -| MIO_PERIPH_INSEL_27 | 0x160 | -| MIO_PERIPH_INSEL_28 | 0x164 | -| MIO_PERIPH_INSEL_29 | 0x168 | -| MIO_PERIPH_INSEL_30 | 0x16c | -| MIO_PERIPH_INSEL_31 | 0x170 | -| MIO_PERIPH_INSEL_32 | 0x174 | -| MIO_PERIPH_INSEL_33 | 0x178 | -| MIO_PERIPH_INSEL_34 | 0x17c | -| MIO_PERIPH_INSEL_35 | 0x180 | -| MIO_PERIPH_INSEL_36 | 0x184 | -| MIO_PERIPH_INSEL_37 | 0x188 | -| MIO_PERIPH_INSEL_38 | 0x18c | -| MIO_PERIPH_INSEL_39 | 0x190 | -| MIO_PERIPH_INSEL_40 | 0x194 | -| MIO_PERIPH_INSEL_41 | 0x198 | -| MIO_PERIPH_INSEL_42 | 0x19c | -| MIO_PERIPH_INSEL_43 | 0x1a0 | -| MIO_PERIPH_INSEL_44 | 0x1a4 | -| MIO_PERIPH_INSEL_45 | 0x1a8 | -| MIO_PERIPH_INSEL_46 | 0x1ac | -| MIO_PERIPH_INSEL_47 | 0x1b0 | -| MIO_PERIPH_INSEL_48 | 0x1b4 | -| MIO_PERIPH_INSEL_49 | 0x1b8 | -| MIO_PERIPH_INSEL_50 | 0x1bc | -| MIO_PERIPH_INSEL_51 | 0x1c0 | -| MIO_PERIPH_INSEL_52 | 0x1c4 | -| MIO_PERIPH_INSEL_53 | 0x1c8 | -| MIO_PERIPH_INSEL_54 | 0x1cc | -| MIO_PERIPH_INSEL_55 | 0x1d0 | -| MIO_PERIPH_INSEL_56 | 0x1d4 | -| MIO_PERIPH_INSEL_57 | 0x1d8 | -| MIO_PERIPH_INSEL_58 | 0x1dc | -| MIO_PERIPH_INSEL_59 | 0x1e0 | +| MIO_PERIPH_INSEL_0 | 0xe8 | +| MIO_PERIPH_INSEL_1 | 0xec | +| MIO_PERIPH_INSEL_2 | 0xf0 | +| MIO_PERIPH_INSEL_3 | 0xf4 | +| MIO_PERIPH_INSEL_4 | 0xf8 | +| MIO_PERIPH_INSEL_5 | 0xfc | +| MIO_PERIPH_INSEL_6 | 0x100 | +| MIO_PERIPH_INSEL_7 | 0x104 | +| MIO_PERIPH_INSEL_8 | 0x108 | +| MIO_PERIPH_INSEL_9 | 0x10c | +| MIO_PERIPH_INSEL_10 | 0x110 | +| MIO_PERIPH_INSEL_11 | 0x114 | +| MIO_PERIPH_INSEL_12 | 0x118 | +| MIO_PERIPH_INSEL_13 | 0x11c | +| MIO_PERIPH_INSEL_14 | 0x120 | +| MIO_PERIPH_INSEL_15 | 0x124 | +| MIO_PERIPH_INSEL_16 | 0x128 | +| MIO_PERIPH_INSEL_17 | 0x12c | +| MIO_PERIPH_INSEL_18 | 0x130 | +| MIO_PERIPH_INSEL_19 | 0x134 | +| MIO_PERIPH_INSEL_20 | 0x138 | +| MIO_PERIPH_INSEL_21 | 0x13c | +| MIO_PERIPH_INSEL_22 | 0x140 | +| MIO_PERIPH_INSEL_23 | 0x144 | +| MIO_PERIPH_INSEL_24 | 0x148 | +| MIO_PERIPH_INSEL_25 | 0x14c | +| MIO_PERIPH_INSEL_26 | 0x150 | +| MIO_PERIPH_INSEL_27 | 0x154 | +| MIO_PERIPH_INSEL_28 | 0x158 | +| MIO_PERIPH_INSEL_29 | 0x15c | +| MIO_PERIPH_INSEL_30 | 0x160 | +| MIO_PERIPH_INSEL_31 | 0x164 | +| MIO_PERIPH_INSEL_32 | 0x168 | +| MIO_PERIPH_INSEL_33 | 0x16c | +| MIO_PERIPH_INSEL_34 | 0x170 | +| MIO_PERIPH_INSEL_35 | 0x174 | +| MIO_PERIPH_INSEL_36 | 0x178 | +| MIO_PERIPH_INSEL_37 | 0x17c | +| MIO_PERIPH_INSEL_38 | 0x180 | +| MIO_PERIPH_INSEL_39 | 0x184 | +| MIO_PERIPH_INSEL_40 | 0x188 | +| MIO_PERIPH_INSEL_41 | 0x18c | +| MIO_PERIPH_INSEL_42 | 0x190 | +| MIO_PERIPH_INSEL_43 | 0x194 | +| MIO_PERIPH_INSEL_44 | 0x198 | +| MIO_PERIPH_INSEL_45 | 0x19c | +| MIO_PERIPH_INSEL_46 | 0x1a0 | +| MIO_PERIPH_INSEL_47 | 0x1a4 | +| MIO_PERIPH_INSEL_48 | 0x1a8 | +| MIO_PERIPH_INSEL_49 | 0x1ac | +| MIO_PERIPH_INSEL_50 | 0x1b0 | +| MIO_PERIPH_INSEL_51 | 0x1b4 | +| MIO_PERIPH_INSEL_52 | 0x1b8 | +| MIO_PERIPH_INSEL_53 | 0x1bc | +| MIO_PERIPH_INSEL_54 | 0x1c0 | +| MIO_PERIPH_INSEL_55 | 0x1c4 | +| MIO_PERIPH_INSEL_56 | 0x1c8 | ### Fields @@ -771,53 +759,53 @@ Register write enable for MIO output selects. | Name | Offset | |:---------------------|:---------| -| MIO_OUTSEL_REGWEN_0 | 0x1e4 | -| MIO_OUTSEL_REGWEN_1 | 0x1e8 | -| MIO_OUTSEL_REGWEN_2 | 0x1ec | -| MIO_OUTSEL_REGWEN_3 | 0x1f0 | -| MIO_OUTSEL_REGWEN_4 | 0x1f4 | -| MIO_OUTSEL_REGWEN_5 | 0x1f8 | -| MIO_OUTSEL_REGWEN_6 | 0x1fc | -| MIO_OUTSEL_REGWEN_7 | 0x200 | -| MIO_OUTSEL_REGWEN_8 | 0x204 | -| MIO_OUTSEL_REGWEN_9 | 0x208 | -| MIO_OUTSEL_REGWEN_10 | 0x20c | -| MIO_OUTSEL_REGWEN_11 | 0x210 | -| MIO_OUTSEL_REGWEN_12 | 0x214 | -| MIO_OUTSEL_REGWEN_13 | 0x218 | -| MIO_OUTSEL_REGWEN_14 | 0x21c | -| MIO_OUTSEL_REGWEN_15 | 0x220 | -| MIO_OUTSEL_REGWEN_16 | 0x224 | -| MIO_OUTSEL_REGWEN_17 | 0x228 | -| MIO_OUTSEL_REGWEN_18 | 0x22c | -| MIO_OUTSEL_REGWEN_19 | 0x230 | -| MIO_OUTSEL_REGWEN_20 | 0x234 | -| MIO_OUTSEL_REGWEN_21 | 0x238 | -| MIO_OUTSEL_REGWEN_22 | 0x23c | -| MIO_OUTSEL_REGWEN_23 | 0x240 | -| MIO_OUTSEL_REGWEN_24 | 0x244 | -| MIO_OUTSEL_REGWEN_25 | 0x248 | -| MIO_OUTSEL_REGWEN_26 | 0x24c | -| MIO_OUTSEL_REGWEN_27 | 0x250 | -| MIO_OUTSEL_REGWEN_28 | 0x254 | -| MIO_OUTSEL_REGWEN_29 | 0x258 | -| MIO_OUTSEL_REGWEN_30 | 0x25c | -| MIO_OUTSEL_REGWEN_31 | 0x260 | -| MIO_OUTSEL_REGWEN_32 | 0x264 | -| MIO_OUTSEL_REGWEN_33 | 0x268 | -| MIO_OUTSEL_REGWEN_34 | 0x26c | -| MIO_OUTSEL_REGWEN_35 | 0x270 | -| MIO_OUTSEL_REGWEN_36 | 0x274 | -| MIO_OUTSEL_REGWEN_37 | 0x278 | -| MIO_OUTSEL_REGWEN_38 | 0x27c | -| MIO_OUTSEL_REGWEN_39 | 0x280 | -| MIO_OUTSEL_REGWEN_40 | 0x284 | -| MIO_OUTSEL_REGWEN_41 | 0x288 | -| MIO_OUTSEL_REGWEN_42 | 0x28c | -| MIO_OUTSEL_REGWEN_43 | 0x290 | -| MIO_OUTSEL_REGWEN_44 | 0x294 | -| MIO_OUTSEL_REGWEN_45 | 0x298 | -| MIO_OUTSEL_REGWEN_46 | 0x29c | +| MIO_OUTSEL_REGWEN_0 | 0x1cc | +| MIO_OUTSEL_REGWEN_1 | 0x1d0 | +| MIO_OUTSEL_REGWEN_2 | 0x1d4 | +| MIO_OUTSEL_REGWEN_3 | 0x1d8 | +| MIO_OUTSEL_REGWEN_4 | 0x1dc | +| MIO_OUTSEL_REGWEN_5 | 0x1e0 | +| MIO_OUTSEL_REGWEN_6 | 0x1e4 | +| MIO_OUTSEL_REGWEN_7 | 0x1e8 | +| MIO_OUTSEL_REGWEN_8 | 0x1ec | +| MIO_OUTSEL_REGWEN_9 | 0x1f0 | +| MIO_OUTSEL_REGWEN_10 | 0x1f4 | +| MIO_OUTSEL_REGWEN_11 | 0x1f8 | +| MIO_OUTSEL_REGWEN_12 | 0x1fc | +| MIO_OUTSEL_REGWEN_13 | 0x200 | +| MIO_OUTSEL_REGWEN_14 | 0x204 | +| MIO_OUTSEL_REGWEN_15 | 0x208 | +| MIO_OUTSEL_REGWEN_16 | 0x20c | +| MIO_OUTSEL_REGWEN_17 | 0x210 | +| MIO_OUTSEL_REGWEN_18 | 0x214 | +| MIO_OUTSEL_REGWEN_19 | 0x218 | +| MIO_OUTSEL_REGWEN_20 | 0x21c | +| MIO_OUTSEL_REGWEN_21 | 0x220 | +| MIO_OUTSEL_REGWEN_22 | 0x224 | +| MIO_OUTSEL_REGWEN_23 | 0x228 | +| MIO_OUTSEL_REGWEN_24 | 0x22c | +| MIO_OUTSEL_REGWEN_25 | 0x230 | +| MIO_OUTSEL_REGWEN_26 | 0x234 | +| MIO_OUTSEL_REGWEN_27 | 0x238 | +| MIO_OUTSEL_REGWEN_28 | 0x23c | +| MIO_OUTSEL_REGWEN_29 | 0x240 | +| MIO_OUTSEL_REGWEN_30 | 0x244 | +| MIO_OUTSEL_REGWEN_31 | 0x248 | +| MIO_OUTSEL_REGWEN_32 | 0x24c | +| MIO_OUTSEL_REGWEN_33 | 0x250 | +| MIO_OUTSEL_REGWEN_34 | 0x254 | +| MIO_OUTSEL_REGWEN_35 | 0x258 | +| MIO_OUTSEL_REGWEN_36 | 0x25c | +| MIO_OUTSEL_REGWEN_37 | 0x260 | +| MIO_OUTSEL_REGWEN_38 | 0x264 | +| MIO_OUTSEL_REGWEN_39 | 0x268 | +| MIO_OUTSEL_REGWEN_40 | 0x26c | +| MIO_OUTSEL_REGWEN_41 | 0x270 | +| MIO_OUTSEL_REGWEN_42 | 0x274 | +| MIO_OUTSEL_REGWEN_43 | 0x278 | +| MIO_OUTSEL_REGWEN_44 | 0x27c | +| MIO_OUTSEL_REGWEN_45 | 0x280 | +| MIO_OUTSEL_REGWEN_46 | 0x284 | ### Fields @@ -841,53 +829,53 @@ For each muxable pad, this selects the peripheral output. | Name | Offset | |:--------------|:---------| -| MIO_OUTSEL_0 | 0x2a0 | -| MIO_OUTSEL_1 | 0x2a4 | -| MIO_OUTSEL_2 | 0x2a8 | -| MIO_OUTSEL_3 | 0x2ac | -| MIO_OUTSEL_4 | 0x2b0 | -| MIO_OUTSEL_5 | 0x2b4 | -| MIO_OUTSEL_6 | 0x2b8 | -| MIO_OUTSEL_7 | 0x2bc | -| MIO_OUTSEL_8 | 0x2c0 | -| MIO_OUTSEL_9 | 0x2c4 | -| MIO_OUTSEL_10 | 0x2c8 | -| MIO_OUTSEL_11 | 0x2cc | -| MIO_OUTSEL_12 | 0x2d0 | -| MIO_OUTSEL_13 | 0x2d4 | -| MIO_OUTSEL_14 | 0x2d8 | -| MIO_OUTSEL_15 | 0x2dc | -| MIO_OUTSEL_16 | 0x2e0 | -| MIO_OUTSEL_17 | 0x2e4 | -| MIO_OUTSEL_18 | 0x2e8 | -| MIO_OUTSEL_19 | 0x2ec | -| MIO_OUTSEL_20 | 0x2f0 | -| MIO_OUTSEL_21 | 0x2f4 | -| MIO_OUTSEL_22 | 0x2f8 | -| MIO_OUTSEL_23 | 0x2fc | -| MIO_OUTSEL_24 | 0x300 | -| MIO_OUTSEL_25 | 0x304 | -| MIO_OUTSEL_26 | 0x308 | -| MIO_OUTSEL_27 | 0x30c | -| MIO_OUTSEL_28 | 0x310 | -| MIO_OUTSEL_29 | 0x314 | -| MIO_OUTSEL_30 | 0x318 | -| MIO_OUTSEL_31 | 0x31c | -| MIO_OUTSEL_32 | 0x320 | -| MIO_OUTSEL_33 | 0x324 | -| MIO_OUTSEL_34 | 0x328 | -| MIO_OUTSEL_35 | 0x32c | -| MIO_OUTSEL_36 | 0x330 | -| MIO_OUTSEL_37 | 0x334 | -| MIO_OUTSEL_38 | 0x338 | -| MIO_OUTSEL_39 | 0x33c | -| MIO_OUTSEL_40 | 0x340 | -| MIO_OUTSEL_41 | 0x344 | -| MIO_OUTSEL_42 | 0x348 | -| MIO_OUTSEL_43 | 0x34c | -| MIO_OUTSEL_44 | 0x350 | -| MIO_OUTSEL_45 | 0x354 | -| MIO_OUTSEL_46 | 0x358 | +| MIO_OUTSEL_0 | 0x288 | +| MIO_OUTSEL_1 | 0x28c | +| MIO_OUTSEL_2 | 0x290 | +| MIO_OUTSEL_3 | 0x294 | +| MIO_OUTSEL_4 | 0x298 | +| MIO_OUTSEL_5 | 0x29c | +| MIO_OUTSEL_6 | 0x2a0 | +| MIO_OUTSEL_7 | 0x2a4 | +| MIO_OUTSEL_8 | 0x2a8 | +| MIO_OUTSEL_9 | 0x2ac | +| MIO_OUTSEL_10 | 0x2b0 | +| MIO_OUTSEL_11 | 0x2b4 | +| MIO_OUTSEL_12 | 0x2b8 | +| MIO_OUTSEL_13 | 0x2bc | +| MIO_OUTSEL_14 | 0x2c0 | +| MIO_OUTSEL_15 | 0x2c4 | +| MIO_OUTSEL_16 | 0x2c8 | +| MIO_OUTSEL_17 | 0x2cc | +| MIO_OUTSEL_18 | 0x2d0 | +| MIO_OUTSEL_19 | 0x2d4 | +| MIO_OUTSEL_20 | 0x2d8 | +| MIO_OUTSEL_21 | 0x2dc | +| MIO_OUTSEL_22 | 0x2e0 | +| MIO_OUTSEL_23 | 0x2e4 | +| MIO_OUTSEL_24 | 0x2e8 | +| MIO_OUTSEL_25 | 0x2ec | +| MIO_OUTSEL_26 | 0x2f0 | +| MIO_OUTSEL_27 | 0x2f4 | +| MIO_OUTSEL_28 | 0x2f8 | +| MIO_OUTSEL_29 | 0x2fc | +| MIO_OUTSEL_30 | 0x300 | +| MIO_OUTSEL_31 | 0x304 | +| MIO_OUTSEL_32 | 0x308 | +| MIO_OUTSEL_33 | 0x30c | +| MIO_OUTSEL_34 | 0x310 | +| MIO_OUTSEL_35 | 0x314 | +| MIO_OUTSEL_36 | 0x318 | +| MIO_OUTSEL_37 | 0x31c | +| MIO_OUTSEL_38 | 0x320 | +| MIO_OUTSEL_39 | 0x324 | +| MIO_OUTSEL_40 | 0x328 | +| MIO_OUTSEL_41 | 0x32c | +| MIO_OUTSEL_42 | 0x330 | +| MIO_OUTSEL_43 | 0x334 | +| MIO_OUTSEL_44 | 0x338 | +| MIO_OUTSEL_45 | 0x33c | +| MIO_OUTSEL_46 | 0x340 | ### Fields @@ -910,53 +898,53 @@ Register write enable for MIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| MIO_PAD_ATTR_REGWEN_0 | 0x35c | -| MIO_PAD_ATTR_REGWEN_1 | 0x360 | -| MIO_PAD_ATTR_REGWEN_2 | 0x364 | -| MIO_PAD_ATTR_REGWEN_3 | 0x368 | -| MIO_PAD_ATTR_REGWEN_4 | 0x36c | -| MIO_PAD_ATTR_REGWEN_5 | 0x370 | -| MIO_PAD_ATTR_REGWEN_6 | 0x374 | -| MIO_PAD_ATTR_REGWEN_7 | 0x378 | -| MIO_PAD_ATTR_REGWEN_8 | 0x37c | -| MIO_PAD_ATTR_REGWEN_9 | 0x380 | -| MIO_PAD_ATTR_REGWEN_10 | 0x384 | -| MIO_PAD_ATTR_REGWEN_11 | 0x388 | -| MIO_PAD_ATTR_REGWEN_12 | 0x38c | -| MIO_PAD_ATTR_REGWEN_13 | 0x390 | -| MIO_PAD_ATTR_REGWEN_14 | 0x394 | -| MIO_PAD_ATTR_REGWEN_15 | 0x398 | -| MIO_PAD_ATTR_REGWEN_16 | 0x39c | -| MIO_PAD_ATTR_REGWEN_17 | 0x3a0 | -| MIO_PAD_ATTR_REGWEN_18 | 0x3a4 | -| MIO_PAD_ATTR_REGWEN_19 | 0x3a8 | -| MIO_PAD_ATTR_REGWEN_20 | 0x3ac | -| MIO_PAD_ATTR_REGWEN_21 | 0x3b0 | -| MIO_PAD_ATTR_REGWEN_22 | 0x3b4 | -| MIO_PAD_ATTR_REGWEN_23 | 0x3b8 | -| MIO_PAD_ATTR_REGWEN_24 | 0x3bc | -| MIO_PAD_ATTR_REGWEN_25 | 0x3c0 | -| MIO_PAD_ATTR_REGWEN_26 | 0x3c4 | -| MIO_PAD_ATTR_REGWEN_27 | 0x3c8 | -| MIO_PAD_ATTR_REGWEN_28 | 0x3cc | -| MIO_PAD_ATTR_REGWEN_29 | 0x3d0 | -| MIO_PAD_ATTR_REGWEN_30 | 0x3d4 | -| MIO_PAD_ATTR_REGWEN_31 | 0x3d8 | -| MIO_PAD_ATTR_REGWEN_32 | 0x3dc | -| MIO_PAD_ATTR_REGWEN_33 | 0x3e0 | -| MIO_PAD_ATTR_REGWEN_34 | 0x3e4 | -| MIO_PAD_ATTR_REGWEN_35 | 0x3e8 | -| MIO_PAD_ATTR_REGWEN_36 | 0x3ec | -| MIO_PAD_ATTR_REGWEN_37 | 0x3f0 | -| MIO_PAD_ATTR_REGWEN_38 | 0x3f4 | -| MIO_PAD_ATTR_REGWEN_39 | 0x3f8 | -| MIO_PAD_ATTR_REGWEN_40 | 0x3fc | -| MIO_PAD_ATTR_REGWEN_41 | 0x400 | -| MIO_PAD_ATTR_REGWEN_42 | 0x404 | -| MIO_PAD_ATTR_REGWEN_43 | 0x408 | -| MIO_PAD_ATTR_REGWEN_44 | 0x40c | -| MIO_PAD_ATTR_REGWEN_45 | 0x410 | -| MIO_PAD_ATTR_REGWEN_46 | 0x414 | +| MIO_PAD_ATTR_REGWEN_0 | 0x344 | +| MIO_PAD_ATTR_REGWEN_1 | 0x348 | +| MIO_PAD_ATTR_REGWEN_2 | 0x34c | +| MIO_PAD_ATTR_REGWEN_3 | 0x350 | +| MIO_PAD_ATTR_REGWEN_4 | 0x354 | +| MIO_PAD_ATTR_REGWEN_5 | 0x358 | +| MIO_PAD_ATTR_REGWEN_6 | 0x35c | +| MIO_PAD_ATTR_REGWEN_7 | 0x360 | +| MIO_PAD_ATTR_REGWEN_8 | 0x364 | +| MIO_PAD_ATTR_REGWEN_9 | 0x368 | +| MIO_PAD_ATTR_REGWEN_10 | 0x36c | +| MIO_PAD_ATTR_REGWEN_11 | 0x370 | +| MIO_PAD_ATTR_REGWEN_12 | 0x374 | +| MIO_PAD_ATTR_REGWEN_13 | 0x378 | +| MIO_PAD_ATTR_REGWEN_14 | 0x37c | +| MIO_PAD_ATTR_REGWEN_15 | 0x380 | +| MIO_PAD_ATTR_REGWEN_16 | 0x384 | +| MIO_PAD_ATTR_REGWEN_17 | 0x388 | +| MIO_PAD_ATTR_REGWEN_18 | 0x38c | +| MIO_PAD_ATTR_REGWEN_19 | 0x390 | +| MIO_PAD_ATTR_REGWEN_20 | 0x394 | +| MIO_PAD_ATTR_REGWEN_21 | 0x398 | +| MIO_PAD_ATTR_REGWEN_22 | 0x39c | +| MIO_PAD_ATTR_REGWEN_23 | 0x3a0 | +| MIO_PAD_ATTR_REGWEN_24 | 0x3a4 | +| MIO_PAD_ATTR_REGWEN_25 | 0x3a8 | +| MIO_PAD_ATTR_REGWEN_26 | 0x3ac | +| MIO_PAD_ATTR_REGWEN_27 | 0x3b0 | +| MIO_PAD_ATTR_REGWEN_28 | 0x3b4 | +| MIO_PAD_ATTR_REGWEN_29 | 0x3b8 | +| MIO_PAD_ATTR_REGWEN_30 | 0x3bc | +| MIO_PAD_ATTR_REGWEN_31 | 0x3c0 | +| MIO_PAD_ATTR_REGWEN_32 | 0x3c4 | +| MIO_PAD_ATTR_REGWEN_33 | 0x3c8 | +| MIO_PAD_ATTR_REGWEN_34 | 0x3cc | +| MIO_PAD_ATTR_REGWEN_35 | 0x3d0 | +| MIO_PAD_ATTR_REGWEN_36 | 0x3d4 | +| MIO_PAD_ATTR_REGWEN_37 | 0x3d8 | +| MIO_PAD_ATTR_REGWEN_38 | 0x3dc | +| MIO_PAD_ATTR_REGWEN_39 | 0x3e0 | +| MIO_PAD_ATTR_REGWEN_40 | 0x3e4 | +| MIO_PAD_ATTR_REGWEN_41 | 0x3e8 | +| MIO_PAD_ATTR_REGWEN_42 | 0x3ec | +| MIO_PAD_ATTR_REGWEN_43 | 0x3f0 | +| MIO_PAD_ATTR_REGWEN_44 | 0x3f4 | +| MIO_PAD_ATTR_REGWEN_45 | 0x3f8 | +| MIO_PAD_ATTR_REGWEN_46 | 0x3fc | ### Fields @@ -983,53 +971,53 @@ The muxed pad that is used for TAP strap 0 has a different reset value, with `pu | Name | Offset | |:----------------|:---------| -| MIO_PAD_ATTR_0 | 0x418 | -| MIO_PAD_ATTR_1 | 0x41c | -| MIO_PAD_ATTR_2 | 0x420 | -| MIO_PAD_ATTR_3 | 0x424 | -| MIO_PAD_ATTR_4 | 0x428 | -| MIO_PAD_ATTR_5 | 0x42c | -| MIO_PAD_ATTR_6 | 0x430 | -| MIO_PAD_ATTR_7 | 0x434 | -| MIO_PAD_ATTR_8 | 0x438 | -| MIO_PAD_ATTR_9 | 0x43c | -| MIO_PAD_ATTR_10 | 0x440 | -| MIO_PAD_ATTR_11 | 0x444 | -| MIO_PAD_ATTR_12 | 0x448 | -| MIO_PAD_ATTR_13 | 0x44c | -| MIO_PAD_ATTR_14 | 0x450 | -| MIO_PAD_ATTR_15 | 0x454 | -| MIO_PAD_ATTR_16 | 0x458 | -| MIO_PAD_ATTR_17 | 0x45c | -| MIO_PAD_ATTR_18 | 0x460 | -| MIO_PAD_ATTR_19 | 0x464 | -| MIO_PAD_ATTR_20 | 0x468 | -| MIO_PAD_ATTR_21 | 0x46c | -| MIO_PAD_ATTR_22 | 0x470 | -| MIO_PAD_ATTR_23 | 0x474 | -| MIO_PAD_ATTR_24 | 0x478 | -| MIO_PAD_ATTR_25 | 0x47c | -| MIO_PAD_ATTR_26 | 0x480 | -| MIO_PAD_ATTR_27 | 0x484 | -| MIO_PAD_ATTR_28 | 0x488 | -| MIO_PAD_ATTR_29 | 0x48c | -| MIO_PAD_ATTR_30 | 0x490 | -| MIO_PAD_ATTR_31 | 0x494 | -| MIO_PAD_ATTR_32 | 0x498 | -| MIO_PAD_ATTR_33 | 0x49c | -| MIO_PAD_ATTR_34 | 0x4a0 | -| MIO_PAD_ATTR_35 | 0x4a4 | -| MIO_PAD_ATTR_36 | 0x4a8 | -| MIO_PAD_ATTR_37 | 0x4ac | -| MIO_PAD_ATTR_38 | 0x4b0 | -| MIO_PAD_ATTR_39 | 0x4b4 | -| MIO_PAD_ATTR_40 | 0x4b8 | -| MIO_PAD_ATTR_41 | 0x4bc | -| MIO_PAD_ATTR_42 | 0x4c0 | -| MIO_PAD_ATTR_43 | 0x4c4 | -| MIO_PAD_ATTR_44 | 0x4c8 | -| MIO_PAD_ATTR_45 | 0x4cc | -| MIO_PAD_ATTR_46 | 0x4d0 | +| MIO_PAD_ATTR_0 | 0x400 | +| MIO_PAD_ATTR_1 | 0x404 | +| MIO_PAD_ATTR_2 | 0x408 | +| MIO_PAD_ATTR_3 | 0x40c | +| MIO_PAD_ATTR_4 | 0x410 | +| MIO_PAD_ATTR_5 | 0x414 | +| MIO_PAD_ATTR_6 | 0x418 | +| MIO_PAD_ATTR_7 | 0x41c | +| MIO_PAD_ATTR_8 | 0x420 | +| MIO_PAD_ATTR_9 | 0x424 | +| MIO_PAD_ATTR_10 | 0x428 | +| MIO_PAD_ATTR_11 | 0x42c | +| MIO_PAD_ATTR_12 | 0x430 | +| MIO_PAD_ATTR_13 | 0x434 | +| MIO_PAD_ATTR_14 | 0x438 | +| MIO_PAD_ATTR_15 | 0x43c | +| MIO_PAD_ATTR_16 | 0x440 | +| MIO_PAD_ATTR_17 | 0x444 | +| MIO_PAD_ATTR_18 | 0x448 | +| MIO_PAD_ATTR_19 | 0x44c | +| MIO_PAD_ATTR_20 | 0x450 | +| MIO_PAD_ATTR_21 | 0x454 | +| MIO_PAD_ATTR_22 | 0x458 | +| MIO_PAD_ATTR_23 | 0x45c | +| MIO_PAD_ATTR_24 | 0x460 | +| MIO_PAD_ATTR_25 | 0x464 | +| MIO_PAD_ATTR_26 | 0x468 | +| MIO_PAD_ATTR_27 | 0x46c | +| MIO_PAD_ATTR_28 | 0x470 | +| MIO_PAD_ATTR_29 | 0x474 | +| MIO_PAD_ATTR_30 | 0x478 | +| MIO_PAD_ATTR_31 | 0x47c | +| MIO_PAD_ATTR_32 | 0x480 | +| MIO_PAD_ATTR_33 | 0x484 | +| MIO_PAD_ATTR_34 | 0x488 | +| MIO_PAD_ATTR_35 | 0x48c | +| MIO_PAD_ATTR_36 | 0x490 | +| MIO_PAD_ATTR_37 | 0x494 | +| MIO_PAD_ATTR_38 | 0x498 | +| MIO_PAD_ATTR_39 | 0x49c | +| MIO_PAD_ATTR_40 | 0x4a0 | +| MIO_PAD_ATTR_41 | 0x4a4 | +| MIO_PAD_ATTR_42 | 0x4a8 | +| MIO_PAD_ATTR_43 | 0x4ac | +| MIO_PAD_ATTR_44 | 0x4b0 | +| MIO_PAD_ATTR_45 | 0x4b4 | +| MIO_PAD_ATTR_46 | 0x4b8 | ### Fields @@ -1100,22 +1088,22 @@ Register write enable for DIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| DIO_PAD_ATTR_REGWEN_0 | 0x4d4 | -| DIO_PAD_ATTR_REGWEN_1 | 0x4d8 | -| DIO_PAD_ATTR_REGWEN_2 | 0x4dc | -| DIO_PAD_ATTR_REGWEN_3 | 0x4e0 | -| DIO_PAD_ATTR_REGWEN_4 | 0x4e4 | -| DIO_PAD_ATTR_REGWEN_5 | 0x4e8 | -| DIO_PAD_ATTR_REGWEN_6 | 0x4ec | -| DIO_PAD_ATTR_REGWEN_7 | 0x4f0 | -| DIO_PAD_ATTR_REGWEN_8 | 0x4f4 | -| DIO_PAD_ATTR_REGWEN_9 | 0x4f8 | -| DIO_PAD_ATTR_REGWEN_10 | 0x4fc | -| DIO_PAD_ATTR_REGWEN_11 | 0x500 | -| DIO_PAD_ATTR_REGWEN_12 | 0x504 | -| DIO_PAD_ATTR_REGWEN_13 | 0x508 | -| DIO_PAD_ATTR_REGWEN_14 | 0x50c | -| DIO_PAD_ATTR_REGWEN_15 | 0x510 | +| DIO_PAD_ATTR_REGWEN_0 | 0x4bc | +| DIO_PAD_ATTR_REGWEN_1 | 0x4c0 | +| DIO_PAD_ATTR_REGWEN_2 | 0x4c4 | +| DIO_PAD_ATTR_REGWEN_3 | 0x4c8 | +| DIO_PAD_ATTR_REGWEN_4 | 0x4cc | +| DIO_PAD_ATTR_REGWEN_5 | 0x4d0 | +| DIO_PAD_ATTR_REGWEN_6 | 0x4d4 | +| DIO_PAD_ATTR_REGWEN_7 | 0x4d8 | +| DIO_PAD_ATTR_REGWEN_8 | 0x4dc | +| DIO_PAD_ATTR_REGWEN_9 | 0x4e0 | +| DIO_PAD_ATTR_REGWEN_10 | 0x4e4 | +| DIO_PAD_ATTR_REGWEN_11 | 0x4e8 | +| DIO_PAD_ATTR_REGWEN_12 | 0x4ec | +| DIO_PAD_ATTR_REGWEN_13 | 0x4f0 | +| DIO_PAD_ATTR_REGWEN_14 | 0x4f4 | +| DIO_PAD_ATTR_REGWEN_15 | 0x4f8 | ### Fields @@ -1141,22 +1129,22 @@ all attributes. | Name | Offset | |:----------------|:---------| -| DIO_PAD_ATTR_0 | 0x514 | -| DIO_PAD_ATTR_1 | 0x518 | -| DIO_PAD_ATTR_2 | 0x51c | -| DIO_PAD_ATTR_3 | 0x520 | -| DIO_PAD_ATTR_4 | 0x524 | -| DIO_PAD_ATTR_5 | 0x528 | -| DIO_PAD_ATTR_6 | 0x52c | -| DIO_PAD_ATTR_7 | 0x530 | -| DIO_PAD_ATTR_8 | 0x534 | -| DIO_PAD_ATTR_9 | 0x538 | -| DIO_PAD_ATTR_10 | 0x53c | -| DIO_PAD_ATTR_11 | 0x540 | -| DIO_PAD_ATTR_12 | 0x544 | -| DIO_PAD_ATTR_13 | 0x548 | -| DIO_PAD_ATTR_14 | 0x54c | -| DIO_PAD_ATTR_15 | 0x550 | +| DIO_PAD_ATTR_0 | 0x4fc | +| DIO_PAD_ATTR_1 | 0x500 | +| DIO_PAD_ATTR_2 | 0x504 | +| DIO_PAD_ATTR_3 | 0x508 | +| DIO_PAD_ATTR_4 | 0x50c | +| DIO_PAD_ATTR_5 | 0x510 | +| DIO_PAD_ATTR_6 | 0x514 | +| DIO_PAD_ATTR_7 | 0x518 | +| DIO_PAD_ATTR_8 | 0x51c | +| DIO_PAD_ATTR_9 | 0x520 | +| DIO_PAD_ATTR_10 | 0x524 | +| DIO_PAD_ATTR_11 | 0x528 | +| DIO_PAD_ATTR_12 | 0x52c | +| DIO_PAD_ATTR_13 | 0x530 | +| DIO_PAD_ATTR_14 | 0x534 | +| DIO_PAD_ATTR_15 | 0x538 | ### Fields @@ -1220,7 +1208,7 @@ Invert input and output levels. ## MIO_PAD_SLEEP_STATUS_0 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x554` +- Offset: `0x53c` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -1267,7 +1255,7 @@ Register indicating whether the corresponding pad is in sleep mode. ## MIO_PAD_SLEEP_STATUS_1 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x558` +- Offset: `0x540` - Reset default: `0x0` - Reset mask: `0x7fff` @@ -1305,53 +1293,53 @@ Register write enable for MIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| MIO_PAD_SLEEP_REGWEN_0 | 0x55c | -| MIO_PAD_SLEEP_REGWEN_1 | 0x560 | -| MIO_PAD_SLEEP_REGWEN_2 | 0x564 | -| MIO_PAD_SLEEP_REGWEN_3 | 0x568 | -| MIO_PAD_SLEEP_REGWEN_4 | 0x56c | -| MIO_PAD_SLEEP_REGWEN_5 | 0x570 | -| MIO_PAD_SLEEP_REGWEN_6 | 0x574 | -| MIO_PAD_SLEEP_REGWEN_7 | 0x578 | -| MIO_PAD_SLEEP_REGWEN_8 | 0x57c | -| MIO_PAD_SLEEP_REGWEN_9 | 0x580 | -| MIO_PAD_SLEEP_REGWEN_10 | 0x584 | -| MIO_PAD_SLEEP_REGWEN_11 | 0x588 | -| MIO_PAD_SLEEP_REGWEN_12 | 0x58c | -| MIO_PAD_SLEEP_REGWEN_13 | 0x590 | -| MIO_PAD_SLEEP_REGWEN_14 | 0x594 | -| MIO_PAD_SLEEP_REGWEN_15 | 0x598 | -| MIO_PAD_SLEEP_REGWEN_16 | 0x59c | -| MIO_PAD_SLEEP_REGWEN_17 | 0x5a0 | -| MIO_PAD_SLEEP_REGWEN_18 | 0x5a4 | -| MIO_PAD_SLEEP_REGWEN_19 | 0x5a8 | -| MIO_PAD_SLEEP_REGWEN_20 | 0x5ac | -| MIO_PAD_SLEEP_REGWEN_21 | 0x5b0 | -| MIO_PAD_SLEEP_REGWEN_22 | 0x5b4 | -| MIO_PAD_SLEEP_REGWEN_23 | 0x5b8 | -| MIO_PAD_SLEEP_REGWEN_24 | 0x5bc | -| MIO_PAD_SLEEP_REGWEN_25 | 0x5c0 | -| MIO_PAD_SLEEP_REGWEN_26 | 0x5c4 | -| MIO_PAD_SLEEP_REGWEN_27 | 0x5c8 | -| MIO_PAD_SLEEP_REGWEN_28 | 0x5cc | -| MIO_PAD_SLEEP_REGWEN_29 | 0x5d0 | -| MIO_PAD_SLEEP_REGWEN_30 | 0x5d4 | -| MIO_PAD_SLEEP_REGWEN_31 | 0x5d8 | -| MIO_PAD_SLEEP_REGWEN_32 | 0x5dc | -| MIO_PAD_SLEEP_REGWEN_33 | 0x5e0 | -| MIO_PAD_SLEEP_REGWEN_34 | 0x5e4 | -| MIO_PAD_SLEEP_REGWEN_35 | 0x5e8 | -| MIO_PAD_SLEEP_REGWEN_36 | 0x5ec | -| MIO_PAD_SLEEP_REGWEN_37 | 0x5f0 | -| MIO_PAD_SLEEP_REGWEN_38 | 0x5f4 | -| MIO_PAD_SLEEP_REGWEN_39 | 0x5f8 | -| MIO_PAD_SLEEP_REGWEN_40 | 0x5fc | -| MIO_PAD_SLEEP_REGWEN_41 | 0x600 | -| MIO_PAD_SLEEP_REGWEN_42 | 0x604 | -| MIO_PAD_SLEEP_REGWEN_43 | 0x608 | -| MIO_PAD_SLEEP_REGWEN_44 | 0x60c | -| MIO_PAD_SLEEP_REGWEN_45 | 0x610 | -| MIO_PAD_SLEEP_REGWEN_46 | 0x614 | +| MIO_PAD_SLEEP_REGWEN_0 | 0x544 | +| MIO_PAD_SLEEP_REGWEN_1 | 0x548 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x54c | +| MIO_PAD_SLEEP_REGWEN_3 | 0x550 | +| MIO_PAD_SLEEP_REGWEN_4 | 0x554 | +| MIO_PAD_SLEEP_REGWEN_5 | 0x558 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x55c | +| MIO_PAD_SLEEP_REGWEN_7 | 0x560 | +| MIO_PAD_SLEEP_REGWEN_8 | 0x564 | +| MIO_PAD_SLEEP_REGWEN_9 | 0x568 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x56c | +| MIO_PAD_SLEEP_REGWEN_11 | 0x570 | +| MIO_PAD_SLEEP_REGWEN_12 | 0x574 | +| MIO_PAD_SLEEP_REGWEN_13 | 0x578 | +| MIO_PAD_SLEEP_REGWEN_14 | 0x57c | +| MIO_PAD_SLEEP_REGWEN_15 | 0x580 | +| MIO_PAD_SLEEP_REGWEN_16 | 0x584 | +| MIO_PAD_SLEEP_REGWEN_17 | 0x588 | +| MIO_PAD_SLEEP_REGWEN_18 | 0x58c | +| MIO_PAD_SLEEP_REGWEN_19 | 0x590 | +| MIO_PAD_SLEEP_REGWEN_20 | 0x594 | +| MIO_PAD_SLEEP_REGWEN_21 | 0x598 | +| MIO_PAD_SLEEP_REGWEN_22 | 0x59c | +| MIO_PAD_SLEEP_REGWEN_23 | 0x5a0 | +| MIO_PAD_SLEEP_REGWEN_24 | 0x5a4 | +| MIO_PAD_SLEEP_REGWEN_25 | 0x5a8 | +| MIO_PAD_SLEEP_REGWEN_26 | 0x5ac | +| MIO_PAD_SLEEP_REGWEN_27 | 0x5b0 | +| MIO_PAD_SLEEP_REGWEN_28 | 0x5b4 | +| MIO_PAD_SLEEP_REGWEN_29 | 0x5b8 | +| MIO_PAD_SLEEP_REGWEN_30 | 0x5bc | +| MIO_PAD_SLEEP_REGWEN_31 | 0x5c0 | +| MIO_PAD_SLEEP_REGWEN_32 | 0x5c4 | +| MIO_PAD_SLEEP_REGWEN_33 | 0x5c8 | +| MIO_PAD_SLEEP_REGWEN_34 | 0x5cc | +| MIO_PAD_SLEEP_REGWEN_35 | 0x5d0 | +| MIO_PAD_SLEEP_REGWEN_36 | 0x5d4 | +| MIO_PAD_SLEEP_REGWEN_37 | 0x5d8 | +| MIO_PAD_SLEEP_REGWEN_38 | 0x5dc | +| MIO_PAD_SLEEP_REGWEN_39 | 0x5e0 | +| MIO_PAD_SLEEP_REGWEN_40 | 0x5e4 | +| MIO_PAD_SLEEP_REGWEN_41 | 0x5e8 | +| MIO_PAD_SLEEP_REGWEN_42 | 0x5ec | +| MIO_PAD_SLEEP_REGWEN_43 | 0x5f0 | +| MIO_PAD_SLEEP_REGWEN_44 | 0x5f4 | +| MIO_PAD_SLEEP_REGWEN_45 | 0x5f8 | +| MIO_PAD_SLEEP_REGWEN_46 | 0x5fc | ### Fields @@ -1375,53 +1363,53 @@ Enables the sleep mode of the corresponding muxed pad. | Name | Offset | |:--------------------|:---------| -| MIO_PAD_SLEEP_EN_0 | 0x618 | -| MIO_PAD_SLEEP_EN_1 | 0x61c | -| MIO_PAD_SLEEP_EN_2 | 0x620 | -| MIO_PAD_SLEEP_EN_3 | 0x624 | -| MIO_PAD_SLEEP_EN_4 | 0x628 | -| MIO_PAD_SLEEP_EN_5 | 0x62c | -| MIO_PAD_SLEEP_EN_6 | 0x630 | -| MIO_PAD_SLEEP_EN_7 | 0x634 | -| MIO_PAD_SLEEP_EN_8 | 0x638 | -| MIO_PAD_SLEEP_EN_9 | 0x63c | -| MIO_PAD_SLEEP_EN_10 | 0x640 | -| MIO_PAD_SLEEP_EN_11 | 0x644 | -| MIO_PAD_SLEEP_EN_12 | 0x648 | -| MIO_PAD_SLEEP_EN_13 | 0x64c | -| MIO_PAD_SLEEP_EN_14 | 0x650 | -| MIO_PAD_SLEEP_EN_15 | 0x654 | -| MIO_PAD_SLEEP_EN_16 | 0x658 | -| MIO_PAD_SLEEP_EN_17 | 0x65c | -| MIO_PAD_SLEEP_EN_18 | 0x660 | -| MIO_PAD_SLEEP_EN_19 | 0x664 | -| MIO_PAD_SLEEP_EN_20 | 0x668 | -| MIO_PAD_SLEEP_EN_21 | 0x66c | -| MIO_PAD_SLEEP_EN_22 | 0x670 | -| MIO_PAD_SLEEP_EN_23 | 0x674 | -| MIO_PAD_SLEEP_EN_24 | 0x678 | -| MIO_PAD_SLEEP_EN_25 | 0x67c | -| MIO_PAD_SLEEP_EN_26 | 0x680 | -| MIO_PAD_SLEEP_EN_27 | 0x684 | -| MIO_PAD_SLEEP_EN_28 | 0x688 | -| MIO_PAD_SLEEP_EN_29 | 0x68c | -| MIO_PAD_SLEEP_EN_30 | 0x690 | -| MIO_PAD_SLEEP_EN_31 | 0x694 | -| MIO_PAD_SLEEP_EN_32 | 0x698 | -| MIO_PAD_SLEEP_EN_33 | 0x69c | -| MIO_PAD_SLEEP_EN_34 | 0x6a0 | -| MIO_PAD_SLEEP_EN_35 | 0x6a4 | -| MIO_PAD_SLEEP_EN_36 | 0x6a8 | -| MIO_PAD_SLEEP_EN_37 | 0x6ac | -| MIO_PAD_SLEEP_EN_38 | 0x6b0 | -| MIO_PAD_SLEEP_EN_39 | 0x6b4 | -| MIO_PAD_SLEEP_EN_40 | 0x6b8 | -| MIO_PAD_SLEEP_EN_41 | 0x6bc | -| MIO_PAD_SLEEP_EN_42 | 0x6c0 | -| MIO_PAD_SLEEP_EN_43 | 0x6c4 | -| MIO_PAD_SLEEP_EN_44 | 0x6c8 | -| MIO_PAD_SLEEP_EN_45 | 0x6cc | -| MIO_PAD_SLEEP_EN_46 | 0x6d0 | +| MIO_PAD_SLEEP_EN_0 | 0x600 | +| MIO_PAD_SLEEP_EN_1 | 0x604 | +| MIO_PAD_SLEEP_EN_2 | 0x608 | +| MIO_PAD_SLEEP_EN_3 | 0x60c | +| MIO_PAD_SLEEP_EN_4 | 0x610 | +| MIO_PAD_SLEEP_EN_5 | 0x614 | +| MIO_PAD_SLEEP_EN_6 | 0x618 | +| MIO_PAD_SLEEP_EN_7 | 0x61c | +| MIO_PAD_SLEEP_EN_8 | 0x620 | +| MIO_PAD_SLEEP_EN_9 | 0x624 | +| MIO_PAD_SLEEP_EN_10 | 0x628 | +| MIO_PAD_SLEEP_EN_11 | 0x62c | +| MIO_PAD_SLEEP_EN_12 | 0x630 | +| MIO_PAD_SLEEP_EN_13 | 0x634 | +| MIO_PAD_SLEEP_EN_14 | 0x638 | +| MIO_PAD_SLEEP_EN_15 | 0x63c | +| MIO_PAD_SLEEP_EN_16 | 0x640 | +| MIO_PAD_SLEEP_EN_17 | 0x644 | +| MIO_PAD_SLEEP_EN_18 | 0x648 | +| MIO_PAD_SLEEP_EN_19 | 0x64c | +| MIO_PAD_SLEEP_EN_20 | 0x650 | +| MIO_PAD_SLEEP_EN_21 | 0x654 | +| MIO_PAD_SLEEP_EN_22 | 0x658 | +| MIO_PAD_SLEEP_EN_23 | 0x65c | +| MIO_PAD_SLEEP_EN_24 | 0x660 | +| MIO_PAD_SLEEP_EN_25 | 0x664 | +| MIO_PAD_SLEEP_EN_26 | 0x668 | +| MIO_PAD_SLEEP_EN_27 | 0x66c | +| MIO_PAD_SLEEP_EN_28 | 0x670 | +| MIO_PAD_SLEEP_EN_29 | 0x674 | +| MIO_PAD_SLEEP_EN_30 | 0x678 | +| MIO_PAD_SLEEP_EN_31 | 0x67c | +| MIO_PAD_SLEEP_EN_32 | 0x680 | +| MIO_PAD_SLEEP_EN_33 | 0x684 | +| MIO_PAD_SLEEP_EN_34 | 0x688 | +| MIO_PAD_SLEEP_EN_35 | 0x68c | +| MIO_PAD_SLEEP_EN_36 | 0x690 | +| MIO_PAD_SLEEP_EN_37 | 0x694 | +| MIO_PAD_SLEEP_EN_38 | 0x698 | +| MIO_PAD_SLEEP_EN_39 | 0x69c | +| MIO_PAD_SLEEP_EN_40 | 0x6a0 | +| MIO_PAD_SLEEP_EN_41 | 0x6a4 | +| MIO_PAD_SLEEP_EN_42 | 0x6a8 | +| MIO_PAD_SLEEP_EN_43 | 0x6ac | +| MIO_PAD_SLEEP_EN_44 | 0x6b0 | +| MIO_PAD_SLEEP_EN_45 | 0x6b4 | +| MIO_PAD_SLEEP_EN_46 | 0x6b8 | ### Fields @@ -1455,53 +1443,53 @@ Defines sleep behavior of the corresponding muxed pad. | Name | Offset | |:----------------------|:---------| -| MIO_PAD_SLEEP_MODE_0 | 0x6d4 | -| MIO_PAD_SLEEP_MODE_1 | 0x6d8 | -| MIO_PAD_SLEEP_MODE_2 | 0x6dc | -| MIO_PAD_SLEEP_MODE_3 | 0x6e0 | -| MIO_PAD_SLEEP_MODE_4 | 0x6e4 | -| MIO_PAD_SLEEP_MODE_5 | 0x6e8 | -| MIO_PAD_SLEEP_MODE_6 | 0x6ec | -| MIO_PAD_SLEEP_MODE_7 | 0x6f0 | -| MIO_PAD_SLEEP_MODE_8 | 0x6f4 | -| MIO_PAD_SLEEP_MODE_9 | 0x6f8 | -| MIO_PAD_SLEEP_MODE_10 | 0x6fc | -| MIO_PAD_SLEEP_MODE_11 | 0x700 | -| MIO_PAD_SLEEP_MODE_12 | 0x704 | -| MIO_PAD_SLEEP_MODE_13 | 0x708 | -| MIO_PAD_SLEEP_MODE_14 | 0x70c | -| MIO_PAD_SLEEP_MODE_15 | 0x710 | -| MIO_PAD_SLEEP_MODE_16 | 0x714 | -| MIO_PAD_SLEEP_MODE_17 | 0x718 | -| MIO_PAD_SLEEP_MODE_18 | 0x71c | -| MIO_PAD_SLEEP_MODE_19 | 0x720 | -| MIO_PAD_SLEEP_MODE_20 | 0x724 | -| MIO_PAD_SLEEP_MODE_21 | 0x728 | -| MIO_PAD_SLEEP_MODE_22 | 0x72c | -| MIO_PAD_SLEEP_MODE_23 | 0x730 | -| MIO_PAD_SLEEP_MODE_24 | 0x734 | -| MIO_PAD_SLEEP_MODE_25 | 0x738 | -| MIO_PAD_SLEEP_MODE_26 | 0x73c | -| MIO_PAD_SLEEP_MODE_27 | 0x740 | -| MIO_PAD_SLEEP_MODE_28 | 0x744 | -| MIO_PAD_SLEEP_MODE_29 | 0x748 | -| MIO_PAD_SLEEP_MODE_30 | 0x74c | -| MIO_PAD_SLEEP_MODE_31 | 0x750 | -| MIO_PAD_SLEEP_MODE_32 | 0x754 | -| MIO_PAD_SLEEP_MODE_33 | 0x758 | -| MIO_PAD_SLEEP_MODE_34 | 0x75c | -| MIO_PAD_SLEEP_MODE_35 | 0x760 | -| MIO_PAD_SLEEP_MODE_36 | 0x764 | -| MIO_PAD_SLEEP_MODE_37 | 0x768 | -| MIO_PAD_SLEEP_MODE_38 | 0x76c | -| MIO_PAD_SLEEP_MODE_39 | 0x770 | -| MIO_PAD_SLEEP_MODE_40 | 0x774 | -| MIO_PAD_SLEEP_MODE_41 | 0x778 | -| MIO_PAD_SLEEP_MODE_42 | 0x77c | -| MIO_PAD_SLEEP_MODE_43 | 0x780 | -| MIO_PAD_SLEEP_MODE_44 | 0x784 | -| MIO_PAD_SLEEP_MODE_45 | 0x788 | -| MIO_PAD_SLEEP_MODE_46 | 0x78c | +| MIO_PAD_SLEEP_MODE_0 | 0x6bc | +| MIO_PAD_SLEEP_MODE_1 | 0x6c0 | +| MIO_PAD_SLEEP_MODE_2 | 0x6c4 | +| MIO_PAD_SLEEP_MODE_3 | 0x6c8 | +| MIO_PAD_SLEEP_MODE_4 | 0x6cc | +| MIO_PAD_SLEEP_MODE_5 | 0x6d0 | +| MIO_PAD_SLEEP_MODE_6 | 0x6d4 | +| MIO_PAD_SLEEP_MODE_7 | 0x6d8 | +| MIO_PAD_SLEEP_MODE_8 | 0x6dc | +| MIO_PAD_SLEEP_MODE_9 | 0x6e0 | +| MIO_PAD_SLEEP_MODE_10 | 0x6e4 | +| MIO_PAD_SLEEP_MODE_11 | 0x6e8 | +| MIO_PAD_SLEEP_MODE_12 | 0x6ec | +| MIO_PAD_SLEEP_MODE_13 | 0x6f0 | +| MIO_PAD_SLEEP_MODE_14 | 0x6f4 | +| MIO_PAD_SLEEP_MODE_15 | 0x6f8 | +| MIO_PAD_SLEEP_MODE_16 | 0x6fc | +| MIO_PAD_SLEEP_MODE_17 | 0x700 | +| MIO_PAD_SLEEP_MODE_18 | 0x704 | +| MIO_PAD_SLEEP_MODE_19 | 0x708 | +| MIO_PAD_SLEEP_MODE_20 | 0x70c | +| MIO_PAD_SLEEP_MODE_21 | 0x710 | +| MIO_PAD_SLEEP_MODE_22 | 0x714 | +| MIO_PAD_SLEEP_MODE_23 | 0x718 | +| MIO_PAD_SLEEP_MODE_24 | 0x71c | +| MIO_PAD_SLEEP_MODE_25 | 0x720 | +| MIO_PAD_SLEEP_MODE_26 | 0x724 | +| MIO_PAD_SLEEP_MODE_27 | 0x728 | +| MIO_PAD_SLEEP_MODE_28 | 0x72c | +| MIO_PAD_SLEEP_MODE_29 | 0x730 | +| MIO_PAD_SLEEP_MODE_30 | 0x734 | +| MIO_PAD_SLEEP_MODE_31 | 0x738 | +| MIO_PAD_SLEEP_MODE_32 | 0x73c | +| MIO_PAD_SLEEP_MODE_33 | 0x740 | +| MIO_PAD_SLEEP_MODE_34 | 0x744 | +| MIO_PAD_SLEEP_MODE_35 | 0x748 | +| MIO_PAD_SLEEP_MODE_36 | 0x74c | +| MIO_PAD_SLEEP_MODE_37 | 0x750 | +| MIO_PAD_SLEEP_MODE_38 | 0x754 | +| MIO_PAD_SLEEP_MODE_39 | 0x758 | +| MIO_PAD_SLEEP_MODE_40 | 0x75c | +| MIO_PAD_SLEEP_MODE_41 | 0x760 | +| MIO_PAD_SLEEP_MODE_42 | 0x764 | +| MIO_PAD_SLEEP_MODE_43 | 0x768 | +| MIO_PAD_SLEEP_MODE_44 | 0x76c | +| MIO_PAD_SLEEP_MODE_45 | 0x770 | +| MIO_PAD_SLEEP_MODE_46 | 0x774 | ### Fields @@ -1528,7 +1516,7 @@ Value to drive in deep sleep. ## DIO_PAD_SLEEP_STATUS Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x790` +- Offset: `0x778` - Reset default: `0x0` - Reset mask: `0xffff` @@ -1567,22 +1555,22 @@ Register write enable for DIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| DIO_PAD_SLEEP_REGWEN_0 | 0x794 | -| DIO_PAD_SLEEP_REGWEN_1 | 0x798 | -| DIO_PAD_SLEEP_REGWEN_2 | 0x79c | -| DIO_PAD_SLEEP_REGWEN_3 | 0x7a0 | -| DIO_PAD_SLEEP_REGWEN_4 | 0x7a4 | -| DIO_PAD_SLEEP_REGWEN_5 | 0x7a8 | -| DIO_PAD_SLEEP_REGWEN_6 | 0x7ac | -| DIO_PAD_SLEEP_REGWEN_7 | 0x7b0 | -| DIO_PAD_SLEEP_REGWEN_8 | 0x7b4 | -| DIO_PAD_SLEEP_REGWEN_9 | 0x7b8 | -| DIO_PAD_SLEEP_REGWEN_10 | 0x7bc | -| DIO_PAD_SLEEP_REGWEN_11 | 0x7c0 | -| DIO_PAD_SLEEP_REGWEN_12 | 0x7c4 | -| DIO_PAD_SLEEP_REGWEN_13 | 0x7c8 | -| DIO_PAD_SLEEP_REGWEN_14 | 0x7cc | -| DIO_PAD_SLEEP_REGWEN_15 | 0x7d0 | +| DIO_PAD_SLEEP_REGWEN_0 | 0x77c | +| DIO_PAD_SLEEP_REGWEN_1 | 0x780 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x784 | +| DIO_PAD_SLEEP_REGWEN_3 | 0x788 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x78c | +| DIO_PAD_SLEEP_REGWEN_5 | 0x790 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x794 | +| DIO_PAD_SLEEP_REGWEN_7 | 0x798 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x79c | +| DIO_PAD_SLEEP_REGWEN_9 | 0x7a0 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x7a4 | +| DIO_PAD_SLEEP_REGWEN_11 | 0x7a8 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x7ac | +| DIO_PAD_SLEEP_REGWEN_13 | 0x7b0 | +| DIO_PAD_SLEEP_REGWEN_14 | 0x7b4 | +| DIO_PAD_SLEEP_REGWEN_15 | 0x7b8 | ### Fields @@ -1606,22 +1594,22 @@ Enables the sleep mode of the corresponding dedicated pad. | Name | Offset | |:--------------------|:---------| -| DIO_PAD_SLEEP_EN_0 | 0x7d4 | -| DIO_PAD_SLEEP_EN_1 | 0x7d8 | -| DIO_PAD_SLEEP_EN_2 | 0x7dc | -| DIO_PAD_SLEEP_EN_3 | 0x7e0 | -| DIO_PAD_SLEEP_EN_4 | 0x7e4 | -| DIO_PAD_SLEEP_EN_5 | 0x7e8 | -| DIO_PAD_SLEEP_EN_6 | 0x7ec | -| DIO_PAD_SLEEP_EN_7 | 0x7f0 | -| DIO_PAD_SLEEP_EN_8 | 0x7f4 | -| DIO_PAD_SLEEP_EN_9 | 0x7f8 | -| DIO_PAD_SLEEP_EN_10 | 0x7fc | -| DIO_PAD_SLEEP_EN_11 | 0x800 | -| DIO_PAD_SLEEP_EN_12 | 0x804 | -| DIO_PAD_SLEEP_EN_13 | 0x808 | -| DIO_PAD_SLEEP_EN_14 | 0x80c | -| DIO_PAD_SLEEP_EN_15 | 0x810 | +| DIO_PAD_SLEEP_EN_0 | 0x7bc | +| DIO_PAD_SLEEP_EN_1 | 0x7c0 | +| DIO_PAD_SLEEP_EN_2 | 0x7c4 | +| DIO_PAD_SLEEP_EN_3 | 0x7c8 | +| DIO_PAD_SLEEP_EN_4 | 0x7cc | +| DIO_PAD_SLEEP_EN_5 | 0x7d0 | +| DIO_PAD_SLEEP_EN_6 | 0x7d4 | +| DIO_PAD_SLEEP_EN_7 | 0x7d8 | +| DIO_PAD_SLEEP_EN_8 | 0x7dc | +| DIO_PAD_SLEEP_EN_9 | 0x7e0 | +| DIO_PAD_SLEEP_EN_10 | 0x7e4 | +| DIO_PAD_SLEEP_EN_11 | 0x7e8 | +| DIO_PAD_SLEEP_EN_12 | 0x7ec | +| DIO_PAD_SLEEP_EN_13 | 0x7f0 | +| DIO_PAD_SLEEP_EN_14 | 0x7f4 | +| DIO_PAD_SLEEP_EN_15 | 0x7f8 | ### Fields @@ -1655,22 +1643,22 @@ Defines sleep behavior of the corresponding dedicated pad. | Name | Offset | |:----------------------|:---------| -| DIO_PAD_SLEEP_MODE_0 | 0x814 | -| DIO_PAD_SLEEP_MODE_1 | 0x818 | -| DIO_PAD_SLEEP_MODE_2 | 0x81c | -| DIO_PAD_SLEEP_MODE_3 | 0x820 | -| DIO_PAD_SLEEP_MODE_4 | 0x824 | -| DIO_PAD_SLEEP_MODE_5 | 0x828 | -| DIO_PAD_SLEEP_MODE_6 | 0x82c | -| DIO_PAD_SLEEP_MODE_7 | 0x830 | -| DIO_PAD_SLEEP_MODE_8 | 0x834 | -| DIO_PAD_SLEEP_MODE_9 | 0x838 | -| DIO_PAD_SLEEP_MODE_10 | 0x83c | -| DIO_PAD_SLEEP_MODE_11 | 0x840 | -| DIO_PAD_SLEEP_MODE_12 | 0x844 | -| DIO_PAD_SLEEP_MODE_13 | 0x848 | -| DIO_PAD_SLEEP_MODE_14 | 0x84c | -| DIO_PAD_SLEEP_MODE_15 | 0x850 | +| DIO_PAD_SLEEP_MODE_0 | 0x7fc | +| DIO_PAD_SLEEP_MODE_1 | 0x800 | +| DIO_PAD_SLEEP_MODE_2 | 0x804 | +| DIO_PAD_SLEEP_MODE_3 | 0x808 | +| DIO_PAD_SLEEP_MODE_4 | 0x80c | +| DIO_PAD_SLEEP_MODE_5 | 0x810 | +| DIO_PAD_SLEEP_MODE_6 | 0x814 | +| DIO_PAD_SLEEP_MODE_7 | 0x818 | +| DIO_PAD_SLEEP_MODE_8 | 0x81c | +| DIO_PAD_SLEEP_MODE_9 | 0x820 | +| DIO_PAD_SLEEP_MODE_10 | 0x824 | +| DIO_PAD_SLEEP_MODE_11 | 0x828 | +| DIO_PAD_SLEEP_MODE_12 | 0x82c | +| DIO_PAD_SLEEP_MODE_13 | 0x830 | +| DIO_PAD_SLEEP_MODE_14 | 0x834 | +| DIO_PAD_SLEEP_MODE_15 | 0x838 | ### Fields @@ -1704,14 +1692,14 @@ Register write enable for wakeup detectors. | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_REGWEN_0 | 0x854 | -| WKUP_DETECTOR_REGWEN_1 | 0x858 | -| WKUP_DETECTOR_REGWEN_2 | 0x85c | -| WKUP_DETECTOR_REGWEN_3 | 0x860 | -| WKUP_DETECTOR_REGWEN_4 | 0x864 | -| WKUP_DETECTOR_REGWEN_5 | 0x868 | -| WKUP_DETECTOR_REGWEN_6 | 0x86c | -| WKUP_DETECTOR_REGWEN_7 | 0x870 | +| WKUP_DETECTOR_REGWEN_0 | 0x83c | +| WKUP_DETECTOR_REGWEN_1 | 0x840 | +| WKUP_DETECTOR_REGWEN_2 | 0x844 | +| WKUP_DETECTOR_REGWEN_3 | 0x848 | +| WKUP_DETECTOR_REGWEN_4 | 0x84c | +| WKUP_DETECTOR_REGWEN_5 | 0x850 | +| WKUP_DETECTOR_REGWEN_6 | 0x854 | +| WKUP_DETECTOR_REGWEN_7 | 0x858 | ### Fields @@ -1738,14 +1726,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-------------------|:---------| -| WKUP_DETECTOR_EN_0 | 0x874 | -| WKUP_DETECTOR_EN_1 | 0x878 | -| WKUP_DETECTOR_EN_2 | 0x87c | -| WKUP_DETECTOR_EN_3 | 0x880 | -| WKUP_DETECTOR_EN_4 | 0x884 | -| WKUP_DETECTOR_EN_5 | 0x888 | -| WKUP_DETECTOR_EN_6 | 0x88c | -| WKUP_DETECTOR_EN_7 | 0x890 | +| WKUP_DETECTOR_EN_0 | 0x85c | +| WKUP_DETECTOR_EN_1 | 0x860 | +| WKUP_DETECTOR_EN_2 | 0x864 | +| WKUP_DETECTOR_EN_3 | 0x868 | +| WKUP_DETECTOR_EN_4 | 0x86c | +| WKUP_DETECTOR_EN_5 | 0x870 | +| WKUP_DETECTOR_EN_6 | 0x874 | +| WKUP_DETECTOR_EN_7 | 0x878 | ### Fields @@ -1775,14 +1763,14 @@ The reason for that is that the pulse width counter is NOT cleared upon a mode c | Name | Offset | |:----------------|:---------| -| WKUP_DETECTOR_0 | 0x894 | -| WKUP_DETECTOR_1 | 0x898 | -| WKUP_DETECTOR_2 | 0x89c | -| WKUP_DETECTOR_3 | 0x8a0 | -| WKUP_DETECTOR_4 | 0x8a4 | -| WKUP_DETECTOR_5 | 0x8a8 | -| WKUP_DETECTOR_6 | 0x8ac | -| WKUP_DETECTOR_7 | 0x8b0 | +| WKUP_DETECTOR_0 | 0x87c | +| WKUP_DETECTOR_1 | 0x880 | +| WKUP_DETECTOR_2 | 0x884 | +| WKUP_DETECTOR_3 | 0x888 | +| WKUP_DETECTOR_4 | 0x88c | +| WKUP_DETECTOR_5 | 0x890 | +| WKUP_DETECTOR_6 | 0x894 | +| WKUP_DETECTOR_7 | 0x898 | ### Fields @@ -1833,14 +1821,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_CNT_TH_0 | 0x8b4 | -| WKUP_DETECTOR_CNT_TH_1 | 0x8b8 | -| WKUP_DETECTOR_CNT_TH_2 | 0x8bc | -| WKUP_DETECTOR_CNT_TH_3 | 0x8c0 | -| WKUP_DETECTOR_CNT_TH_4 | 0x8c4 | -| WKUP_DETECTOR_CNT_TH_5 | 0x8c8 | -| WKUP_DETECTOR_CNT_TH_6 | 0x8cc | -| WKUP_DETECTOR_CNT_TH_7 | 0x8d0 | +| WKUP_DETECTOR_CNT_TH_0 | 0x89c | +| WKUP_DETECTOR_CNT_TH_1 | 0x8a0 | +| WKUP_DETECTOR_CNT_TH_2 | 0x8a4 | +| WKUP_DETECTOR_CNT_TH_3 | 0x8a8 | +| WKUP_DETECTOR_CNT_TH_4 | 0x8ac | +| WKUP_DETECTOR_CNT_TH_5 | 0x8b0 | +| WKUP_DETECTOR_CNT_TH_6 | 0x8b4 | +| WKUP_DETECTOR_CNT_TH_7 | 0x8b8 | ### Fields @@ -1865,14 +1853,14 @@ This register is NOT synced to the AON domain since the muxing mechanism is impl | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_PADSEL_0 | 0x8d4 | -| WKUP_DETECTOR_PADSEL_1 | 0x8d8 | -| WKUP_DETECTOR_PADSEL_2 | 0x8dc | -| WKUP_DETECTOR_PADSEL_3 | 0x8e0 | -| WKUP_DETECTOR_PADSEL_4 | 0x8e4 | -| WKUP_DETECTOR_PADSEL_5 | 0x8e8 | -| WKUP_DETECTOR_PADSEL_6 | 0x8ec | -| WKUP_DETECTOR_PADSEL_7 | 0x8f0 | +| WKUP_DETECTOR_PADSEL_0 | 0x8bc | +| WKUP_DETECTOR_PADSEL_1 | 0x8c0 | +| WKUP_DETECTOR_PADSEL_2 | 0x8c4 | +| WKUP_DETECTOR_PADSEL_3 | 0x8c8 | +| WKUP_DETECTOR_PADSEL_4 | 0x8cc | +| WKUP_DETECTOR_PADSEL_5 | 0x8d0 | +| WKUP_DETECTOR_PADSEL_6 | 0x8d4 | +| WKUP_DETECTOR_PADSEL_7 | 0x8d8 | ### Fields @@ -1897,7 +1885,7 @@ Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed. -- Offset: `0x8f4` +- Offset: `0x8dc` - Reset default: `0x0` - Reset mask: `0xff` diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md index eabe947d5a321..27558d130dc34 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md @@ -6,6 +6,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ --> | Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables | |:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:-------------------------------------:| -| ASIC | 4 | 47 | 14 | 9 | 70 | [Pinout Table](./pinout_asic.md) | -| VERILATOR | 4 | 47 | 14 | 9 | 70 | [Pinout Table](./pinout_verilator.md) | +| ASIC | 4 | 47 | 14 | 6 | 67 | [Pinout Table](./pinout_asic.md) | +| VERILATOR | 4 | 47 | 14 | 6 | 67 | [Pinout Table](./pinout_verilator.md) | | CW340 | 4 | 47 | 14 | 13 | 74 | [Pinout Table](./pinout_cw340.md) | diff --git a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv index a8781f97cd376..128969e0d805f 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv @@ -7,8 +7,8 @@ package pinmux_reg_pkg; // Param list - parameter int NMioPeriphIn = 60; - parameter int NMioPeriphOut = 65; + parameter int NMioPeriphIn = 57; + parameter int NMioPeriphOut = 64; parameter int NMioPads = 47; parameter int NDioPads = 16; parameter int NWkupDetect = 8; @@ -19,7 +19,7 @@ package pinmux_reg_pkg; parameter int BlockAw = 12; // Number of registers for every interface - parameter int NumRegs = 574; + parameter int NumRegs = 568; // Alert indices typedef enum int { @@ -264,8 +264,8 @@ package pinmux_reg_pkg; // Register -> HW type typedef struct packed { - pinmux_reg2hw_alert_test_reg_t alert_test; // [2622:2621] - pinmux_reg2hw_mio_periph_insel_mreg_t [59:0] mio_periph_insel; // [2620:2261] + pinmux_reg2hw_alert_test_reg_t alert_test; // [2604:2603] + pinmux_reg2hw_mio_periph_insel_mreg_t [56:0] mio_periph_insel; // [2602:2261] pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [2260:1932] pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1931:804] pinmux_reg2hw_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [803:420] @@ -350,522 +350,516 @@ package pinmux_reg_pkg; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET = 12'h e0; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET = 12'h e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET = 12'h e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET = 12'h ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET = 12'h f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h 100; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h 104; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h 108; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 10c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 110; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 114; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 118; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 11c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 120; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 124; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 128; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 12c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 130; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 134; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 138; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 13c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 140; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 144; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 148; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 14c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 150; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 154; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 158; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 15c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 160; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 164; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 168; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 16c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 170; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 174; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 178; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 17c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 180; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 184; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 188; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 18c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 190; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 194; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 198; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 19c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 1a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 1a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 1a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_57_OFFSET = 12'h 1d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_58_OFFSET = 12'h 1dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_59_OFFSET = 12'h 1e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 200; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 344; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 348; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 34c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 350; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 354; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 358; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 35c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 360; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 364; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 368; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 36c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 370; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 374; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 378; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 37c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 380; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 384; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 388; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 38c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 390; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 394; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 398; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 39c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 400; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 404; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 408; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 40c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 410; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 414; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 418; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 41c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 420; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 424; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 428; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 42c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 430; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 434; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 438; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 43c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 440; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 444; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 448; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 44c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 450; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 454; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 458; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 45c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 460; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 464; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 468; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 46c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 470; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 474; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 478; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 47c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 480; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 484; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 488; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 48c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 490; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 494; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 498; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 49c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 4a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 4a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 4a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 500; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 504; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 508; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 50c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 510; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 514; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 518; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 51c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 520; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 524; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 528; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 52c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 530; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 534; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 538; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 53c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 540; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 544; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 548; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 54c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 550; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 554; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 558; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 55c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 560; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 564; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 568; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 56c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 570; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 574; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 578; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 57c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 580; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 584; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 588; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 58c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 590; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 594; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 598; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 59c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 5a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 600; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 604; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 608; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 60c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 610; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 614; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 618; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 61c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 620; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 624; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 628; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 62c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 630; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 634; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 638; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 63c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 640; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 644; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 648; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 64c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 650; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 654; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 658; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 65c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 660; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 664; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 668; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 66c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 670; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 674; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 678; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 67c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 680; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 684; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 688; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 68c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 690; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 694; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 698; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 69c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 6a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 700; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 704; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 708; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 70c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 710; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 714; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 718; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 71c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 720; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 724; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 728; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 72c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 730; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 734; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 738; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 73c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 740; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 744; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 748; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 74c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 750; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 754; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 758; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 75c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 760; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 764; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 768; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 76c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 770; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 774; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 778; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 77c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 780; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 784; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 788; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 78c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 790; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 794; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 798; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 79c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 7a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 7a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 7a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 7ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 7b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 7b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 800; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 804; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 808; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 80c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 810; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 814; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 818; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 81c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 820; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 824; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 828; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 82c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 830; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 834; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 838; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 83c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 840; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 844; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 848; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 84c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 850; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 854; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 858; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 85c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 860; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 864; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 868; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 86c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 870; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 874; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 878; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 87c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 880; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 884; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 888; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 88c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 890; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 894; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 898; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 89c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 8a0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 8a4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 8a8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 8ac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 8b0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 8b4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8b8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8dc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8e0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8e4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8e8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8ec; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8f0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 100; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 104; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 108; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 10c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 110; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 114; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 118; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 11c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 120; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 124; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 128; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 12c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 130; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 134; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 138; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 13c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 140; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 144; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 148; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 14c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 150; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 154; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 158; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 15c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 160; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 164; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 168; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 16c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 170; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 174; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 178; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 17c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 180; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 184; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 188; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 18c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 190; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 194; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 198; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 19c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 200; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 204; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 538; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 53c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 540; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 544; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 548; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 54c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 550; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 554; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 558; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 55c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 560; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 564; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 568; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 56c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 570; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 574; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 578; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 57c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 580; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 584; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 588; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 58c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 590; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 594; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 598; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 59c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 600; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 604; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 608; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 60c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 610; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 614; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 618; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 61c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 620; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 624; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 628; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 62c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 630; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 634; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 638; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 63c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 640; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 644; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 648; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 64c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 650; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 654; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 658; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 65c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 660; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 664; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 668; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 66c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 670; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 674; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 678; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 67c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 680; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 684; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 688; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 68c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 690; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 694; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 698; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 69c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 700; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 704; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 708; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 70c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 710; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 714; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 718; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 71c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 720; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 724; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 728; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 72c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 730; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 734; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 738; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 73c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 740; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 744; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 748; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 74c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 750; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 754; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 758; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 75c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 760; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 764; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 768; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 76c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 770; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 774; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 778; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 77c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 780; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 784; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 788; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 78c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 790; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 794; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 798; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 79c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 7e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 7ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 7f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 7f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 7f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 7fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 800; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 804; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 808; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 80c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 810; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 814; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 818; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 81c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 820; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 824; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 828; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 82c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 830; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 834; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 838; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 83c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 840; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 844; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 848; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 84c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 850; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 854; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 858; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 85c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 860; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 864; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 868; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 86c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 870; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 874; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 878; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 87c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 880; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 884; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 888; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 88c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 890; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 894; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 898; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 89c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8d8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8dc; // Reset values for hwext registers and their fields parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; @@ -1624,9 +1618,6 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_REGWEN_54, PINMUX_MIO_PERIPH_INSEL_REGWEN_55, PINMUX_MIO_PERIPH_INSEL_REGWEN_56, - PINMUX_MIO_PERIPH_INSEL_REGWEN_57, - PINMUX_MIO_PERIPH_INSEL_REGWEN_58, - PINMUX_MIO_PERIPH_INSEL_REGWEN_59, PINMUX_MIO_PERIPH_INSEL_0, PINMUX_MIO_PERIPH_INSEL_1, PINMUX_MIO_PERIPH_INSEL_2, @@ -1684,9 +1675,6 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_54, PINMUX_MIO_PERIPH_INSEL_55, PINMUX_MIO_PERIPH_INSEL_56, - PINMUX_MIO_PERIPH_INSEL_57, - PINMUX_MIO_PERIPH_INSEL_58, - PINMUX_MIO_PERIPH_INSEL_59, PINMUX_MIO_OUTSEL_REGWEN_0, PINMUX_MIO_OUTSEL_REGWEN_1, PINMUX_MIO_OUTSEL_REGWEN_2, @@ -2143,7 +2131,7 @@ package pinmux_reg_pkg; } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [574] = '{ + parameter logic [3:0] PINMUX_PERMIT [568] = '{ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 @@ -2202,522 +2190,516 @@ package pinmux_reg_pkg; 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_REGWEN_55 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_REGWEN_56 - 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_REGWEN_57 - 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_REGWEN_58 - 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_REGWEN_59 - 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_0 - 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_1 - 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_2 - 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_3 - 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_4 - 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_5 - 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_6 - 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_7 - 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_8 - 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_9 - 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_10 - 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_11 - 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_12 - 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_13 - 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_14 - 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_15 - 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_16 - 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_17 - 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_18 - 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_19 - 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_20 - 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_21 - 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_22 - 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_23 - 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_24 - 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_25 - 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_26 - 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_27 - 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_28 - 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_29 - 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_30 - 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_31 - 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_32 - 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_33 - 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_34 - 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_35 - 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_36 - 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_37 - 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_38 - 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_39 - 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_40 - 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_41 - 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_42 - 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_43 - 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_44 - 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_45 - 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_46 - 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_47 - 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_48 - 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_49 - 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_50 - 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_51 - 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_52 - 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_53 - 4'b 0001, // index[115] PINMUX_MIO_PERIPH_INSEL_54 - 4'b 0001, // index[116] PINMUX_MIO_PERIPH_INSEL_55 - 4'b 0001, // index[117] PINMUX_MIO_PERIPH_INSEL_56 - 4'b 0001, // index[118] PINMUX_MIO_PERIPH_INSEL_57 - 4'b 0001, // index[119] PINMUX_MIO_PERIPH_INSEL_58 - 4'b 0001, // index[120] PINMUX_MIO_PERIPH_INSEL_59 - 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_0 - 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_1 - 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_2 - 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_3 - 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_4 - 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_5 - 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_6 - 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_7 - 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_8 - 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_9 - 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_10 - 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_11 - 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_12 - 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_13 - 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_14 - 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_15 - 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_16 - 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_17 - 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_18 - 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_19 - 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_20 - 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_21 - 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_22 - 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_23 - 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_24 - 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_25 - 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_26 - 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_27 - 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_28 - 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_29 - 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_30 - 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_31 - 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_32 - 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_33 - 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_34 - 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_35 - 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_36 - 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_37 - 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_38 - 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_39 - 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_40 - 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_REGWEN_41 - 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_REGWEN_42 - 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_REGWEN_43 - 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_REGWEN_44 - 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_REGWEN_45 - 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_REGWEN_46 - 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_0 - 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_1 - 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_2 - 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_3 - 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_4 - 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_5 - 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_6 - 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_7 - 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_8 - 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_9 - 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_10 - 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_11 - 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_12 - 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_13 - 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_14 - 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_15 - 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_16 - 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_17 - 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_18 - 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_19 - 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_20 - 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_21 - 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_22 - 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_23 - 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_24 - 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_25 - 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_26 - 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_27 - 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_28 - 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_29 - 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_30 - 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_32 - 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_33 - 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_34 - 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_35 - 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_36 - 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_37 - 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_38 - 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_39 - 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_40 - 4'b 0001, // index[209] PINMUX_MIO_OUTSEL_41 - 4'b 0001, // index[210] PINMUX_MIO_OUTSEL_42 - 4'b 0001, // index[211] PINMUX_MIO_OUTSEL_43 - 4'b 0001, // index[212] PINMUX_MIO_OUTSEL_44 - 4'b 0001, // index[213] PINMUX_MIO_OUTSEL_45 - 4'b 0001, // index[214] PINMUX_MIO_OUTSEL_46 - 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_36 - 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_37 - 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_38 - 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_39 - 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_40 - 4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_41 - 4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_42 - 4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_43 - 4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_44 - 4'b 0001, // index[260] PINMUX_MIO_PAD_ATTR_REGWEN_45 - 4'b 0001, // index[261] PINMUX_MIO_PAD_ATTR_REGWEN_46 - 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_0 - 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_1 - 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_2 - 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_3 - 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_4 - 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_5 - 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_6 - 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_7 - 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_8 - 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_9 - 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_10 - 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_11 - 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_12 - 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_13 - 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_14 - 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_15 - 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_16 - 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_17 - 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_18 - 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_19 - 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_20 - 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_21 - 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_22 - 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_23 - 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_24 - 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_25 - 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_26 - 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_27 - 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_28 - 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_29 - 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_30 - 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_31 - 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_32 - 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_33 - 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_34 - 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_35 - 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_36 - 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_37 - 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_38 - 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_39 - 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_40 - 4'b 0111, // index[303] PINMUX_MIO_PAD_ATTR_41 - 4'b 0111, // index[304] PINMUX_MIO_PAD_ATTR_42 - 4'b 0111, // index[305] PINMUX_MIO_PAD_ATTR_43 - 4'b 0111, // index[306] PINMUX_MIO_PAD_ATTR_44 - 4'b 0111, // index[307] PINMUX_MIO_PAD_ATTR_45 - 4'b 0111, // index[308] PINMUX_MIO_PAD_ATTR_46 - 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[323] PINMUX_DIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[324] PINMUX_DIO_PAD_ATTR_REGWEN_15 - 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_0 - 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_1 - 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_2 - 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_3 - 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_4 - 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_5 - 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_6 - 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_7 - 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_8 - 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_9 - 4'b 0111, // index[335] PINMUX_DIO_PAD_ATTR_10 - 4'b 0111, // index[336] PINMUX_DIO_PAD_ATTR_11 - 4'b 0111, // index[337] PINMUX_DIO_PAD_ATTR_12 - 4'b 0111, // index[338] PINMUX_DIO_PAD_ATTR_13 - 4'b 0111, // index[339] PINMUX_DIO_PAD_ATTR_14 - 4'b 0111, // index[340] PINMUX_DIO_PAD_ATTR_15 - 4'b 1111, // index[341] PINMUX_MIO_PAD_SLEEP_STATUS_0 - 4'b 0011, // index[342] PINMUX_MIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_37 - 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_38 - 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_39 - 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_40 - 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_41 - 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_42 - 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_43 - 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_44 - 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_45 - 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_46 - 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_37 - 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_38 - 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_39 - 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_40 - 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_41 - 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_42 - 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_43 - 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_44 - 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_EN_45 - 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_EN_46 - 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_37 - 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_38 - 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_39 - 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_40 - 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_41 - 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_42 - 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_43 - 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_44 - 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_MODE_45 - 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_MODE_46 - 4'b 0011, // index[484] PINMUX_DIO_PAD_SLEEP_STATUS - 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[571] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[572] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[573] PINMUX_WKUP_CAUSE + 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_4 + 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_5 + 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_6 + 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_7 + 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_8 + 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_9 + 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_10 + 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_11 + 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_12 + 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_13 + 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_14 + 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_15 + 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_16 + 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_17 + 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_18 + 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_19 + 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_20 + 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_21 + 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_22 + 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_23 + 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_24 + 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_25 + 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_26 + 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_27 + 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_28 + 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_29 + 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_30 + 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_31 + 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_32 + 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_33 + 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_34 + 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_35 + 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_36 + 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_37 + 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_38 + 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_39 + 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_40 + 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_41 + 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_42 + 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_43 + 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_44 + 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_45 + 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_46 + 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_47 + 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_48 + 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_49 + 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_50 + 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_51 + 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_52 + 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_53 + 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_54 + 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_55 + 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_56 + 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_12 + 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_13 + 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_14 + 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_15 + 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_16 + 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_17 + 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_18 + 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_19 + 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_20 + 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_21 + 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_22 + 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_23 + 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_24 + 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_25 + 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_26 + 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_27 + 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_28 + 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_29 + 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_30 + 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_31 + 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_32 + 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_33 + 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_34 + 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_35 + 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_36 + 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_37 + 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_38 + 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_39 + 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_40 + 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_41 + 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_42 + 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_43 + 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_44 + 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_45 + 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_46 + 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_12 + 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_13 + 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_14 + 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_15 + 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_16 + 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_17 + 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_18 + 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_19 + 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_20 + 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_21 + 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_22 + 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_23 + 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_24 + 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_25 + 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_26 + 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_27 + 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_28 + 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_29 + 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_30 + 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_31 + 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_32 + 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_33 + 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_34 + 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_35 + 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_36 + 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_37 + 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_38 + 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_39 + 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_40 + 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_41 + 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_42 + 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_43 + 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_44 + 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_45 + 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_46 + 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_46 + 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[259] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_11 + 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_12 + 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_13 + 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_14 + 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_15 + 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_16 + 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_17 + 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_18 + 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_19 + 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_20 + 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_21 + 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_22 + 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_23 + 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_24 + 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_25 + 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_26 + 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_27 + 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_28 + 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_29 + 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_30 + 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_31 + 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_32 + 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_33 + 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_34 + 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_35 + 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_36 + 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_37 + 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_38 + 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_39 + 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_40 + 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_41 + 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_42 + 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_43 + 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_44 + 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_45 + 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_46 + 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0111, // index[319] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[320] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[321] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[322] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[323] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[324] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_15 + 4'b 1111, // index[335] PINMUX_MIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[336] PINMUX_MIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_46 + 4'b 0011, // index[478] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[479] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[480] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[481] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[482] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[483] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[484] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[527] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[528] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[529] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[530] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[531] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[532] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[567] PINMUX_WKUP_CAUSE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv index 6f0634c6474b1..c55fd381d5485 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv @@ -54,9 +54,9 @@ module pinmux_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [573:0] reg_we_check; + logic [567:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(574) + .OneHotWidth(568) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -296,15 +296,6 @@ module pinmux_reg_top ( logic mio_periph_insel_regwen_56_we; logic mio_periph_insel_regwen_56_qs; logic mio_periph_insel_regwen_56_wd; - logic mio_periph_insel_regwen_57_we; - logic mio_periph_insel_regwen_57_qs; - logic mio_periph_insel_regwen_57_wd; - logic mio_periph_insel_regwen_58_we; - logic mio_periph_insel_regwen_58_qs; - logic mio_periph_insel_regwen_58_wd; - logic mio_periph_insel_regwen_59_we; - logic mio_periph_insel_regwen_59_qs; - logic mio_periph_insel_regwen_59_wd; logic mio_periph_insel_0_we; logic [5:0] mio_periph_insel_0_qs; logic [5:0] mio_periph_insel_0_wd; @@ -476,15 +467,6 @@ module pinmux_reg_top ( logic mio_periph_insel_56_we; logic [5:0] mio_periph_insel_56_qs; logic [5:0] mio_periph_insel_56_wd; - logic mio_periph_insel_57_we; - logic [5:0] mio_periph_insel_57_qs; - logic [5:0] mio_periph_insel_57_wd; - logic mio_periph_insel_58_we; - logic [5:0] mio_periph_insel_58_qs; - logic [5:0] mio_periph_insel_58_wd; - logic mio_periph_insel_59_we; - logic [5:0] mio_periph_insel_59_qs; - logic [5:0] mio_periph_insel_59_wd; logic mio_outsel_regwen_0_we; logic mio_outsel_regwen_0_qs; logic mio_outsel_regwen_0_wd; @@ -5877,93 +5859,6 @@ module pinmux_reg_top ( ); - // Subregister 57 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_57]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_57 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_57_we), - .wd (mio_periph_insel_regwen_57_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_57_qs) - ); - - - // Subregister 58 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_58]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_58 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_58_we), - .wd (mio_periph_insel_regwen_58_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_58_qs) - ); - - - // Subregister 59 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_59]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_59 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_59_we), - .wd (mio_periph_insel_regwen_59_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_59_qs) - ); - - // Subregister 0 of Multireg mio_periph_insel // R[mio_periph_insel_0]: V(False) // Create REGWEN-gated WE signal @@ -7788,102 +7683,6 @@ module pinmux_reg_top ( ); - // Subregister 57 of Multireg mio_periph_insel - // R[mio_periph_insel_57]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_57_gated_we; - assign mio_periph_insel_57_gated_we = mio_periph_insel_57_we & mio_periph_insel_regwen_57_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_57 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_57_gated_we), - .wd (mio_periph_insel_57_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[57].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_57_qs) - ); - - - // Subregister 58 of Multireg mio_periph_insel - // R[mio_periph_insel_58]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_58_gated_we; - assign mio_periph_insel_58_gated_we = mio_periph_insel_58_we & mio_periph_insel_regwen_58_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_58 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_58_gated_we), - .wd (mio_periph_insel_58_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[58].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_58_qs) - ); - - - // Subregister 59 of Multireg mio_periph_insel - // R[mio_periph_insel_59]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_59_gated_we; - assign mio_periph_insel_59_gated_we = mio_periph_insel_59_we & mio_periph_insel_regwen_59_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_59 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_59_gated_we), - .wd (mio_periph_insel_59_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[59].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_59_qs) - ); - - // Subregister 0 of Multireg mio_outsel_regwen // R[mio_outsel_regwen_0]: V(False) prim_subreg #( @@ -32728,7 +32527,7 @@ module pinmux_reg_top ( - logic [573:0] addr_hit; + logic [567:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); @@ -32788,522 +32587,516 @@ module pinmux_reg_top ( addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET); addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET); addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET); - addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET); - addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET); - addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET); - addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); - addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); - addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); - addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); - addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); - addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); - addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); - addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); - addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); - addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); - addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); - addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); - addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); - addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); - addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); - addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); - addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); - addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); - addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); - addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); - addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); - addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); - addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); - addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); - addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); - addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); - addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); - addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); - addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); - addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); - addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); - addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); - addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); - addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); - addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); - addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); - addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); - addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); - addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); - addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); - addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); - addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); - addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); - addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); - addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); - addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); - addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); - addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); - addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); - addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); - addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); - addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); - addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); - addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); - addr_hit[115] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); - addr_hit[116] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); - addr_hit[117] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); - addr_hit[118] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_57_OFFSET); - addr_hit[119] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_58_OFFSET); - addr_hit[120] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_59_OFFSET); - addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); - addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); - addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); - addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); - addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); - addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); - addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); - addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); - addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); - addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); - addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); - addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); - addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); - addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); - addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); - addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); - addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); - addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); - addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); - addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); - addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); - addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); - addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); - addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); - addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); - addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); - addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); - addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); - addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); - addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); - addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); - addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); - addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); - addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); - addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); - addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); - addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); - addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); - addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); - addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); - addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); - addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); - addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); - addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); - addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); - addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); - addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); - addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); - addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); - addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); - addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); - addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); - addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); - addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); - addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); - addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); - addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); - addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); - addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); - addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); - addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); - addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); - addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); - addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); - addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); - addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); - addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); - addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); - addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); - addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); - addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); - addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); - addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); - addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); - addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); - addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); - addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); - addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); - addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); - addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); - addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); - addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); - addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); - addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); - addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[571] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[572] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[573] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[527] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[528] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[529] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[530] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[531] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[532] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[567] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -33878,13 +33671,7 @@ module pinmux_reg_top ( (addr_hit[564] & (|(PINMUX_PERMIT[564] & ~reg_be))) | (addr_hit[565] & (|(PINMUX_PERMIT[565] & ~reg_be))) | (addr_hit[566] & (|(PINMUX_PERMIT[566] & ~reg_be))) | - (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))) | - (addr_hit[568] & (|(PINMUX_PERMIT[568] & ~reg_be))) | - (addr_hit[569] & (|(PINMUX_PERMIT[569] & ~reg_be))) | - (addr_hit[570] & (|(PINMUX_PERMIT[570] & ~reg_be))) | - (addr_hit[571] & (|(PINMUX_PERMIT[571] & ~reg_be))) | - (addr_hit[572] & (|(PINMUX_PERMIT[572] & ~reg_be))) | - (addr_hit[573] & (|(PINMUX_PERMIT[573] & ~reg_be))))); + (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))))); end // Generate write-enables @@ -34062,620 +33849,602 @@ module pinmux_reg_top ( assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error; assign mio_periph_insel_regwen_56_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_57_we = addr_hit[58] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_57_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_58_we = addr_hit[59] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_58_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_59_we = addr_hit[60] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_59_wd = reg_wdata[0]; - assign mio_periph_insel_0_we = addr_hit[61] & reg_we & !reg_error; + assign mio_periph_insel_0_we = addr_hit[58] & reg_we & !reg_error; assign mio_periph_insel_0_wd = reg_wdata[5:0]; - assign mio_periph_insel_1_we = addr_hit[62] & reg_we & !reg_error; + assign mio_periph_insel_1_we = addr_hit[59] & reg_we & !reg_error; assign mio_periph_insel_1_wd = reg_wdata[5:0]; - assign mio_periph_insel_2_we = addr_hit[63] & reg_we & !reg_error; + assign mio_periph_insel_2_we = addr_hit[60] & reg_we & !reg_error; assign mio_periph_insel_2_wd = reg_wdata[5:0]; - assign mio_periph_insel_3_we = addr_hit[64] & reg_we & !reg_error; + assign mio_periph_insel_3_we = addr_hit[61] & reg_we & !reg_error; assign mio_periph_insel_3_wd = reg_wdata[5:0]; - assign mio_periph_insel_4_we = addr_hit[65] & reg_we & !reg_error; + assign mio_periph_insel_4_we = addr_hit[62] & reg_we & !reg_error; assign mio_periph_insel_4_wd = reg_wdata[5:0]; - assign mio_periph_insel_5_we = addr_hit[66] & reg_we & !reg_error; + assign mio_periph_insel_5_we = addr_hit[63] & reg_we & !reg_error; assign mio_periph_insel_5_wd = reg_wdata[5:0]; - assign mio_periph_insel_6_we = addr_hit[67] & reg_we & !reg_error; + assign mio_periph_insel_6_we = addr_hit[64] & reg_we & !reg_error; assign mio_periph_insel_6_wd = reg_wdata[5:0]; - assign mio_periph_insel_7_we = addr_hit[68] & reg_we & !reg_error; + assign mio_periph_insel_7_we = addr_hit[65] & reg_we & !reg_error; assign mio_periph_insel_7_wd = reg_wdata[5:0]; - assign mio_periph_insel_8_we = addr_hit[69] & reg_we & !reg_error; + assign mio_periph_insel_8_we = addr_hit[66] & reg_we & !reg_error; assign mio_periph_insel_8_wd = reg_wdata[5:0]; - assign mio_periph_insel_9_we = addr_hit[70] & reg_we & !reg_error; + assign mio_periph_insel_9_we = addr_hit[67] & reg_we & !reg_error; assign mio_periph_insel_9_wd = reg_wdata[5:0]; - assign mio_periph_insel_10_we = addr_hit[71] & reg_we & !reg_error; + assign mio_periph_insel_10_we = addr_hit[68] & reg_we & !reg_error; assign mio_periph_insel_10_wd = reg_wdata[5:0]; - assign mio_periph_insel_11_we = addr_hit[72] & reg_we & !reg_error; + assign mio_periph_insel_11_we = addr_hit[69] & reg_we & !reg_error; assign mio_periph_insel_11_wd = reg_wdata[5:0]; - assign mio_periph_insel_12_we = addr_hit[73] & reg_we & !reg_error; + assign mio_periph_insel_12_we = addr_hit[70] & reg_we & !reg_error; assign mio_periph_insel_12_wd = reg_wdata[5:0]; - assign mio_periph_insel_13_we = addr_hit[74] & reg_we & !reg_error; + assign mio_periph_insel_13_we = addr_hit[71] & reg_we & !reg_error; assign mio_periph_insel_13_wd = reg_wdata[5:0]; - assign mio_periph_insel_14_we = addr_hit[75] & reg_we & !reg_error; + assign mio_periph_insel_14_we = addr_hit[72] & reg_we & !reg_error; assign mio_periph_insel_14_wd = reg_wdata[5:0]; - assign mio_periph_insel_15_we = addr_hit[76] & reg_we & !reg_error; + assign mio_periph_insel_15_we = addr_hit[73] & reg_we & !reg_error; assign mio_periph_insel_15_wd = reg_wdata[5:0]; - assign mio_periph_insel_16_we = addr_hit[77] & reg_we & !reg_error; + assign mio_periph_insel_16_we = addr_hit[74] & reg_we & !reg_error; assign mio_periph_insel_16_wd = reg_wdata[5:0]; - assign mio_periph_insel_17_we = addr_hit[78] & reg_we & !reg_error; + assign mio_periph_insel_17_we = addr_hit[75] & reg_we & !reg_error; assign mio_periph_insel_17_wd = reg_wdata[5:0]; - assign mio_periph_insel_18_we = addr_hit[79] & reg_we & !reg_error; + assign mio_periph_insel_18_we = addr_hit[76] & reg_we & !reg_error; assign mio_periph_insel_18_wd = reg_wdata[5:0]; - assign mio_periph_insel_19_we = addr_hit[80] & reg_we & !reg_error; + assign mio_periph_insel_19_we = addr_hit[77] & reg_we & !reg_error; assign mio_periph_insel_19_wd = reg_wdata[5:0]; - assign mio_periph_insel_20_we = addr_hit[81] & reg_we & !reg_error; + assign mio_periph_insel_20_we = addr_hit[78] & reg_we & !reg_error; assign mio_periph_insel_20_wd = reg_wdata[5:0]; - assign mio_periph_insel_21_we = addr_hit[82] & reg_we & !reg_error; + assign mio_periph_insel_21_we = addr_hit[79] & reg_we & !reg_error; assign mio_periph_insel_21_wd = reg_wdata[5:0]; - assign mio_periph_insel_22_we = addr_hit[83] & reg_we & !reg_error; + assign mio_periph_insel_22_we = addr_hit[80] & reg_we & !reg_error; assign mio_periph_insel_22_wd = reg_wdata[5:0]; - assign mio_periph_insel_23_we = addr_hit[84] & reg_we & !reg_error; + assign mio_periph_insel_23_we = addr_hit[81] & reg_we & !reg_error; assign mio_periph_insel_23_wd = reg_wdata[5:0]; - assign mio_periph_insel_24_we = addr_hit[85] & reg_we & !reg_error; + assign mio_periph_insel_24_we = addr_hit[82] & reg_we & !reg_error; assign mio_periph_insel_24_wd = reg_wdata[5:0]; - assign mio_periph_insel_25_we = addr_hit[86] & reg_we & !reg_error; + assign mio_periph_insel_25_we = addr_hit[83] & reg_we & !reg_error; assign mio_periph_insel_25_wd = reg_wdata[5:0]; - assign mio_periph_insel_26_we = addr_hit[87] & reg_we & !reg_error; + assign mio_periph_insel_26_we = addr_hit[84] & reg_we & !reg_error; assign mio_periph_insel_26_wd = reg_wdata[5:0]; - assign mio_periph_insel_27_we = addr_hit[88] & reg_we & !reg_error; + assign mio_periph_insel_27_we = addr_hit[85] & reg_we & !reg_error; assign mio_periph_insel_27_wd = reg_wdata[5:0]; - assign mio_periph_insel_28_we = addr_hit[89] & reg_we & !reg_error; + assign mio_periph_insel_28_we = addr_hit[86] & reg_we & !reg_error; assign mio_periph_insel_28_wd = reg_wdata[5:0]; - assign mio_periph_insel_29_we = addr_hit[90] & reg_we & !reg_error; + assign mio_periph_insel_29_we = addr_hit[87] & reg_we & !reg_error; assign mio_periph_insel_29_wd = reg_wdata[5:0]; - assign mio_periph_insel_30_we = addr_hit[91] & reg_we & !reg_error; + assign mio_periph_insel_30_we = addr_hit[88] & reg_we & !reg_error; assign mio_periph_insel_30_wd = reg_wdata[5:0]; - assign mio_periph_insel_31_we = addr_hit[92] & reg_we & !reg_error; + assign mio_periph_insel_31_we = addr_hit[89] & reg_we & !reg_error; assign mio_periph_insel_31_wd = reg_wdata[5:0]; - assign mio_periph_insel_32_we = addr_hit[93] & reg_we & !reg_error; + assign mio_periph_insel_32_we = addr_hit[90] & reg_we & !reg_error; assign mio_periph_insel_32_wd = reg_wdata[5:0]; - assign mio_periph_insel_33_we = addr_hit[94] & reg_we & !reg_error; + assign mio_periph_insel_33_we = addr_hit[91] & reg_we & !reg_error; assign mio_periph_insel_33_wd = reg_wdata[5:0]; - assign mio_periph_insel_34_we = addr_hit[95] & reg_we & !reg_error; + assign mio_periph_insel_34_we = addr_hit[92] & reg_we & !reg_error; assign mio_periph_insel_34_wd = reg_wdata[5:0]; - assign mio_periph_insel_35_we = addr_hit[96] & reg_we & !reg_error; + assign mio_periph_insel_35_we = addr_hit[93] & reg_we & !reg_error; assign mio_periph_insel_35_wd = reg_wdata[5:0]; - assign mio_periph_insel_36_we = addr_hit[97] & reg_we & !reg_error; + assign mio_periph_insel_36_we = addr_hit[94] & reg_we & !reg_error; assign mio_periph_insel_36_wd = reg_wdata[5:0]; - assign mio_periph_insel_37_we = addr_hit[98] & reg_we & !reg_error; + assign mio_periph_insel_37_we = addr_hit[95] & reg_we & !reg_error; assign mio_periph_insel_37_wd = reg_wdata[5:0]; - assign mio_periph_insel_38_we = addr_hit[99] & reg_we & !reg_error; + assign mio_periph_insel_38_we = addr_hit[96] & reg_we & !reg_error; assign mio_periph_insel_38_wd = reg_wdata[5:0]; - assign mio_periph_insel_39_we = addr_hit[100] & reg_we & !reg_error; + assign mio_periph_insel_39_we = addr_hit[97] & reg_we & !reg_error; assign mio_periph_insel_39_wd = reg_wdata[5:0]; - assign mio_periph_insel_40_we = addr_hit[101] & reg_we & !reg_error; + assign mio_periph_insel_40_we = addr_hit[98] & reg_we & !reg_error; assign mio_periph_insel_40_wd = reg_wdata[5:0]; - assign mio_periph_insel_41_we = addr_hit[102] & reg_we & !reg_error; + assign mio_periph_insel_41_we = addr_hit[99] & reg_we & !reg_error; assign mio_periph_insel_41_wd = reg_wdata[5:0]; - assign mio_periph_insel_42_we = addr_hit[103] & reg_we & !reg_error; + assign mio_periph_insel_42_we = addr_hit[100] & reg_we & !reg_error; assign mio_periph_insel_42_wd = reg_wdata[5:0]; - assign mio_periph_insel_43_we = addr_hit[104] & reg_we & !reg_error; + assign mio_periph_insel_43_we = addr_hit[101] & reg_we & !reg_error; assign mio_periph_insel_43_wd = reg_wdata[5:0]; - assign mio_periph_insel_44_we = addr_hit[105] & reg_we & !reg_error; + assign mio_periph_insel_44_we = addr_hit[102] & reg_we & !reg_error; assign mio_periph_insel_44_wd = reg_wdata[5:0]; - assign mio_periph_insel_45_we = addr_hit[106] & reg_we & !reg_error; + assign mio_periph_insel_45_we = addr_hit[103] & reg_we & !reg_error; assign mio_periph_insel_45_wd = reg_wdata[5:0]; - assign mio_periph_insel_46_we = addr_hit[107] & reg_we & !reg_error; + assign mio_periph_insel_46_we = addr_hit[104] & reg_we & !reg_error; assign mio_periph_insel_46_wd = reg_wdata[5:0]; - assign mio_periph_insel_47_we = addr_hit[108] & reg_we & !reg_error; + assign mio_periph_insel_47_we = addr_hit[105] & reg_we & !reg_error; assign mio_periph_insel_47_wd = reg_wdata[5:0]; - assign mio_periph_insel_48_we = addr_hit[109] & reg_we & !reg_error; + assign mio_periph_insel_48_we = addr_hit[106] & reg_we & !reg_error; assign mio_periph_insel_48_wd = reg_wdata[5:0]; - assign mio_periph_insel_49_we = addr_hit[110] & reg_we & !reg_error; + assign mio_periph_insel_49_we = addr_hit[107] & reg_we & !reg_error; assign mio_periph_insel_49_wd = reg_wdata[5:0]; - assign mio_periph_insel_50_we = addr_hit[111] & reg_we & !reg_error; + assign mio_periph_insel_50_we = addr_hit[108] & reg_we & !reg_error; assign mio_periph_insel_50_wd = reg_wdata[5:0]; - assign mio_periph_insel_51_we = addr_hit[112] & reg_we & !reg_error; + assign mio_periph_insel_51_we = addr_hit[109] & reg_we & !reg_error; assign mio_periph_insel_51_wd = reg_wdata[5:0]; - assign mio_periph_insel_52_we = addr_hit[113] & reg_we & !reg_error; + assign mio_periph_insel_52_we = addr_hit[110] & reg_we & !reg_error; assign mio_periph_insel_52_wd = reg_wdata[5:0]; - assign mio_periph_insel_53_we = addr_hit[114] & reg_we & !reg_error; + assign mio_periph_insel_53_we = addr_hit[111] & reg_we & !reg_error; assign mio_periph_insel_53_wd = reg_wdata[5:0]; - assign mio_periph_insel_54_we = addr_hit[115] & reg_we & !reg_error; + assign mio_periph_insel_54_we = addr_hit[112] & reg_we & !reg_error; assign mio_periph_insel_54_wd = reg_wdata[5:0]; - assign mio_periph_insel_55_we = addr_hit[116] & reg_we & !reg_error; + assign mio_periph_insel_55_we = addr_hit[113] & reg_we & !reg_error; assign mio_periph_insel_55_wd = reg_wdata[5:0]; - assign mio_periph_insel_56_we = addr_hit[117] & reg_we & !reg_error; + assign mio_periph_insel_56_we = addr_hit[114] & reg_we & !reg_error; assign mio_periph_insel_56_wd = reg_wdata[5:0]; - assign mio_periph_insel_57_we = addr_hit[118] & reg_we & !reg_error; - - assign mio_periph_insel_57_wd = reg_wdata[5:0]; - assign mio_periph_insel_58_we = addr_hit[119] & reg_we & !reg_error; - - assign mio_periph_insel_58_wd = reg_wdata[5:0]; - assign mio_periph_insel_59_we = addr_hit[120] & reg_we & !reg_error; - - assign mio_periph_insel_59_wd = reg_wdata[5:0]; - assign mio_outsel_regwen_0_we = addr_hit[121] & reg_we & !reg_error; + assign mio_outsel_regwen_0_we = addr_hit[115] & reg_we & !reg_error; assign mio_outsel_regwen_0_wd = reg_wdata[0]; - assign mio_outsel_regwen_1_we = addr_hit[122] & reg_we & !reg_error; + assign mio_outsel_regwen_1_we = addr_hit[116] & reg_we & !reg_error; assign mio_outsel_regwen_1_wd = reg_wdata[0]; - assign mio_outsel_regwen_2_we = addr_hit[123] & reg_we & !reg_error; + assign mio_outsel_regwen_2_we = addr_hit[117] & reg_we & !reg_error; assign mio_outsel_regwen_2_wd = reg_wdata[0]; - assign mio_outsel_regwen_3_we = addr_hit[124] & reg_we & !reg_error; + assign mio_outsel_regwen_3_we = addr_hit[118] & reg_we & !reg_error; assign mio_outsel_regwen_3_wd = reg_wdata[0]; - assign mio_outsel_regwen_4_we = addr_hit[125] & reg_we & !reg_error; + assign mio_outsel_regwen_4_we = addr_hit[119] & reg_we & !reg_error; assign mio_outsel_regwen_4_wd = reg_wdata[0]; - assign mio_outsel_regwen_5_we = addr_hit[126] & reg_we & !reg_error; + assign mio_outsel_regwen_5_we = addr_hit[120] & reg_we & !reg_error; assign mio_outsel_regwen_5_wd = reg_wdata[0]; - assign mio_outsel_regwen_6_we = addr_hit[127] & reg_we & !reg_error; + assign mio_outsel_regwen_6_we = addr_hit[121] & reg_we & !reg_error; assign mio_outsel_regwen_6_wd = reg_wdata[0]; - assign mio_outsel_regwen_7_we = addr_hit[128] & reg_we & !reg_error; + assign mio_outsel_regwen_7_we = addr_hit[122] & reg_we & !reg_error; assign mio_outsel_regwen_7_wd = reg_wdata[0]; - assign mio_outsel_regwen_8_we = addr_hit[129] & reg_we & !reg_error; + assign mio_outsel_regwen_8_we = addr_hit[123] & reg_we & !reg_error; assign mio_outsel_regwen_8_wd = reg_wdata[0]; - assign mio_outsel_regwen_9_we = addr_hit[130] & reg_we & !reg_error; + assign mio_outsel_regwen_9_we = addr_hit[124] & reg_we & !reg_error; assign mio_outsel_regwen_9_wd = reg_wdata[0]; - assign mio_outsel_regwen_10_we = addr_hit[131] & reg_we & !reg_error; + assign mio_outsel_regwen_10_we = addr_hit[125] & reg_we & !reg_error; assign mio_outsel_regwen_10_wd = reg_wdata[0]; - assign mio_outsel_regwen_11_we = addr_hit[132] & reg_we & !reg_error; + assign mio_outsel_regwen_11_we = addr_hit[126] & reg_we & !reg_error; assign mio_outsel_regwen_11_wd = reg_wdata[0]; - assign mio_outsel_regwen_12_we = addr_hit[133] & reg_we & !reg_error; + assign mio_outsel_regwen_12_we = addr_hit[127] & reg_we & !reg_error; assign mio_outsel_regwen_12_wd = reg_wdata[0]; - assign mio_outsel_regwen_13_we = addr_hit[134] & reg_we & !reg_error; + assign mio_outsel_regwen_13_we = addr_hit[128] & reg_we & !reg_error; assign mio_outsel_regwen_13_wd = reg_wdata[0]; - assign mio_outsel_regwen_14_we = addr_hit[135] & reg_we & !reg_error; + assign mio_outsel_regwen_14_we = addr_hit[129] & reg_we & !reg_error; assign mio_outsel_regwen_14_wd = reg_wdata[0]; - assign mio_outsel_regwen_15_we = addr_hit[136] & reg_we & !reg_error; + assign mio_outsel_regwen_15_we = addr_hit[130] & reg_we & !reg_error; assign mio_outsel_regwen_15_wd = reg_wdata[0]; - assign mio_outsel_regwen_16_we = addr_hit[137] & reg_we & !reg_error; + assign mio_outsel_regwen_16_we = addr_hit[131] & reg_we & !reg_error; assign mio_outsel_regwen_16_wd = reg_wdata[0]; - assign mio_outsel_regwen_17_we = addr_hit[138] & reg_we & !reg_error; + assign mio_outsel_regwen_17_we = addr_hit[132] & reg_we & !reg_error; assign mio_outsel_regwen_17_wd = reg_wdata[0]; - assign mio_outsel_regwen_18_we = addr_hit[139] & reg_we & !reg_error; + assign mio_outsel_regwen_18_we = addr_hit[133] & reg_we & !reg_error; assign mio_outsel_regwen_18_wd = reg_wdata[0]; - assign mio_outsel_regwen_19_we = addr_hit[140] & reg_we & !reg_error; + assign mio_outsel_regwen_19_we = addr_hit[134] & reg_we & !reg_error; assign mio_outsel_regwen_19_wd = reg_wdata[0]; - assign mio_outsel_regwen_20_we = addr_hit[141] & reg_we & !reg_error; + assign mio_outsel_regwen_20_we = addr_hit[135] & reg_we & !reg_error; assign mio_outsel_regwen_20_wd = reg_wdata[0]; - assign mio_outsel_regwen_21_we = addr_hit[142] & reg_we & !reg_error; + assign mio_outsel_regwen_21_we = addr_hit[136] & reg_we & !reg_error; assign mio_outsel_regwen_21_wd = reg_wdata[0]; - assign mio_outsel_regwen_22_we = addr_hit[143] & reg_we & !reg_error; + assign mio_outsel_regwen_22_we = addr_hit[137] & reg_we & !reg_error; assign mio_outsel_regwen_22_wd = reg_wdata[0]; - assign mio_outsel_regwen_23_we = addr_hit[144] & reg_we & !reg_error; + assign mio_outsel_regwen_23_we = addr_hit[138] & reg_we & !reg_error; assign mio_outsel_regwen_23_wd = reg_wdata[0]; - assign mio_outsel_regwen_24_we = addr_hit[145] & reg_we & !reg_error; + assign mio_outsel_regwen_24_we = addr_hit[139] & reg_we & !reg_error; assign mio_outsel_regwen_24_wd = reg_wdata[0]; - assign mio_outsel_regwen_25_we = addr_hit[146] & reg_we & !reg_error; + assign mio_outsel_regwen_25_we = addr_hit[140] & reg_we & !reg_error; assign mio_outsel_regwen_25_wd = reg_wdata[0]; - assign mio_outsel_regwen_26_we = addr_hit[147] & reg_we & !reg_error; + assign mio_outsel_regwen_26_we = addr_hit[141] & reg_we & !reg_error; assign mio_outsel_regwen_26_wd = reg_wdata[0]; - assign mio_outsel_regwen_27_we = addr_hit[148] & reg_we & !reg_error; + assign mio_outsel_regwen_27_we = addr_hit[142] & reg_we & !reg_error; assign mio_outsel_regwen_27_wd = reg_wdata[0]; - assign mio_outsel_regwen_28_we = addr_hit[149] & reg_we & !reg_error; + assign mio_outsel_regwen_28_we = addr_hit[143] & reg_we & !reg_error; assign mio_outsel_regwen_28_wd = reg_wdata[0]; - assign mio_outsel_regwen_29_we = addr_hit[150] & reg_we & !reg_error; + assign mio_outsel_regwen_29_we = addr_hit[144] & reg_we & !reg_error; assign mio_outsel_regwen_29_wd = reg_wdata[0]; - assign mio_outsel_regwen_30_we = addr_hit[151] & reg_we & !reg_error; + assign mio_outsel_regwen_30_we = addr_hit[145] & reg_we & !reg_error; assign mio_outsel_regwen_30_wd = reg_wdata[0]; - assign mio_outsel_regwen_31_we = addr_hit[152] & reg_we & !reg_error; + assign mio_outsel_regwen_31_we = addr_hit[146] & reg_we & !reg_error; assign mio_outsel_regwen_31_wd = reg_wdata[0]; - assign mio_outsel_regwen_32_we = addr_hit[153] & reg_we & !reg_error; + assign mio_outsel_regwen_32_we = addr_hit[147] & reg_we & !reg_error; assign mio_outsel_regwen_32_wd = reg_wdata[0]; - assign mio_outsel_regwen_33_we = addr_hit[154] & reg_we & !reg_error; + assign mio_outsel_regwen_33_we = addr_hit[148] & reg_we & !reg_error; assign mio_outsel_regwen_33_wd = reg_wdata[0]; - assign mio_outsel_regwen_34_we = addr_hit[155] & reg_we & !reg_error; + assign mio_outsel_regwen_34_we = addr_hit[149] & reg_we & !reg_error; assign mio_outsel_regwen_34_wd = reg_wdata[0]; - assign mio_outsel_regwen_35_we = addr_hit[156] & reg_we & !reg_error; + assign mio_outsel_regwen_35_we = addr_hit[150] & reg_we & !reg_error; assign mio_outsel_regwen_35_wd = reg_wdata[0]; - assign mio_outsel_regwen_36_we = addr_hit[157] & reg_we & !reg_error; + assign mio_outsel_regwen_36_we = addr_hit[151] & reg_we & !reg_error; assign mio_outsel_regwen_36_wd = reg_wdata[0]; - assign mio_outsel_regwen_37_we = addr_hit[158] & reg_we & !reg_error; + assign mio_outsel_regwen_37_we = addr_hit[152] & reg_we & !reg_error; assign mio_outsel_regwen_37_wd = reg_wdata[0]; - assign mio_outsel_regwen_38_we = addr_hit[159] & reg_we & !reg_error; + assign mio_outsel_regwen_38_we = addr_hit[153] & reg_we & !reg_error; assign mio_outsel_regwen_38_wd = reg_wdata[0]; - assign mio_outsel_regwen_39_we = addr_hit[160] & reg_we & !reg_error; + assign mio_outsel_regwen_39_we = addr_hit[154] & reg_we & !reg_error; assign mio_outsel_regwen_39_wd = reg_wdata[0]; - assign mio_outsel_regwen_40_we = addr_hit[161] & reg_we & !reg_error; + assign mio_outsel_regwen_40_we = addr_hit[155] & reg_we & !reg_error; assign mio_outsel_regwen_40_wd = reg_wdata[0]; - assign mio_outsel_regwen_41_we = addr_hit[162] & reg_we & !reg_error; + assign mio_outsel_regwen_41_we = addr_hit[156] & reg_we & !reg_error; assign mio_outsel_regwen_41_wd = reg_wdata[0]; - assign mio_outsel_regwen_42_we = addr_hit[163] & reg_we & !reg_error; + assign mio_outsel_regwen_42_we = addr_hit[157] & reg_we & !reg_error; assign mio_outsel_regwen_42_wd = reg_wdata[0]; - assign mio_outsel_regwen_43_we = addr_hit[164] & reg_we & !reg_error; + assign mio_outsel_regwen_43_we = addr_hit[158] & reg_we & !reg_error; assign mio_outsel_regwen_43_wd = reg_wdata[0]; - assign mio_outsel_regwen_44_we = addr_hit[165] & reg_we & !reg_error; + assign mio_outsel_regwen_44_we = addr_hit[159] & reg_we & !reg_error; assign mio_outsel_regwen_44_wd = reg_wdata[0]; - assign mio_outsel_regwen_45_we = addr_hit[166] & reg_we & !reg_error; + assign mio_outsel_regwen_45_we = addr_hit[160] & reg_we & !reg_error; assign mio_outsel_regwen_45_wd = reg_wdata[0]; - assign mio_outsel_regwen_46_we = addr_hit[167] & reg_we & !reg_error; + assign mio_outsel_regwen_46_we = addr_hit[161] & reg_we & !reg_error; assign mio_outsel_regwen_46_wd = reg_wdata[0]; - assign mio_outsel_0_we = addr_hit[168] & reg_we & !reg_error; + assign mio_outsel_0_we = addr_hit[162] & reg_we & !reg_error; assign mio_outsel_0_wd = reg_wdata[6:0]; - assign mio_outsel_1_we = addr_hit[169] & reg_we & !reg_error; + assign mio_outsel_1_we = addr_hit[163] & reg_we & !reg_error; assign mio_outsel_1_wd = reg_wdata[6:0]; - assign mio_outsel_2_we = addr_hit[170] & reg_we & !reg_error; + assign mio_outsel_2_we = addr_hit[164] & reg_we & !reg_error; assign mio_outsel_2_wd = reg_wdata[6:0]; - assign mio_outsel_3_we = addr_hit[171] & reg_we & !reg_error; + assign mio_outsel_3_we = addr_hit[165] & reg_we & !reg_error; assign mio_outsel_3_wd = reg_wdata[6:0]; - assign mio_outsel_4_we = addr_hit[172] & reg_we & !reg_error; + assign mio_outsel_4_we = addr_hit[166] & reg_we & !reg_error; assign mio_outsel_4_wd = reg_wdata[6:0]; - assign mio_outsel_5_we = addr_hit[173] & reg_we & !reg_error; + assign mio_outsel_5_we = addr_hit[167] & reg_we & !reg_error; assign mio_outsel_5_wd = reg_wdata[6:0]; - assign mio_outsel_6_we = addr_hit[174] & reg_we & !reg_error; + assign mio_outsel_6_we = addr_hit[168] & reg_we & !reg_error; assign mio_outsel_6_wd = reg_wdata[6:0]; - assign mio_outsel_7_we = addr_hit[175] & reg_we & !reg_error; + assign mio_outsel_7_we = addr_hit[169] & reg_we & !reg_error; assign mio_outsel_7_wd = reg_wdata[6:0]; - assign mio_outsel_8_we = addr_hit[176] & reg_we & !reg_error; + assign mio_outsel_8_we = addr_hit[170] & reg_we & !reg_error; assign mio_outsel_8_wd = reg_wdata[6:0]; - assign mio_outsel_9_we = addr_hit[177] & reg_we & !reg_error; + assign mio_outsel_9_we = addr_hit[171] & reg_we & !reg_error; assign mio_outsel_9_wd = reg_wdata[6:0]; - assign mio_outsel_10_we = addr_hit[178] & reg_we & !reg_error; + assign mio_outsel_10_we = addr_hit[172] & reg_we & !reg_error; assign mio_outsel_10_wd = reg_wdata[6:0]; - assign mio_outsel_11_we = addr_hit[179] & reg_we & !reg_error; + assign mio_outsel_11_we = addr_hit[173] & reg_we & !reg_error; assign mio_outsel_11_wd = reg_wdata[6:0]; - assign mio_outsel_12_we = addr_hit[180] & reg_we & !reg_error; + assign mio_outsel_12_we = addr_hit[174] & reg_we & !reg_error; assign mio_outsel_12_wd = reg_wdata[6:0]; - assign mio_outsel_13_we = addr_hit[181] & reg_we & !reg_error; + assign mio_outsel_13_we = addr_hit[175] & reg_we & !reg_error; assign mio_outsel_13_wd = reg_wdata[6:0]; - assign mio_outsel_14_we = addr_hit[182] & reg_we & !reg_error; + assign mio_outsel_14_we = addr_hit[176] & reg_we & !reg_error; assign mio_outsel_14_wd = reg_wdata[6:0]; - assign mio_outsel_15_we = addr_hit[183] & reg_we & !reg_error; + assign mio_outsel_15_we = addr_hit[177] & reg_we & !reg_error; assign mio_outsel_15_wd = reg_wdata[6:0]; - assign mio_outsel_16_we = addr_hit[184] & reg_we & !reg_error; + assign mio_outsel_16_we = addr_hit[178] & reg_we & !reg_error; assign mio_outsel_16_wd = reg_wdata[6:0]; - assign mio_outsel_17_we = addr_hit[185] & reg_we & !reg_error; + assign mio_outsel_17_we = addr_hit[179] & reg_we & !reg_error; assign mio_outsel_17_wd = reg_wdata[6:0]; - assign mio_outsel_18_we = addr_hit[186] & reg_we & !reg_error; + assign mio_outsel_18_we = addr_hit[180] & reg_we & !reg_error; assign mio_outsel_18_wd = reg_wdata[6:0]; - assign mio_outsel_19_we = addr_hit[187] & reg_we & !reg_error; + assign mio_outsel_19_we = addr_hit[181] & reg_we & !reg_error; assign mio_outsel_19_wd = reg_wdata[6:0]; - assign mio_outsel_20_we = addr_hit[188] & reg_we & !reg_error; + assign mio_outsel_20_we = addr_hit[182] & reg_we & !reg_error; assign mio_outsel_20_wd = reg_wdata[6:0]; - assign mio_outsel_21_we = addr_hit[189] & reg_we & !reg_error; + assign mio_outsel_21_we = addr_hit[183] & reg_we & !reg_error; assign mio_outsel_21_wd = reg_wdata[6:0]; - assign mio_outsel_22_we = addr_hit[190] & reg_we & !reg_error; + assign mio_outsel_22_we = addr_hit[184] & reg_we & !reg_error; assign mio_outsel_22_wd = reg_wdata[6:0]; - assign mio_outsel_23_we = addr_hit[191] & reg_we & !reg_error; + assign mio_outsel_23_we = addr_hit[185] & reg_we & !reg_error; assign mio_outsel_23_wd = reg_wdata[6:0]; - assign mio_outsel_24_we = addr_hit[192] & reg_we & !reg_error; + assign mio_outsel_24_we = addr_hit[186] & reg_we & !reg_error; assign mio_outsel_24_wd = reg_wdata[6:0]; - assign mio_outsel_25_we = addr_hit[193] & reg_we & !reg_error; + assign mio_outsel_25_we = addr_hit[187] & reg_we & !reg_error; assign mio_outsel_25_wd = reg_wdata[6:0]; - assign mio_outsel_26_we = addr_hit[194] & reg_we & !reg_error; + assign mio_outsel_26_we = addr_hit[188] & reg_we & !reg_error; assign mio_outsel_26_wd = reg_wdata[6:0]; - assign mio_outsel_27_we = addr_hit[195] & reg_we & !reg_error; + assign mio_outsel_27_we = addr_hit[189] & reg_we & !reg_error; assign mio_outsel_27_wd = reg_wdata[6:0]; - assign mio_outsel_28_we = addr_hit[196] & reg_we & !reg_error; + assign mio_outsel_28_we = addr_hit[190] & reg_we & !reg_error; assign mio_outsel_28_wd = reg_wdata[6:0]; - assign mio_outsel_29_we = addr_hit[197] & reg_we & !reg_error; + assign mio_outsel_29_we = addr_hit[191] & reg_we & !reg_error; assign mio_outsel_29_wd = reg_wdata[6:0]; - assign mio_outsel_30_we = addr_hit[198] & reg_we & !reg_error; + assign mio_outsel_30_we = addr_hit[192] & reg_we & !reg_error; assign mio_outsel_30_wd = reg_wdata[6:0]; - assign mio_outsel_31_we = addr_hit[199] & reg_we & !reg_error; + assign mio_outsel_31_we = addr_hit[193] & reg_we & !reg_error; assign mio_outsel_31_wd = reg_wdata[6:0]; - assign mio_outsel_32_we = addr_hit[200] & reg_we & !reg_error; + assign mio_outsel_32_we = addr_hit[194] & reg_we & !reg_error; assign mio_outsel_32_wd = reg_wdata[6:0]; - assign mio_outsel_33_we = addr_hit[201] & reg_we & !reg_error; + assign mio_outsel_33_we = addr_hit[195] & reg_we & !reg_error; assign mio_outsel_33_wd = reg_wdata[6:0]; - assign mio_outsel_34_we = addr_hit[202] & reg_we & !reg_error; + assign mio_outsel_34_we = addr_hit[196] & reg_we & !reg_error; assign mio_outsel_34_wd = reg_wdata[6:0]; - assign mio_outsel_35_we = addr_hit[203] & reg_we & !reg_error; + assign mio_outsel_35_we = addr_hit[197] & reg_we & !reg_error; assign mio_outsel_35_wd = reg_wdata[6:0]; - assign mio_outsel_36_we = addr_hit[204] & reg_we & !reg_error; + assign mio_outsel_36_we = addr_hit[198] & reg_we & !reg_error; assign mio_outsel_36_wd = reg_wdata[6:0]; - assign mio_outsel_37_we = addr_hit[205] & reg_we & !reg_error; + assign mio_outsel_37_we = addr_hit[199] & reg_we & !reg_error; assign mio_outsel_37_wd = reg_wdata[6:0]; - assign mio_outsel_38_we = addr_hit[206] & reg_we & !reg_error; + assign mio_outsel_38_we = addr_hit[200] & reg_we & !reg_error; assign mio_outsel_38_wd = reg_wdata[6:0]; - assign mio_outsel_39_we = addr_hit[207] & reg_we & !reg_error; + assign mio_outsel_39_we = addr_hit[201] & reg_we & !reg_error; assign mio_outsel_39_wd = reg_wdata[6:0]; - assign mio_outsel_40_we = addr_hit[208] & reg_we & !reg_error; + assign mio_outsel_40_we = addr_hit[202] & reg_we & !reg_error; assign mio_outsel_40_wd = reg_wdata[6:0]; - assign mio_outsel_41_we = addr_hit[209] & reg_we & !reg_error; + assign mio_outsel_41_we = addr_hit[203] & reg_we & !reg_error; assign mio_outsel_41_wd = reg_wdata[6:0]; - assign mio_outsel_42_we = addr_hit[210] & reg_we & !reg_error; + assign mio_outsel_42_we = addr_hit[204] & reg_we & !reg_error; assign mio_outsel_42_wd = reg_wdata[6:0]; - assign mio_outsel_43_we = addr_hit[211] & reg_we & !reg_error; + assign mio_outsel_43_we = addr_hit[205] & reg_we & !reg_error; assign mio_outsel_43_wd = reg_wdata[6:0]; - assign mio_outsel_44_we = addr_hit[212] & reg_we & !reg_error; + assign mio_outsel_44_we = addr_hit[206] & reg_we & !reg_error; assign mio_outsel_44_wd = reg_wdata[6:0]; - assign mio_outsel_45_we = addr_hit[213] & reg_we & !reg_error; + assign mio_outsel_45_we = addr_hit[207] & reg_we & !reg_error; assign mio_outsel_45_wd = reg_wdata[6:0]; - assign mio_outsel_46_we = addr_hit[214] & reg_we & !reg_error; + assign mio_outsel_46_we = addr_hit[208] & reg_we & !reg_error; assign mio_outsel_46_wd = reg_wdata[6:0]; - assign mio_pad_attr_regwen_0_we = addr_hit[215] & reg_we & !reg_error; + assign mio_pad_attr_regwen_0_we = addr_hit[209] & reg_we & !reg_error; assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_1_we = addr_hit[216] & reg_we & !reg_error; + assign mio_pad_attr_regwen_1_we = addr_hit[210] & reg_we & !reg_error; assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_2_we = addr_hit[217] & reg_we & !reg_error; + assign mio_pad_attr_regwen_2_we = addr_hit[211] & reg_we & !reg_error; assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_3_we = addr_hit[218] & reg_we & !reg_error; + assign mio_pad_attr_regwen_3_we = addr_hit[212] & reg_we & !reg_error; assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_4_we = addr_hit[219] & reg_we & !reg_error; + assign mio_pad_attr_regwen_4_we = addr_hit[213] & reg_we & !reg_error; assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_5_we = addr_hit[220] & reg_we & !reg_error; + assign mio_pad_attr_regwen_5_we = addr_hit[214] & reg_we & !reg_error; assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_6_we = addr_hit[221] & reg_we & !reg_error; + assign mio_pad_attr_regwen_6_we = addr_hit[215] & reg_we & !reg_error; assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_7_we = addr_hit[222] & reg_we & !reg_error; + assign mio_pad_attr_regwen_7_we = addr_hit[216] & reg_we & !reg_error; assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_8_we = addr_hit[223] & reg_we & !reg_error; + assign mio_pad_attr_regwen_8_we = addr_hit[217] & reg_we & !reg_error; assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_9_we = addr_hit[224] & reg_we & !reg_error; + assign mio_pad_attr_regwen_9_we = addr_hit[218] & reg_we & !reg_error; assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_10_we = addr_hit[225] & reg_we & !reg_error; + assign mio_pad_attr_regwen_10_we = addr_hit[219] & reg_we & !reg_error; assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_11_we = addr_hit[226] & reg_we & !reg_error; + assign mio_pad_attr_regwen_11_we = addr_hit[220] & reg_we & !reg_error; assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_12_we = addr_hit[227] & reg_we & !reg_error; + assign mio_pad_attr_regwen_12_we = addr_hit[221] & reg_we & !reg_error; assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_13_we = addr_hit[228] & reg_we & !reg_error; + assign mio_pad_attr_regwen_13_we = addr_hit[222] & reg_we & !reg_error; assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_14_we = addr_hit[229] & reg_we & !reg_error; + assign mio_pad_attr_regwen_14_we = addr_hit[223] & reg_we & !reg_error; assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_15_we = addr_hit[230] & reg_we & !reg_error; + assign mio_pad_attr_regwen_15_we = addr_hit[224] & reg_we & !reg_error; assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_16_we = addr_hit[231] & reg_we & !reg_error; + assign mio_pad_attr_regwen_16_we = addr_hit[225] & reg_we & !reg_error; assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_17_we = addr_hit[232] & reg_we & !reg_error; + assign mio_pad_attr_regwen_17_we = addr_hit[226] & reg_we & !reg_error; assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_18_we = addr_hit[233] & reg_we & !reg_error; + assign mio_pad_attr_regwen_18_we = addr_hit[227] & reg_we & !reg_error; assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_19_we = addr_hit[234] & reg_we & !reg_error; + assign mio_pad_attr_regwen_19_we = addr_hit[228] & reg_we & !reg_error; assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_20_we = addr_hit[235] & reg_we & !reg_error; + assign mio_pad_attr_regwen_20_we = addr_hit[229] & reg_we & !reg_error; assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_21_we = addr_hit[236] & reg_we & !reg_error; + assign mio_pad_attr_regwen_21_we = addr_hit[230] & reg_we & !reg_error; assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_22_we = addr_hit[237] & reg_we & !reg_error; + assign mio_pad_attr_regwen_22_we = addr_hit[231] & reg_we & !reg_error; assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_23_we = addr_hit[238] & reg_we & !reg_error; + assign mio_pad_attr_regwen_23_we = addr_hit[232] & reg_we & !reg_error; assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_24_we = addr_hit[239] & reg_we & !reg_error; + assign mio_pad_attr_regwen_24_we = addr_hit[233] & reg_we & !reg_error; assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_25_we = addr_hit[240] & reg_we & !reg_error; + assign mio_pad_attr_regwen_25_we = addr_hit[234] & reg_we & !reg_error; assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_26_we = addr_hit[241] & reg_we & !reg_error; + assign mio_pad_attr_regwen_26_we = addr_hit[235] & reg_we & !reg_error; assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_27_we = addr_hit[242] & reg_we & !reg_error; + assign mio_pad_attr_regwen_27_we = addr_hit[236] & reg_we & !reg_error; assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_28_we = addr_hit[243] & reg_we & !reg_error; + assign mio_pad_attr_regwen_28_we = addr_hit[237] & reg_we & !reg_error; assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_29_we = addr_hit[244] & reg_we & !reg_error; + assign mio_pad_attr_regwen_29_we = addr_hit[238] & reg_we & !reg_error; assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_30_we = addr_hit[245] & reg_we & !reg_error; + assign mio_pad_attr_regwen_30_we = addr_hit[239] & reg_we & !reg_error; assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_31_we = addr_hit[246] & reg_we & !reg_error; + assign mio_pad_attr_regwen_31_we = addr_hit[240] & reg_we & !reg_error; assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_32_we = addr_hit[247] & reg_we & !reg_error; + assign mio_pad_attr_regwen_32_we = addr_hit[241] & reg_we & !reg_error; assign mio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_33_we = addr_hit[248] & reg_we & !reg_error; + assign mio_pad_attr_regwen_33_we = addr_hit[242] & reg_we & !reg_error; assign mio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_34_we = addr_hit[249] & reg_we & !reg_error; + assign mio_pad_attr_regwen_34_we = addr_hit[243] & reg_we & !reg_error; assign mio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_35_we = addr_hit[250] & reg_we & !reg_error; + assign mio_pad_attr_regwen_35_we = addr_hit[244] & reg_we & !reg_error; assign mio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_36_we = addr_hit[251] & reg_we & !reg_error; + assign mio_pad_attr_regwen_36_we = addr_hit[245] & reg_we & !reg_error; assign mio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_37_we = addr_hit[252] & reg_we & !reg_error; + assign mio_pad_attr_regwen_37_we = addr_hit[246] & reg_we & !reg_error; assign mio_pad_attr_regwen_37_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_38_we = addr_hit[253] & reg_we & !reg_error; + assign mio_pad_attr_regwen_38_we = addr_hit[247] & reg_we & !reg_error; assign mio_pad_attr_regwen_38_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_39_we = addr_hit[254] & reg_we & !reg_error; + assign mio_pad_attr_regwen_39_we = addr_hit[248] & reg_we & !reg_error; assign mio_pad_attr_regwen_39_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_40_we = addr_hit[255] & reg_we & !reg_error; + assign mio_pad_attr_regwen_40_we = addr_hit[249] & reg_we & !reg_error; assign mio_pad_attr_regwen_40_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_41_we = addr_hit[256] & reg_we & !reg_error; + assign mio_pad_attr_regwen_41_we = addr_hit[250] & reg_we & !reg_error; assign mio_pad_attr_regwen_41_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_42_we = addr_hit[257] & reg_we & !reg_error; + assign mio_pad_attr_regwen_42_we = addr_hit[251] & reg_we & !reg_error; assign mio_pad_attr_regwen_42_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_43_we = addr_hit[258] & reg_we & !reg_error; + assign mio_pad_attr_regwen_43_we = addr_hit[252] & reg_we & !reg_error; assign mio_pad_attr_regwen_43_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_44_we = addr_hit[259] & reg_we & !reg_error; + assign mio_pad_attr_regwen_44_we = addr_hit[253] & reg_we & !reg_error; assign mio_pad_attr_regwen_44_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_45_we = addr_hit[260] & reg_we & !reg_error; + assign mio_pad_attr_regwen_45_we = addr_hit[254] & reg_we & !reg_error; assign mio_pad_attr_regwen_45_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_46_we = addr_hit[261] & reg_we & !reg_error; + assign mio_pad_attr_regwen_46_we = addr_hit[255] & reg_we & !reg_error; assign mio_pad_attr_regwen_46_wd = reg_wdata[0]; - assign mio_pad_attr_0_re = addr_hit[262] & reg_re & !reg_error; - assign mio_pad_attr_0_we = addr_hit[262] & reg_we & !reg_error; + assign mio_pad_attr_0_re = addr_hit[256] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[256] & reg_we & !reg_error; assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -34696,8 +34465,8 @@ module pinmux_reg_top ( assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign mio_pad_attr_1_re = addr_hit[263] & reg_re & !reg_error; - assign mio_pad_attr_1_we = addr_hit[263] & reg_we & !reg_error; + assign mio_pad_attr_1_re = addr_hit[257] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[257] & reg_we & !reg_error; assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -34718,8 +34487,8 @@ module pinmux_reg_top ( assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign mio_pad_attr_2_re = addr_hit[264] & reg_re & !reg_error; - assign mio_pad_attr_2_we = addr_hit[264] & reg_we & !reg_error; + assign mio_pad_attr_2_re = addr_hit[258] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[258] & reg_we & !reg_error; assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -34740,8 +34509,8 @@ module pinmux_reg_top ( assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign mio_pad_attr_3_re = addr_hit[265] & reg_re & !reg_error; - assign mio_pad_attr_3_we = addr_hit[265] & reg_we & !reg_error; + assign mio_pad_attr_3_re = addr_hit[259] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[259] & reg_we & !reg_error; assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -34762,8 +34531,8 @@ module pinmux_reg_top ( assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign mio_pad_attr_4_re = addr_hit[266] & reg_re & !reg_error; - assign mio_pad_attr_4_we = addr_hit[266] & reg_we & !reg_error; + assign mio_pad_attr_4_re = addr_hit[260] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[260] & reg_we & !reg_error; assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -34784,8 +34553,8 @@ module pinmux_reg_top ( assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign mio_pad_attr_5_re = addr_hit[267] & reg_re & !reg_error; - assign mio_pad_attr_5_we = addr_hit[267] & reg_we & !reg_error; + assign mio_pad_attr_5_re = addr_hit[261] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[261] & reg_we & !reg_error; assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -34806,8 +34575,8 @@ module pinmux_reg_top ( assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign mio_pad_attr_6_re = addr_hit[268] & reg_re & !reg_error; - assign mio_pad_attr_6_we = addr_hit[268] & reg_we & !reg_error; + assign mio_pad_attr_6_re = addr_hit[262] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[262] & reg_we & !reg_error; assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -34828,8 +34597,8 @@ module pinmux_reg_top ( assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign mio_pad_attr_7_re = addr_hit[269] & reg_re & !reg_error; - assign mio_pad_attr_7_we = addr_hit[269] & reg_we & !reg_error; + assign mio_pad_attr_7_re = addr_hit[263] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[263] & reg_we & !reg_error; assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -34850,8 +34619,8 @@ module pinmux_reg_top ( assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign mio_pad_attr_8_re = addr_hit[270] & reg_re & !reg_error; - assign mio_pad_attr_8_we = addr_hit[270] & reg_we & !reg_error; + assign mio_pad_attr_8_re = addr_hit[264] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[264] & reg_we & !reg_error; assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -34872,8 +34641,8 @@ module pinmux_reg_top ( assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign mio_pad_attr_9_re = addr_hit[271] & reg_re & !reg_error; - assign mio_pad_attr_9_we = addr_hit[271] & reg_we & !reg_error; + assign mio_pad_attr_9_re = addr_hit[265] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[265] & reg_we & !reg_error; assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -34894,8 +34663,8 @@ module pinmux_reg_top ( assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign mio_pad_attr_10_re = addr_hit[272] & reg_re & !reg_error; - assign mio_pad_attr_10_we = addr_hit[272] & reg_we & !reg_error; + assign mio_pad_attr_10_re = addr_hit[266] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[266] & reg_we & !reg_error; assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -34916,8 +34685,8 @@ module pinmux_reg_top ( assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign mio_pad_attr_11_re = addr_hit[273] & reg_re & !reg_error; - assign mio_pad_attr_11_we = addr_hit[273] & reg_we & !reg_error; + assign mio_pad_attr_11_re = addr_hit[267] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[267] & reg_we & !reg_error; assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -34938,8 +34707,8 @@ module pinmux_reg_top ( assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign mio_pad_attr_12_re = addr_hit[274] & reg_re & !reg_error; - assign mio_pad_attr_12_we = addr_hit[274] & reg_we & !reg_error; + assign mio_pad_attr_12_re = addr_hit[268] & reg_re & !reg_error; + assign mio_pad_attr_12_we = addr_hit[268] & reg_we & !reg_error; assign mio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -34960,8 +34729,8 @@ module pinmux_reg_top ( assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign mio_pad_attr_13_re = addr_hit[275] & reg_re & !reg_error; - assign mio_pad_attr_13_we = addr_hit[275] & reg_we & !reg_error; + assign mio_pad_attr_13_re = addr_hit[269] & reg_re & !reg_error; + assign mio_pad_attr_13_we = addr_hit[269] & reg_we & !reg_error; assign mio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -34982,8 +34751,8 @@ module pinmux_reg_top ( assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_attr_14_re = addr_hit[276] & reg_re & !reg_error; - assign mio_pad_attr_14_we = addr_hit[276] & reg_we & !reg_error; + assign mio_pad_attr_14_re = addr_hit[270] & reg_re & !reg_error; + assign mio_pad_attr_14_we = addr_hit[270] & reg_we & !reg_error; assign mio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -35004,8 +34773,8 @@ module pinmux_reg_top ( assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign mio_pad_attr_15_re = addr_hit[277] & reg_re & !reg_error; - assign mio_pad_attr_15_we = addr_hit[277] & reg_we & !reg_error; + assign mio_pad_attr_15_re = addr_hit[271] & reg_re & !reg_error; + assign mio_pad_attr_15_we = addr_hit[271] & reg_we & !reg_error; assign mio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -35026,8 +34795,8 @@ module pinmux_reg_top ( assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_attr_16_re = addr_hit[278] & reg_re & !reg_error; - assign mio_pad_attr_16_we = addr_hit[278] & reg_we & !reg_error; + assign mio_pad_attr_16_re = addr_hit[272] & reg_re & !reg_error; + assign mio_pad_attr_16_we = addr_hit[272] & reg_we & !reg_error; assign mio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -35048,8 +34817,8 @@ module pinmux_reg_top ( assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign mio_pad_attr_17_re = addr_hit[279] & reg_re & !reg_error; - assign mio_pad_attr_17_we = addr_hit[279] & reg_we & !reg_error; + assign mio_pad_attr_17_re = addr_hit[273] & reg_re & !reg_error; + assign mio_pad_attr_17_we = addr_hit[273] & reg_we & !reg_error; assign mio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -35070,8 +34839,8 @@ module pinmux_reg_top ( assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign mio_pad_attr_18_re = addr_hit[280] & reg_re & !reg_error; - assign mio_pad_attr_18_we = addr_hit[280] & reg_we & !reg_error; + assign mio_pad_attr_18_re = addr_hit[274] & reg_re & !reg_error; + assign mio_pad_attr_18_we = addr_hit[274] & reg_we & !reg_error; assign mio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -35092,8 +34861,8 @@ module pinmux_reg_top ( assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign mio_pad_attr_19_re = addr_hit[281] & reg_re & !reg_error; - assign mio_pad_attr_19_we = addr_hit[281] & reg_we & !reg_error; + assign mio_pad_attr_19_re = addr_hit[275] & reg_re & !reg_error; + assign mio_pad_attr_19_we = addr_hit[275] & reg_we & !reg_error; assign mio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -35114,8 +34883,8 @@ module pinmux_reg_top ( assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign mio_pad_attr_20_re = addr_hit[282] & reg_re & !reg_error; - assign mio_pad_attr_20_we = addr_hit[282] & reg_we & !reg_error; + assign mio_pad_attr_20_re = addr_hit[276] & reg_re & !reg_error; + assign mio_pad_attr_20_we = addr_hit[276] & reg_we & !reg_error; assign mio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -35136,8 +34905,8 @@ module pinmux_reg_top ( assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign mio_pad_attr_21_re = addr_hit[283] & reg_re & !reg_error; - assign mio_pad_attr_21_we = addr_hit[283] & reg_we & !reg_error; + assign mio_pad_attr_21_re = addr_hit[277] & reg_re & !reg_error; + assign mio_pad_attr_21_we = addr_hit[277] & reg_we & !reg_error; assign mio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -35158,8 +34927,8 @@ module pinmux_reg_top ( assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign mio_pad_attr_22_re = addr_hit[284] & reg_re & !reg_error; - assign mio_pad_attr_22_we = addr_hit[284] & reg_we & !reg_error; + assign mio_pad_attr_22_re = addr_hit[278] & reg_re & !reg_error; + assign mio_pad_attr_22_we = addr_hit[278] & reg_we & !reg_error; assign mio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -35180,8 +34949,8 @@ module pinmux_reg_top ( assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign mio_pad_attr_23_re = addr_hit[285] & reg_re & !reg_error; - assign mio_pad_attr_23_we = addr_hit[285] & reg_we & !reg_error; + assign mio_pad_attr_23_re = addr_hit[279] & reg_re & !reg_error; + assign mio_pad_attr_23_we = addr_hit[279] & reg_we & !reg_error; assign mio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -35202,8 +34971,8 @@ module pinmux_reg_top ( assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign mio_pad_attr_24_re = addr_hit[286] & reg_re & !reg_error; - assign mio_pad_attr_24_we = addr_hit[286] & reg_we & !reg_error; + assign mio_pad_attr_24_re = addr_hit[280] & reg_re & !reg_error; + assign mio_pad_attr_24_we = addr_hit[280] & reg_we & !reg_error; assign mio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -35224,8 +34993,8 @@ module pinmux_reg_top ( assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign mio_pad_attr_25_re = addr_hit[287] & reg_re & !reg_error; - assign mio_pad_attr_25_we = addr_hit[287] & reg_we & !reg_error; + assign mio_pad_attr_25_re = addr_hit[281] & reg_re & !reg_error; + assign mio_pad_attr_25_we = addr_hit[281] & reg_we & !reg_error; assign mio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -35246,8 +35015,8 @@ module pinmux_reg_top ( assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign mio_pad_attr_26_re = addr_hit[288] & reg_re & !reg_error; - assign mio_pad_attr_26_we = addr_hit[288] & reg_we & !reg_error; + assign mio_pad_attr_26_re = addr_hit[282] & reg_re & !reg_error; + assign mio_pad_attr_26_we = addr_hit[282] & reg_we & !reg_error; assign mio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -35268,8 +35037,8 @@ module pinmux_reg_top ( assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign mio_pad_attr_27_re = addr_hit[289] & reg_re & !reg_error; - assign mio_pad_attr_27_we = addr_hit[289] & reg_we & !reg_error; + assign mio_pad_attr_27_re = addr_hit[283] & reg_re & !reg_error; + assign mio_pad_attr_27_we = addr_hit[283] & reg_we & !reg_error; assign mio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -35290,8 +35059,8 @@ module pinmux_reg_top ( assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign mio_pad_attr_28_re = addr_hit[290] & reg_re & !reg_error; - assign mio_pad_attr_28_we = addr_hit[290] & reg_we & !reg_error; + assign mio_pad_attr_28_re = addr_hit[284] & reg_re & !reg_error; + assign mio_pad_attr_28_we = addr_hit[284] & reg_we & !reg_error; assign mio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -35312,8 +35081,8 @@ module pinmux_reg_top ( assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign mio_pad_attr_29_re = addr_hit[291] & reg_re & !reg_error; - assign mio_pad_attr_29_we = addr_hit[291] & reg_we & !reg_error; + assign mio_pad_attr_29_re = addr_hit[285] & reg_re & !reg_error; + assign mio_pad_attr_29_we = addr_hit[285] & reg_we & !reg_error; assign mio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -35334,8 +35103,8 @@ module pinmux_reg_top ( assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign mio_pad_attr_30_re = addr_hit[292] & reg_re & !reg_error; - assign mio_pad_attr_30_we = addr_hit[292] & reg_we & !reg_error; + assign mio_pad_attr_30_re = addr_hit[286] & reg_re & !reg_error; + assign mio_pad_attr_30_we = addr_hit[286] & reg_we & !reg_error; assign mio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -35356,8 +35125,8 @@ module pinmux_reg_top ( assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign mio_pad_attr_31_re = addr_hit[293] & reg_re & !reg_error; - assign mio_pad_attr_31_we = addr_hit[293] & reg_we & !reg_error; + assign mio_pad_attr_31_re = addr_hit[287] & reg_re & !reg_error; + assign mio_pad_attr_31_we = addr_hit[287] & reg_we & !reg_error; assign mio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -35378,8 +35147,8 @@ module pinmux_reg_top ( assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign mio_pad_attr_32_re = addr_hit[294] & reg_re & !reg_error; - assign mio_pad_attr_32_we = addr_hit[294] & reg_we & !reg_error; + assign mio_pad_attr_32_re = addr_hit[288] & reg_re & !reg_error; + assign mio_pad_attr_32_we = addr_hit[288] & reg_we & !reg_error; assign mio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -35400,8 +35169,8 @@ module pinmux_reg_top ( assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign mio_pad_attr_33_re = addr_hit[295] & reg_re & !reg_error; - assign mio_pad_attr_33_we = addr_hit[295] & reg_we & !reg_error; + assign mio_pad_attr_33_re = addr_hit[289] & reg_re & !reg_error; + assign mio_pad_attr_33_we = addr_hit[289] & reg_we & !reg_error; assign mio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -35422,8 +35191,8 @@ module pinmux_reg_top ( assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign mio_pad_attr_34_re = addr_hit[296] & reg_re & !reg_error; - assign mio_pad_attr_34_we = addr_hit[296] & reg_we & !reg_error; + assign mio_pad_attr_34_re = addr_hit[290] & reg_re & !reg_error; + assign mio_pad_attr_34_we = addr_hit[290] & reg_we & !reg_error; assign mio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -35444,8 +35213,8 @@ module pinmux_reg_top ( assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign mio_pad_attr_35_re = addr_hit[297] & reg_re & !reg_error; - assign mio_pad_attr_35_we = addr_hit[297] & reg_we & !reg_error; + assign mio_pad_attr_35_re = addr_hit[291] & reg_re & !reg_error; + assign mio_pad_attr_35_we = addr_hit[291] & reg_we & !reg_error; assign mio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -35466,8 +35235,8 @@ module pinmux_reg_top ( assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign mio_pad_attr_36_re = addr_hit[298] & reg_re & !reg_error; - assign mio_pad_attr_36_we = addr_hit[298] & reg_we & !reg_error; + assign mio_pad_attr_36_re = addr_hit[292] & reg_re & !reg_error; + assign mio_pad_attr_36_we = addr_hit[292] & reg_we & !reg_error; assign mio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -35488,8 +35257,8 @@ module pinmux_reg_top ( assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_attr_37_re = addr_hit[299] & reg_re & !reg_error; - assign mio_pad_attr_37_we = addr_hit[299] & reg_we & !reg_error; + assign mio_pad_attr_37_re = addr_hit[293] & reg_re & !reg_error; + assign mio_pad_attr_37_we = addr_hit[293] & reg_we & !reg_error; assign mio_pad_attr_37_invert_37_wd = reg_wdata[0]; @@ -35510,8 +35279,8 @@ module pinmux_reg_top ( assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; - assign mio_pad_attr_38_re = addr_hit[300] & reg_re & !reg_error; - assign mio_pad_attr_38_we = addr_hit[300] & reg_we & !reg_error; + assign mio_pad_attr_38_re = addr_hit[294] & reg_re & !reg_error; + assign mio_pad_attr_38_we = addr_hit[294] & reg_we & !reg_error; assign mio_pad_attr_38_invert_38_wd = reg_wdata[0]; @@ -35532,8 +35301,8 @@ module pinmux_reg_top ( assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; - assign mio_pad_attr_39_re = addr_hit[301] & reg_re & !reg_error; - assign mio_pad_attr_39_we = addr_hit[301] & reg_we & !reg_error; + assign mio_pad_attr_39_re = addr_hit[295] & reg_re & !reg_error; + assign mio_pad_attr_39_we = addr_hit[295] & reg_we & !reg_error; assign mio_pad_attr_39_invert_39_wd = reg_wdata[0]; @@ -35554,8 +35323,8 @@ module pinmux_reg_top ( assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; - assign mio_pad_attr_40_re = addr_hit[302] & reg_re & !reg_error; - assign mio_pad_attr_40_we = addr_hit[302] & reg_we & !reg_error; + assign mio_pad_attr_40_re = addr_hit[296] & reg_re & !reg_error; + assign mio_pad_attr_40_we = addr_hit[296] & reg_we & !reg_error; assign mio_pad_attr_40_invert_40_wd = reg_wdata[0]; @@ -35576,8 +35345,8 @@ module pinmux_reg_top ( assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; - assign mio_pad_attr_41_re = addr_hit[303] & reg_re & !reg_error; - assign mio_pad_attr_41_we = addr_hit[303] & reg_we & !reg_error; + assign mio_pad_attr_41_re = addr_hit[297] & reg_re & !reg_error; + assign mio_pad_attr_41_we = addr_hit[297] & reg_we & !reg_error; assign mio_pad_attr_41_invert_41_wd = reg_wdata[0]; @@ -35598,8 +35367,8 @@ module pinmux_reg_top ( assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; - assign mio_pad_attr_42_re = addr_hit[304] & reg_re & !reg_error; - assign mio_pad_attr_42_we = addr_hit[304] & reg_we & !reg_error; + assign mio_pad_attr_42_re = addr_hit[298] & reg_re & !reg_error; + assign mio_pad_attr_42_we = addr_hit[298] & reg_we & !reg_error; assign mio_pad_attr_42_invert_42_wd = reg_wdata[0]; @@ -35620,8 +35389,8 @@ module pinmux_reg_top ( assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; - assign mio_pad_attr_43_re = addr_hit[305] & reg_re & !reg_error; - assign mio_pad_attr_43_we = addr_hit[305] & reg_we & !reg_error; + assign mio_pad_attr_43_re = addr_hit[299] & reg_re & !reg_error; + assign mio_pad_attr_43_we = addr_hit[299] & reg_we & !reg_error; assign mio_pad_attr_43_invert_43_wd = reg_wdata[0]; @@ -35642,8 +35411,8 @@ module pinmux_reg_top ( assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; - assign mio_pad_attr_44_re = addr_hit[306] & reg_re & !reg_error; - assign mio_pad_attr_44_we = addr_hit[306] & reg_we & !reg_error; + assign mio_pad_attr_44_re = addr_hit[300] & reg_re & !reg_error; + assign mio_pad_attr_44_we = addr_hit[300] & reg_we & !reg_error; assign mio_pad_attr_44_invert_44_wd = reg_wdata[0]; @@ -35664,8 +35433,8 @@ module pinmux_reg_top ( assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; - assign mio_pad_attr_45_re = addr_hit[307] & reg_re & !reg_error; - assign mio_pad_attr_45_we = addr_hit[307] & reg_we & !reg_error; + assign mio_pad_attr_45_re = addr_hit[301] & reg_re & !reg_error; + assign mio_pad_attr_45_we = addr_hit[301] & reg_we & !reg_error; assign mio_pad_attr_45_invert_45_wd = reg_wdata[0]; @@ -35686,8 +35455,8 @@ module pinmux_reg_top ( assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; - assign mio_pad_attr_46_re = addr_hit[308] & reg_re & !reg_error; - assign mio_pad_attr_46_we = addr_hit[308] & reg_we & !reg_error; + assign mio_pad_attr_46_re = addr_hit[302] & reg_re & !reg_error; + assign mio_pad_attr_46_we = addr_hit[302] & reg_we & !reg_error; assign mio_pad_attr_46_invert_46_wd = reg_wdata[0]; @@ -35708,56 +35477,56 @@ module pinmux_reg_top ( assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; - assign dio_pad_attr_regwen_0_we = addr_hit[309] & reg_we & !reg_error; + assign dio_pad_attr_regwen_0_we = addr_hit[303] & reg_we & !reg_error; assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_1_we = addr_hit[310] & reg_we & !reg_error; + assign dio_pad_attr_regwen_1_we = addr_hit[304] & reg_we & !reg_error; assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_2_we = addr_hit[311] & reg_we & !reg_error; + assign dio_pad_attr_regwen_2_we = addr_hit[305] & reg_we & !reg_error; assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_3_we = addr_hit[312] & reg_we & !reg_error; + assign dio_pad_attr_regwen_3_we = addr_hit[306] & reg_we & !reg_error; assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_4_we = addr_hit[313] & reg_we & !reg_error; + assign dio_pad_attr_regwen_4_we = addr_hit[307] & reg_we & !reg_error; assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_5_we = addr_hit[314] & reg_we & !reg_error; + assign dio_pad_attr_regwen_5_we = addr_hit[308] & reg_we & !reg_error; assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_6_we = addr_hit[315] & reg_we & !reg_error; + assign dio_pad_attr_regwen_6_we = addr_hit[309] & reg_we & !reg_error; assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_7_we = addr_hit[316] & reg_we & !reg_error; + assign dio_pad_attr_regwen_7_we = addr_hit[310] & reg_we & !reg_error; assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_8_we = addr_hit[317] & reg_we & !reg_error; + assign dio_pad_attr_regwen_8_we = addr_hit[311] & reg_we & !reg_error; assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_9_we = addr_hit[318] & reg_we & !reg_error; + assign dio_pad_attr_regwen_9_we = addr_hit[312] & reg_we & !reg_error; assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_10_we = addr_hit[319] & reg_we & !reg_error; + assign dio_pad_attr_regwen_10_we = addr_hit[313] & reg_we & !reg_error; assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_11_we = addr_hit[320] & reg_we & !reg_error; + assign dio_pad_attr_regwen_11_we = addr_hit[314] & reg_we & !reg_error; assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_12_we = addr_hit[321] & reg_we & !reg_error; + assign dio_pad_attr_regwen_12_we = addr_hit[315] & reg_we & !reg_error; assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_13_we = addr_hit[322] & reg_we & !reg_error; + assign dio_pad_attr_regwen_13_we = addr_hit[316] & reg_we & !reg_error; assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_14_we = addr_hit[323] & reg_we & !reg_error; + assign dio_pad_attr_regwen_14_we = addr_hit[317] & reg_we & !reg_error; assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_15_we = addr_hit[324] & reg_we & !reg_error; + assign dio_pad_attr_regwen_15_we = addr_hit[318] & reg_we & !reg_error; assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign dio_pad_attr_0_re = addr_hit[325] & reg_re & !reg_error; - assign dio_pad_attr_0_we = addr_hit[325] & reg_we & !reg_error; + assign dio_pad_attr_0_re = addr_hit[319] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[319] & reg_we & !reg_error; assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -35778,8 +35547,8 @@ module pinmux_reg_top ( assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign dio_pad_attr_1_re = addr_hit[326] & reg_re & !reg_error; - assign dio_pad_attr_1_we = addr_hit[326] & reg_we & !reg_error; + assign dio_pad_attr_1_re = addr_hit[320] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[320] & reg_we & !reg_error; assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -35800,8 +35569,8 @@ module pinmux_reg_top ( assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign dio_pad_attr_2_re = addr_hit[327] & reg_re & !reg_error; - assign dio_pad_attr_2_we = addr_hit[327] & reg_we & !reg_error; + assign dio_pad_attr_2_re = addr_hit[321] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[321] & reg_we & !reg_error; assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -35822,8 +35591,8 @@ module pinmux_reg_top ( assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign dio_pad_attr_3_re = addr_hit[328] & reg_re & !reg_error; - assign dio_pad_attr_3_we = addr_hit[328] & reg_we & !reg_error; + assign dio_pad_attr_3_re = addr_hit[322] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[322] & reg_we & !reg_error; assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -35844,8 +35613,8 @@ module pinmux_reg_top ( assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign dio_pad_attr_4_re = addr_hit[329] & reg_re & !reg_error; - assign dio_pad_attr_4_we = addr_hit[329] & reg_we & !reg_error; + assign dio_pad_attr_4_re = addr_hit[323] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[323] & reg_we & !reg_error; assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -35866,8 +35635,8 @@ module pinmux_reg_top ( assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign dio_pad_attr_5_re = addr_hit[330] & reg_re & !reg_error; - assign dio_pad_attr_5_we = addr_hit[330] & reg_we & !reg_error; + assign dio_pad_attr_5_re = addr_hit[324] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[324] & reg_we & !reg_error; assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -35888,8 +35657,8 @@ module pinmux_reg_top ( assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign dio_pad_attr_6_re = addr_hit[331] & reg_re & !reg_error; - assign dio_pad_attr_6_we = addr_hit[331] & reg_we & !reg_error; + assign dio_pad_attr_6_re = addr_hit[325] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[325] & reg_we & !reg_error; assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -35910,8 +35679,8 @@ module pinmux_reg_top ( assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign dio_pad_attr_7_re = addr_hit[332] & reg_re & !reg_error; - assign dio_pad_attr_7_we = addr_hit[332] & reg_we & !reg_error; + assign dio_pad_attr_7_re = addr_hit[326] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[326] & reg_we & !reg_error; assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -35932,8 +35701,8 @@ module pinmux_reg_top ( assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign dio_pad_attr_8_re = addr_hit[333] & reg_re & !reg_error; - assign dio_pad_attr_8_we = addr_hit[333] & reg_we & !reg_error; + assign dio_pad_attr_8_re = addr_hit[327] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[327] & reg_we & !reg_error; assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -35954,8 +35723,8 @@ module pinmux_reg_top ( assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign dio_pad_attr_9_re = addr_hit[334] & reg_re & !reg_error; - assign dio_pad_attr_9_we = addr_hit[334] & reg_we & !reg_error; + assign dio_pad_attr_9_re = addr_hit[328] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[328] & reg_we & !reg_error; assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -35976,8 +35745,8 @@ module pinmux_reg_top ( assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign dio_pad_attr_10_re = addr_hit[335] & reg_re & !reg_error; - assign dio_pad_attr_10_we = addr_hit[335] & reg_we & !reg_error; + assign dio_pad_attr_10_re = addr_hit[329] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[329] & reg_we & !reg_error; assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -35998,8 +35767,8 @@ module pinmux_reg_top ( assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign dio_pad_attr_11_re = addr_hit[336] & reg_re & !reg_error; - assign dio_pad_attr_11_we = addr_hit[336] & reg_we & !reg_error; + assign dio_pad_attr_11_re = addr_hit[330] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[330] & reg_we & !reg_error; assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -36020,8 +35789,8 @@ module pinmux_reg_top ( assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign dio_pad_attr_12_re = addr_hit[337] & reg_re & !reg_error; - assign dio_pad_attr_12_we = addr_hit[337] & reg_we & !reg_error; + assign dio_pad_attr_12_re = addr_hit[331] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[331] & reg_we & !reg_error; assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -36042,8 +35811,8 @@ module pinmux_reg_top ( assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign dio_pad_attr_13_re = addr_hit[338] & reg_re & !reg_error; - assign dio_pad_attr_13_we = addr_hit[338] & reg_we & !reg_error; + assign dio_pad_attr_13_re = addr_hit[332] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[332] & reg_we & !reg_error; assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -36064,8 +35833,8 @@ module pinmux_reg_top ( assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign dio_pad_attr_14_re = addr_hit[339] & reg_re & !reg_error; - assign dio_pad_attr_14_we = addr_hit[339] & reg_we & !reg_error; + assign dio_pad_attr_14_re = addr_hit[333] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[333] & reg_we & !reg_error; assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -36086,8 +35855,8 @@ module pinmux_reg_top ( assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign dio_pad_attr_15_re = addr_hit[340] & reg_re & !reg_error; - assign dio_pad_attr_15_we = addr_hit[340] & reg_we & !reg_error; + assign dio_pad_attr_15_re = addr_hit[334] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[334] & reg_we & !reg_error; assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -36108,7 +35877,7 @@ module pinmux_reg_top ( assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_sleep_status_0_we = addr_hit[341] & reg_we & !reg_error; + assign mio_pad_sleep_status_0_we = addr_hit[335] & reg_we & !reg_error; assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -36173,7 +35942,7 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign mio_pad_sleep_status_1_we = addr_hit[342] & reg_we & !reg_error; + assign mio_pad_sleep_status_1_we = addr_hit[336] & reg_we & !reg_error; assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -36204,430 +35973,430 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; - assign mio_pad_sleep_regwen_0_we = addr_hit[343] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_0_we = addr_hit[337] & reg_we & !reg_error; assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_1_we = addr_hit[344] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_1_we = addr_hit[338] & reg_we & !reg_error; assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_2_we = addr_hit[345] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_2_we = addr_hit[339] & reg_we & !reg_error; assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_3_we = addr_hit[346] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_3_we = addr_hit[340] & reg_we & !reg_error; assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_4_we = addr_hit[347] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_4_we = addr_hit[341] & reg_we & !reg_error; assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_5_we = addr_hit[348] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_5_we = addr_hit[342] & reg_we & !reg_error; assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_6_we = addr_hit[349] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_6_we = addr_hit[343] & reg_we & !reg_error; assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_7_we = addr_hit[350] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_7_we = addr_hit[344] & reg_we & !reg_error; assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_8_we = addr_hit[351] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_8_we = addr_hit[345] & reg_we & !reg_error; assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_9_we = addr_hit[352] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_9_we = addr_hit[346] & reg_we & !reg_error; assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_10_we = addr_hit[353] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_10_we = addr_hit[347] & reg_we & !reg_error; assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_11_we = addr_hit[354] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_11_we = addr_hit[348] & reg_we & !reg_error; assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_12_we = addr_hit[355] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_12_we = addr_hit[349] & reg_we & !reg_error; assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_13_we = addr_hit[356] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_13_we = addr_hit[350] & reg_we & !reg_error; assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_14_we = addr_hit[357] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_14_we = addr_hit[351] & reg_we & !reg_error; assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_15_we = addr_hit[358] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_15_we = addr_hit[352] & reg_we & !reg_error; assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_16_we = addr_hit[359] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_16_we = addr_hit[353] & reg_we & !reg_error; assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_17_we = addr_hit[360] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_17_we = addr_hit[354] & reg_we & !reg_error; assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_18_we = addr_hit[361] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_18_we = addr_hit[355] & reg_we & !reg_error; assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_19_we = addr_hit[362] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_19_we = addr_hit[356] & reg_we & !reg_error; assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_20_we = addr_hit[363] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_20_we = addr_hit[357] & reg_we & !reg_error; assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_21_we = addr_hit[364] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_21_we = addr_hit[358] & reg_we & !reg_error; assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_22_we = addr_hit[365] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_22_we = addr_hit[359] & reg_we & !reg_error; assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_23_we = addr_hit[366] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_23_we = addr_hit[360] & reg_we & !reg_error; assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_24_we = addr_hit[367] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_24_we = addr_hit[361] & reg_we & !reg_error; assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_25_we = addr_hit[368] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_25_we = addr_hit[362] & reg_we & !reg_error; assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_26_we = addr_hit[369] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_26_we = addr_hit[363] & reg_we & !reg_error; assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_27_we = addr_hit[370] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_27_we = addr_hit[364] & reg_we & !reg_error; assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_28_we = addr_hit[371] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_28_we = addr_hit[365] & reg_we & !reg_error; assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_29_we = addr_hit[372] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_29_we = addr_hit[366] & reg_we & !reg_error; assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_30_we = addr_hit[373] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_30_we = addr_hit[367] & reg_we & !reg_error; assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_31_we = addr_hit[374] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_31_we = addr_hit[368] & reg_we & !reg_error; assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_32_we = addr_hit[375] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_32_we = addr_hit[369] & reg_we & !reg_error; assign mio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_33_we = addr_hit[376] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_33_we = addr_hit[370] & reg_we & !reg_error; assign mio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_34_we = addr_hit[377] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_34_we = addr_hit[371] & reg_we & !reg_error; assign mio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_35_we = addr_hit[378] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_35_we = addr_hit[372] & reg_we & !reg_error; assign mio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_36_we = addr_hit[379] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_36_we = addr_hit[373] & reg_we & !reg_error; assign mio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_37_we = addr_hit[380] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_37_we = addr_hit[374] & reg_we & !reg_error; assign mio_pad_sleep_regwen_37_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_38_we = addr_hit[381] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_38_we = addr_hit[375] & reg_we & !reg_error; assign mio_pad_sleep_regwen_38_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_39_we = addr_hit[382] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_39_we = addr_hit[376] & reg_we & !reg_error; assign mio_pad_sleep_regwen_39_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_40_we = addr_hit[383] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_40_we = addr_hit[377] & reg_we & !reg_error; assign mio_pad_sleep_regwen_40_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_41_we = addr_hit[384] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_41_we = addr_hit[378] & reg_we & !reg_error; assign mio_pad_sleep_regwen_41_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_42_we = addr_hit[385] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_42_we = addr_hit[379] & reg_we & !reg_error; assign mio_pad_sleep_regwen_42_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_43_we = addr_hit[386] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_43_we = addr_hit[380] & reg_we & !reg_error; assign mio_pad_sleep_regwen_43_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_44_we = addr_hit[387] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_44_we = addr_hit[381] & reg_we & !reg_error; assign mio_pad_sleep_regwen_44_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_45_we = addr_hit[388] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_45_we = addr_hit[382] & reg_we & !reg_error; assign mio_pad_sleep_regwen_45_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_46_we = addr_hit[389] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_46_we = addr_hit[383] & reg_we & !reg_error; assign mio_pad_sleep_regwen_46_wd = reg_wdata[0]; - assign mio_pad_sleep_en_0_we = addr_hit[390] & reg_we & !reg_error; + assign mio_pad_sleep_en_0_we = addr_hit[384] & reg_we & !reg_error; assign mio_pad_sleep_en_0_wd = reg_wdata[0]; - assign mio_pad_sleep_en_1_we = addr_hit[391] & reg_we & !reg_error; + assign mio_pad_sleep_en_1_we = addr_hit[385] & reg_we & !reg_error; assign mio_pad_sleep_en_1_wd = reg_wdata[0]; - assign mio_pad_sleep_en_2_we = addr_hit[392] & reg_we & !reg_error; + assign mio_pad_sleep_en_2_we = addr_hit[386] & reg_we & !reg_error; assign mio_pad_sleep_en_2_wd = reg_wdata[0]; - assign mio_pad_sleep_en_3_we = addr_hit[393] & reg_we & !reg_error; + assign mio_pad_sleep_en_3_we = addr_hit[387] & reg_we & !reg_error; assign mio_pad_sleep_en_3_wd = reg_wdata[0]; - assign mio_pad_sleep_en_4_we = addr_hit[394] & reg_we & !reg_error; + assign mio_pad_sleep_en_4_we = addr_hit[388] & reg_we & !reg_error; assign mio_pad_sleep_en_4_wd = reg_wdata[0]; - assign mio_pad_sleep_en_5_we = addr_hit[395] & reg_we & !reg_error; + assign mio_pad_sleep_en_5_we = addr_hit[389] & reg_we & !reg_error; assign mio_pad_sleep_en_5_wd = reg_wdata[0]; - assign mio_pad_sleep_en_6_we = addr_hit[396] & reg_we & !reg_error; + assign mio_pad_sleep_en_6_we = addr_hit[390] & reg_we & !reg_error; assign mio_pad_sleep_en_6_wd = reg_wdata[0]; - assign mio_pad_sleep_en_7_we = addr_hit[397] & reg_we & !reg_error; + assign mio_pad_sleep_en_7_we = addr_hit[391] & reg_we & !reg_error; assign mio_pad_sleep_en_7_wd = reg_wdata[0]; - assign mio_pad_sleep_en_8_we = addr_hit[398] & reg_we & !reg_error; + assign mio_pad_sleep_en_8_we = addr_hit[392] & reg_we & !reg_error; assign mio_pad_sleep_en_8_wd = reg_wdata[0]; - assign mio_pad_sleep_en_9_we = addr_hit[399] & reg_we & !reg_error; + assign mio_pad_sleep_en_9_we = addr_hit[393] & reg_we & !reg_error; assign mio_pad_sleep_en_9_wd = reg_wdata[0]; - assign mio_pad_sleep_en_10_we = addr_hit[400] & reg_we & !reg_error; + assign mio_pad_sleep_en_10_we = addr_hit[394] & reg_we & !reg_error; assign mio_pad_sleep_en_10_wd = reg_wdata[0]; - assign mio_pad_sleep_en_11_we = addr_hit[401] & reg_we & !reg_error; + assign mio_pad_sleep_en_11_we = addr_hit[395] & reg_we & !reg_error; assign mio_pad_sleep_en_11_wd = reg_wdata[0]; - assign mio_pad_sleep_en_12_we = addr_hit[402] & reg_we & !reg_error; + assign mio_pad_sleep_en_12_we = addr_hit[396] & reg_we & !reg_error; assign mio_pad_sleep_en_12_wd = reg_wdata[0]; - assign mio_pad_sleep_en_13_we = addr_hit[403] & reg_we & !reg_error; + assign mio_pad_sleep_en_13_we = addr_hit[397] & reg_we & !reg_error; assign mio_pad_sleep_en_13_wd = reg_wdata[0]; - assign mio_pad_sleep_en_14_we = addr_hit[404] & reg_we & !reg_error; + assign mio_pad_sleep_en_14_we = addr_hit[398] & reg_we & !reg_error; assign mio_pad_sleep_en_14_wd = reg_wdata[0]; - assign mio_pad_sleep_en_15_we = addr_hit[405] & reg_we & !reg_error; + assign mio_pad_sleep_en_15_we = addr_hit[399] & reg_we & !reg_error; assign mio_pad_sleep_en_15_wd = reg_wdata[0]; - assign mio_pad_sleep_en_16_we = addr_hit[406] & reg_we & !reg_error; + assign mio_pad_sleep_en_16_we = addr_hit[400] & reg_we & !reg_error; assign mio_pad_sleep_en_16_wd = reg_wdata[0]; - assign mio_pad_sleep_en_17_we = addr_hit[407] & reg_we & !reg_error; + assign mio_pad_sleep_en_17_we = addr_hit[401] & reg_we & !reg_error; assign mio_pad_sleep_en_17_wd = reg_wdata[0]; - assign mio_pad_sleep_en_18_we = addr_hit[408] & reg_we & !reg_error; + assign mio_pad_sleep_en_18_we = addr_hit[402] & reg_we & !reg_error; assign mio_pad_sleep_en_18_wd = reg_wdata[0]; - assign mio_pad_sleep_en_19_we = addr_hit[409] & reg_we & !reg_error; + assign mio_pad_sleep_en_19_we = addr_hit[403] & reg_we & !reg_error; assign mio_pad_sleep_en_19_wd = reg_wdata[0]; - assign mio_pad_sleep_en_20_we = addr_hit[410] & reg_we & !reg_error; + assign mio_pad_sleep_en_20_we = addr_hit[404] & reg_we & !reg_error; assign mio_pad_sleep_en_20_wd = reg_wdata[0]; - assign mio_pad_sleep_en_21_we = addr_hit[411] & reg_we & !reg_error; + assign mio_pad_sleep_en_21_we = addr_hit[405] & reg_we & !reg_error; assign mio_pad_sleep_en_21_wd = reg_wdata[0]; - assign mio_pad_sleep_en_22_we = addr_hit[412] & reg_we & !reg_error; + assign mio_pad_sleep_en_22_we = addr_hit[406] & reg_we & !reg_error; assign mio_pad_sleep_en_22_wd = reg_wdata[0]; - assign mio_pad_sleep_en_23_we = addr_hit[413] & reg_we & !reg_error; + assign mio_pad_sleep_en_23_we = addr_hit[407] & reg_we & !reg_error; assign mio_pad_sleep_en_23_wd = reg_wdata[0]; - assign mio_pad_sleep_en_24_we = addr_hit[414] & reg_we & !reg_error; + assign mio_pad_sleep_en_24_we = addr_hit[408] & reg_we & !reg_error; assign mio_pad_sleep_en_24_wd = reg_wdata[0]; - assign mio_pad_sleep_en_25_we = addr_hit[415] & reg_we & !reg_error; + assign mio_pad_sleep_en_25_we = addr_hit[409] & reg_we & !reg_error; assign mio_pad_sleep_en_25_wd = reg_wdata[0]; - assign mio_pad_sleep_en_26_we = addr_hit[416] & reg_we & !reg_error; + assign mio_pad_sleep_en_26_we = addr_hit[410] & reg_we & !reg_error; assign mio_pad_sleep_en_26_wd = reg_wdata[0]; - assign mio_pad_sleep_en_27_we = addr_hit[417] & reg_we & !reg_error; + assign mio_pad_sleep_en_27_we = addr_hit[411] & reg_we & !reg_error; assign mio_pad_sleep_en_27_wd = reg_wdata[0]; - assign mio_pad_sleep_en_28_we = addr_hit[418] & reg_we & !reg_error; + assign mio_pad_sleep_en_28_we = addr_hit[412] & reg_we & !reg_error; assign mio_pad_sleep_en_28_wd = reg_wdata[0]; - assign mio_pad_sleep_en_29_we = addr_hit[419] & reg_we & !reg_error; + assign mio_pad_sleep_en_29_we = addr_hit[413] & reg_we & !reg_error; assign mio_pad_sleep_en_29_wd = reg_wdata[0]; - assign mio_pad_sleep_en_30_we = addr_hit[420] & reg_we & !reg_error; + assign mio_pad_sleep_en_30_we = addr_hit[414] & reg_we & !reg_error; assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_pad_sleep_en_31_we = addr_hit[421] & reg_we & !reg_error; + assign mio_pad_sleep_en_31_we = addr_hit[415] & reg_we & !reg_error; assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_pad_sleep_en_32_we = addr_hit[422] & reg_we & !reg_error; + assign mio_pad_sleep_en_32_we = addr_hit[416] & reg_we & !reg_error; assign mio_pad_sleep_en_32_wd = reg_wdata[0]; - assign mio_pad_sleep_en_33_we = addr_hit[423] & reg_we & !reg_error; + assign mio_pad_sleep_en_33_we = addr_hit[417] & reg_we & !reg_error; assign mio_pad_sleep_en_33_wd = reg_wdata[0]; - assign mio_pad_sleep_en_34_we = addr_hit[424] & reg_we & !reg_error; + assign mio_pad_sleep_en_34_we = addr_hit[418] & reg_we & !reg_error; assign mio_pad_sleep_en_34_wd = reg_wdata[0]; - assign mio_pad_sleep_en_35_we = addr_hit[425] & reg_we & !reg_error; + assign mio_pad_sleep_en_35_we = addr_hit[419] & reg_we & !reg_error; assign mio_pad_sleep_en_35_wd = reg_wdata[0]; - assign mio_pad_sleep_en_36_we = addr_hit[426] & reg_we & !reg_error; + assign mio_pad_sleep_en_36_we = addr_hit[420] & reg_we & !reg_error; assign mio_pad_sleep_en_36_wd = reg_wdata[0]; - assign mio_pad_sleep_en_37_we = addr_hit[427] & reg_we & !reg_error; + assign mio_pad_sleep_en_37_we = addr_hit[421] & reg_we & !reg_error; assign mio_pad_sleep_en_37_wd = reg_wdata[0]; - assign mio_pad_sleep_en_38_we = addr_hit[428] & reg_we & !reg_error; + assign mio_pad_sleep_en_38_we = addr_hit[422] & reg_we & !reg_error; assign mio_pad_sleep_en_38_wd = reg_wdata[0]; - assign mio_pad_sleep_en_39_we = addr_hit[429] & reg_we & !reg_error; + assign mio_pad_sleep_en_39_we = addr_hit[423] & reg_we & !reg_error; assign mio_pad_sleep_en_39_wd = reg_wdata[0]; - assign mio_pad_sleep_en_40_we = addr_hit[430] & reg_we & !reg_error; + assign mio_pad_sleep_en_40_we = addr_hit[424] & reg_we & !reg_error; assign mio_pad_sleep_en_40_wd = reg_wdata[0]; - assign mio_pad_sleep_en_41_we = addr_hit[431] & reg_we & !reg_error; + assign mio_pad_sleep_en_41_we = addr_hit[425] & reg_we & !reg_error; assign mio_pad_sleep_en_41_wd = reg_wdata[0]; - assign mio_pad_sleep_en_42_we = addr_hit[432] & reg_we & !reg_error; + assign mio_pad_sleep_en_42_we = addr_hit[426] & reg_we & !reg_error; assign mio_pad_sleep_en_42_wd = reg_wdata[0]; - assign mio_pad_sleep_en_43_we = addr_hit[433] & reg_we & !reg_error; + assign mio_pad_sleep_en_43_we = addr_hit[427] & reg_we & !reg_error; assign mio_pad_sleep_en_43_wd = reg_wdata[0]; - assign mio_pad_sleep_en_44_we = addr_hit[434] & reg_we & !reg_error; + assign mio_pad_sleep_en_44_we = addr_hit[428] & reg_we & !reg_error; assign mio_pad_sleep_en_44_wd = reg_wdata[0]; - assign mio_pad_sleep_en_45_we = addr_hit[435] & reg_we & !reg_error; + assign mio_pad_sleep_en_45_we = addr_hit[429] & reg_we & !reg_error; assign mio_pad_sleep_en_45_wd = reg_wdata[0]; - assign mio_pad_sleep_en_46_we = addr_hit[436] & reg_we & !reg_error; + assign mio_pad_sleep_en_46_we = addr_hit[430] & reg_we & !reg_error; assign mio_pad_sleep_en_46_wd = reg_wdata[0]; - assign mio_pad_sleep_mode_0_we = addr_hit[437] & reg_we & !reg_error; + assign mio_pad_sleep_mode_0_we = addr_hit[431] & reg_we & !reg_error; assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_1_we = addr_hit[438] & reg_we & !reg_error; + assign mio_pad_sleep_mode_1_we = addr_hit[432] & reg_we & !reg_error; assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_2_we = addr_hit[439] & reg_we & !reg_error; + assign mio_pad_sleep_mode_2_we = addr_hit[433] & reg_we & !reg_error; assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_3_we = addr_hit[440] & reg_we & !reg_error; + assign mio_pad_sleep_mode_3_we = addr_hit[434] & reg_we & !reg_error; assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_4_we = addr_hit[441] & reg_we & !reg_error; + assign mio_pad_sleep_mode_4_we = addr_hit[435] & reg_we & !reg_error; assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_5_we = addr_hit[442] & reg_we & !reg_error; + assign mio_pad_sleep_mode_5_we = addr_hit[436] & reg_we & !reg_error; assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_6_we = addr_hit[443] & reg_we & !reg_error; + assign mio_pad_sleep_mode_6_we = addr_hit[437] & reg_we & !reg_error; assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_7_we = addr_hit[444] & reg_we & !reg_error; + assign mio_pad_sleep_mode_7_we = addr_hit[438] & reg_we & !reg_error; assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_8_we = addr_hit[445] & reg_we & !reg_error; + assign mio_pad_sleep_mode_8_we = addr_hit[439] & reg_we & !reg_error; assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_9_we = addr_hit[446] & reg_we & !reg_error; + assign mio_pad_sleep_mode_9_we = addr_hit[440] & reg_we & !reg_error; assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_10_we = addr_hit[447] & reg_we & !reg_error; + assign mio_pad_sleep_mode_10_we = addr_hit[441] & reg_we & !reg_error; assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_11_we = addr_hit[448] & reg_we & !reg_error; + assign mio_pad_sleep_mode_11_we = addr_hit[442] & reg_we & !reg_error; assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_12_we = addr_hit[449] & reg_we & !reg_error; + assign mio_pad_sleep_mode_12_we = addr_hit[443] & reg_we & !reg_error; assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_13_we = addr_hit[450] & reg_we & !reg_error; + assign mio_pad_sleep_mode_13_we = addr_hit[444] & reg_we & !reg_error; assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_14_we = addr_hit[451] & reg_we & !reg_error; + assign mio_pad_sleep_mode_14_we = addr_hit[445] & reg_we & !reg_error; assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_15_we = addr_hit[452] & reg_we & !reg_error; + assign mio_pad_sleep_mode_15_we = addr_hit[446] & reg_we & !reg_error; assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_16_we = addr_hit[453] & reg_we & !reg_error; + assign mio_pad_sleep_mode_16_we = addr_hit[447] & reg_we & !reg_error; assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_17_we = addr_hit[454] & reg_we & !reg_error; + assign mio_pad_sleep_mode_17_we = addr_hit[448] & reg_we & !reg_error; assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_18_we = addr_hit[455] & reg_we & !reg_error; + assign mio_pad_sleep_mode_18_we = addr_hit[449] & reg_we & !reg_error; assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_19_we = addr_hit[456] & reg_we & !reg_error; + assign mio_pad_sleep_mode_19_we = addr_hit[450] & reg_we & !reg_error; assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_20_we = addr_hit[457] & reg_we & !reg_error; + assign mio_pad_sleep_mode_20_we = addr_hit[451] & reg_we & !reg_error; assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_21_we = addr_hit[458] & reg_we & !reg_error; + assign mio_pad_sleep_mode_21_we = addr_hit[452] & reg_we & !reg_error; assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_22_we = addr_hit[459] & reg_we & !reg_error; + assign mio_pad_sleep_mode_22_we = addr_hit[453] & reg_we & !reg_error; assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_23_we = addr_hit[460] & reg_we & !reg_error; + assign mio_pad_sleep_mode_23_we = addr_hit[454] & reg_we & !reg_error; assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_24_we = addr_hit[461] & reg_we & !reg_error; + assign mio_pad_sleep_mode_24_we = addr_hit[455] & reg_we & !reg_error; assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_25_we = addr_hit[462] & reg_we & !reg_error; + assign mio_pad_sleep_mode_25_we = addr_hit[456] & reg_we & !reg_error; assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_26_we = addr_hit[463] & reg_we & !reg_error; + assign mio_pad_sleep_mode_26_we = addr_hit[457] & reg_we & !reg_error; assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_27_we = addr_hit[464] & reg_we & !reg_error; + assign mio_pad_sleep_mode_27_we = addr_hit[458] & reg_we & !reg_error; assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_28_we = addr_hit[465] & reg_we & !reg_error; + assign mio_pad_sleep_mode_28_we = addr_hit[459] & reg_we & !reg_error; assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_29_we = addr_hit[466] & reg_we & !reg_error; + assign mio_pad_sleep_mode_29_we = addr_hit[460] & reg_we & !reg_error; assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_30_we = addr_hit[467] & reg_we & !reg_error; + assign mio_pad_sleep_mode_30_we = addr_hit[461] & reg_we & !reg_error; assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_31_we = addr_hit[468] & reg_we & !reg_error; + assign mio_pad_sleep_mode_31_we = addr_hit[462] & reg_we & !reg_error; assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_32_we = addr_hit[469] & reg_we & !reg_error; + assign mio_pad_sleep_mode_32_we = addr_hit[463] & reg_we & !reg_error; assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_33_we = addr_hit[470] & reg_we & !reg_error; + assign mio_pad_sleep_mode_33_we = addr_hit[464] & reg_we & !reg_error; assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_34_we = addr_hit[471] & reg_we & !reg_error; + assign mio_pad_sleep_mode_34_we = addr_hit[465] & reg_we & !reg_error; assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_35_we = addr_hit[472] & reg_we & !reg_error; + assign mio_pad_sleep_mode_35_we = addr_hit[466] & reg_we & !reg_error; assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_36_we = addr_hit[473] & reg_we & !reg_error; + assign mio_pad_sleep_mode_36_we = addr_hit[467] & reg_we & !reg_error; assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_37_we = addr_hit[474] & reg_we & !reg_error; + assign mio_pad_sleep_mode_37_we = addr_hit[468] & reg_we & !reg_error; assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_38_we = addr_hit[475] & reg_we & !reg_error; + assign mio_pad_sleep_mode_38_we = addr_hit[469] & reg_we & !reg_error; assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_39_we = addr_hit[476] & reg_we & !reg_error; + assign mio_pad_sleep_mode_39_we = addr_hit[470] & reg_we & !reg_error; assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_40_we = addr_hit[477] & reg_we & !reg_error; + assign mio_pad_sleep_mode_40_we = addr_hit[471] & reg_we & !reg_error; assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_41_we = addr_hit[478] & reg_we & !reg_error; + assign mio_pad_sleep_mode_41_we = addr_hit[472] & reg_we & !reg_error; assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_42_we = addr_hit[479] & reg_we & !reg_error; + assign mio_pad_sleep_mode_42_we = addr_hit[473] & reg_we & !reg_error; assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_43_we = addr_hit[480] & reg_we & !reg_error; + assign mio_pad_sleep_mode_43_we = addr_hit[474] & reg_we & !reg_error; assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_44_we = addr_hit[481] & reg_we & !reg_error; + assign mio_pad_sleep_mode_44_we = addr_hit[475] & reg_we & !reg_error; assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_45_we = addr_hit[482] & reg_we & !reg_error; + assign mio_pad_sleep_mode_45_we = addr_hit[476] & reg_we & !reg_error; assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_46_we = addr_hit[483] & reg_we & !reg_error; + assign mio_pad_sleep_mode_46_we = addr_hit[477] & reg_we & !reg_error; assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0]; - assign dio_pad_sleep_status_we = addr_hit[484] & reg_we & !reg_error; + assign dio_pad_sleep_status_we = addr_hit[478] & reg_we & !reg_error; assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; @@ -36660,263 +36429,263 @@ module pinmux_reg_top ( assign dio_pad_sleep_status_en_14_wd = reg_wdata[14]; assign dio_pad_sleep_status_en_15_wd = reg_wdata[15]; - assign dio_pad_sleep_regwen_0_we = addr_hit[485] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_0_we = addr_hit[479] & reg_we & !reg_error; assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_1_we = addr_hit[486] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_1_we = addr_hit[480] & reg_we & !reg_error; assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_2_we = addr_hit[487] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_2_we = addr_hit[481] & reg_we & !reg_error; assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_3_we = addr_hit[488] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_3_we = addr_hit[482] & reg_we & !reg_error; assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_4_we = addr_hit[489] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_4_we = addr_hit[483] & reg_we & !reg_error; assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_5_we = addr_hit[490] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_5_we = addr_hit[484] & reg_we & !reg_error; assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_6_we = addr_hit[491] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_6_we = addr_hit[485] & reg_we & !reg_error; assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_7_we = addr_hit[492] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_7_we = addr_hit[486] & reg_we & !reg_error; assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_8_we = addr_hit[493] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_8_we = addr_hit[487] & reg_we & !reg_error; assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_9_we = addr_hit[494] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_9_we = addr_hit[488] & reg_we & !reg_error; assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_10_we = addr_hit[495] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_10_we = addr_hit[489] & reg_we & !reg_error; assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_11_we = addr_hit[496] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_11_we = addr_hit[490] & reg_we & !reg_error; assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_12_we = addr_hit[497] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_12_we = addr_hit[491] & reg_we & !reg_error; assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_13_we = addr_hit[498] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_13_we = addr_hit[492] & reg_we & !reg_error; assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_14_we = addr_hit[499] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_14_we = addr_hit[493] & reg_we & !reg_error; assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_15_we = addr_hit[500] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_15_we = addr_hit[494] & reg_we & !reg_error; assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign dio_pad_sleep_en_0_we = addr_hit[501] & reg_we & !reg_error; + assign dio_pad_sleep_en_0_we = addr_hit[495] & reg_we & !reg_error; assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_pad_sleep_en_1_we = addr_hit[502] & reg_we & !reg_error; + assign dio_pad_sleep_en_1_we = addr_hit[496] & reg_we & !reg_error; assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_pad_sleep_en_2_we = addr_hit[503] & reg_we & !reg_error; + assign dio_pad_sleep_en_2_we = addr_hit[497] & reg_we & !reg_error; assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_pad_sleep_en_3_we = addr_hit[504] & reg_we & !reg_error; + assign dio_pad_sleep_en_3_we = addr_hit[498] & reg_we & !reg_error; assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_pad_sleep_en_4_we = addr_hit[505] & reg_we & !reg_error; + assign dio_pad_sleep_en_4_we = addr_hit[499] & reg_we & !reg_error; assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_pad_sleep_en_5_we = addr_hit[506] & reg_we & !reg_error; + assign dio_pad_sleep_en_5_we = addr_hit[500] & reg_we & !reg_error; assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_pad_sleep_en_6_we = addr_hit[507] & reg_we & !reg_error; + assign dio_pad_sleep_en_6_we = addr_hit[501] & reg_we & !reg_error; assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_pad_sleep_en_7_we = addr_hit[508] & reg_we & !reg_error; + assign dio_pad_sleep_en_7_we = addr_hit[502] & reg_we & !reg_error; assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_pad_sleep_en_8_we = addr_hit[509] & reg_we & !reg_error; + assign dio_pad_sleep_en_8_we = addr_hit[503] & reg_we & !reg_error; assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_pad_sleep_en_9_we = addr_hit[510] & reg_we & !reg_error; + assign dio_pad_sleep_en_9_we = addr_hit[504] & reg_we & !reg_error; assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_pad_sleep_en_10_we = addr_hit[511] & reg_we & !reg_error; + assign dio_pad_sleep_en_10_we = addr_hit[505] & reg_we & !reg_error; assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_pad_sleep_en_11_we = addr_hit[512] & reg_we & !reg_error; + assign dio_pad_sleep_en_11_we = addr_hit[506] & reg_we & !reg_error; assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_pad_sleep_en_12_we = addr_hit[513] & reg_we & !reg_error; + assign dio_pad_sleep_en_12_we = addr_hit[507] & reg_we & !reg_error; assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_pad_sleep_en_13_we = addr_hit[514] & reg_we & !reg_error; + assign dio_pad_sleep_en_13_we = addr_hit[508] & reg_we & !reg_error; assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_pad_sleep_en_14_we = addr_hit[515] & reg_we & !reg_error; + assign dio_pad_sleep_en_14_we = addr_hit[509] & reg_we & !reg_error; assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_pad_sleep_en_15_we = addr_hit[516] & reg_we & !reg_error; + assign dio_pad_sleep_en_15_we = addr_hit[510] & reg_we & !reg_error; assign dio_pad_sleep_en_15_wd = reg_wdata[0]; - assign dio_pad_sleep_mode_0_we = addr_hit[517] & reg_we & !reg_error; + assign dio_pad_sleep_mode_0_we = addr_hit[511] & reg_we & !reg_error; assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_1_we = addr_hit[518] & reg_we & !reg_error; + assign dio_pad_sleep_mode_1_we = addr_hit[512] & reg_we & !reg_error; assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_2_we = addr_hit[519] & reg_we & !reg_error; + assign dio_pad_sleep_mode_2_we = addr_hit[513] & reg_we & !reg_error; assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_3_we = addr_hit[520] & reg_we & !reg_error; + assign dio_pad_sleep_mode_3_we = addr_hit[514] & reg_we & !reg_error; assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_4_we = addr_hit[521] & reg_we & !reg_error; + assign dio_pad_sleep_mode_4_we = addr_hit[515] & reg_we & !reg_error; assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_5_we = addr_hit[522] & reg_we & !reg_error; + assign dio_pad_sleep_mode_5_we = addr_hit[516] & reg_we & !reg_error; assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_6_we = addr_hit[523] & reg_we & !reg_error; + assign dio_pad_sleep_mode_6_we = addr_hit[517] & reg_we & !reg_error; assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_7_we = addr_hit[524] & reg_we & !reg_error; + assign dio_pad_sleep_mode_7_we = addr_hit[518] & reg_we & !reg_error; assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_8_we = addr_hit[525] & reg_we & !reg_error; + assign dio_pad_sleep_mode_8_we = addr_hit[519] & reg_we & !reg_error; assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_9_we = addr_hit[526] & reg_we & !reg_error; + assign dio_pad_sleep_mode_9_we = addr_hit[520] & reg_we & !reg_error; assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_10_we = addr_hit[527] & reg_we & !reg_error; + assign dio_pad_sleep_mode_10_we = addr_hit[521] & reg_we & !reg_error; assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_11_we = addr_hit[528] & reg_we & !reg_error; + assign dio_pad_sleep_mode_11_we = addr_hit[522] & reg_we & !reg_error; assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_12_we = addr_hit[529] & reg_we & !reg_error; + assign dio_pad_sleep_mode_12_we = addr_hit[523] & reg_we & !reg_error; assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_13_we = addr_hit[530] & reg_we & !reg_error; + assign dio_pad_sleep_mode_13_we = addr_hit[524] & reg_we & !reg_error; assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_14_we = addr_hit[531] & reg_we & !reg_error; + assign dio_pad_sleep_mode_14_we = addr_hit[525] & reg_we & !reg_error; assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_15_we = addr_hit[532] & reg_we & !reg_error; + assign dio_pad_sleep_mode_15_we = addr_hit[526] & reg_we & !reg_error; assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[533] & reg_we & !reg_error; + assign wkup_detector_regwen_0_we = addr_hit[527] & reg_we & !reg_error; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[534] & reg_we & !reg_error; + assign wkup_detector_regwen_1_we = addr_hit[528] & reg_we & !reg_error; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[535] & reg_we & !reg_error; + assign wkup_detector_regwen_2_we = addr_hit[529] & reg_we & !reg_error; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[536] & reg_we & !reg_error; + assign wkup_detector_regwen_3_we = addr_hit[530] & reg_we & !reg_error; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[537] & reg_we & !reg_error; + assign wkup_detector_regwen_4_we = addr_hit[531] & reg_we & !reg_error; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[538] & reg_we & !reg_error; + assign wkup_detector_regwen_5_we = addr_hit[532] & reg_we & !reg_error; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[539] & reg_we & !reg_error; + assign wkup_detector_regwen_6_we = addr_hit[533] & reg_we & !reg_error; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[540] & reg_we & !reg_error; + assign wkup_detector_regwen_7_we = addr_hit[534] & reg_we & !reg_error; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[541] & reg_we & !reg_error; + assign wkup_detector_en_0_we = addr_hit[535] & reg_we & !reg_error; - assign wkup_detector_en_1_we = addr_hit[542] & reg_we & !reg_error; + assign wkup_detector_en_1_we = addr_hit[536] & reg_we & !reg_error; - assign wkup_detector_en_2_we = addr_hit[543] & reg_we & !reg_error; + assign wkup_detector_en_2_we = addr_hit[537] & reg_we & !reg_error; - assign wkup_detector_en_3_we = addr_hit[544] & reg_we & !reg_error; + assign wkup_detector_en_3_we = addr_hit[538] & reg_we & !reg_error; - assign wkup_detector_en_4_we = addr_hit[545] & reg_we & !reg_error; + assign wkup_detector_en_4_we = addr_hit[539] & reg_we & !reg_error; - assign wkup_detector_en_5_we = addr_hit[546] & reg_we & !reg_error; + assign wkup_detector_en_5_we = addr_hit[540] & reg_we & !reg_error; - assign wkup_detector_en_6_we = addr_hit[547] & reg_we & !reg_error; + assign wkup_detector_en_6_we = addr_hit[541] & reg_we & !reg_error; - assign wkup_detector_en_7_we = addr_hit[548] & reg_we & !reg_error; + assign wkup_detector_en_7_we = addr_hit[542] & reg_we & !reg_error; - assign wkup_detector_0_we = addr_hit[549] & reg_we & !reg_error; + assign wkup_detector_0_we = addr_hit[543] & reg_we & !reg_error; - assign wkup_detector_1_we = addr_hit[550] & reg_we & !reg_error; + assign wkup_detector_1_we = addr_hit[544] & reg_we & !reg_error; - assign wkup_detector_2_we = addr_hit[551] & reg_we & !reg_error; + assign wkup_detector_2_we = addr_hit[545] & reg_we & !reg_error; - assign wkup_detector_3_we = addr_hit[552] & reg_we & !reg_error; + assign wkup_detector_3_we = addr_hit[546] & reg_we & !reg_error; - assign wkup_detector_4_we = addr_hit[553] & reg_we & !reg_error; + assign wkup_detector_4_we = addr_hit[547] & reg_we & !reg_error; - assign wkup_detector_5_we = addr_hit[554] & reg_we & !reg_error; + assign wkup_detector_5_we = addr_hit[548] & reg_we & !reg_error; - assign wkup_detector_6_we = addr_hit[555] & reg_we & !reg_error; + assign wkup_detector_6_we = addr_hit[549] & reg_we & !reg_error; - assign wkup_detector_7_we = addr_hit[556] & reg_we & !reg_error; + assign wkup_detector_7_we = addr_hit[550] & reg_we & !reg_error; - assign wkup_detector_cnt_th_0_we = addr_hit[557] & reg_we & !reg_error; + assign wkup_detector_cnt_th_0_we = addr_hit[551] & reg_we & !reg_error; - assign wkup_detector_cnt_th_1_we = addr_hit[558] & reg_we & !reg_error; + assign wkup_detector_cnt_th_1_we = addr_hit[552] & reg_we & !reg_error; - assign wkup_detector_cnt_th_2_we = addr_hit[559] & reg_we & !reg_error; + assign wkup_detector_cnt_th_2_we = addr_hit[553] & reg_we & !reg_error; - assign wkup_detector_cnt_th_3_we = addr_hit[560] & reg_we & !reg_error; + assign wkup_detector_cnt_th_3_we = addr_hit[554] & reg_we & !reg_error; - assign wkup_detector_cnt_th_4_we = addr_hit[561] & reg_we & !reg_error; + assign wkup_detector_cnt_th_4_we = addr_hit[555] & reg_we & !reg_error; - assign wkup_detector_cnt_th_5_we = addr_hit[562] & reg_we & !reg_error; + assign wkup_detector_cnt_th_5_we = addr_hit[556] & reg_we & !reg_error; - assign wkup_detector_cnt_th_6_we = addr_hit[563] & reg_we & !reg_error; + assign wkup_detector_cnt_th_6_we = addr_hit[557] & reg_we & !reg_error; - assign wkup_detector_cnt_th_7_we = addr_hit[564] & reg_we & !reg_error; + assign wkup_detector_cnt_th_7_we = addr_hit[558] & reg_we & !reg_error; - assign wkup_detector_padsel_0_we = addr_hit[565] & reg_we & !reg_error; + assign wkup_detector_padsel_0_we = addr_hit[559] & reg_we & !reg_error; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[566] & reg_we & !reg_error; + assign wkup_detector_padsel_1_we = addr_hit[560] & reg_we & !reg_error; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[567] & reg_we & !reg_error; + assign wkup_detector_padsel_2_we = addr_hit[561] & reg_we & !reg_error; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[568] & reg_we & !reg_error; + assign wkup_detector_padsel_3_we = addr_hit[562] & reg_we & !reg_error; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[569] & reg_we & !reg_error; + assign wkup_detector_padsel_4_we = addr_hit[563] & reg_we & !reg_error; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[570] & reg_we & !reg_error; + assign wkup_detector_padsel_5_we = addr_hit[564] & reg_we & !reg_error; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[571] & reg_we & !reg_error; + assign wkup_detector_padsel_6_we = addr_hit[565] & reg_we & !reg_error; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[572] & reg_we & !reg_error; + assign wkup_detector_padsel_7_we = addr_hit[566] & reg_we & !reg_error; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_we = addr_hit[573] & reg_we & !reg_error; + assign wkup_cause_we = addr_hit[567] & reg_we & !reg_error; @@ -36986,522 +36755,516 @@ module pinmux_reg_top ( reg_we_check[55] = mio_periph_insel_regwen_54_we; reg_we_check[56] = mio_periph_insel_regwen_55_we; reg_we_check[57] = mio_periph_insel_regwen_56_we; - reg_we_check[58] = mio_periph_insel_regwen_57_we; - reg_we_check[59] = mio_periph_insel_regwen_58_we; - reg_we_check[60] = mio_periph_insel_regwen_59_we; - reg_we_check[61] = mio_periph_insel_0_gated_we; - reg_we_check[62] = mio_periph_insel_1_gated_we; - reg_we_check[63] = mio_periph_insel_2_gated_we; - reg_we_check[64] = mio_periph_insel_3_gated_we; - reg_we_check[65] = mio_periph_insel_4_gated_we; - reg_we_check[66] = mio_periph_insel_5_gated_we; - reg_we_check[67] = mio_periph_insel_6_gated_we; - reg_we_check[68] = mio_periph_insel_7_gated_we; - reg_we_check[69] = mio_periph_insel_8_gated_we; - reg_we_check[70] = mio_periph_insel_9_gated_we; - reg_we_check[71] = mio_periph_insel_10_gated_we; - reg_we_check[72] = mio_periph_insel_11_gated_we; - reg_we_check[73] = mio_periph_insel_12_gated_we; - reg_we_check[74] = mio_periph_insel_13_gated_we; - reg_we_check[75] = mio_periph_insel_14_gated_we; - reg_we_check[76] = mio_periph_insel_15_gated_we; - reg_we_check[77] = mio_periph_insel_16_gated_we; - reg_we_check[78] = mio_periph_insel_17_gated_we; - reg_we_check[79] = mio_periph_insel_18_gated_we; - reg_we_check[80] = mio_periph_insel_19_gated_we; - reg_we_check[81] = mio_periph_insel_20_gated_we; - reg_we_check[82] = mio_periph_insel_21_gated_we; - reg_we_check[83] = mio_periph_insel_22_gated_we; - reg_we_check[84] = mio_periph_insel_23_gated_we; - reg_we_check[85] = mio_periph_insel_24_gated_we; - reg_we_check[86] = mio_periph_insel_25_gated_we; - reg_we_check[87] = mio_periph_insel_26_gated_we; - reg_we_check[88] = mio_periph_insel_27_gated_we; - reg_we_check[89] = mio_periph_insel_28_gated_we; - reg_we_check[90] = mio_periph_insel_29_gated_we; - reg_we_check[91] = mio_periph_insel_30_gated_we; - reg_we_check[92] = mio_periph_insel_31_gated_we; - reg_we_check[93] = mio_periph_insel_32_gated_we; - reg_we_check[94] = mio_periph_insel_33_gated_we; - reg_we_check[95] = mio_periph_insel_34_gated_we; - reg_we_check[96] = mio_periph_insel_35_gated_we; - reg_we_check[97] = mio_periph_insel_36_gated_we; - reg_we_check[98] = mio_periph_insel_37_gated_we; - reg_we_check[99] = mio_periph_insel_38_gated_we; - reg_we_check[100] = mio_periph_insel_39_gated_we; - reg_we_check[101] = mio_periph_insel_40_gated_we; - reg_we_check[102] = mio_periph_insel_41_gated_we; - reg_we_check[103] = mio_periph_insel_42_gated_we; - reg_we_check[104] = mio_periph_insel_43_gated_we; - reg_we_check[105] = mio_periph_insel_44_gated_we; - reg_we_check[106] = mio_periph_insel_45_gated_we; - reg_we_check[107] = mio_periph_insel_46_gated_we; - reg_we_check[108] = mio_periph_insel_47_gated_we; - reg_we_check[109] = mio_periph_insel_48_gated_we; - reg_we_check[110] = mio_periph_insel_49_gated_we; - reg_we_check[111] = mio_periph_insel_50_gated_we; - reg_we_check[112] = mio_periph_insel_51_gated_we; - reg_we_check[113] = mio_periph_insel_52_gated_we; - reg_we_check[114] = mio_periph_insel_53_gated_we; - reg_we_check[115] = mio_periph_insel_54_gated_we; - reg_we_check[116] = mio_periph_insel_55_gated_we; - reg_we_check[117] = mio_periph_insel_56_gated_we; - reg_we_check[118] = mio_periph_insel_57_gated_we; - reg_we_check[119] = mio_periph_insel_58_gated_we; - reg_we_check[120] = mio_periph_insel_59_gated_we; - reg_we_check[121] = mio_outsel_regwen_0_we; - reg_we_check[122] = mio_outsel_regwen_1_we; - reg_we_check[123] = mio_outsel_regwen_2_we; - reg_we_check[124] = mio_outsel_regwen_3_we; - reg_we_check[125] = mio_outsel_regwen_4_we; - reg_we_check[126] = mio_outsel_regwen_5_we; - reg_we_check[127] = mio_outsel_regwen_6_we; - reg_we_check[128] = mio_outsel_regwen_7_we; - reg_we_check[129] = mio_outsel_regwen_8_we; - reg_we_check[130] = mio_outsel_regwen_9_we; - reg_we_check[131] = mio_outsel_regwen_10_we; - reg_we_check[132] = mio_outsel_regwen_11_we; - reg_we_check[133] = mio_outsel_regwen_12_we; - reg_we_check[134] = mio_outsel_regwen_13_we; - reg_we_check[135] = mio_outsel_regwen_14_we; - reg_we_check[136] = mio_outsel_regwen_15_we; - reg_we_check[137] = mio_outsel_regwen_16_we; - reg_we_check[138] = mio_outsel_regwen_17_we; - reg_we_check[139] = mio_outsel_regwen_18_we; - reg_we_check[140] = mio_outsel_regwen_19_we; - reg_we_check[141] = mio_outsel_regwen_20_we; - reg_we_check[142] = mio_outsel_regwen_21_we; - reg_we_check[143] = mio_outsel_regwen_22_we; - reg_we_check[144] = mio_outsel_regwen_23_we; - reg_we_check[145] = mio_outsel_regwen_24_we; - reg_we_check[146] = mio_outsel_regwen_25_we; - reg_we_check[147] = mio_outsel_regwen_26_we; - reg_we_check[148] = mio_outsel_regwen_27_we; - reg_we_check[149] = mio_outsel_regwen_28_we; - reg_we_check[150] = mio_outsel_regwen_29_we; - reg_we_check[151] = mio_outsel_regwen_30_we; - reg_we_check[152] = mio_outsel_regwen_31_we; - reg_we_check[153] = mio_outsel_regwen_32_we; - reg_we_check[154] = mio_outsel_regwen_33_we; - reg_we_check[155] = mio_outsel_regwen_34_we; - reg_we_check[156] = mio_outsel_regwen_35_we; - reg_we_check[157] = mio_outsel_regwen_36_we; - reg_we_check[158] = mio_outsel_regwen_37_we; - reg_we_check[159] = mio_outsel_regwen_38_we; - reg_we_check[160] = mio_outsel_regwen_39_we; - reg_we_check[161] = mio_outsel_regwen_40_we; - reg_we_check[162] = mio_outsel_regwen_41_we; - reg_we_check[163] = mio_outsel_regwen_42_we; - reg_we_check[164] = mio_outsel_regwen_43_we; - reg_we_check[165] = mio_outsel_regwen_44_we; - reg_we_check[166] = mio_outsel_regwen_45_we; - reg_we_check[167] = mio_outsel_regwen_46_we; - reg_we_check[168] = mio_outsel_0_gated_we; - reg_we_check[169] = mio_outsel_1_gated_we; - reg_we_check[170] = mio_outsel_2_gated_we; - reg_we_check[171] = mio_outsel_3_gated_we; - reg_we_check[172] = mio_outsel_4_gated_we; - reg_we_check[173] = mio_outsel_5_gated_we; - reg_we_check[174] = mio_outsel_6_gated_we; - reg_we_check[175] = mio_outsel_7_gated_we; - reg_we_check[176] = mio_outsel_8_gated_we; - reg_we_check[177] = mio_outsel_9_gated_we; - reg_we_check[178] = mio_outsel_10_gated_we; - reg_we_check[179] = mio_outsel_11_gated_we; - reg_we_check[180] = mio_outsel_12_gated_we; - reg_we_check[181] = mio_outsel_13_gated_we; - reg_we_check[182] = mio_outsel_14_gated_we; - reg_we_check[183] = mio_outsel_15_gated_we; - reg_we_check[184] = mio_outsel_16_gated_we; - reg_we_check[185] = mio_outsel_17_gated_we; - reg_we_check[186] = mio_outsel_18_gated_we; - reg_we_check[187] = mio_outsel_19_gated_we; - reg_we_check[188] = mio_outsel_20_gated_we; - reg_we_check[189] = mio_outsel_21_gated_we; - reg_we_check[190] = mio_outsel_22_gated_we; - reg_we_check[191] = mio_outsel_23_gated_we; - reg_we_check[192] = mio_outsel_24_gated_we; - reg_we_check[193] = mio_outsel_25_gated_we; - reg_we_check[194] = mio_outsel_26_gated_we; - reg_we_check[195] = mio_outsel_27_gated_we; - reg_we_check[196] = mio_outsel_28_gated_we; - reg_we_check[197] = mio_outsel_29_gated_we; - reg_we_check[198] = mio_outsel_30_gated_we; - reg_we_check[199] = mio_outsel_31_gated_we; - reg_we_check[200] = mio_outsel_32_gated_we; - reg_we_check[201] = mio_outsel_33_gated_we; - reg_we_check[202] = mio_outsel_34_gated_we; - reg_we_check[203] = mio_outsel_35_gated_we; - reg_we_check[204] = mio_outsel_36_gated_we; - reg_we_check[205] = mio_outsel_37_gated_we; - reg_we_check[206] = mio_outsel_38_gated_we; - reg_we_check[207] = mio_outsel_39_gated_we; - reg_we_check[208] = mio_outsel_40_gated_we; - reg_we_check[209] = mio_outsel_41_gated_we; - reg_we_check[210] = mio_outsel_42_gated_we; - reg_we_check[211] = mio_outsel_43_gated_we; - reg_we_check[212] = mio_outsel_44_gated_we; - reg_we_check[213] = mio_outsel_45_gated_we; - reg_we_check[214] = mio_outsel_46_gated_we; - reg_we_check[215] = mio_pad_attr_regwen_0_we; - reg_we_check[216] = mio_pad_attr_regwen_1_we; - reg_we_check[217] = mio_pad_attr_regwen_2_we; - reg_we_check[218] = mio_pad_attr_regwen_3_we; - reg_we_check[219] = mio_pad_attr_regwen_4_we; - reg_we_check[220] = mio_pad_attr_regwen_5_we; - reg_we_check[221] = mio_pad_attr_regwen_6_we; - reg_we_check[222] = mio_pad_attr_regwen_7_we; - reg_we_check[223] = mio_pad_attr_regwen_8_we; - reg_we_check[224] = mio_pad_attr_regwen_9_we; - reg_we_check[225] = mio_pad_attr_regwen_10_we; - reg_we_check[226] = mio_pad_attr_regwen_11_we; - reg_we_check[227] = mio_pad_attr_regwen_12_we; - reg_we_check[228] = mio_pad_attr_regwen_13_we; - reg_we_check[229] = mio_pad_attr_regwen_14_we; - reg_we_check[230] = mio_pad_attr_regwen_15_we; - reg_we_check[231] = mio_pad_attr_regwen_16_we; - reg_we_check[232] = mio_pad_attr_regwen_17_we; - reg_we_check[233] = mio_pad_attr_regwen_18_we; - reg_we_check[234] = mio_pad_attr_regwen_19_we; - reg_we_check[235] = mio_pad_attr_regwen_20_we; - reg_we_check[236] = mio_pad_attr_regwen_21_we; - reg_we_check[237] = mio_pad_attr_regwen_22_we; - reg_we_check[238] = mio_pad_attr_regwen_23_we; - reg_we_check[239] = mio_pad_attr_regwen_24_we; - reg_we_check[240] = mio_pad_attr_regwen_25_we; - reg_we_check[241] = mio_pad_attr_regwen_26_we; - reg_we_check[242] = mio_pad_attr_regwen_27_we; - reg_we_check[243] = mio_pad_attr_regwen_28_we; - reg_we_check[244] = mio_pad_attr_regwen_29_we; - reg_we_check[245] = mio_pad_attr_regwen_30_we; - reg_we_check[246] = mio_pad_attr_regwen_31_we; - reg_we_check[247] = mio_pad_attr_regwen_32_we; - reg_we_check[248] = mio_pad_attr_regwen_33_we; - reg_we_check[249] = mio_pad_attr_regwen_34_we; - reg_we_check[250] = mio_pad_attr_regwen_35_we; - reg_we_check[251] = mio_pad_attr_regwen_36_we; - reg_we_check[252] = mio_pad_attr_regwen_37_we; - reg_we_check[253] = mio_pad_attr_regwen_38_we; - reg_we_check[254] = mio_pad_attr_regwen_39_we; - reg_we_check[255] = mio_pad_attr_regwen_40_we; - reg_we_check[256] = mio_pad_attr_regwen_41_we; - reg_we_check[257] = mio_pad_attr_regwen_42_we; - reg_we_check[258] = mio_pad_attr_regwen_43_we; - reg_we_check[259] = mio_pad_attr_regwen_44_we; - reg_we_check[260] = mio_pad_attr_regwen_45_we; - reg_we_check[261] = mio_pad_attr_regwen_46_we; - reg_we_check[262] = mio_pad_attr_0_gated_we; - reg_we_check[263] = mio_pad_attr_1_gated_we; - reg_we_check[264] = mio_pad_attr_2_gated_we; - reg_we_check[265] = mio_pad_attr_3_gated_we; - reg_we_check[266] = mio_pad_attr_4_gated_we; - reg_we_check[267] = mio_pad_attr_5_gated_we; - reg_we_check[268] = mio_pad_attr_6_gated_we; - reg_we_check[269] = mio_pad_attr_7_gated_we; - reg_we_check[270] = mio_pad_attr_8_gated_we; - reg_we_check[271] = mio_pad_attr_9_gated_we; - reg_we_check[272] = mio_pad_attr_10_gated_we; - reg_we_check[273] = mio_pad_attr_11_gated_we; - reg_we_check[274] = mio_pad_attr_12_gated_we; - reg_we_check[275] = mio_pad_attr_13_gated_we; - reg_we_check[276] = mio_pad_attr_14_gated_we; - reg_we_check[277] = mio_pad_attr_15_gated_we; - reg_we_check[278] = mio_pad_attr_16_gated_we; - reg_we_check[279] = mio_pad_attr_17_gated_we; - reg_we_check[280] = mio_pad_attr_18_gated_we; - reg_we_check[281] = mio_pad_attr_19_gated_we; - reg_we_check[282] = mio_pad_attr_20_gated_we; - reg_we_check[283] = mio_pad_attr_21_gated_we; - reg_we_check[284] = mio_pad_attr_22_gated_we; - reg_we_check[285] = mio_pad_attr_23_gated_we; - reg_we_check[286] = mio_pad_attr_24_gated_we; - reg_we_check[287] = mio_pad_attr_25_gated_we; - reg_we_check[288] = mio_pad_attr_26_gated_we; - reg_we_check[289] = mio_pad_attr_27_gated_we; - reg_we_check[290] = mio_pad_attr_28_gated_we; - reg_we_check[291] = mio_pad_attr_29_gated_we; - reg_we_check[292] = mio_pad_attr_30_gated_we; - reg_we_check[293] = mio_pad_attr_31_gated_we; - reg_we_check[294] = mio_pad_attr_32_gated_we; - reg_we_check[295] = mio_pad_attr_33_gated_we; - reg_we_check[296] = mio_pad_attr_34_gated_we; - reg_we_check[297] = mio_pad_attr_35_gated_we; - reg_we_check[298] = mio_pad_attr_36_gated_we; - reg_we_check[299] = mio_pad_attr_37_gated_we; - reg_we_check[300] = mio_pad_attr_38_gated_we; - reg_we_check[301] = mio_pad_attr_39_gated_we; - reg_we_check[302] = mio_pad_attr_40_gated_we; - reg_we_check[303] = mio_pad_attr_41_gated_we; - reg_we_check[304] = mio_pad_attr_42_gated_we; - reg_we_check[305] = mio_pad_attr_43_gated_we; - reg_we_check[306] = mio_pad_attr_44_gated_we; - reg_we_check[307] = mio_pad_attr_45_gated_we; - reg_we_check[308] = mio_pad_attr_46_gated_we; - reg_we_check[309] = dio_pad_attr_regwen_0_we; - reg_we_check[310] = dio_pad_attr_regwen_1_we; - reg_we_check[311] = dio_pad_attr_regwen_2_we; - reg_we_check[312] = dio_pad_attr_regwen_3_we; - reg_we_check[313] = dio_pad_attr_regwen_4_we; - reg_we_check[314] = dio_pad_attr_regwen_5_we; - reg_we_check[315] = dio_pad_attr_regwen_6_we; - reg_we_check[316] = dio_pad_attr_regwen_7_we; - reg_we_check[317] = dio_pad_attr_regwen_8_we; - reg_we_check[318] = dio_pad_attr_regwen_9_we; - reg_we_check[319] = dio_pad_attr_regwen_10_we; - reg_we_check[320] = dio_pad_attr_regwen_11_we; - reg_we_check[321] = dio_pad_attr_regwen_12_we; - reg_we_check[322] = dio_pad_attr_regwen_13_we; - reg_we_check[323] = dio_pad_attr_regwen_14_we; - reg_we_check[324] = dio_pad_attr_regwen_15_we; - reg_we_check[325] = dio_pad_attr_0_gated_we; - reg_we_check[326] = dio_pad_attr_1_gated_we; - reg_we_check[327] = dio_pad_attr_2_gated_we; - reg_we_check[328] = dio_pad_attr_3_gated_we; - reg_we_check[329] = dio_pad_attr_4_gated_we; - reg_we_check[330] = dio_pad_attr_5_gated_we; - reg_we_check[331] = dio_pad_attr_6_gated_we; - reg_we_check[332] = dio_pad_attr_7_gated_we; - reg_we_check[333] = dio_pad_attr_8_gated_we; - reg_we_check[334] = dio_pad_attr_9_gated_we; - reg_we_check[335] = dio_pad_attr_10_gated_we; - reg_we_check[336] = dio_pad_attr_11_gated_we; - reg_we_check[337] = dio_pad_attr_12_gated_we; - reg_we_check[338] = dio_pad_attr_13_gated_we; - reg_we_check[339] = dio_pad_attr_14_gated_we; - reg_we_check[340] = dio_pad_attr_15_gated_we; - reg_we_check[341] = mio_pad_sleep_status_0_we; - reg_we_check[342] = mio_pad_sleep_status_1_we; - reg_we_check[343] = mio_pad_sleep_regwen_0_we; - reg_we_check[344] = mio_pad_sleep_regwen_1_we; - reg_we_check[345] = mio_pad_sleep_regwen_2_we; - reg_we_check[346] = mio_pad_sleep_regwen_3_we; - reg_we_check[347] = mio_pad_sleep_regwen_4_we; - reg_we_check[348] = mio_pad_sleep_regwen_5_we; - reg_we_check[349] = mio_pad_sleep_regwen_6_we; - reg_we_check[350] = mio_pad_sleep_regwen_7_we; - reg_we_check[351] = mio_pad_sleep_regwen_8_we; - reg_we_check[352] = mio_pad_sleep_regwen_9_we; - reg_we_check[353] = mio_pad_sleep_regwen_10_we; - reg_we_check[354] = mio_pad_sleep_regwen_11_we; - reg_we_check[355] = mio_pad_sleep_regwen_12_we; - reg_we_check[356] = mio_pad_sleep_regwen_13_we; - reg_we_check[357] = mio_pad_sleep_regwen_14_we; - reg_we_check[358] = mio_pad_sleep_regwen_15_we; - reg_we_check[359] = mio_pad_sleep_regwen_16_we; - reg_we_check[360] = mio_pad_sleep_regwen_17_we; - reg_we_check[361] = mio_pad_sleep_regwen_18_we; - reg_we_check[362] = mio_pad_sleep_regwen_19_we; - reg_we_check[363] = mio_pad_sleep_regwen_20_we; - reg_we_check[364] = mio_pad_sleep_regwen_21_we; - reg_we_check[365] = mio_pad_sleep_regwen_22_we; - reg_we_check[366] = mio_pad_sleep_regwen_23_we; - reg_we_check[367] = mio_pad_sleep_regwen_24_we; - reg_we_check[368] = mio_pad_sleep_regwen_25_we; - reg_we_check[369] = mio_pad_sleep_regwen_26_we; - reg_we_check[370] = mio_pad_sleep_regwen_27_we; - reg_we_check[371] = mio_pad_sleep_regwen_28_we; - reg_we_check[372] = mio_pad_sleep_regwen_29_we; - reg_we_check[373] = mio_pad_sleep_regwen_30_we; - reg_we_check[374] = mio_pad_sleep_regwen_31_we; - reg_we_check[375] = mio_pad_sleep_regwen_32_we; - reg_we_check[376] = mio_pad_sleep_regwen_33_we; - reg_we_check[377] = mio_pad_sleep_regwen_34_we; - reg_we_check[378] = mio_pad_sleep_regwen_35_we; - reg_we_check[379] = mio_pad_sleep_regwen_36_we; - reg_we_check[380] = mio_pad_sleep_regwen_37_we; - reg_we_check[381] = mio_pad_sleep_regwen_38_we; - reg_we_check[382] = mio_pad_sleep_regwen_39_we; - reg_we_check[383] = mio_pad_sleep_regwen_40_we; - reg_we_check[384] = mio_pad_sleep_regwen_41_we; - reg_we_check[385] = mio_pad_sleep_regwen_42_we; - reg_we_check[386] = mio_pad_sleep_regwen_43_we; - reg_we_check[387] = mio_pad_sleep_regwen_44_we; - reg_we_check[388] = mio_pad_sleep_regwen_45_we; - reg_we_check[389] = mio_pad_sleep_regwen_46_we; - reg_we_check[390] = mio_pad_sleep_en_0_gated_we; - reg_we_check[391] = mio_pad_sleep_en_1_gated_we; - reg_we_check[392] = mio_pad_sleep_en_2_gated_we; - reg_we_check[393] = mio_pad_sleep_en_3_gated_we; - reg_we_check[394] = mio_pad_sleep_en_4_gated_we; - reg_we_check[395] = mio_pad_sleep_en_5_gated_we; - reg_we_check[396] = mio_pad_sleep_en_6_gated_we; - reg_we_check[397] = mio_pad_sleep_en_7_gated_we; - reg_we_check[398] = mio_pad_sleep_en_8_gated_we; - reg_we_check[399] = mio_pad_sleep_en_9_gated_we; - reg_we_check[400] = mio_pad_sleep_en_10_gated_we; - reg_we_check[401] = mio_pad_sleep_en_11_gated_we; - reg_we_check[402] = mio_pad_sleep_en_12_gated_we; - reg_we_check[403] = mio_pad_sleep_en_13_gated_we; - reg_we_check[404] = mio_pad_sleep_en_14_gated_we; - reg_we_check[405] = mio_pad_sleep_en_15_gated_we; - reg_we_check[406] = mio_pad_sleep_en_16_gated_we; - reg_we_check[407] = mio_pad_sleep_en_17_gated_we; - reg_we_check[408] = mio_pad_sleep_en_18_gated_we; - reg_we_check[409] = mio_pad_sleep_en_19_gated_we; - reg_we_check[410] = mio_pad_sleep_en_20_gated_we; - reg_we_check[411] = mio_pad_sleep_en_21_gated_we; - reg_we_check[412] = mio_pad_sleep_en_22_gated_we; - reg_we_check[413] = mio_pad_sleep_en_23_gated_we; - reg_we_check[414] = mio_pad_sleep_en_24_gated_we; - reg_we_check[415] = mio_pad_sleep_en_25_gated_we; - reg_we_check[416] = mio_pad_sleep_en_26_gated_we; - reg_we_check[417] = mio_pad_sleep_en_27_gated_we; - reg_we_check[418] = mio_pad_sleep_en_28_gated_we; - reg_we_check[419] = mio_pad_sleep_en_29_gated_we; - reg_we_check[420] = mio_pad_sleep_en_30_gated_we; - reg_we_check[421] = mio_pad_sleep_en_31_gated_we; - reg_we_check[422] = mio_pad_sleep_en_32_gated_we; - reg_we_check[423] = mio_pad_sleep_en_33_gated_we; - reg_we_check[424] = mio_pad_sleep_en_34_gated_we; - reg_we_check[425] = mio_pad_sleep_en_35_gated_we; - reg_we_check[426] = mio_pad_sleep_en_36_gated_we; - reg_we_check[427] = mio_pad_sleep_en_37_gated_we; - reg_we_check[428] = mio_pad_sleep_en_38_gated_we; - reg_we_check[429] = mio_pad_sleep_en_39_gated_we; - reg_we_check[430] = mio_pad_sleep_en_40_gated_we; - reg_we_check[431] = mio_pad_sleep_en_41_gated_we; - reg_we_check[432] = mio_pad_sleep_en_42_gated_we; - reg_we_check[433] = mio_pad_sleep_en_43_gated_we; - reg_we_check[434] = mio_pad_sleep_en_44_gated_we; - reg_we_check[435] = mio_pad_sleep_en_45_gated_we; - reg_we_check[436] = mio_pad_sleep_en_46_gated_we; - reg_we_check[437] = mio_pad_sleep_mode_0_gated_we; - reg_we_check[438] = mio_pad_sleep_mode_1_gated_we; - reg_we_check[439] = mio_pad_sleep_mode_2_gated_we; - reg_we_check[440] = mio_pad_sleep_mode_3_gated_we; - reg_we_check[441] = mio_pad_sleep_mode_4_gated_we; - reg_we_check[442] = mio_pad_sleep_mode_5_gated_we; - reg_we_check[443] = mio_pad_sleep_mode_6_gated_we; - reg_we_check[444] = mio_pad_sleep_mode_7_gated_we; - reg_we_check[445] = mio_pad_sleep_mode_8_gated_we; - reg_we_check[446] = mio_pad_sleep_mode_9_gated_we; - reg_we_check[447] = mio_pad_sleep_mode_10_gated_we; - reg_we_check[448] = mio_pad_sleep_mode_11_gated_we; - reg_we_check[449] = mio_pad_sleep_mode_12_gated_we; - reg_we_check[450] = mio_pad_sleep_mode_13_gated_we; - reg_we_check[451] = mio_pad_sleep_mode_14_gated_we; - reg_we_check[452] = mio_pad_sleep_mode_15_gated_we; - reg_we_check[453] = mio_pad_sleep_mode_16_gated_we; - reg_we_check[454] = mio_pad_sleep_mode_17_gated_we; - reg_we_check[455] = mio_pad_sleep_mode_18_gated_we; - reg_we_check[456] = mio_pad_sleep_mode_19_gated_we; - reg_we_check[457] = mio_pad_sleep_mode_20_gated_we; - reg_we_check[458] = mio_pad_sleep_mode_21_gated_we; - reg_we_check[459] = mio_pad_sleep_mode_22_gated_we; - reg_we_check[460] = mio_pad_sleep_mode_23_gated_we; - reg_we_check[461] = mio_pad_sleep_mode_24_gated_we; - reg_we_check[462] = mio_pad_sleep_mode_25_gated_we; - reg_we_check[463] = mio_pad_sleep_mode_26_gated_we; - reg_we_check[464] = mio_pad_sleep_mode_27_gated_we; - reg_we_check[465] = mio_pad_sleep_mode_28_gated_we; - reg_we_check[466] = mio_pad_sleep_mode_29_gated_we; - reg_we_check[467] = mio_pad_sleep_mode_30_gated_we; - reg_we_check[468] = mio_pad_sleep_mode_31_gated_we; - reg_we_check[469] = mio_pad_sleep_mode_32_gated_we; - reg_we_check[470] = mio_pad_sleep_mode_33_gated_we; - reg_we_check[471] = mio_pad_sleep_mode_34_gated_we; - reg_we_check[472] = mio_pad_sleep_mode_35_gated_we; - reg_we_check[473] = mio_pad_sleep_mode_36_gated_we; - reg_we_check[474] = mio_pad_sleep_mode_37_gated_we; - reg_we_check[475] = mio_pad_sleep_mode_38_gated_we; - reg_we_check[476] = mio_pad_sleep_mode_39_gated_we; - reg_we_check[477] = mio_pad_sleep_mode_40_gated_we; - reg_we_check[478] = mio_pad_sleep_mode_41_gated_we; - reg_we_check[479] = mio_pad_sleep_mode_42_gated_we; - reg_we_check[480] = mio_pad_sleep_mode_43_gated_we; - reg_we_check[481] = mio_pad_sleep_mode_44_gated_we; - reg_we_check[482] = mio_pad_sleep_mode_45_gated_we; - reg_we_check[483] = mio_pad_sleep_mode_46_gated_we; - reg_we_check[484] = dio_pad_sleep_status_we; - reg_we_check[485] = dio_pad_sleep_regwen_0_we; - reg_we_check[486] = dio_pad_sleep_regwen_1_we; - reg_we_check[487] = dio_pad_sleep_regwen_2_we; - reg_we_check[488] = dio_pad_sleep_regwen_3_we; - reg_we_check[489] = dio_pad_sleep_regwen_4_we; - reg_we_check[490] = dio_pad_sleep_regwen_5_we; - reg_we_check[491] = dio_pad_sleep_regwen_6_we; - reg_we_check[492] = dio_pad_sleep_regwen_7_we; - reg_we_check[493] = dio_pad_sleep_regwen_8_we; - reg_we_check[494] = dio_pad_sleep_regwen_9_we; - reg_we_check[495] = dio_pad_sleep_regwen_10_we; - reg_we_check[496] = dio_pad_sleep_regwen_11_we; - reg_we_check[497] = dio_pad_sleep_regwen_12_we; - reg_we_check[498] = dio_pad_sleep_regwen_13_we; - reg_we_check[499] = dio_pad_sleep_regwen_14_we; - reg_we_check[500] = dio_pad_sleep_regwen_15_we; - reg_we_check[501] = dio_pad_sleep_en_0_gated_we; - reg_we_check[502] = dio_pad_sleep_en_1_gated_we; - reg_we_check[503] = dio_pad_sleep_en_2_gated_we; - reg_we_check[504] = dio_pad_sleep_en_3_gated_we; - reg_we_check[505] = dio_pad_sleep_en_4_gated_we; - reg_we_check[506] = dio_pad_sleep_en_5_gated_we; - reg_we_check[507] = dio_pad_sleep_en_6_gated_we; - reg_we_check[508] = dio_pad_sleep_en_7_gated_we; - reg_we_check[509] = dio_pad_sleep_en_8_gated_we; - reg_we_check[510] = dio_pad_sleep_en_9_gated_we; - reg_we_check[511] = dio_pad_sleep_en_10_gated_we; - reg_we_check[512] = dio_pad_sleep_en_11_gated_we; - reg_we_check[513] = dio_pad_sleep_en_12_gated_we; - reg_we_check[514] = dio_pad_sleep_en_13_gated_we; - reg_we_check[515] = dio_pad_sleep_en_14_gated_we; - reg_we_check[516] = dio_pad_sleep_en_15_gated_we; - reg_we_check[517] = dio_pad_sleep_mode_0_gated_we; - reg_we_check[518] = dio_pad_sleep_mode_1_gated_we; - reg_we_check[519] = dio_pad_sleep_mode_2_gated_we; - reg_we_check[520] = dio_pad_sleep_mode_3_gated_we; - reg_we_check[521] = dio_pad_sleep_mode_4_gated_we; - reg_we_check[522] = dio_pad_sleep_mode_5_gated_we; - reg_we_check[523] = dio_pad_sleep_mode_6_gated_we; - reg_we_check[524] = dio_pad_sleep_mode_7_gated_we; - reg_we_check[525] = dio_pad_sleep_mode_8_gated_we; - reg_we_check[526] = dio_pad_sleep_mode_9_gated_we; - reg_we_check[527] = dio_pad_sleep_mode_10_gated_we; - reg_we_check[528] = dio_pad_sleep_mode_11_gated_we; - reg_we_check[529] = dio_pad_sleep_mode_12_gated_we; - reg_we_check[530] = dio_pad_sleep_mode_13_gated_we; - reg_we_check[531] = dio_pad_sleep_mode_14_gated_we; - reg_we_check[532] = dio_pad_sleep_mode_15_gated_we; - reg_we_check[533] = wkup_detector_regwen_0_we; - reg_we_check[534] = wkup_detector_regwen_1_we; - reg_we_check[535] = wkup_detector_regwen_2_we; - reg_we_check[536] = wkup_detector_regwen_3_we; - reg_we_check[537] = wkup_detector_regwen_4_we; - reg_we_check[538] = wkup_detector_regwen_5_we; - reg_we_check[539] = wkup_detector_regwen_6_we; - reg_we_check[540] = wkup_detector_regwen_7_we; - reg_we_check[541] = wkup_detector_en_0_we; - reg_we_check[542] = wkup_detector_en_1_we; - reg_we_check[543] = wkup_detector_en_2_we; - reg_we_check[544] = wkup_detector_en_3_we; - reg_we_check[545] = wkup_detector_en_4_we; - reg_we_check[546] = wkup_detector_en_5_we; - reg_we_check[547] = wkup_detector_en_6_we; - reg_we_check[548] = wkup_detector_en_7_we; - reg_we_check[549] = wkup_detector_0_we; - reg_we_check[550] = wkup_detector_1_we; - reg_we_check[551] = wkup_detector_2_we; - reg_we_check[552] = wkup_detector_3_we; - reg_we_check[553] = wkup_detector_4_we; - reg_we_check[554] = wkup_detector_5_we; - reg_we_check[555] = wkup_detector_6_we; - reg_we_check[556] = wkup_detector_7_we; - reg_we_check[557] = wkup_detector_cnt_th_0_we; - reg_we_check[558] = wkup_detector_cnt_th_1_we; - reg_we_check[559] = wkup_detector_cnt_th_2_we; - reg_we_check[560] = wkup_detector_cnt_th_3_we; - reg_we_check[561] = wkup_detector_cnt_th_4_we; - reg_we_check[562] = wkup_detector_cnt_th_5_we; - reg_we_check[563] = wkup_detector_cnt_th_6_we; - reg_we_check[564] = wkup_detector_cnt_th_7_we; - reg_we_check[565] = wkup_detector_padsel_0_gated_we; - reg_we_check[566] = wkup_detector_padsel_1_gated_we; - reg_we_check[567] = wkup_detector_padsel_2_gated_we; - reg_we_check[568] = wkup_detector_padsel_3_gated_we; - reg_we_check[569] = wkup_detector_padsel_4_gated_we; - reg_we_check[570] = wkup_detector_padsel_5_gated_we; - reg_we_check[571] = wkup_detector_padsel_6_gated_we; - reg_we_check[572] = wkup_detector_padsel_7_gated_we; - reg_we_check[573] = wkup_cause_we; + reg_we_check[58] = mio_periph_insel_0_gated_we; + reg_we_check[59] = mio_periph_insel_1_gated_we; + reg_we_check[60] = mio_periph_insel_2_gated_we; + reg_we_check[61] = mio_periph_insel_3_gated_we; + reg_we_check[62] = mio_periph_insel_4_gated_we; + reg_we_check[63] = mio_periph_insel_5_gated_we; + reg_we_check[64] = mio_periph_insel_6_gated_we; + reg_we_check[65] = mio_periph_insel_7_gated_we; + reg_we_check[66] = mio_periph_insel_8_gated_we; + reg_we_check[67] = mio_periph_insel_9_gated_we; + reg_we_check[68] = mio_periph_insel_10_gated_we; + reg_we_check[69] = mio_periph_insel_11_gated_we; + reg_we_check[70] = mio_periph_insel_12_gated_we; + reg_we_check[71] = mio_periph_insel_13_gated_we; + reg_we_check[72] = mio_periph_insel_14_gated_we; + reg_we_check[73] = mio_periph_insel_15_gated_we; + reg_we_check[74] = mio_periph_insel_16_gated_we; + reg_we_check[75] = mio_periph_insel_17_gated_we; + reg_we_check[76] = mio_periph_insel_18_gated_we; + reg_we_check[77] = mio_periph_insel_19_gated_we; + reg_we_check[78] = mio_periph_insel_20_gated_we; + reg_we_check[79] = mio_periph_insel_21_gated_we; + reg_we_check[80] = mio_periph_insel_22_gated_we; + reg_we_check[81] = mio_periph_insel_23_gated_we; + reg_we_check[82] = mio_periph_insel_24_gated_we; + reg_we_check[83] = mio_periph_insel_25_gated_we; + reg_we_check[84] = mio_periph_insel_26_gated_we; + reg_we_check[85] = mio_periph_insel_27_gated_we; + reg_we_check[86] = mio_periph_insel_28_gated_we; + reg_we_check[87] = mio_periph_insel_29_gated_we; + reg_we_check[88] = mio_periph_insel_30_gated_we; + reg_we_check[89] = mio_periph_insel_31_gated_we; + reg_we_check[90] = mio_periph_insel_32_gated_we; + reg_we_check[91] = mio_periph_insel_33_gated_we; + reg_we_check[92] = mio_periph_insel_34_gated_we; + reg_we_check[93] = mio_periph_insel_35_gated_we; + reg_we_check[94] = mio_periph_insel_36_gated_we; + reg_we_check[95] = mio_periph_insel_37_gated_we; + reg_we_check[96] = mio_periph_insel_38_gated_we; + reg_we_check[97] = mio_periph_insel_39_gated_we; + reg_we_check[98] = mio_periph_insel_40_gated_we; + reg_we_check[99] = mio_periph_insel_41_gated_we; + reg_we_check[100] = mio_periph_insel_42_gated_we; + reg_we_check[101] = mio_periph_insel_43_gated_we; + reg_we_check[102] = mio_periph_insel_44_gated_we; + reg_we_check[103] = mio_periph_insel_45_gated_we; + reg_we_check[104] = mio_periph_insel_46_gated_we; + reg_we_check[105] = mio_periph_insel_47_gated_we; + reg_we_check[106] = mio_periph_insel_48_gated_we; + reg_we_check[107] = mio_periph_insel_49_gated_we; + reg_we_check[108] = mio_periph_insel_50_gated_we; + reg_we_check[109] = mio_periph_insel_51_gated_we; + reg_we_check[110] = mio_periph_insel_52_gated_we; + reg_we_check[111] = mio_periph_insel_53_gated_we; + reg_we_check[112] = mio_periph_insel_54_gated_we; + reg_we_check[113] = mio_periph_insel_55_gated_we; + reg_we_check[114] = mio_periph_insel_56_gated_we; + reg_we_check[115] = mio_outsel_regwen_0_we; + reg_we_check[116] = mio_outsel_regwen_1_we; + reg_we_check[117] = mio_outsel_regwen_2_we; + reg_we_check[118] = mio_outsel_regwen_3_we; + reg_we_check[119] = mio_outsel_regwen_4_we; + reg_we_check[120] = mio_outsel_regwen_5_we; + reg_we_check[121] = mio_outsel_regwen_6_we; + reg_we_check[122] = mio_outsel_regwen_7_we; + reg_we_check[123] = mio_outsel_regwen_8_we; + reg_we_check[124] = mio_outsel_regwen_9_we; + reg_we_check[125] = mio_outsel_regwen_10_we; + reg_we_check[126] = mio_outsel_regwen_11_we; + reg_we_check[127] = mio_outsel_regwen_12_we; + reg_we_check[128] = mio_outsel_regwen_13_we; + reg_we_check[129] = mio_outsel_regwen_14_we; + reg_we_check[130] = mio_outsel_regwen_15_we; + reg_we_check[131] = mio_outsel_regwen_16_we; + reg_we_check[132] = mio_outsel_regwen_17_we; + reg_we_check[133] = mio_outsel_regwen_18_we; + reg_we_check[134] = mio_outsel_regwen_19_we; + reg_we_check[135] = mio_outsel_regwen_20_we; + reg_we_check[136] = mio_outsel_regwen_21_we; + reg_we_check[137] = mio_outsel_regwen_22_we; + reg_we_check[138] = mio_outsel_regwen_23_we; + reg_we_check[139] = mio_outsel_regwen_24_we; + reg_we_check[140] = mio_outsel_regwen_25_we; + reg_we_check[141] = mio_outsel_regwen_26_we; + reg_we_check[142] = mio_outsel_regwen_27_we; + reg_we_check[143] = mio_outsel_regwen_28_we; + reg_we_check[144] = mio_outsel_regwen_29_we; + reg_we_check[145] = mio_outsel_regwen_30_we; + reg_we_check[146] = mio_outsel_regwen_31_we; + reg_we_check[147] = mio_outsel_regwen_32_we; + reg_we_check[148] = mio_outsel_regwen_33_we; + reg_we_check[149] = mio_outsel_regwen_34_we; + reg_we_check[150] = mio_outsel_regwen_35_we; + reg_we_check[151] = mio_outsel_regwen_36_we; + reg_we_check[152] = mio_outsel_regwen_37_we; + reg_we_check[153] = mio_outsel_regwen_38_we; + reg_we_check[154] = mio_outsel_regwen_39_we; + reg_we_check[155] = mio_outsel_regwen_40_we; + reg_we_check[156] = mio_outsel_regwen_41_we; + reg_we_check[157] = mio_outsel_regwen_42_we; + reg_we_check[158] = mio_outsel_regwen_43_we; + reg_we_check[159] = mio_outsel_regwen_44_we; + reg_we_check[160] = mio_outsel_regwen_45_we; + reg_we_check[161] = mio_outsel_regwen_46_we; + reg_we_check[162] = mio_outsel_0_gated_we; + reg_we_check[163] = mio_outsel_1_gated_we; + reg_we_check[164] = mio_outsel_2_gated_we; + reg_we_check[165] = mio_outsel_3_gated_we; + reg_we_check[166] = mio_outsel_4_gated_we; + reg_we_check[167] = mio_outsel_5_gated_we; + reg_we_check[168] = mio_outsel_6_gated_we; + reg_we_check[169] = mio_outsel_7_gated_we; + reg_we_check[170] = mio_outsel_8_gated_we; + reg_we_check[171] = mio_outsel_9_gated_we; + reg_we_check[172] = mio_outsel_10_gated_we; + reg_we_check[173] = mio_outsel_11_gated_we; + reg_we_check[174] = mio_outsel_12_gated_we; + reg_we_check[175] = mio_outsel_13_gated_we; + reg_we_check[176] = mio_outsel_14_gated_we; + reg_we_check[177] = mio_outsel_15_gated_we; + reg_we_check[178] = mio_outsel_16_gated_we; + reg_we_check[179] = mio_outsel_17_gated_we; + reg_we_check[180] = mio_outsel_18_gated_we; + reg_we_check[181] = mio_outsel_19_gated_we; + reg_we_check[182] = mio_outsel_20_gated_we; + reg_we_check[183] = mio_outsel_21_gated_we; + reg_we_check[184] = mio_outsel_22_gated_we; + reg_we_check[185] = mio_outsel_23_gated_we; + reg_we_check[186] = mio_outsel_24_gated_we; + reg_we_check[187] = mio_outsel_25_gated_we; + reg_we_check[188] = mio_outsel_26_gated_we; + reg_we_check[189] = mio_outsel_27_gated_we; + reg_we_check[190] = mio_outsel_28_gated_we; + reg_we_check[191] = mio_outsel_29_gated_we; + reg_we_check[192] = mio_outsel_30_gated_we; + reg_we_check[193] = mio_outsel_31_gated_we; + reg_we_check[194] = mio_outsel_32_gated_we; + reg_we_check[195] = mio_outsel_33_gated_we; + reg_we_check[196] = mio_outsel_34_gated_we; + reg_we_check[197] = mio_outsel_35_gated_we; + reg_we_check[198] = mio_outsel_36_gated_we; + reg_we_check[199] = mio_outsel_37_gated_we; + reg_we_check[200] = mio_outsel_38_gated_we; + reg_we_check[201] = mio_outsel_39_gated_we; + reg_we_check[202] = mio_outsel_40_gated_we; + reg_we_check[203] = mio_outsel_41_gated_we; + reg_we_check[204] = mio_outsel_42_gated_we; + reg_we_check[205] = mio_outsel_43_gated_we; + reg_we_check[206] = mio_outsel_44_gated_we; + reg_we_check[207] = mio_outsel_45_gated_we; + reg_we_check[208] = mio_outsel_46_gated_we; + reg_we_check[209] = mio_pad_attr_regwen_0_we; + reg_we_check[210] = mio_pad_attr_regwen_1_we; + reg_we_check[211] = mio_pad_attr_regwen_2_we; + reg_we_check[212] = mio_pad_attr_regwen_3_we; + reg_we_check[213] = mio_pad_attr_regwen_4_we; + reg_we_check[214] = mio_pad_attr_regwen_5_we; + reg_we_check[215] = mio_pad_attr_regwen_6_we; + reg_we_check[216] = mio_pad_attr_regwen_7_we; + reg_we_check[217] = mio_pad_attr_regwen_8_we; + reg_we_check[218] = mio_pad_attr_regwen_9_we; + reg_we_check[219] = mio_pad_attr_regwen_10_we; + reg_we_check[220] = mio_pad_attr_regwen_11_we; + reg_we_check[221] = mio_pad_attr_regwen_12_we; + reg_we_check[222] = mio_pad_attr_regwen_13_we; + reg_we_check[223] = mio_pad_attr_regwen_14_we; + reg_we_check[224] = mio_pad_attr_regwen_15_we; + reg_we_check[225] = mio_pad_attr_regwen_16_we; + reg_we_check[226] = mio_pad_attr_regwen_17_we; + reg_we_check[227] = mio_pad_attr_regwen_18_we; + reg_we_check[228] = mio_pad_attr_regwen_19_we; + reg_we_check[229] = mio_pad_attr_regwen_20_we; + reg_we_check[230] = mio_pad_attr_regwen_21_we; + reg_we_check[231] = mio_pad_attr_regwen_22_we; + reg_we_check[232] = mio_pad_attr_regwen_23_we; + reg_we_check[233] = mio_pad_attr_regwen_24_we; + reg_we_check[234] = mio_pad_attr_regwen_25_we; + reg_we_check[235] = mio_pad_attr_regwen_26_we; + reg_we_check[236] = mio_pad_attr_regwen_27_we; + reg_we_check[237] = mio_pad_attr_regwen_28_we; + reg_we_check[238] = mio_pad_attr_regwen_29_we; + reg_we_check[239] = mio_pad_attr_regwen_30_we; + reg_we_check[240] = mio_pad_attr_regwen_31_we; + reg_we_check[241] = mio_pad_attr_regwen_32_we; + reg_we_check[242] = mio_pad_attr_regwen_33_we; + reg_we_check[243] = mio_pad_attr_regwen_34_we; + reg_we_check[244] = mio_pad_attr_regwen_35_we; + reg_we_check[245] = mio_pad_attr_regwen_36_we; + reg_we_check[246] = mio_pad_attr_regwen_37_we; + reg_we_check[247] = mio_pad_attr_regwen_38_we; + reg_we_check[248] = mio_pad_attr_regwen_39_we; + reg_we_check[249] = mio_pad_attr_regwen_40_we; + reg_we_check[250] = mio_pad_attr_regwen_41_we; + reg_we_check[251] = mio_pad_attr_regwen_42_we; + reg_we_check[252] = mio_pad_attr_regwen_43_we; + reg_we_check[253] = mio_pad_attr_regwen_44_we; + reg_we_check[254] = mio_pad_attr_regwen_45_we; + reg_we_check[255] = mio_pad_attr_regwen_46_we; + reg_we_check[256] = mio_pad_attr_0_gated_we; + reg_we_check[257] = mio_pad_attr_1_gated_we; + reg_we_check[258] = mio_pad_attr_2_gated_we; + reg_we_check[259] = mio_pad_attr_3_gated_we; + reg_we_check[260] = mio_pad_attr_4_gated_we; + reg_we_check[261] = mio_pad_attr_5_gated_we; + reg_we_check[262] = mio_pad_attr_6_gated_we; + reg_we_check[263] = mio_pad_attr_7_gated_we; + reg_we_check[264] = mio_pad_attr_8_gated_we; + reg_we_check[265] = mio_pad_attr_9_gated_we; + reg_we_check[266] = mio_pad_attr_10_gated_we; + reg_we_check[267] = mio_pad_attr_11_gated_we; + reg_we_check[268] = mio_pad_attr_12_gated_we; + reg_we_check[269] = mio_pad_attr_13_gated_we; + reg_we_check[270] = mio_pad_attr_14_gated_we; + reg_we_check[271] = mio_pad_attr_15_gated_we; + reg_we_check[272] = mio_pad_attr_16_gated_we; + reg_we_check[273] = mio_pad_attr_17_gated_we; + reg_we_check[274] = mio_pad_attr_18_gated_we; + reg_we_check[275] = mio_pad_attr_19_gated_we; + reg_we_check[276] = mio_pad_attr_20_gated_we; + reg_we_check[277] = mio_pad_attr_21_gated_we; + reg_we_check[278] = mio_pad_attr_22_gated_we; + reg_we_check[279] = mio_pad_attr_23_gated_we; + reg_we_check[280] = mio_pad_attr_24_gated_we; + reg_we_check[281] = mio_pad_attr_25_gated_we; + reg_we_check[282] = mio_pad_attr_26_gated_we; + reg_we_check[283] = mio_pad_attr_27_gated_we; + reg_we_check[284] = mio_pad_attr_28_gated_we; + reg_we_check[285] = mio_pad_attr_29_gated_we; + reg_we_check[286] = mio_pad_attr_30_gated_we; + reg_we_check[287] = mio_pad_attr_31_gated_we; + reg_we_check[288] = mio_pad_attr_32_gated_we; + reg_we_check[289] = mio_pad_attr_33_gated_we; + reg_we_check[290] = mio_pad_attr_34_gated_we; + reg_we_check[291] = mio_pad_attr_35_gated_we; + reg_we_check[292] = mio_pad_attr_36_gated_we; + reg_we_check[293] = mio_pad_attr_37_gated_we; + reg_we_check[294] = mio_pad_attr_38_gated_we; + reg_we_check[295] = mio_pad_attr_39_gated_we; + reg_we_check[296] = mio_pad_attr_40_gated_we; + reg_we_check[297] = mio_pad_attr_41_gated_we; + reg_we_check[298] = mio_pad_attr_42_gated_we; + reg_we_check[299] = mio_pad_attr_43_gated_we; + reg_we_check[300] = mio_pad_attr_44_gated_we; + reg_we_check[301] = mio_pad_attr_45_gated_we; + reg_we_check[302] = mio_pad_attr_46_gated_we; + reg_we_check[303] = dio_pad_attr_regwen_0_we; + reg_we_check[304] = dio_pad_attr_regwen_1_we; + reg_we_check[305] = dio_pad_attr_regwen_2_we; + reg_we_check[306] = dio_pad_attr_regwen_3_we; + reg_we_check[307] = dio_pad_attr_regwen_4_we; + reg_we_check[308] = dio_pad_attr_regwen_5_we; + reg_we_check[309] = dio_pad_attr_regwen_6_we; + reg_we_check[310] = dio_pad_attr_regwen_7_we; + reg_we_check[311] = dio_pad_attr_regwen_8_we; + reg_we_check[312] = dio_pad_attr_regwen_9_we; + reg_we_check[313] = dio_pad_attr_regwen_10_we; + reg_we_check[314] = dio_pad_attr_regwen_11_we; + reg_we_check[315] = dio_pad_attr_regwen_12_we; + reg_we_check[316] = dio_pad_attr_regwen_13_we; + reg_we_check[317] = dio_pad_attr_regwen_14_we; + reg_we_check[318] = dio_pad_attr_regwen_15_we; + reg_we_check[319] = dio_pad_attr_0_gated_we; + reg_we_check[320] = dio_pad_attr_1_gated_we; + reg_we_check[321] = dio_pad_attr_2_gated_we; + reg_we_check[322] = dio_pad_attr_3_gated_we; + reg_we_check[323] = dio_pad_attr_4_gated_we; + reg_we_check[324] = dio_pad_attr_5_gated_we; + reg_we_check[325] = dio_pad_attr_6_gated_we; + reg_we_check[326] = dio_pad_attr_7_gated_we; + reg_we_check[327] = dio_pad_attr_8_gated_we; + reg_we_check[328] = dio_pad_attr_9_gated_we; + reg_we_check[329] = dio_pad_attr_10_gated_we; + reg_we_check[330] = dio_pad_attr_11_gated_we; + reg_we_check[331] = dio_pad_attr_12_gated_we; + reg_we_check[332] = dio_pad_attr_13_gated_we; + reg_we_check[333] = dio_pad_attr_14_gated_we; + reg_we_check[334] = dio_pad_attr_15_gated_we; + reg_we_check[335] = mio_pad_sleep_status_0_we; + reg_we_check[336] = mio_pad_sleep_status_1_we; + reg_we_check[337] = mio_pad_sleep_regwen_0_we; + reg_we_check[338] = mio_pad_sleep_regwen_1_we; + reg_we_check[339] = mio_pad_sleep_regwen_2_we; + reg_we_check[340] = mio_pad_sleep_regwen_3_we; + reg_we_check[341] = mio_pad_sleep_regwen_4_we; + reg_we_check[342] = mio_pad_sleep_regwen_5_we; + reg_we_check[343] = mio_pad_sleep_regwen_6_we; + reg_we_check[344] = mio_pad_sleep_regwen_7_we; + reg_we_check[345] = mio_pad_sleep_regwen_8_we; + reg_we_check[346] = mio_pad_sleep_regwen_9_we; + reg_we_check[347] = mio_pad_sleep_regwen_10_we; + reg_we_check[348] = mio_pad_sleep_regwen_11_we; + reg_we_check[349] = mio_pad_sleep_regwen_12_we; + reg_we_check[350] = mio_pad_sleep_regwen_13_we; + reg_we_check[351] = mio_pad_sleep_regwen_14_we; + reg_we_check[352] = mio_pad_sleep_regwen_15_we; + reg_we_check[353] = mio_pad_sleep_regwen_16_we; + reg_we_check[354] = mio_pad_sleep_regwen_17_we; + reg_we_check[355] = mio_pad_sleep_regwen_18_we; + reg_we_check[356] = mio_pad_sleep_regwen_19_we; + reg_we_check[357] = mio_pad_sleep_regwen_20_we; + reg_we_check[358] = mio_pad_sleep_regwen_21_we; + reg_we_check[359] = mio_pad_sleep_regwen_22_we; + reg_we_check[360] = mio_pad_sleep_regwen_23_we; + reg_we_check[361] = mio_pad_sleep_regwen_24_we; + reg_we_check[362] = mio_pad_sleep_regwen_25_we; + reg_we_check[363] = mio_pad_sleep_regwen_26_we; + reg_we_check[364] = mio_pad_sleep_regwen_27_we; + reg_we_check[365] = mio_pad_sleep_regwen_28_we; + reg_we_check[366] = mio_pad_sleep_regwen_29_we; + reg_we_check[367] = mio_pad_sleep_regwen_30_we; + reg_we_check[368] = mio_pad_sleep_regwen_31_we; + reg_we_check[369] = mio_pad_sleep_regwen_32_we; + reg_we_check[370] = mio_pad_sleep_regwen_33_we; + reg_we_check[371] = mio_pad_sleep_regwen_34_we; + reg_we_check[372] = mio_pad_sleep_regwen_35_we; + reg_we_check[373] = mio_pad_sleep_regwen_36_we; + reg_we_check[374] = mio_pad_sleep_regwen_37_we; + reg_we_check[375] = mio_pad_sleep_regwen_38_we; + reg_we_check[376] = mio_pad_sleep_regwen_39_we; + reg_we_check[377] = mio_pad_sleep_regwen_40_we; + reg_we_check[378] = mio_pad_sleep_regwen_41_we; + reg_we_check[379] = mio_pad_sleep_regwen_42_we; + reg_we_check[380] = mio_pad_sleep_regwen_43_we; + reg_we_check[381] = mio_pad_sleep_regwen_44_we; + reg_we_check[382] = mio_pad_sleep_regwen_45_we; + reg_we_check[383] = mio_pad_sleep_regwen_46_we; + reg_we_check[384] = mio_pad_sleep_en_0_gated_we; + reg_we_check[385] = mio_pad_sleep_en_1_gated_we; + reg_we_check[386] = mio_pad_sleep_en_2_gated_we; + reg_we_check[387] = mio_pad_sleep_en_3_gated_we; + reg_we_check[388] = mio_pad_sleep_en_4_gated_we; + reg_we_check[389] = mio_pad_sleep_en_5_gated_we; + reg_we_check[390] = mio_pad_sleep_en_6_gated_we; + reg_we_check[391] = mio_pad_sleep_en_7_gated_we; + reg_we_check[392] = mio_pad_sleep_en_8_gated_we; + reg_we_check[393] = mio_pad_sleep_en_9_gated_we; + reg_we_check[394] = mio_pad_sleep_en_10_gated_we; + reg_we_check[395] = mio_pad_sleep_en_11_gated_we; + reg_we_check[396] = mio_pad_sleep_en_12_gated_we; + reg_we_check[397] = mio_pad_sleep_en_13_gated_we; + reg_we_check[398] = mio_pad_sleep_en_14_gated_we; + reg_we_check[399] = mio_pad_sleep_en_15_gated_we; + reg_we_check[400] = mio_pad_sleep_en_16_gated_we; + reg_we_check[401] = mio_pad_sleep_en_17_gated_we; + reg_we_check[402] = mio_pad_sleep_en_18_gated_we; + reg_we_check[403] = mio_pad_sleep_en_19_gated_we; + reg_we_check[404] = mio_pad_sleep_en_20_gated_we; + reg_we_check[405] = mio_pad_sleep_en_21_gated_we; + reg_we_check[406] = mio_pad_sleep_en_22_gated_we; + reg_we_check[407] = mio_pad_sleep_en_23_gated_we; + reg_we_check[408] = mio_pad_sleep_en_24_gated_we; + reg_we_check[409] = mio_pad_sleep_en_25_gated_we; + reg_we_check[410] = mio_pad_sleep_en_26_gated_we; + reg_we_check[411] = mio_pad_sleep_en_27_gated_we; + reg_we_check[412] = mio_pad_sleep_en_28_gated_we; + reg_we_check[413] = mio_pad_sleep_en_29_gated_we; + reg_we_check[414] = mio_pad_sleep_en_30_gated_we; + reg_we_check[415] = mio_pad_sleep_en_31_gated_we; + reg_we_check[416] = mio_pad_sleep_en_32_gated_we; + reg_we_check[417] = mio_pad_sleep_en_33_gated_we; + reg_we_check[418] = mio_pad_sleep_en_34_gated_we; + reg_we_check[419] = mio_pad_sleep_en_35_gated_we; + reg_we_check[420] = mio_pad_sleep_en_36_gated_we; + reg_we_check[421] = mio_pad_sleep_en_37_gated_we; + reg_we_check[422] = mio_pad_sleep_en_38_gated_we; + reg_we_check[423] = mio_pad_sleep_en_39_gated_we; + reg_we_check[424] = mio_pad_sleep_en_40_gated_we; + reg_we_check[425] = mio_pad_sleep_en_41_gated_we; + reg_we_check[426] = mio_pad_sleep_en_42_gated_we; + reg_we_check[427] = mio_pad_sleep_en_43_gated_we; + reg_we_check[428] = mio_pad_sleep_en_44_gated_we; + reg_we_check[429] = mio_pad_sleep_en_45_gated_we; + reg_we_check[430] = mio_pad_sleep_en_46_gated_we; + reg_we_check[431] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[432] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[433] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[434] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[435] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[436] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[437] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[438] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[439] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[440] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[441] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[442] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[443] = mio_pad_sleep_mode_12_gated_we; + reg_we_check[444] = mio_pad_sleep_mode_13_gated_we; + reg_we_check[445] = mio_pad_sleep_mode_14_gated_we; + reg_we_check[446] = mio_pad_sleep_mode_15_gated_we; + reg_we_check[447] = mio_pad_sleep_mode_16_gated_we; + reg_we_check[448] = mio_pad_sleep_mode_17_gated_we; + reg_we_check[449] = mio_pad_sleep_mode_18_gated_we; + reg_we_check[450] = mio_pad_sleep_mode_19_gated_we; + reg_we_check[451] = mio_pad_sleep_mode_20_gated_we; + reg_we_check[452] = mio_pad_sleep_mode_21_gated_we; + reg_we_check[453] = mio_pad_sleep_mode_22_gated_we; + reg_we_check[454] = mio_pad_sleep_mode_23_gated_we; + reg_we_check[455] = mio_pad_sleep_mode_24_gated_we; + reg_we_check[456] = mio_pad_sleep_mode_25_gated_we; + reg_we_check[457] = mio_pad_sleep_mode_26_gated_we; + reg_we_check[458] = mio_pad_sleep_mode_27_gated_we; + reg_we_check[459] = mio_pad_sleep_mode_28_gated_we; + reg_we_check[460] = mio_pad_sleep_mode_29_gated_we; + reg_we_check[461] = mio_pad_sleep_mode_30_gated_we; + reg_we_check[462] = mio_pad_sleep_mode_31_gated_we; + reg_we_check[463] = mio_pad_sleep_mode_32_gated_we; + reg_we_check[464] = mio_pad_sleep_mode_33_gated_we; + reg_we_check[465] = mio_pad_sleep_mode_34_gated_we; + reg_we_check[466] = mio_pad_sleep_mode_35_gated_we; + reg_we_check[467] = mio_pad_sleep_mode_36_gated_we; + reg_we_check[468] = mio_pad_sleep_mode_37_gated_we; + reg_we_check[469] = mio_pad_sleep_mode_38_gated_we; + reg_we_check[470] = mio_pad_sleep_mode_39_gated_we; + reg_we_check[471] = mio_pad_sleep_mode_40_gated_we; + reg_we_check[472] = mio_pad_sleep_mode_41_gated_we; + reg_we_check[473] = mio_pad_sleep_mode_42_gated_we; + reg_we_check[474] = mio_pad_sleep_mode_43_gated_we; + reg_we_check[475] = mio_pad_sleep_mode_44_gated_we; + reg_we_check[476] = mio_pad_sleep_mode_45_gated_we; + reg_we_check[477] = mio_pad_sleep_mode_46_gated_we; + reg_we_check[478] = dio_pad_sleep_status_we; + reg_we_check[479] = dio_pad_sleep_regwen_0_we; + reg_we_check[480] = dio_pad_sleep_regwen_1_we; + reg_we_check[481] = dio_pad_sleep_regwen_2_we; + reg_we_check[482] = dio_pad_sleep_regwen_3_we; + reg_we_check[483] = dio_pad_sleep_regwen_4_we; + reg_we_check[484] = dio_pad_sleep_regwen_5_we; + reg_we_check[485] = dio_pad_sleep_regwen_6_we; + reg_we_check[486] = dio_pad_sleep_regwen_7_we; + reg_we_check[487] = dio_pad_sleep_regwen_8_we; + reg_we_check[488] = dio_pad_sleep_regwen_9_we; + reg_we_check[489] = dio_pad_sleep_regwen_10_we; + reg_we_check[490] = dio_pad_sleep_regwen_11_we; + reg_we_check[491] = dio_pad_sleep_regwen_12_we; + reg_we_check[492] = dio_pad_sleep_regwen_13_we; + reg_we_check[493] = dio_pad_sleep_regwen_14_we; + reg_we_check[494] = dio_pad_sleep_regwen_15_we; + reg_we_check[495] = dio_pad_sleep_en_0_gated_we; + reg_we_check[496] = dio_pad_sleep_en_1_gated_we; + reg_we_check[497] = dio_pad_sleep_en_2_gated_we; + reg_we_check[498] = dio_pad_sleep_en_3_gated_we; + reg_we_check[499] = dio_pad_sleep_en_4_gated_we; + reg_we_check[500] = dio_pad_sleep_en_5_gated_we; + reg_we_check[501] = dio_pad_sleep_en_6_gated_we; + reg_we_check[502] = dio_pad_sleep_en_7_gated_we; + reg_we_check[503] = dio_pad_sleep_en_8_gated_we; + reg_we_check[504] = dio_pad_sleep_en_9_gated_we; + reg_we_check[505] = dio_pad_sleep_en_10_gated_we; + reg_we_check[506] = dio_pad_sleep_en_11_gated_we; + reg_we_check[507] = dio_pad_sleep_en_12_gated_we; + reg_we_check[508] = dio_pad_sleep_en_13_gated_we; + reg_we_check[509] = dio_pad_sleep_en_14_gated_we; + reg_we_check[510] = dio_pad_sleep_en_15_gated_we; + reg_we_check[511] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[512] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[513] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[514] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[515] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[516] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[517] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[518] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[519] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[520] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[521] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[522] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[523] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[524] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[525] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[526] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[527] = wkup_detector_regwen_0_we; + reg_we_check[528] = wkup_detector_regwen_1_we; + reg_we_check[529] = wkup_detector_regwen_2_we; + reg_we_check[530] = wkup_detector_regwen_3_we; + reg_we_check[531] = wkup_detector_regwen_4_we; + reg_we_check[532] = wkup_detector_regwen_5_we; + reg_we_check[533] = wkup_detector_regwen_6_we; + reg_we_check[534] = wkup_detector_regwen_7_we; + reg_we_check[535] = wkup_detector_en_0_we; + reg_we_check[536] = wkup_detector_en_1_we; + reg_we_check[537] = wkup_detector_en_2_we; + reg_we_check[538] = wkup_detector_en_3_we; + reg_we_check[539] = wkup_detector_en_4_we; + reg_we_check[540] = wkup_detector_en_5_we; + reg_we_check[541] = wkup_detector_en_6_we; + reg_we_check[542] = wkup_detector_en_7_we; + reg_we_check[543] = wkup_detector_0_we; + reg_we_check[544] = wkup_detector_1_we; + reg_we_check[545] = wkup_detector_2_we; + reg_we_check[546] = wkup_detector_3_we; + reg_we_check[547] = wkup_detector_4_we; + reg_we_check[548] = wkup_detector_5_we; + reg_we_check[549] = wkup_detector_6_we; + reg_we_check[550] = wkup_detector_7_we; + reg_we_check[551] = wkup_detector_cnt_th_0_we; + reg_we_check[552] = wkup_detector_cnt_th_1_we; + reg_we_check[553] = wkup_detector_cnt_th_2_we; + reg_we_check[554] = wkup_detector_cnt_th_3_we; + reg_we_check[555] = wkup_detector_cnt_th_4_we; + reg_we_check[556] = wkup_detector_cnt_th_5_we; + reg_we_check[557] = wkup_detector_cnt_th_6_we; + reg_we_check[558] = wkup_detector_cnt_th_7_we; + reg_we_check[559] = wkup_detector_padsel_0_gated_we; + reg_we_check[560] = wkup_detector_padsel_1_gated_we; + reg_we_check[561] = wkup_detector_padsel_2_gated_we; + reg_we_check[562] = wkup_detector_padsel_3_gated_we; + reg_we_check[563] = wkup_detector_padsel_4_gated_we; + reg_we_check[564] = wkup_detector_padsel_5_gated_we; + reg_we_check[565] = wkup_detector_padsel_6_gated_we; + reg_we_check[566] = wkup_detector_padsel_7_gated_we; + reg_we_check[567] = wkup_cause_we; end // Read data return @@ -37741,822 +37504,798 @@ module pinmux_reg_top ( end addr_hit[58]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_57_qs; - end - - addr_hit[59]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_58_qs; - end - - addr_hit[60]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_59_qs; - end - - addr_hit[61]: begin reg_rdata_next[5:0] = mio_periph_insel_0_qs; end - addr_hit[62]: begin + addr_hit[59]: begin reg_rdata_next[5:0] = mio_periph_insel_1_qs; end - addr_hit[63]: begin + addr_hit[60]: begin reg_rdata_next[5:0] = mio_periph_insel_2_qs; end - addr_hit[64]: begin + addr_hit[61]: begin reg_rdata_next[5:0] = mio_periph_insel_3_qs; end - addr_hit[65]: begin + addr_hit[62]: begin reg_rdata_next[5:0] = mio_periph_insel_4_qs; end - addr_hit[66]: begin + addr_hit[63]: begin reg_rdata_next[5:0] = mio_periph_insel_5_qs; end - addr_hit[67]: begin + addr_hit[64]: begin reg_rdata_next[5:0] = mio_periph_insel_6_qs; end - addr_hit[68]: begin + addr_hit[65]: begin reg_rdata_next[5:0] = mio_periph_insel_7_qs; end - addr_hit[69]: begin + addr_hit[66]: begin reg_rdata_next[5:0] = mio_periph_insel_8_qs; end - addr_hit[70]: begin + addr_hit[67]: begin reg_rdata_next[5:0] = mio_periph_insel_9_qs; end - addr_hit[71]: begin + addr_hit[68]: begin reg_rdata_next[5:0] = mio_periph_insel_10_qs; end - addr_hit[72]: begin + addr_hit[69]: begin reg_rdata_next[5:0] = mio_periph_insel_11_qs; end - addr_hit[73]: begin + addr_hit[70]: begin reg_rdata_next[5:0] = mio_periph_insel_12_qs; end - addr_hit[74]: begin + addr_hit[71]: begin reg_rdata_next[5:0] = mio_periph_insel_13_qs; end - addr_hit[75]: begin + addr_hit[72]: begin reg_rdata_next[5:0] = mio_periph_insel_14_qs; end - addr_hit[76]: begin + addr_hit[73]: begin reg_rdata_next[5:0] = mio_periph_insel_15_qs; end - addr_hit[77]: begin + addr_hit[74]: begin reg_rdata_next[5:0] = mio_periph_insel_16_qs; end - addr_hit[78]: begin + addr_hit[75]: begin reg_rdata_next[5:0] = mio_periph_insel_17_qs; end - addr_hit[79]: begin + addr_hit[76]: begin reg_rdata_next[5:0] = mio_periph_insel_18_qs; end - addr_hit[80]: begin + addr_hit[77]: begin reg_rdata_next[5:0] = mio_periph_insel_19_qs; end - addr_hit[81]: begin + addr_hit[78]: begin reg_rdata_next[5:0] = mio_periph_insel_20_qs; end - addr_hit[82]: begin + addr_hit[79]: begin reg_rdata_next[5:0] = mio_periph_insel_21_qs; end - addr_hit[83]: begin + addr_hit[80]: begin reg_rdata_next[5:0] = mio_periph_insel_22_qs; end - addr_hit[84]: begin + addr_hit[81]: begin reg_rdata_next[5:0] = mio_periph_insel_23_qs; end - addr_hit[85]: begin + addr_hit[82]: begin reg_rdata_next[5:0] = mio_periph_insel_24_qs; end - addr_hit[86]: begin + addr_hit[83]: begin reg_rdata_next[5:0] = mio_periph_insel_25_qs; end - addr_hit[87]: begin + addr_hit[84]: begin reg_rdata_next[5:0] = mio_periph_insel_26_qs; end - addr_hit[88]: begin + addr_hit[85]: begin reg_rdata_next[5:0] = mio_periph_insel_27_qs; end - addr_hit[89]: begin + addr_hit[86]: begin reg_rdata_next[5:0] = mio_periph_insel_28_qs; end - addr_hit[90]: begin + addr_hit[87]: begin reg_rdata_next[5:0] = mio_periph_insel_29_qs; end - addr_hit[91]: begin + addr_hit[88]: begin reg_rdata_next[5:0] = mio_periph_insel_30_qs; end - addr_hit[92]: begin + addr_hit[89]: begin reg_rdata_next[5:0] = mio_periph_insel_31_qs; end - addr_hit[93]: begin + addr_hit[90]: begin reg_rdata_next[5:0] = mio_periph_insel_32_qs; end - addr_hit[94]: begin + addr_hit[91]: begin reg_rdata_next[5:0] = mio_periph_insel_33_qs; end - addr_hit[95]: begin + addr_hit[92]: begin reg_rdata_next[5:0] = mio_periph_insel_34_qs; end - addr_hit[96]: begin + addr_hit[93]: begin reg_rdata_next[5:0] = mio_periph_insel_35_qs; end - addr_hit[97]: begin + addr_hit[94]: begin reg_rdata_next[5:0] = mio_periph_insel_36_qs; end - addr_hit[98]: begin + addr_hit[95]: begin reg_rdata_next[5:0] = mio_periph_insel_37_qs; end - addr_hit[99]: begin + addr_hit[96]: begin reg_rdata_next[5:0] = mio_periph_insel_38_qs; end - addr_hit[100]: begin + addr_hit[97]: begin reg_rdata_next[5:0] = mio_periph_insel_39_qs; end - addr_hit[101]: begin + addr_hit[98]: begin reg_rdata_next[5:0] = mio_periph_insel_40_qs; end - addr_hit[102]: begin + addr_hit[99]: begin reg_rdata_next[5:0] = mio_periph_insel_41_qs; end - addr_hit[103]: begin + addr_hit[100]: begin reg_rdata_next[5:0] = mio_periph_insel_42_qs; end - addr_hit[104]: begin + addr_hit[101]: begin reg_rdata_next[5:0] = mio_periph_insel_43_qs; end - addr_hit[105]: begin + addr_hit[102]: begin reg_rdata_next[5:0] = mio_periph_insel_44_qs; end - addr_hit[106]: begin + addr_hit[103]: begin reg_rdata_next[5:0] = mio_periph_insel_45_qs; end - addr_hit[107]: begin + addr_hit[104]: begin reg_rdata_next[5:0] = mio_periph_insel_46_qs; end - addr_hit[108]: begin + addr_hit[105]: begin reg_rdata_next[5:0] = mio_periph_insel_47_qs; end - addr_hit[109]: begin + addr_hit[106]: begin reg_rdata_next[5:0] = mio_periph_insel_48_qs; end - addr_hit[110]: begin + addr_hit[107]: begin reg_rdata_next[5:0] = mio_periph_insel_49_qs; end - addr_hit[111]: begin + addr_hit[108]: begin reg_rdata_next[5:0] = mio_periph_insel_50_qs; end - addr_hit[112]: begin + addr_hit[109]: begin reg_rdata_next[5:0] = mio_periph_insel_51_qs; end - addr_hit[113]: begin + addr_hit[110]: begin reg_rdata_next[5:0] = mio_periph_insel_52_qs; end - addr_hit[114]: begin + addr_hit[111]: begin reg_rdata_next[5:0] = mio_periph_insel_53_qs; end - addr_hit[115]: begin + addr_hit[112]: begin reg_rdata_next[5:0] = mio_periph_insel_54_qs; end - addr_hit[116]: begin + addr_hit[113]: begin reg_rdata_next[5:0] = mio_periph_insel_55_qs; end - addr_hit[117]: begin + addr_hit[114]: begin reg_rdata_next[5:0] = mio_periph_insel_56_qs; end - addr_hit[118]: begin - reg_rdata_next[5:0] = mio_periph_insel_57_qs; - end - - addr_hit[119]: begin - reg_rdata_next[5:0] = mio_periph_insel_58_qs; - end - - addr_hit[120]: begin - reg_rdata_next[5:0] = mio_periph_insel_59_qs; - end - - addr_hit[121]: begin + addr_hit[115]: begin reg_rdata_next[0] = mio_outsel_regwen_0_qs; end - addr_hit[122]: begin + addr_hit[116]: begin reg_rdata_next[0] = mio_outsel_regwen_1_qs; end - addr_hit[123]: begin + addr_hit[117]: begin reg_rdata_next[0] = mio_outsel_regwen_2_qs; end - addr_hit[124]: begin + addr_hit[118]: begin reg_rdata_next[0] = mio_outsel_regwen_3_qs; end - addr_hit[125]: begin + addr_hit[119]: begin reg_rdata_next[0] = mio_outsel_regwen_4_qs; end - addr_hit[126]: begin + addr_hit[120]: begin reg_rdata_next[0] = mio_outsel_regwen_5_qs; end - addr_hit[127]: begin + addr_hit[121]: begin reg_rdata_next[0] = mio_outsel_regwen_6_qs; end - addr_hit[128]: begin + addr_hit[122]: begin reg_rdata_next[0] = mio_outsel_regwen_7_qs; end - addr_hit[129]: begin + addr_hit[123]: begin reg_rdata_next[0] = mio_outsel_regwen_8_qs; end - addr_hit[130]: begin + addr_hit[124]: begin reg_rdata_next[0] = mio_outsel_regwen_9_qs; end - addr_hit[131]: begin + addr_hit[125]: begin reg_rdata_next[0] = mio_outsel_regwen_10_qs; end - addr_hit[132]: begin + addr_hit[126]: begin reg_rdata_next[0] = mio_outsel_regwen_11_qs; end - addr_hit[133]: begin + addr_hit[127]: begin reg_rdata_next[0] = mio_outsel_regwen_12_qs; end - addr_hit[134]: begin + addr_hit[128]: begin reg_rdata_next[0] = mio_outsel_regwen_13_qs; end - addr_hit[135]: begin + addr_hit[129]: begin reg_rdata_next[0] = mio_outsel_regwen_14_qs; end - addr_hit[136]: begin + addr_hit[130]: begin reg_rdata_next[0] = mio_outsel_regwen_15_qs; end - addr_hit[137]: begin + addr_hit[131]: begin reg_rdata_next[0] = mio_outsel_regwen_16_qs; end - addr_hit[138]: begin + addr_hit[132]: begin reg_rdata_next[0] = mio_outsel_regwen_17_qs; end - addr_hit[139]: begin + addr_hit[133]: begin reg_rdata_next[0] = mio_outsel_regwen_18_qs; end - addr_hit[140]: begin + addr_hit[134]: begin reg_rdata_next[0] = mio_outsel_regwen_19_qs; end - addr_hit[141]: begin + addr_hit[135]: begin reg_rdata_next[0] = mio_outsel_regwen_20_qs; end - addr_hit[142]: begin + addr_hit[136]: begin reg_rdata_next[0] = mio_outsel_regwen_21_qs; end - addr_hit[143]: begin + addr_hit[137]: begin reg_rdata_next[0] = mio_outsel_regwen_22_qs; end - addr_hit[144]: begin + addr_hit[138]: begin reg_rdata_next[0] = mio_outsel_regwen_23_qs; end - addr_hit[145]: begin + addr_hit[139]: begin reg_rdata_next[0] = mio_outsel_regwen_24_qs; end - addr_hit[146]: begin + addr_hit[140]: begin reg_rdata_next[0] = mio_outsel_regwen_25_qs; end - addr_hit[147]: begin + addr_hit[141]: begin reg_rdata_next[0] = mio_outsel_regwen_26_qs; end - addr_hit[148]: begin + addr_hit[142]: begin reg_rdata_next[0] = mio_outsel_regwen_27_qs; end - addr_hit[149]: begin + addr_hit[143]: begin reg_rdata_next[0] = mio_outsel_regwen_28_qs; end - addr_hit[150]: begin + addr_hit[144]: begin reg_rdata_next[0] = mio_outsel_regwen_29_qs; end - addr_hit[151]: begin + addr_hit[145]: begin reg_rdata_next[0] = mio_outsel_regwen_30_qs; end - addr_hit[152]: begin + addr_hit[146]: begin reg_rdata_next[0] = mio_outsel_regwen_31_qs; end - addr_hit[153]: begin + addr_hit[147]: begin reg_rdata_next[0] = mio_outsel_regwen_32_qs; end - addr_hit[154]: begin + addr_hit[148]: begin reg_rdata_next[0] = mio_outsel_regwen_33_qs; end - addr_hit[155]: begin + addr_hit[149]: begin reg_rdata_next[0] = mio_outsel_regwen_34_qs; end - addr_hit[156]: begin + addr_hit[150]: begin reg_rdata_next[0] = mio_outsel_regwen_35_qs; end - addr_hit[157]: begin + addr_hit[151]: begin reg_rdata_next[0] = mio_outsel_regwen_36_qs; end - addr_hit[158]: begin + addr_hit[152]: begin reg_rdata_next[0] = mio_outsel_regwen_37_qs; end - addr_hit[159]: begin + addr_hit[153]: begin reg_rdata_next[0] = mio_outsel_regwen_38_qs; end - addr_hit[160]: begin + addr_hit[154]: begin reg_rdata_next[0] = mio_outsel_regwen_39_qs; end - addr_hit[161]: begin + addr_hit[155]: begin reg_rdata_next[0] = mio_outsel_regwen_40_qs; end - addr_hit[162]: begin + addr_hit[156]: begin reg_rdata_next[0] = mio_outsel_regwen_41_qs; end - addr_hit[163]: begin + addr_hit[157]: begin reg_rdata_next[0] = mio_outsel_regwen_42_qs; end - addr_hit[164]: begin + addr_hit[158]: begin reg_rdata_next[0] = mio_outsel_regwen_43_qs; end - addr_hit[165]: begin + addr_hit[159]: begin reg_rdata_next[0] = mio_outsel_regwen_44_qs; end - addr_hit[166]: begin + addr_hit[160]: begin reg_rdata_next[0] = mio_outsel_regwen_45_qs; end - addr_hit[167]: begin + addr_hit[161]: begin reg_rdata_next[0] = mio_outsel_regwen_46_qs; end - addr_hit[168]: begin + addr_hit[162]: begin reg_rdata_next[6:0] = mio_outsel_0_qs; end - addr_hit[169]: begin + addr_hit[163]: begin reg_rdata_next[6:0] = mio_outsel_1_qs; end - addr_hit[170]: begin + addr_hit[164]: begin reg_rdata_next[6:0] = mio_outsel_2_qs; end - addr_hit[171]: begin + addr_hit[165]: begin reg_rdata_next[6:0] = mio_outsel_3_qs; end - addr_hit[172]: begin + addr_hit[166]: begin reg_rdata_next[6:0] = mio_outsel_4_qs; end - addr_hit[173]: begin + addr_hit[167]: begin reg_rdata_next[6:0] = mio_outsel_5_qs; end - addr_hit[174]: begin + addr_hit[168]: begin reg_rdata_next[6:0] = mio_outsel_6_qs; end - addr_hit[175]: begin + addr_hit[169]: begin reg_rdata_next[6:0] = mio_outsel_7_qs; end - addr_hit[176]: begin + addr_hit[170]: begin reg_rdata_next[6:0] = mio_outsel_8_qs; end - addr_hit[177]: begin + addr_hit[171]: begin reg_rdata_next[6:0] = mio_outsel_9_qs; end - addr_hit[178]: begin + addr_hit[172]: begin reg_rdata_next[6:0] = mio_outsel_10_qs; end - addr_hit[179]: begin + addr_hit[173]: begin reg_rdata_next[6:0] = mio_outsel_11_qs; end - addr_hit[180]: begin + addr_hit[174]: begin reg_rdata_next[6:0] = mio_outsel_12_qs; end - addr_hit[181]: begin + addr_hit[175]: begin reg_rdata_next[6:0] = mio_outsel_13_qs; end - addr_hit[182]: begin + addr_hit[176]: begin reg_rdata_next[6:0] = mio_outsel_14_qs; end - addr_hit[183]: begin + addr_hit[177]: begin reg_rdata_next[6:0] = mio_outsel_15_qs; end - addr_hit[184]: begin + addr_hit[178]: begin reg_rdata_next[6:0] = mio_outsel_16_qs; end - addr_hit[185]: begin + addr_hit[179]: begin reg_rdata_next[6:0] = mio_outsel_17_qs; end - addr_hit[186]: begin + addr_hit[180]: begin reg_rdata_next[6:0] = mio_outsel_18_qs; end - addr_hit[187]: begin + addr_hit[181]: begin reg_rdata_next[6:0] = mio_outsel_19_qs; end - addr_hit[188]: begin + addr_hit[182]: begin reg_rdata_next[6:0] = mio_outsel_20_qs; end - addr_hit[189]: begin + addr_hit[183]: begin reg_rdata_next[6:0] = mio_outsel_21_qs; end - addr_hit[190]: begin + addr_hit[184]: begin reg_rdata_next[6:0] = mio_outsel_22_qs; end - addr_hit[191]: begin + addr_hit[185]: begin reg_rdata_next[6:0] = mio_outsel_23_qs; end - addr_hit[192]: begin + addr_hit[186]: begin reg_rdata_next[6:0] = mio_outsel_24_qs; end - addr_hit[193]: begin + addr_hit[187]: begin reg_rdata_next[6:0] = mio_outsel_25_qs; end - addr_hit[194]: begin + addr_hit[188]: begin reg_rdata_next[6:0] = mio_outsel_26_qs; end - addr_hit[195]: begin + addr_hit[189]: begin reg_rdata_next[6:0] = mio_outsel_27_qs; end - addr_hit[196]: begin + addr_hit[190]: begin reg_rdata_next[6:0] = mio_outsel_28_qs; end - addr_hit[197]: begin + addr_hit[191]: begin reg_rdata_next[6:0] = mio_outsel_29_qs; end - addr_hit[198]: begin + addr_hit[192]: begin reg_rdata_next[6:0] = mio_outsel_30_qs; end - addr_hit[199]: begin + addr_hit[193]: begin reg_rdata_next[6:0] = mio_outsel_31_qs; end - addr_hit[200]: begin + addr_hit[194]: begin reg_rdata_next[6:0] = mio_outsel_32_qs; end - addr_hit[201]: begin + addr_hit[195]: begin reg_rdata_next[6:0] = mio_outsel_33_qs; end - addr_hit[202]: begin + addr_hit[196]: begin reg_rdata_next[6:0] = mio_outsel_34_qs; end - addr_hit[203]: begin + addr_hit[197]: begin reg_rdata_next[6:0] = mio_outsel_35_qs; end - addr_hit[204]: begin + addr_hit[198]: begin reg_rdata_next[6:0] = mio_outsel_36_qs; end - addr_hit[205]: begin + addr_hit[199]: begin reg_rdata_next[6:0] = mio_outsel_37_qs; end - addr_hit[206]: begin + addr_hit[200]: begin reg_rdata_next[6:0] = mio_outsel_38_qs; end - addr_hit[207]: begin + addr_hit[201]: begin reg_rdata_next[6:0] = mio_outsel_39_qs; end - addr_hit[208]: begin + addr_hit[202]: begin reg_rdata_next[6:0] = mio_outsel_40_qs; end - addr_hit[209]: begin + addr_hit[203]: begin reg_rdata_next[6:0] = mio_outsel_41_qs; end - addr_hit[210]: begin + addr_hit[204]: begin reg_rdata_next[6:0] = mio_outsel_42_qs; end - addr_hit[211]: begin + addr_hit[205]: begin reg_rdata_next[6:0] = mio_outsel_43_qs; end - addr_hit[212]: begin + addr_hit[206]: begin reg_rdata_next[6:0] = mio_outsel_44_qs; end - addr_hit[213]: begin + addr_hit[207]: begin reg_rdata_next[6:0] = mio_outsel_45_qs; end - addr_hit[214]: begin + addr_hit[208]: begin reg_rdata_next[6:0] = mio_outsel_46_qs; end - addr_hit[215]: begin + addr_hit[209]: begin reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end - addr_hit[216]: begin + addr_hit[210]: begin reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end - addr_hit[217]: begin + addr_hit[211]: begin reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end - addr_hit[218]: begin + addr_hit[212]: begin reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end - addr_hit[219]: begin + addr_hit[213]: begin reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end - addr_hit[220]: begin + addr_hit[214]: begin reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end - addr_hit[221]: begin + addr_hit[215]: begin reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end - addr_hit[222]: begin + addr_hit[216]: begin reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end - addr_hit[223]: begin + addr_hit[217]: begin reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end - addr_hit[224]: begin + addr_hit[218]: begin reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end - addr_hit[225]: begin + addr_hit[219]: begin reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end - addr_hit[226]: begin + addr_hit[220]: begin reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end - addr_hit[227]: begin + addr_hit[221]: begin reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end - addr_hit[228]: begin + addr_hit[222]: begin reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end - addr_hit[229]: begin + addr_hit[223]: begin reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end - addr_hit[230]: begin + addr_hit[224]: begin reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end - addr_hit[231]: begin + addr_hit[225]: begin reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end - addr_hit[232]: begin + addr_hit[226]: begin reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end - addr_hit[233]: begin + addr_hit[227]: begin reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end - addr_hit[234]: begin + addr_hit[228]: begin reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end - addr_hit[235]: begin + addr_hit[229]: begin reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end - addr_hit[236]: begin + addr_hit[230]: begin reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end - addr_hit[237]: begin + addr_hit[231]: begin reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end - addr_hit[238]: begin + addr_hit[232]: begin reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end - addr_hit[239]: begin + addr_hit[233]: begin reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end - addr_hit[240]: begin + addr_hit[234]: begin reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end - addr_hit[241]: begin + addr_hit[235]: begin reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end - addr_hit[242]: begin + addr_hit[236]: begin reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end - addr_hit[243]: begin + addr_hit[237]: begin reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end - addr_hit[244]: begin + addr_hit[238]: begin reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end - addr_hit[245]: begin + addr_hit[239]: begin reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end - addr_hit[246]: begin + addr_hit[240]: begin reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end - addr_hit[247]: begin + addr_hit[241]: begin reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; end - addr_hit[248]: begin + addr_hit[242]: begin reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; end - addr_hit[249]: begin + addr_hit[243]: begin reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; end - addr_hit[250]: begin + addr_hit[244]: begin reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; end - addr_hit[251]: begin + addr_hit[245]: begin reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; end - addr_hit[252]: begin + addr_hit[246]: begin reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; end - addr_hit[253]: begin + addr_hit[247]: begin reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; end - addr_hit[254]: begin + addr_hit[248]: begin reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; end - addr_hit[255]: begin + addr_hit[249]: begin reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; end - addr_hit[256]: begin + addr_hit[250]: begin reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; end - addr_hit[257]: begin + addr_hit[251]: begin reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; end - addr_hit[258]: begin + addr_hit[252]: begin reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; end - addr_hit[259]: begin + addr_hit[253]: begin reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; end - addr_hit[260]: begin + addr_hit[254]: begin reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; end - addr_hit[261]: begin + addr_hit[255]: begin reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; end - addr_hit[262]: begin + addr_hit[256]: begin reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; @@ -38569,7 +38308,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; end - addr_hit[263]: begin + addr_hit[257]: begin reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; @@ -38582,7 +38321,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; end - addr_hit[264]: begin + addr_hit[258]: begin reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; @@ -38595,7 +38334,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; end - addr_hit[265]: begin + addr_hit[259]: begin reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; @@ -38608,7 +38347,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; end - addr_hit[266]: begin + addr_hit[260]: begin reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; @@ -38621,7 +38360,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; end - addr_hit[267]: begin + addr_hit[261]: begin reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; @@ -38634,7 +38373,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; end - addr_hit[268]: begin + addr_hit[262]: begin reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; @@ -38647,7 +38386,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; end - addr_hit[269]: begin + addr_hit[263]: begin reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; @@ -38660,7 +38399,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; end - addr_hit[270]: begin + addr_hit[264]: begin reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; @@ -38673,7 +38412,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; end - addr_hit[271]: begin + addr_hit[265]: begin reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; @@ -38686,7 +38425,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; end - addr_hit[272]: begin + addr_hit[266]: begin reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; @@ -38699,7 +38438,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; end - addr_hit[273]: begin + addr_hit[267]: begin reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; @@ -38712,7 +38451,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; end - addr_hit[274]: begin + addr_hit[268]: begin reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs; @@ -38725,7 +38464,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs; end - addr_hit[275]: begin + addr_hit[269]: begin reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs; @@ -38738,7 +38477,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs; end - addr_hit[276]: begin + addr_hit[270]: begin reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs; @@ -38751,7 +38490,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs; end - addr_hit[277]: begin + addr_hit[271]: begin reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs; @@ -38764,7 +38503,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs; end - addr_hit[278]: begin + addr_hit[272]: begin reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs; @@ -38777,7 +38516,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs; end - addr_hit[279]: begin + addr_hit[273]: begin reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs; @@ -38790,7 +38529,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs; end - addr_hit[280]: begin + addr_hit[274]: begin reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs; @@ -38803,7 +38542,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs; end - addr_hit[281]: begin + addr_hit[275]: begin reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs; @@ -38816,7 +38555,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs; end - addr_hit[282]: begin + addr_hit[276]: begin reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs; @@ -38829,7 +38568,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs; end - addr_hit[283]: begin + addr_hit[277]: begin reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs; @@ -38842,7 +38581,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs; end - addr_hit[284]: begin + addr_hit[278]: begin reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs; @@ -38855,7 +38594,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs; end - addr_hit[285]: begin + addr_hit[279]: begin reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs; @@ -38868,7 +38607,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs; end - addr_hit[286]: begin + addr_hit[280]: begin reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs; @@ -38881,7 +38620,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs; end - addr_hit[287]: begin + addr_hit[281]: begin reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs; @@ -38894,7 +38633,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs; end - addr_hit[288]: begin + addr_hit[282]: begin reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs; @@ -38907,7 +38646,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs; end - addr_hit[289]: begin + addr_hit[283]: begin reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs; @@ -38920,7 +38659,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs; end - addr_hit[290]: begin + addr_hit[284]: begin reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs; @@ -38933,7 +38672,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs; end - addr_hit[291]: begin + addr_hit[285]: begin reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs; @@ -38946,7 +38685,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs; end - addr_hit[292]: begin + addr_hit[286]: begin reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs; @@ -38959,7 +38698,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs; end - addr_hit[293]: begin + addr_hit[287]: begin reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs; @@ -38972,7 +38711,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs; end - addr_hit[294]: begin + addr_hit[288]: begin reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs; @@ -38985,7 +38724,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs; end - addr_hit[295]: begin + addr_hit[289]: begin reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs; @@ -38998,7 +38737,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs; end - addr_hit[296]: begin + addr_hit[290]: begin reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs; @@ -39011,7 +38750,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs; end - addr_hit[297]: begin + addr_hit[291]: begin reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs; @@ -39024,7 +38763,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs; end - addr_hit[298]: begin + addr_hit[292]: begin reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs; @@ -39037,7 +38776,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs; end - addr_hit[299]: begin + addr_hit[293]: begin reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs; reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs; reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs; @@ -39050,7 +38789,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs; end - addr_hit[300]: begin + addr_hit[294]: begin reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs; reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs; reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs; @@ -39063,7 +38802,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs; end - addr_hit[301]: begin + addr_hit[295]: begin reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs; reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs; reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs; @@ -39076,7 +38815,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs; end - addr_hit[302]: begin + addr_hit[296]: begin reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs; reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs; reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs; @@ -39089,7 +38828,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs; end - addr_hit[303]: begin + addr_hit[297]: begin reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs; reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs; reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs; @@ -39102,7 +38841,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs; end - addr_hit[304]: begin + addr_hit[298]: begin reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs; reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs; reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs; @@ -39115,7 +38854,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs; end - addr_hit[305]: begin + addr_hit[299]: begin reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs; reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs; reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs; @@ -39128,7 +38867,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs; end - addr_hit[306]: begin + addr_hit[300]: begin reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs; reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs; reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs; @@ -39141,7 +38880,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs; end - addr_hit[307]: begin + addr_hit[301]: begin reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs; reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs; reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs; @@ -39154,7 +38893,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs; end - addr_hit[308]: begin + addr_hit[302]: begin reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs; reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs; reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs; @@ -39167,71 +38906,71 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs; end - addr_hit[309]: begin + addr_hit[303]: begin reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end - addr_hit[310]: begin + addr_hit[304]: begin reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end - addr_hit[311]: begin + addr_hit[305]: begin reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end - addr_hit[312]: begin + addr_hit[306]: begin reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end - addr_hit[313]: begin + addr_hit[307]: begin reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end - addr_hit[314]: begin + addr_hit[308]: begin reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end - addr_hit[315]: begin + addr_hit[309]: begin reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end - addr_hit[316]: begin + addr_hit[310]: begin reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end - addr_hit[317]: begin + addr_hit[311]: begin reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end - addr_hit[318]: begin + addr_hit[312]: begin reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end - addr_hit[319]: begin + addr_hit[313]: begin reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end - addr_hit[320]: begin + addr_hit[314]: begin reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end - addr_hit[321]: begin + addr_hit[315]: begin reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end - addr_hit[322]: begin + addr_hit[316]: begin reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end - addr_hit[323]: begin + addr_hit[317]: begin reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end - addr_hit[324]: begin + addr_hit[318]: begin reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; end - addr_hit[325]: begin + addr_hit[319]: begin reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; @@ -39244,7 +38983,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; end - addr_hit[326]: begin + addr_hit[320]: begin reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; @@ -39257,7 +38996,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; end - addr_hit[327]: begin + addr_hit[321]: begin reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; @@ -39270,7 +39009,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; end - addr_hit[328]: begin + addr_hit[322]: begin reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; @@ -39283,7 +39022,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; end - addr_hit[329]: begin + addr_hit[323]: begin reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; @@ -39296,7 +39035,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; end - addr_hit[330]: begin + addr_hit[324]: begin reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; @@ -39309,7 +39048,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; end - addr_hit[331]: begin + addr_hit[325]: begin reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; @@ -39322,7 +39061,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; end - addr_hit[332]: begin + addr_hit[326]: begin reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; @@ -39335,7 +39074,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; end - addr_hit[333]: begin + addr_hit[327]: begin reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; @@ -39348,7 +39087,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; end - addr_hit[334]: begin + addr_hit[328]: begin reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; @@ -39361,7 +39100,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; end - addr_hit[335]: begin + addr_hit[329]: begin reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; @@ -39374,7 +39113,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; end - addr_hit[336]: begin + addr_hit[330]: begin reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; @@ -39387,7 +39126,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; end - addr_hit[337]: begin + addr_hit[331]: begin reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; @@ -39400,7 +39139,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; end - addr_hit[338]: begin + addr_hit[332]: begin reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; @@ -39413,7 +39152,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; end - addr_hit[339]: begin + addr_hit[333]: begin reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; @@ -39426,7 +39165,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; end - addr_hit[340]: begin + addr_hit[334]: begin reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; @@ -39439,7 +39178,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; end - addr_hit[341]: begin + addr_hit[335]: begin reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs; @@ -39474,7 +39213,7 @@ module pinmux_reg_top ( reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs; end - addr_hit[342]: begin + addr_hit[336]: begin reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs; @@ -39492,571 +39231,571 @@ module pinmux_reg_top ( reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs; end - addr_hit[343]: begin + addr_hit[337]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end - addr_hit[344]: begin + addr_hit[338]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end - addr_hit[345]: begin + addr_hit[339]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end - addr_hit[346]: begin + addr_hit[340]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end - addr_hit[347]: begin + addr_hit[341]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end - addr_hit[348]: begin + addr_hit[342]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end - addr_hit[349]: begin + addr_hit[343]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end - addr_hit[350]: begin + addr_hit[344]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end - addr_hit[351]: begin + addr_hit[345]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end - addr_hit[352]: begin + addr_hit[346]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end - addr_hit[353]: begin + addr_hit[347]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end - addr_hit[354]: begin + addr_hit[348]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end - addr_hit[355]: begin + addr_hit[349]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end - addr_hit[356]: begin + addr_hit[350]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end - addr_hit[357]: begin + addr_hit[351]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end - addr_hit[358]: begin + addr_hit[352]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; end - addr_hit[359]: begin + addr_hit[353]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; end - addr_hit[360]: begin + addr_hit[354]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; end - addr_hit[361]: begin + addr_hit[355]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; end - addr_hit[362]: begin + addr_hit[356]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; end - addr_hit[363]: begin + addr_hit[357]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; end - addr_hit[364]: begin + addr_hit[358]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; end - addr_hit[365]: begin + addr_hit[359]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; end - addr_hit[366]: begin + addr_hit[360]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; end - addr_hit[367]: begin + addr_hit[361]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; end - addr_hit[368]: begin + addr_hit[362]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; end - addr_hit[369]: begin + addr_hit[363]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; end - addr_hit[370]: begin + addr_hit[364]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; end - addr_hit[371]: begin + addr_hit[365]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; end - addr_hit[372]: begin + addr_hit[366]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; end - addr_hit[373]: begin + addr_hit[367]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; end - addr_hit[374]: begin + addr_hit[368]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; end - addr_hit[375]: begin + addr_hit[369]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs; end - addr_hit[376]: begin + addr_hit[370]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs; end - addr_hit[377]: begin + addr_hit[371]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs; end - addr_hit[378]: begin + addr_hit[372]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs; end - addr_hit[379]: begin + addr_hit[373]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs; end - addr_hit[380]: begin + addr_hit[374]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs; end - addr_hit[381]: begin + addr_hit[375]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs; end - addr_hit[382]: begin + addr_hit[376]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs; end - addr_hit[383]: begin + addr_hit[377]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs; end - addr_hit[384]: begin + addr_hit[378]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs; end - addr_hit[385]: begin + addr_hit[379]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs; end - addr_hit[386]: begin + addr_hit[380]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs; end - addr_hit[387]: begin + addr_hit[381]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs; end - addr_hit[388]: begin + addr_hit[382]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs; end - addr_hit[389]: begin + addr_hit[383]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs; end - addr_hit[390]: begin + addr_hit[384]: begin reg_rdata_next[0] = mio_pad_sleep_en_0_qs; end - addr_hit[391]: begin + addr_hit[385]: begin reg_rdata_next[0] = mio_pad_sleep_en_1_qs; end - addr_hit[392]: begin + addr_hit[386]: begin reg_rdata_next[0] = mio_pad_sleep_en_2_qs; end - addr_hit[393]: begin + addr_hit[387]: begin reg_rdata_next[0] = mio_pad_sleep_en_3_qs; end - addr_hit[394]: begin + addr_hit[388]: begin reg_rdata_next[0] = mio_pad_sleep_en_4_qs; end - addr_hit[395]: begin + addr_hit[389]: begin reg_rdata_next[0] = mio_pad_sleep_en_5_qs; end - addr_hit[396]: begin + addr_hit[390]: begin reg_rdata_next[0] = mio_pad_sleep_en_6_qs; end - addr_hit[397]: begin + addr_hit[391]: begin reg_rdata_next[0] = mio_pad_sleep_en_7_qs; end - addr_hit[398]: begin + addr_hit[392]: begin reg_rdata_next[0] = mio_pad_sleep_en_8_qs; end - addr_hit[399]: begin + addr_hit[393]: begin reg_rdata_next[0] = mio_pad_sleep_en_9_qs; end - addr_hit[400]: begin + addr_hit[394]: begin reg_rdata_next[0] = mio_pad_sleep_en_10_qs; end - addr_hit[401]: begin + addr_hit[395]: begin reg_rdata_next[0] = mio_pad_sleep_en_11_qs; end - addr_hit[402]: begin + addr_hit[396]: begin reg_rdata_next[0] = mio_pad_sleep_en_12_qs; end - addr_hit[403]: begin + addr_hit[397]: begin reg_rdata_next[0] = mio_pad_sleep_en_13_qs; end - addr_hit[404]: begin + addr_hit[398]: begin reg_rdata_next[0] = mio_pad_sleep_en_14_qs; end - addr_hit[405]: begin + addr_hit[399]: begin reg_rdata_next[0] = mio_pad_sleep_en_15_qs; end - addr_hit[406]: begin + addr_hit[400]: begin reg_rdata_next[0] = mio_pad_sleep_en_16_qs; end - addr_hit[407]: begin + addr_hit[401]: begin reg_rdata_next[0] = mio_pad_sleep_en_17_qs; end - addr_hit[408]: begin + addr_hit[402]: begin reg_rdata_next[0] = mio_pad_sleep_en_18_qs; end - addr_hit[409]: begin + addr_hit[403]: begin reg_rdata_next[0] = mio_pad_sleep_en_19_qs; end - addr_hit[410]: begin + addr_hit[404]: begin reg_rdata_next[0] = mio_pad_sleep_en_20_qs; end - addr_hit[411]: begin + addr_hit[405]: begin reg_rdata_next[0] = mio_pad_sleep_en_21_qs; end - addr_hit[412]: begin + addr_hit[406]: begin reg_rdata_next[0] = mio_pad_sleep_en_22_qs; end - addr_hit[413]: begin + addr_hit[407]: begin reg_rdata_next[0] = mio_pad_sleep_en_23_qs; end - addr_hit[414]: begin + addr_hit[408]: begin reg_rdata_next[0] = mio_pad_sleep_en_24_qs; end - addr_hit[415]: begin + addr_hit[409]: begin reg_rdata_next[0] = mio_pad_sleep_en_25_qs; end - addr_hit[416]: begin + addr_hit[410]: begin reg_rdata_next[0] = mio_pad_sleep_en_26_qs; end - addr_hit[417]: begin + addr_hit[411]: begin reg_rdata_next[0] = mio_pad_sleep_en_27_qs; end - addr_hit[418]: begin + addr_hit[412]: begin reg_rdata_next[0] = mio_pad_sleep_en_28_qs; end - addr_hit[419]: begin + addr_hit[413]: begin reg_rdata_next[0] = mio_pad_sleep_en_29_qs; end - addr_hit[420]: begin + addr_hit[414]: begin reg_rdata_next[0] = mio_pad_sleep_en_30_qs; end - addr_hit[421]: begin + addr_hit[415]: begin reg_rdata_next[0] = mio_pad_sleep_en_31_qs; end - addr_hit[422]: begin + addr_hit[416]: begin reg_rdata_next[0] = mio_pad_sleep_en_32_qs; end - addr_hit[423]: begin + addr_hit[417]: begin reg_rdata_next[0] = mio_pad_sleep_en_33_qs; end - addr_hit[424]: begin + addr_hit[418]: begin reg_rdata_next[0] = mio_pad_sleep_en_34_qs; end - addr_hit[425]: begin + addr_hit[419]: begin reg_rdata_next[0] = mio_pad_sleep_en_35_qs; end - addr_hit[426]: begin + addr_hit[420]: begin reg_rdata_next[0] = mio_pad_sleep_en_36_qs; end - addr_hit[427]: begin + addr_hit[421]: begin reg_rdata_next[0] = mio_pad_sleep_en_37_qs; end - addr_hit[428]: begin + addr_hit[422]: begin reg_rdata_next[0] = mio_pad_sleep_en_38_qs; end - addr_hit[429]: begin + addr_hit[423]: begin reg_rdata_next[0] = mio_pad_sleep_en_39_qs; end - addr_hit[430]: begin + addr_hit[424]: begin reg_rdata_next[0] = mio_pad_sleep_en_40_qs; end - addr_hit[431]: begin + addr_hit[425]: begin reg_rdata_next[0] = mio_pad_sleep_en_41_qs; end - addr_hit[432]: begin + addr_hit[426]: begin reg_rdata_next[0] = mio_pad_sleep_en_42_qs; end - addr_hit[433]: begin + addr_hit[427]: begin reg_rdata_next[0] = mio_pad_sleep_en_43_qs; end - addr_hit[434]: begin + addr_hit[428]: begin reg_rdata_next[0] = mio_pad_sleep_en_44_qs; end - addr_hit[435]: begin + addr_hit[429]: begin reg_rdata_next[0] = mio_pad_sleep_en_45_qs; end - addr_hit[436]: begin + addr_hit[430]: begin reg_rdata_next[0] = mio_pad_sleep_en_46_qs; end - addr_hit[437]: begin + addr_hit[431]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; end - addr_hit[438]: begin + addr_hit[432]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; end - addr_hit[439]: begin + addr_hit[433]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; end - addr_hit[440]: begin + addr_hit[434]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; end - addr_hit[441]: begin + addr_hit[435]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; end - addr_hit[442]: begin + addr_hit[436]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; end - addr_hit[443]: begin + addr_hit[437]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; end - addr_hit[444]: begin + addr_hit[438]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; end - addr_hit[445]: begin + addr_hit[439]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; end - addr_hit[446]: begin + addr_hit[440]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; end - addr_hit[447]: begin + addr_hit[441]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; end - addr_hit[448]: begin + addr_hit[442]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; end - addr_hit[449]: begin + addr_hit[443]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; end - addr_hit[450]: begin + addr_hit[444]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; end - addr_hit[451]: begin + addr_hit[445]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; end - addr_hit[452]: begin + addr_hit[446]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; end - addr_hit[453]: begin + addr_hit[447]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; end - addr_hit[454]: begin + addr_hit[448]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; end - addr_hit[455]: begin + addr_hit[449]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; end - addr_hit[456]: begin + addr_hit[450]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; end - addr_hit[457]: begin + addr_hit[451]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; end - addr_hit[458]: begin + addr_hit[452]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; end - addr_hit[459]: begin + addr_hit[453]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; end - addr_hit[460]: begin + addr_hit[454]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; end - addr_hit[461]: begin + addr_hit[455]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; end - addr_hit[462]: begin + addr_hit[456]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; end - addr_hit[463]: begin + addr_hit[457]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; end - addr_hit[464]: begin + addr_hit[458]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; end - addr_hit[465]: begin + addr_hit[459]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; end - addr_hit[466]: begin + addr_hit[460]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; end - addr_hit[467]: begin + addr_hit[461]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; end - addr_hit[468]: begin + addr_hit[462]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; end - addr_hit[469]: begin + addr_hit[463]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs; end - addr_hit[470]: begin + addr_hit[464]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs; end - addr_hit[471]: begin + addr_hit[465]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs; end - addr_hit[472]: begin + addr_hit[466]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs; end - addr_hit[473]: begin + addr_hit[467]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs; end - addr_hit[474]: begin + addr_hit[468]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs; end - addr_hit[475]: begin + addr_hit[469]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs; end - addr_hit[476]: begin + addr_hit[470]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs; end - addr_hit[477]: begin + addr_hit[471]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs; end - addr_hit[478]: begin + addr_hit[472]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs; end - addr_hit[479]: begin + addr_hit[473]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs; end - addr_hit[480]: begin + addr_hit[474]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs; end - addr_hit[481]: begin + addr_hit[475]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs; end - addr_hit[482]: begin + addr_hit[476]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs; end - addr_hit[483]: begin + addr_hit[477]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs; end - addr_hit[484]: begin + addr_hit[478]: begin reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; @@ -40075,335 +39814,335 @@ module pinmux_reg_top ( reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs; end - addr_hit[485]: begin + addr_hit[479]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; end - addr_hit[486]: begin + addr_hit[480]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; end - addr_hit[487]: begin + addr_hit[481]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; end - addr_hit[488]: begin + addr_hit[482]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; end - addr_hit[489]: begin + addr_hit[483]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; end - addr_hit[490]: begin + addr_hit[484]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; end - addr_hit[491]: begin + addr_hit[485]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; end - addr_hit[492]: begin + addr_hit[486]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; end - addr_hit[493]: begin + addr_hit[487]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; end - addr_hit[494]: begin + addr_hit[488]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; end - addr_hit[495]: begin + addr_hit[489]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; end - addr_hit[496]: begin + addr_hit[490]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; end - addr_hit[497]: begin + addr_hit[491]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; end - addr_hit[498]: begin + addr_hit[492]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; end - addr_hit[499]: begin + addr_hit[493]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; end - addr_hit[500]: begin + addr_hit[494]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; end - addr_hit[501]: begin + addr_hit[495]: begin reg_rdata_next[0] = dio_pad_sleep_en_0_qs; end - addr_hit[502]: begin + addr_hit[496]: begin reg_rdata_next[0] = dio_pad_sleep_en_1_qs; end - addr_hit[503]: begin + addr_hit[497]: begin reg_rdata_next[0] = dio_pad_sleep_en_2_qs; end - addr_hit[504]: begin + addr_hit[498]: begin reg_rdata_next[0] = dio_pad_sleep_en_3_qs; end - addr_hit[505]: begin + addr_hit[499]: begin reg_rdata_next[0] = dio_pad_sleep_en_4_qs; end - addr_hit[506]: begin + addr_hit[500]: begin reg_rdata_next[0] = dio_pad_sleep_en_5_qs; end - addr_hit[507]: begin + addr_hit[501]: begin reg_rdata_next[0] = dio_pad_sleep_en_6_qs; end - addr_hit[508]: begin + addr_hit[502]: begin reg_rdata_next[0] = dio_pad_sleep_en_7_qs; end - addr_hit[509]: begin + addr_hit[503]: begin reg_rdata_next[0] = dio_pad_sleep_en_8_qs; end - addr_hit[510]: begin + addr_hit[504]: begin reg_rdata_next[0] = dio_pad_sleep_en_9_qs; end - addr_hit[511]: begin + addr_hit[505]: begin reg_rdata_next[0] = dio_pad_sleep_en_10_qs; end - addr_hit[512]: begin + addr_hit[506]: begin reg_rdata_next[0] = dio_pad_sleep_en_11_qs; end - addr_hit[513]: begin + addr_hit[507]: begin reg_rdata_next[0] = dio_pad_sleep_en_12_qs; end - addr_hit[514]: begin + addr_hit[508]: begin reg_rdata_next[0] = dio_pad_sleep_en_13_qs; end - addr_hit[515]: begin + addr_hit[509]: begin reg_rdata_next[0] = dio_pad_sleep_en_14_qs; end - addr_hit[516]: begin + addr_hit[510]: begin reg_rdata_next[0] = dio_pad_sleep_en_15_qs; end - addr_hit[517]: begin + addr_hit[511]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; end - addr_hit[518]: begin + addr_hit[512]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; end - addr_hit[519]: begin + addr_hit[513]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; end - addr_hit[520]: begin + addr_hit[514]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; end - addr_hit[521]: begin + addr_hit[515]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; end - addr_hit[522]: begin + addr_hit[516]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; end - addr_hit[523]: begin + addr_hit[517]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; end - addr_hit[524]: begin + addr_hit[518]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; end - addr_hit[525]: begin + addr_hit[519]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; end - addr_hit[526]: begin + addr_hit[520]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; end - addr_hit[527]: begin + addr_hit[521]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; end - addr_hit[528]: begin + addr_hit[522]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; end - addr_hit[529]: begin + addr_hit[523]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; end - addr_hit[530]: begin + addr_hit[524]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; end - addr_hit[531]: begin + addr_hit[525]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; end - addr_hit[532]: begin + addr_hit[526]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; end - addr_hit[533]: begin + addr_hit[527]: begin reg_rdata_next[0] = wkup_detector_regwen_0_qs; end - addr_hit[534]: begin + addr_hit[528]: begin reg_rdata_next[0] = wkup_detector_regwen_1_qs; end - addr_hit[535]: begin + addr_hit[529]: begin reg_rdata_next[0] = wkup_detector_regwen_2_qs; end - addr_hit[536]: begin + addr_hit[530]: begin reg_rdata_next[0] = wkup_detector_regwen_3_qs; end - addr_hit[537]: begin + addr_hit[531]: begin reg_rdata_next[0] = wkup_detector_regwen_4_qs; end - addr_hit[538]: begin + addr_hit[532]: begin reg_rdata_next[0] = wkup_detector_regwen_5_qs; end - addr_hit[539]: begin + addr_hit[533]: begin reg_rdata_next[0] = wkup_detector_regwen_6_qs; end - addr_hit[540]: begin + addr_hit[534]: begin reg_rdata_next[0] = wkup_detector_regwen_7_qs; end - addr_hit[541]: begin + addr_hit[535]: begin reg_rdata_next = DW'(wkup_detector_en_0_qs); end - addr_hit[542]: begin + addr_hit[536]: begin reg_rdata_next = DW'(wkup_detector_en_1_qs); end - addr_hit[543]: begin + addr_hit[537]: begin reg_rdata_next = DW'(wkup_detector_en_2_qs); end - addr_hit[544]: begin + addr_hit[538]: begin reg_rdata_next = DW'(wkup_detector_en_3_qs); end - addr_hit[545]: begin + addr_hit[539]: begin reg_rdata_next = DW'(wkup_detector_en_4_qs); end - addr_hit[546]: begin + addr_hit[540]: begin reg_rdata_next = DW'(wkup_detector_en_5_qs); end - addr_hit[547]: begin + addr_hit[541]: begin reg_rdata_next = DW'(wkup_detector_en_6_qs); end - addr_hit[548]: begin + addr_hit[542]: begin reg_rdata_next = DW'(wkup_detector_en_7_qs); end - addr_hit[549]: begin + addr_hit[543]: begin reg_rdata_next = DW'(wkup_detector_0_qs); end - addr_hit[550]: begin + addr_hit[544]: begin reg_rdata_next = DW'(wkup_detector_1_qs); end - addr_hit[551]: begin + addr_hit[545]: begin reg_rdata_next = DW'(wkup_detector_2_qs); end - addr_hit[552]: begin + addr_hit[546]: begin reg_rdata_next = DW'(wkup_detector_3_qs); end - addr_hit[553]: begin + addr_hit[547]: begin reg_rdata_next = DW'(wkup_detector_4_qs); end - addr_hit[554]: begin + addr_hit[548]: begin reg_rdata_next = DW'(wkup_detector_5_qs); end - addr_hit[555]: begin + addr_hit[549]: begin reg_rdata_next = DW'(wkup_detector_6_qs); end - addr_hit[556]: begin + addr_hit[550]: begin reg_rdata_next = DW'(wkup_detector_7_qs); end - addr_hit[557]: begin + addr_hit[551]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); end - addr_hit[558]: begin + addr_hit[552]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); end - addr_hit[559]: begin + addr_hit[553]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); end - addr_hit[560]: begin + addr_hit[554]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); end - addr_hit[561]: begin + addr_hit[555]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); end - addr_hit[562]: begin + addr_hit[556]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); end - addr_hit[563]: begin + addr_hit[557]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); end - addr_hit[564]: begin + addr_hit[558]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); end - addr_hit[565]: begin + addr_hit[559]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[566]: begin + addr_hit[560]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[567]: begin + addr_hit[561]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[568]: begin + addr_hit[562]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[569]: begin + addr_hit[563]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[570]: begin + addr_hit[564]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[571]: begin + addr_hit[565]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[572]: begin + addr_hit[566]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[573]: begin + addr_hit[567]: begin reg_rdata_next = DW'(wkup_cause_qs); end default: begin @@ -40422,79 +40161,79 @@ module pinmux_reg_top ( always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[541]: begin + addr_hit[535]: begin reg_busy_sel = wkup_detector_en_0_busy; end - addr_hit[542]: begin + addr_hit[536]: begin reg_busy_sel = wkup_detector_en_1_busy; end - addr_hit[543]: begin + addr_hit[537]: begin reg_busy_sel = wkup_detector_en_2_busy; end - addr_hit[544]: begin + addr_hit[538]: begin reg_busy_sel = wkup_detector_en_3_busy; end - addr_hit[545]: begin + addr_hit[539]: begin reg_busy_sel = wkup_detector_en_4_busy; end - addr_hit[546]: begin + addr_hit[540]: begin reg_busy_sel = wkup_detector_en_5_busy; end - addr_hit[547]: begin + addr_hit[541]: begin reg_busy_sel = wkup_detector_en_6_busy; end - addr_hit[548]: begin + addr_hit[542]: begin reg_busy_sel = wkup_detector_en_7_busy; end - addr_hit[549]: begin + addr_hit[543]: begin reg_busy_sel = wkup_detector_0_busy; end - addr_hit[550]: begin + addr_hit[544]: begin reg_busy_sel = wkup_detector_1_busy; end - addr_hit[551]: begin + addr_hit[545]: begin reg_busy_sel = wkup_detector_2_busy; end - addr_hit[552]: begin + addr_hit[546]: begin reg_busy_sel = wkup_detector_3_busy; end - addr_hit[553]: begin + addr_hit[547]: begin reg_busy_sel = wkup_detector_4_busy; end - addr_hit[554]: begin + addr_hit[548]: begin reg_busy_sel = wkup_detector_5_busy; end - addr_hit[555]: begin + addr_hit[549]: begin reg_busy_sel = wkup_detector_6_busy; end - addr_hit[556]: begin + addr_hit[550]: begin reg_busy_sel = wkup_detector_7_busy; end - addr_hit[557]: begin + addr_hit[551]: begin reg_busy_sel = wkup_detector_cnt_th_0_busy; end - addr_hit[558]: begin + addr_hit[552]: begin reg_busy_sel = wkup_detector_cnt_th_1_busy; end - addr_hit[559]: begin + addr_hit[553]: begin reg_busy_sel = wkup_detector_cnt_th_2_busy; end - addr_hit[560]: begin + addr_hit[554]: begin reg_busy_sel = wkup_detector_cnt_th_3_busy; end - addr_hit[561]: begin + addr_hit[555]: begin reg_busy_sel = wkup_detector_cnt_th_4_busy; end - addr_hit[562]: begin + addr_hit[556]: begin reg_busy_sel = wkup_detector_cnt_th_5_busy; end - addr_hit[563]: begin + addr_hit[557]: begin reg_busy_sel = wkup_detector_cnt_th_6_busy; end - addr_hit[564]: begin + addr_hit[558]: begin reg_busy_sel = wkup_detector_cnt_th_7_busy; end - addr_hit[573]: begin + addr_hit[567]: begin reg_busy_sel = wkup_cause_busy; end default: begin diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson index 9184072914a0b..7fbf9757c3a0f 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson @@ -44,7 +44,7 @@ { name: "NumSrc", desc: "Number of interrupt sources", type: "int", - default: "190", + default: "184", local: "true" }, { name: "NumTarget", diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson index f5efed2cd40c4..dfcda5dc1aed6 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson @@ -6,7 +6,7 @@ param_values: { module_instance_name: rv_plic - src: 190 + src: 184 target: 1 prio: 3 topname: earlgrey diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv index 253d0b1850212..a0e9c2192bd71 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -280,17 +280,11 @@ module rv_plic import rv_plic_reg_pkg::*; #( assign prio[181] = reg2hw.prio[181].q; assign prio[182] = reg2hw.prio[182].q; assign prio[183] = reg2hw.prio[183].q; - assign prio[184] = reg2hw.prio[184].q; - assign prio[185] = reg2hw.prio[185].q; - assign prio[186] = reg2hw.prio[186].q; - assign prio[187] = reg2hw.prio[187].q; - assign prio[188] = reg2hw.prio[188].q; - assign prio[189] = reg2hw.prio[189].q; ////////////////////// // Interrupt Enable // ////////////////////// - for (genvar s = 0; s < 190; s++) begin : gen_ie0 + for (genvar s = 0; s < 184; s++) begin : gen_ie0 assign ie[0][s] = reg2hw.ie0[s].q; end @@ -316,7 +310,7 @@ module rv_plic import rv_plic_reg_pkg::*; #( //////// // IP // //////// - for (genvar s = 0; s < 190; s++) begin : gen_ip + for (genvar s = 0; s < 184; s++) begin : gen_ip assign hw2reg.ip[s].de = 1'b1; // Always write assign hw2reg.ip[s].d = ip[s]; end diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv index 71d52a259b151..e914a5517ce5e 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -7,7 +7,7 @@ package rv_plic_reg_pkg; // Param list - parameter int NumSrc = 190; + parameter int NumSrc = 184; parameter int NumTarget = 1; parameter int PrioWidth = 2; parameter int NumAlerts = 1; @@ -16,7 +16,7 @@ package rv_plic_reg_pkg; parameter int BlockAw = 27; // Number of registers for every interface - parameter int NumRegs = 206; + parameter int NumRegs = 200; // Alert indices typedef enum int { @@ -65,8 +65,8 @@ package rv_plic_reg_pkg; // Register -> HW type typedef struct packed { - rv_plic_reg2hw_prio_mreg_t [189:0] prio; // [584:205] - rv_plic_reg2hw_ie0_mreg_t [189:0] ie0; // [204:15] + rv_plic_reg2hw_prio_mreg_t [183:0] prio; // [566:199] + rv_plic_reg2hw_ie0_mreg_t [183:0] ie0; // [198:15] rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] @@ -75,7 +75,7 @@ package rv_plic_reg_pkg; // HW -> register type typedef struct packed { - rv_plic_hw2reg_ip_mreg_t [189:0] ip; // [387:8] + rv_plic_hw2reg_ip_mreg_t [183:0] ip; // [375:8] rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] } rv_plic_hw2reg_t; @@ -264,12 +264,6 @@ package rv_plic_reg_pkg; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_181_OFFSET = 27'h 2d4; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_182_OFFSET = 27'h 2d8; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_183_OFFSET = 27'h 2dc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_184_OFFSET = 27'h 2e0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_185_OFFSET = 27'h 2e4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_186_OFFSET = 27'h 2e8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_187_OFFSET = 27'h 2ec; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_188_OFFSET = 27'h 2f0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO_189_OFFSET = 27'h 2f4; parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; @@ -477,12 +471,6 @@ package rv_plic_reg_pkg; RV_PLIC_PRIO_181, RV_PLIC_PRIO_182, RV_PLIC_PRIO_183, - RV_PLIC_PRIO_184, - RV_PLIC_PRIO_185, - RV_PLIC_PRIO_186, - RV_PLIC_PRIO_187, - RV_PLIC_PRIO_188, - RV_PLIC_PRIO_189, RV_PLIC_IP_0, RV_PLIC_IP_1, RV_PLIC_IP_2, @@ -502,7 +490,7 @@ package rv_plic_reg_pkg; } rv_plic_id_e; // Register width information to check illegal writes - parameter logic [3:0] RV_PLIC_PERMIT [206] = '{ + parameter logic [3:0] RV_PLIC_PERMIT [200] = '{ 4'b 0001, // index[ 0] RV_PLIC_PRIO_0 4'b 0001, // index[ 1] RV_PLIC_PRIO_1 4'b 0001, // index[ 2] RV_PLIC_PRIO_2 @@ -687,28 +675,22 @@ package rv_plic_reg_pkg; 4'b 0001, // index[181] RV_PLIC_PRIO_181 4'b 0001, // index[182] RV_PLIC_PRIO_182 4'b 0001, // index[183] RV_PLIC_PRIO_183 - 4'b 0001, // index[184] RV_PLIC_PRIO_184 - 4'b 0001, // index[185] RV_PLIC_PRIO_185 - 4'b 0001, // index[186] RV_PLIC_PRIO_186 - 4'b 0001, // index[187] RV_PLIC_PRIO_187 - 4'b 0001, // index[188] RV_PLIC_PRIO_188 - 4'b 0001, // index[189] RV_PLIC_PRIO_189 - 4'b 1111, // index[190] RV_PLIC_IP_0 - 4'b 1111, // index[191] RV_PLIC_IP_1 - 4'b 1111, // index[192] RV_PLIC_IP_2 - 4'b 1111, // index[193] RV_PLIC_IP_3 - 4'b 1111, // index[194] RV_PLIC_IP_4 - 4'b 1111, // index[195] RV_PLIC_IP_5 - 4'b 1111, // index[196] RV_PLIC_IE0_0 - 4'b 1111, // index[197] RV_PLIC_IE0_1 - 4'b 1111, // index[198] RV_PLIC_IE0_2 - 4'b 1111, // index[199] RV_PLIC_IE0_3 - 4'b 1111, // index[200] RV_PLIC_IE0_4 - 4'b 1111, // index[201] RV_PLIC_IE0_5 - 4'b 0001, // index[202] RV_PLIC_THRESHOLD0 - 4'b 0001, // index[203] RV_PLIC_CC0 - 4'b 0001, // index[204] RV_PLIC_MSIP0 - 4'b 0001 // index[205] RV_PLIC_ALERT_TEST + 4'b 1111, // index[184] RV_PLIC_IP_0 + 4'b 1111, // index[185] RV_PLIC_IP_1 + 4'b 1111, // index[186] RV_PLIC_IP_2 + 4'b 1111, // index[187] RV_PLIC_IP_3 + 4'b 1111, // index[188] RV_PLIC_IP_4 + 4'b 0111, // index[189] RV_PLIC_IP_5 + 4'b 1111, // index[190] RV_PLIC_IE0_0 + 4'b 1111, // index[191] RV_PLIC_IE0_1 + 4'b 1111, // index[192] RV_PLIC_IE0_2 + 4'b 1111, // index[193] RV_PLIC_IE0_3 + 4'b 1111, // index[194] RV_PLIC_IE0_4 + 4'b 0111, // index[195] RV_PLIC_IE0_5 + 4'b 0001, // index[196] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[197] RV_PLIC_CC0 + 4'b 0001, // index[198] RV_PLIC_MSIP0 + 4'b 0001 // index[199] RV_PLIC_ALERT_TEST }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv index f7e3aacdc0656..fe267439e9eb7 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -52,9 +52,9 @@ module rv_plic_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [205:0] reg_we_check; + logic [199:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(206) + .OneHotWidth(200) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -673,24 +673,6 @@ module rv_plic_reg_top ( logic prio_183_we; logic [1:0] prio_183_qs; logic [1:0] prio_183_wd; - logic prio_184_we; - logic [1:0] prio_184_qs; - logic [1:0] prio_184_wd; - logic prio_185_we; - logic [1:0] prio_185_qs; - logic [1:0] prio_185_wd; - logic prio_186_we; - logic [1:0] prio_186_qs; - logic [1:0] prio_186_wd; - logic prio_187_we; - logic [1:0] prio_187_qs; - logic [1:0] prio_187_wd; - logic prio_188_we; - logic [1:0] prio_188_qs; - logic [1:0] prio_188_wd; - logic prio_189_we; - logic [1:0] prio_189_qs; - logic [1:0] prio_189_wd; logic ip_0_p_0_qs; logic ip_0_p_1_qs; logic ip_0_p_2_qs; @@ -875,12 +857,6 @@ module rv_plic_reg_top ( logic ip_5_p_181_qs; logic ip_5_p_182_qs; logic ip_5_p_183_qs; - logic ip_5_p_184_qs; - logic ip_5_p_185_qs; - logic ip_5_p_186_qs; - logic ip_5_p_187_qs; - logic ip_5_p_188_qs; - logic ip_5_p_189_qs; logic ie0_0_we; logic ie0_0_e_0_qs; logic ie0_0_e_0_wd; @@ -1255,18 +1231,6 @@ module rv_plic_reg_top ( logic ie0_5_e_182_wd; logic ie0_5_e_183_qs; logic ie0_5_e_183_wd; - logic ie0_5_e_184_qs; - logic ie0_5_e_184_wd; - logic ie0_5_e_185_qs; - logic ie0_5_e_185_wd; - logic ie0_5_e_186_qs; - logic ie0_5_e_186_wd; - logic ie0_5_e_187_qs; - logic ie0_5_e_187_wd; - logic ie0_5_e_188_qs; - logic ie0_5_e_188_wd; - logic ie0_5_e_189_qs; - logic ie0_5_e_189_wd; logic threshold0_we; logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; @@ -6617,180 +6581,6 @@ module rv_plic_reg_top ( ); - // Subregister 184 of Multireg prio - // R[prio_184]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_184 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_184_we), - .wd (prio_184_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[184].q), - .ds (), - - // to register interface (read) - .qs (prio_184_qs) - ); - - - // Subregister 185 of Multireg prio - // R[prio_185]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_185 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_185_we), - .wd (prio_185_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[185].q), - .ds (), - - // to register interface (read) - .qs (prio_185_qs) - ); - - - // Subregister 186 of Multireg prio - // R[prio_186]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_186 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_186_we), - .wd (prio_186_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[186].q), - .ds (), - - // to register interface (read) - .qs (prio_186_qs) - ); - - - // Subregister 187 of Multireg prio - // R[prio_187]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_187 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_187_we), - .wd (prio_187_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[187].q), - .ds (), - - // to register interface (read) - .qs (prio_187_qs) - ); - - - // Subregister 188 of Multireg prio - // R[prio_188]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_188 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_188_we), - .wd (prio_188_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[188].q), - .ds (), - - // to register interface (read) - .qs (prio_188_qs) - ); - - - // Subregister 189 of Multireg prio - // R[prio_189]: V(False) - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_prio_189 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (prio_189_we), - .wd (prio_189_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.prio[189].q), - .ds (), - - // to register interface (read) - .qs (prio_189_qs) - ); - - // Subregister 0 of Multireg ip // R[ip_0]: V(False) // F[p_0]: 0:0 @@ -11776,168 +11566,6 @@ module rv_plic_reg_top ( .qs (ip_5_p_183_qs) ); - // F[p_184]: 24:24 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_184 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[184].de), - .d (hw2reg.ip[184].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_184_qs) - ); - - // F[p_185]: 25:25 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_185 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[185].de), - .d (hw2reg.ip[185].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_185_qs) - ); - - // F[p_186]: 26:26 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_186 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[186].de), - .d (hw2reg.ip[186].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_186_qs) - ); - - // F[p_187]: 27:27 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_187 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[187].de), - .d (hw2reg.ip[187].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_187_qs) - ); - - // F[p_188]: 28:28 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_188 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[188].de), - .d (hw2reg.ip[188].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_188_qs) - ); - - // F[p_189]: 29:29 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ip_5_p_189 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.ip[189].de), - .d (hw2reg.ip[189].d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (ip_5_p_189_qs) - ); - // Subregister 0 of Multireg ie0 // R[ie0_0]: V(False) @@ -16924,168 +16552,6 @@ module rv_plic_reg_top ( .qs (ie0_5_e_183_qs) ); - // F[e_184]: 24:24 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_184 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_184_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[184].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_184_qs) - ); - - // F[e_185]: 25:25 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_185 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_185_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[185].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_185_qs) - ); - - // F[e_186]: 26:26 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_186 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_186_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[186].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_186_qs) - ); - - // F[e_187]: 27:27 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_187 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_187_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[187].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_187_qs) - ); - - // F[e_188]: 28:28 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_188 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_188_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[188].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_188_qs) - ); - - // F[e_189]: 29:29 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_ie0_5_e_189 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (ie0_5_we), - .wd (ie0_5_e_189_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.ie0[189].q), - .ds (), - - // to register interface (read) - .qs (ie0_5_e_189_qs) - ); - // R[threshold0]: V(False) prim_subreg #( @@ -17184,7 +16650,7 @@ module rv_plic_reg_top ( - logic [205:0] addr_hit; + logic [199:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO_0_OFFSET); addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO_1_OFFSET); @@ -17370,28 +16836,22 @@ module rv_plic_reg_top ( addr_hit[181] = (reg_addr == RV_PLIC_PRIO_181_OFFSET); addr_hit[182] = (reg_addr == RV_PLIC_PRIO_182_OFFSET); addr_hit[183] = (reg_addr == RV_PLIC_PRIO_183_OFFSET); - addr_hit[184] = (reg_addr == RV_PLIC_PRIO_184_OFFSET); - addr_hit[185] = (reg_addr == RV_PLIC_PRIO_185_OFFSET); - addr_hit[186] = (reg_addr == RV_PLIC_PRIO_186_OFFSET); - addr_hit[187] = (reg_addr == RV_PLIC_PRIO_187_OFFSET); - addr_hit[188] = (reg_addr == RV_PLIC_PRIO_188_OFFSET); - addr_hit[189] = (reg_addr == RV_PLIC_PRIO_189_OFFSET); - addr_hit[190] = (reg_addr == RV_PLIC_IP_0_OFFSET); - addr_hit[191] = (reg_addr == RV_PLIC_IP_1_OFFSET); - addr_hit[192] = (reg_addr == RV_PLIC_IP_2_OFFSET); - addr_hit[193] = (reg_addr == RV_PLIC_IP_3_OFFSET); - addr_hit[194] = (reg_addr == RV_PLIC_IP_4_OFFSET); - addr_hit[195] = (reg_addr == RV_PLIC_IP_5_OFFSET); - addr_hit[196] = (reg_addr == RV_PLIC_IE0_0_OFFSET); - addr_hit[197] = (reg_addr == RV_PLIC_IE0_1_OFFSET); - addr_hit[198] = (reg_addr == RV_PLIC_IE0_2_OFFSET); - addr_hit[199] = (reg_addr == RV_PLIC_IE0_3_OFFSET); - addr_hit[200] = (reg_addr == RV_PLIC_IE0_4_OFFSET); - addr_hit[201] = (reg_addr == RV_PLIC_IE0_5_OFFSET); - addr_hit[202] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); - addr_hit[203] = (reg_addr == RV_PLIC_CC0_OFFSET); - addr_hit[204] = (reg_addr == RV_PLIC_MSIP0_OFFSET); - addr_hit[205] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + addr_hit[184] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[185] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[186] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[187] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[188] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[189] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[190] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[191] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[192] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[193] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[194] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[195] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[196] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[197] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[198] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[199] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -17598,13 +17058,7 @@ module rv_plic_reg_top ( (addr_hit[196] & (|(RV_PLIC_PERMIT[196] & ~reg_be))) | (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))) | (addr_hit[198] & (|(RV_PLIC_PERMIT[198] & ~reg_be))) | - (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))) | - (addr_hit[200] & (|(RV_PLIC_PERMIT[200] & ~reg_be))) | - (addr_hit[201] & (|(RV_PLIC_PERMIT[201] & ~reg_be))) | - (addr_hit[202] & (|(RV_PLIC_PERMIT[202] & ~reg_be))) | - (addr_hit[203] & (|(RV_PLIC_PERMIT[203] & ~reg_be))) | - (addr_hit[204] & (|(RV_PLIC_PERMIT[204] & ~reg_be))) | - (addr_hit[205] & (|(RV_PLIC_PERMIT[205] & ~reg_be))))); + (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))))); end // Generate write-enables @@ -18160,25 +17614,7 @@ module rv_plic_reg_top ( assign prio_183_we = addr_hit[183] & reg_we & !reg_error; assign prio_183_wd = reg_wdata[1:0]; - assign prio_184_we = addr_hit[184] & reg_we & !reg_error; - - assign prio_184_wd = reg_wdata[1:0]; - assign prio_185_we = addr_hit[185] & reg_we & !reg_error; - - assign prio_185_wd = reg_wdata[1:0]; - assign prio_186_we = addr_hit[186] & reg_we & !reg_error; - - assign prio_186_wd = reg_wdata[1:0]; - assign prio_187_we = addr_hit[187] & reg_we & !reg_error; - - assign prio_187_wd = reg_wdata[1:0]; - assign prio_188_we = addr_hit[188] & reg_we & !reg_error; - - assign prio_188_wd = reg_wdata[1:0]; - assign prio_189_we = addr_hit[189] & reg_we & !reg_error; - - assign prio_189_wd = reg_wdata[1:0]; - assign ie0_0_we = addr_hit[196] & reg_we & !reg_error; + assign ie0_0_we = addr_hit[190] & reg_we & !reg_error; assign ie0_0_e_0_wd = reg_wdata[0]; @@ -18243,7 +17679,7 @@ module rv_plic_reg_top ( assign ie0_0_e_30_wd = reg_wdata[30]; assign ie0_0_e_31_wd = reg_wdata[31]; - assign ie0_1_we = addr_hit[197] & reg_we & !reg_error; + assign ie0_1_we = addr_hit[191] & reg_we & !reg_error; assign ie0_1_e_32_wd = reg_wdata[0]; @@ -18308,7 +17744,7 @@ module rv_plic_reg_top ( assign ie0_1_e_62_wd = reg_wdata[30]; assign ie0_1_e_63_wd = reg_wdata[31]; - assign ie0_2_we = addr_hit[198] & reg_we & !reg_error; + assign ie0_2_we = addr_hit[192] & reg_we & !reg_error; assign ie0_2_e_64_wd = reg_wdata[0]; @@ -18373,7 +17809,7 @@ module rv_plic_reg_top ( assign ie0_2_e_94_wd = reg_wdata[30]; assign ie0_2_e_95_wd = reg_wdata[31]; - assign ie0_3_we = addr_hit[199] & reg_we & !reg_error; + assign ie0_3_we = addr_hit[193] & reg_we & !reg_error; assign ie0_3_e_96_wd = reg_wdata[0]; @@ -18438,7 +17874,7 @@ module rv_plic_reg_top ( assign ie0_3_e_126_wd = reg_wdata[30]; assign ie0_3_e_127_wd = reg_wdata[31]; - assign ie0_4_we = addr_hit[200] & reg_we & !reg_error; + assign ie0_4_we = addr_hit[194] & reg_we & !reg_error; assign ie0_4_e_128_wd = reg_wdata[0]; @@ -18503,7 +17939,7 @@ module rv_plic_reg_top ( assign ie0_4_e_158_wd = reg_wdata[30]; assign ie0_4_e_159_wd = reg_wdata[31]; - assign ie0_5_we = addr_hit[201] & reg_we & !reg_error; + assign ie0_5_we = addr_hit[195] & reg_we & !reg_error; assign ie0_5_e_160_wd = reg_wdata[0]; @@ -18552,29 +17988,17 @@ module rv_plic_reg_top ( assign ie0_5_e_182_wd = reg_wdata[22]; assign ie0_5_e_183_wd = reg_wdata[23]; - - assign ie0_5_e_184_wd = reg_wdata[24]; - - assign ie0_5_e_185_wd = reg_wdata[25]; - - assign ie0_5_e_186_wd = reg_wdata[26]; - - assign ie0_5_e_187_wd = reg_wdata[27]; - - assign ie0_5_e_188_wd = reg_wdata[28]; - - assign ie0_5_e_189_wd = reg_wdata[29]; - assign threshold0_we = addr_hit[202] & reg_we & !reg_error; + assign threshold0_we = addr_hit[196] & reg_we & !reg_error; assign threshold0_wd = reg_wdata[1:0]; - assign cc0_re = addr_hit[203] & reg_re & !reg_error; - assign cc0_we = addr_hit[203] & reg_we & !reg_error; + assign cc0_re = addr_hit[197] & reg_re & !reg_error; + assign cc0_we = addr_hit[197] & reg_we & !reg_error; assign cc0_wd = reg_wdata[7:0]; - assign msip0_we = addr_hit[204] & reg_we & !reg_error; + assign msip0_we = addr_hit[198] & reg_we & !reg_error; assign msip0_wd = reg_wdata[0]; - assign alert_test_we = addr_hit[205] & reg_we & !reg_error; + assign alert_test_we = addr_hit[199] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; @@ -18764,28 +18188,22 @@ module rv_plic_reg_top ( reg_we_check[181] = prio_181_we; reg_we_check[182] = prio_182_we; reg_we_check[183] = prio_183_we; - reg_we_check[184] = prio_184_we; - reg_we_check[185] = prio_185_we; - reg_we_check[186] = prio_186_we; - reg_we_check[187] = prio_187_we; - reg_we_check[188] = prio_188_we; - reg_we_check[189] = prio_189_we; - reg_we_check[190] = 1'b0; - reg_we_check[191] = 1'b0; - reg_we_check[192] = 1'b0; - reg_we_check[193] = 1'b0; - reg_we_check[194] = 1'b0; - reg_we_check[195] = 1'b0; - reg_we_check[196] = ie0_0_we; - reg_we_check[197] = ie0_1_we; - reg_we_check[198] = ie0_2_we; - reg_we_check[199] = ie0_3_we; - reg_we_check[200] = ie0_4_we; - reg_we_check[201] = ie0_5_we; - reg_we_check[202] = threshold0_we; - reg_we_check[203] = cc0_we; - reg_we_check[204] = msip0_we; - reg_we_check[205] = alert_test_we; + reg_we_check[184] = 1'b0; + reg_we_check[185] = 1'b0; + reg_we_check[186] = 1'b0; + reg_we_check[187] = 1'b0; + reg_we_check[188] = 1'b0; + reg_we_check[189] = 1'b0; + reg_we_check[190] = ie0_0_we; + reg_we_check[191] = ie0_1_we; + reg_we_check[192] = ie0_2_we; + reg_we_check[193] = ie0_3_we; + reg_we_check[194] = ie0_4_we; + reg_we_check[195] = ie0_5_we; + reg_we_check[196] = threshold0_we; + reg_we_check[197] = cc0_we; + reg_we_check[198] = msip0_we; + reg_we_check[199] = alert_test_we; end // Read data return @@ -19529,30 +18947,6 @@ module rv_plic_reg_top ( end addr_hit[184]: begin - reg_rdata_next[1:0] = prio_184_qs; - end - - addr_hit[185]: begin - reg_rdata_next[1:0] = prio_185_qs; - end - - addr_hit[186]: begin - reg_rdata_next[1:0] = prio_186_qs; - end - - addr_hit[187]: begin - reg_rdata_next[1:0] = prio_187_qs; - end - - addr_hit[188]: begin - reg_rdata_next[1:0] = prio_188_qs; - end - - addr_hit[189]: begin - reg_rdata_next[1:0] = prio_189_qs; - end - - addr_hit[190]: begin reg_rdata_next[0] = ip_0_p_0_qs; reg_rdata_next[1] = ip_0_p_1_qs; reg_rdata_next[2] = ip_0_p_2_qs; @@ -19587,7 +18981,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_0_p_31_qs; end - addr_hit[191]: begin + addr_hit[185]: begin reg_rdata_next[0] = ip_1_p_32_qs; reg_rdata_next[1] = ip_1_p_33_qs; reg_rdata_next[2] = ip_1_p_34_qs; @@ -19622,7 +19016,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_1_p_63_qs; end - addr_hit[192]: begin + addr_hit[186]: begin reg_rdata_next[0] = ip_2_p_64_qs; reg_rdata_next[1] = ip_2_p_65_qs; reg_rdata_next[2] = ip_2_p_66_qs; @@ -19657,7 +19051,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_2_p_95_qs; end - addr_hit[193]: begin + addr_hit[187]: begin reg_rdata_next[0] = ip_3_p_96_qs; reg_rdata_next[1] = ip_3_p_97_qs; reg_rdata_next[2] = ip_3_p_98_qs; @@ -19692,7 +19086,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_3_p_127_qs; end - addr_hit[194]: begin + addr_hit[188]: begin reg_rdata_next[0] = ip_4_p_128_qs; reg_rdata_next[1] = ip_4_p_129_qs; reg_rdata_next[2] = ip_4_p_130_qs; @@ -19727,7 +19121,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_4_p_159_qs; end - addr_hit[195]: begin + addr_hit[189]: begin reg_rdata_next[0] = ip_5_p_160_qs; reg_rdata_next[1] = ip_5_p_161_qs; reg_rdata_next[2] = ip_5_p_162_qs; @@ -19752,15 +19146,9 @@ module rv_plic_reg_top ( reg_rdata_next[21] = ip_5_p_181_qs; reg_rdata_next[22] = ip_5_p_182_qs; reg_rdata_next[23] = ip_5_p_183_qs; - reg_rdata_next[24] = ip_5_p_184_qs; - reg_rdata_next[25] = ip_5_p_185_qs; - reg_rdata_next[26] = ip_5_p_186_qs; - reg_rdata_next[27] = ip_5_p_187_qs; - reg_rdata_next[28] = ip_5_p_188_qs; - reg_rdata_next[29] = ip_5_p_189_qs; end - addr_hit[196]: begin + addr_hit[190]: begin reg_rdata_next[0] = ie0_0_e_0_qs; reg_rdata_next[1] = ie0_0_e_1_qs; reg_rdata_next[2] = ie0_0_e_2_qs; @@ -19795,7 +19183,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_0_e_31_qs; end - addr_hit[197]: begin + addr_hit[191]: begin reg_rdata_next[0] = ie0_1_e_32_qs; reg_rdata_next[1] = ie0_1_e_33_qs; reg_rdata_next[2] = ie0_1_e_34_qs; @@ -19830,7 +19218,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_1_e_63_qs; end - addr_hit[198]: begin + addr_hit[192]: begin reg_rdata_next[0] = ie0_2_e_64_qs; reg_rdata_next[1] = ie0_2_e_65_qs; reg_rdata_next[2] = ie0_2_e_66_qs; @@ -19865,7 +19253,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_2_e_95_qs; end - addr_hit[199]: begin + addr_hit[193]: begin reg_rdata_next[0] = ie0_3_e_96_qs; reg_rdata_next[1] = ie0_3_e_97_qs; reg_rdata_next[2] = ie0_3_e_98_qs; @@ -19900,7 +19288,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_3_e_127_qs; end - addr_hit[200]: begin + addr_hit[194]: begin reg_rdata_next[0] = ie0_4_e_128_qs; reg_rdata_next[1] = ie0_4_e_129_qs; reg_rdata_next[2] = ie0_4_e_130_qs; @@ -19935,7 +19323,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_4_e_159_qs; end - addr_hit[201]: begin + addr_hit[195]: begin reg_rdata_next[0] = ie0_5_e_160_qs; reg_rdata_next[1] = ie0_5_e_161_qs; reg_rdata_next[2] = ie0_5_e_162_qs; @@ -19960,27 +19348,21 @@ module rv_plic_reg_top ( reg_rdata_next[21] = ie0_5_e_181_qs; reg_rdata_next[22] = ie0_5_e_182_qs; reg_rdata_next[23] = ie0_5_e_183_qs; - reg_rdata_next[24] = ie0_5_e_184_qs; - reg_rdata_next[25] = ie0_5_e_185_qs; - reg_rdata_next[26] = ie0_5_e_186_qs; - reg_rdata_next[27] = ie0_5_e_187_qs; - reg_rdata_next[28] = ie0_5_e_188_qs; - reg_rdata_next[29] = ie0_5_e_189_qs; end - addr_hit[202]: begin + addr_hit[196]: begin reg_rdata_next[1:0] = threshold0_qs; end - addr_hit[203]: begin + addr_hit[197]: begin reg_rdata_next[7:0] = cc0_qs; end - addr_hit[204]: begin + addr_hit[198]: begin reg_rdata_next[0] = msip0_qs; end - addr_hit[205]: begin + addr_hit[199]: begin reg_rdata_next[0] = '0; end diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index a5269a7208142..027ecde4b7c40 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -19,9 +19,6 @@ module chip_earlgrey_asic #( inout USB_N, // Manual Pad `INOUT_AI CC1, // Manual Pad `INOUT_AI CC2, // Manual Pad - inout FLASH_TEST_VOLT, // Manual Pad - inout FLASH_TEST_MODE0, // Manual Pad - inout FLASH_TEST_MODE1, // Manual Pad inout RRAM_ANALOG, // Manual Pad inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd @@ -275,7 +272,7 @@ module chip_earlgrey_asic #( logic [3:0] mux_iob_sel; logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; - logic [22:0] dio_in_raw; + logic [19:0] dio_in_raw; logic unused_mio_in_raw; logic unused_dio_in_raw; @@ -288,9 +285,6 @@ module chip_earlgrey_asic #( logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n; logic manual_in_cc1, manual_out_cc1, manual_oe_cc1; logic manual_in_cc2, manual_out_cc2, manual_oe_cc2; - logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt; - logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0; - logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1; logic manual_in_rram_analog, manual_out_rram_analog, manual_oe_rram_analog; pad_attr_t manual_attr_por_n; @@ -298,9 +292,6 @@ module chip_earlgrey_asic #( pad_attr_t manual_attr_usb_n; pad_attr_t manual_attr_cc1; pad_attr_t manual_attr_cc2; - pad_attr_t manual_attr_flash_test_volt; - pad_attr_t manual_attr_flash_test_mode0; - pad_attr_t manual_attr_flash_test_mode1; pad_attr_t manual_attr_rram_analog; ////////////////////// @@ -314,7 +305,7 @@ module chip_earlgrey_asic #( padring #( // Padring specific counts may differ from pinmux config due // to custom, stubbed or added pads. - .NDioPads(23), + .NDioPads(20), .NMioPads(47), .PhysicalPads(1), .NIoBanks(int'(IoBankCount)), @@ -334,9 +325,6 @@ module chip_earlgrey_asic #( scan_role_pkg::DioPadSpiHostD1ScanRole, scan_role_pkg::DioPadSpiHostD0ScanRole, scan_role_pkg::DioPadRramAnalogScanRole, - scan_role_pkg::DioPadFlashTestMode1ScanRole, - scan_role_pkg::DioPadFlashTestMode0ScanRole, - scan_role_pkg::DioPadFlashTestVoltScanRole, scan_role_pkg::DioPadCc2ScanRole, scan_role_pkg::DioPadCc1ScanRole, scan_role_pkg::DioPadUsbNScanRole, @@ -408,9 +396,6 @@ module chip_earlgrey_asic #( pad_orient_pkg::DioPadSpiHostD1PadOrient, pad_orient_pkg::DioPadSpiHostD0PadOrient, pad_orient_pkg::DioPadRramAnalogPadOrient, - pad_orient_pkg::DioPadFlashTestMode1PadOrient, - pad_orient_pkg::DioPadFlashTestMode0PadOrient, - pad_orient_pkg::DioPadFlashTestVoltPadOrient, pad_orient_pkg::DioPadCc2PadOrient, pad_orient_pkg::DioPadCc1PadOrient, pad_orient_pkg::DioPadUsbNPadOrient, @@ -482,9 +467,6 @@ module chip_earlgrey_asic #( IoBankVioa, // SPI_HOST_D1 IoBankVioa, // SPI_HOST_D0 IoBankVcc, // RRAM_ANALOG - IoBankVcc, // FLASH_TEST_MODE1 - IoBankVcc, // FLASH_TEST_MODE0 - IoBankVcc, // FLASH_TEST_VOLT IoBankAvcc, // CC2 IoBankAvcc, // CC1 IoBankVcc, // USB_N @@ -556,9 +538,6 @@ module chip_earlgrey_asic #( BidirStd, // SPI_HOST_D1 BidirStd, // SPI_HOST_D0 AnalogIn0, // RRAM_ANALOG - InputStd, // FLASH_TEST_MODE1 - InputStd, // FLASH_TEST_MODE0 - AnalogIn0, // FLASH_TEST_VOLT BidirTol, // CC2 BidirTol, // CC1 DualBidirTol, // USB_N @@ -639,9 +618,6 @@ module chip_earlgrey_asic #( SPI_HOST_D1, SPI_HOST_D0, RRAM_ANALOG, - FLASH_TEST_MODE1, - FLASH_TEST_MODE0, - FLASH_TEST_VOLT, `ifdef ANALOGSIM '0, `else @@ -732,9 +708,6 @@ module chip_earlgrey_asic #( dio_in[DioSpiHost0Sd1], dio_in[DioSpiHost0Sd0], manual_in_rram_analog, - manual_in_flash_test_mode1, - manual_in_flash_test_mode0, - manual_in_flash_test_volt, manual_in_cc2, manual_in_cc1, manual_in_usb_n, @@ -757,9 +730,6 @@ module chip_earlgrey_asic #( dio_out[DioSpiHost0Sd1], dio_out[DioSpiHost0Sd0], manual_out_rram_analog, - manual_out_flash_test_mode1, - manual_out_flash_test_mode0, - manual_out_flash_test_volt, manual_out_cc2, manual_out_cc1, manual_out_usb_n, @@ -782,9 +752,6 @@ module chip_earlgrey_asic #( dio_oe[DioSpiHost0Sd1], dio_oe[DioSpiHost0Sd0], manual_oe_rram_analog, - manual_oe_flash_test_mode1, - manual_oe_flash_test_mode0, - manual_oe_flash_test_volt, manual_oe_cc2, manual_oe_cc1, manual_oe_usb_n, @@ -807,9 +774,6 @@ module chip_earlgrey_asic #( dio_attr[DioSpiHost0Sd1], dio_attr[DioSpiHost0Sd0], manual_attr_rram_analog, - manual_attr_flash_test_mode1, - manual_attr_flash_test_mode0, - manual_attr_flash_test_volt, manual_attr_cc2, manual_attr_cc1, manual_attr_usb_n, @@ -877,10 +841,11 @@ module chip_earlgrey_asic #( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; + assign flash_obs = '0; // clock bypass req/ack prim_mubi_pkg::mubi4_t io_clk_byp_req; @@ -1052,7 +1017,7 @@ module chip_earlgrey_asic #( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -1109,6 +1074,7 @@ module chip_earlgrey_asic #( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections // Single aggregated request/response struct, driven from the AST's internal @@ -1121,6 +1087,12 @@ module chip_earlgrey_asic #( .scan_reset_no ( scan_rst_n ) ); + logic unused_flash_ast_sigs; + assign unused_flash_ast_sigs = ^{ + flash_bist_enable, + flash_power_down_h, + flash_power_ready_h + }; ////////////////////////////////// @@ -1135,12 +1107,6 @@ module chip_earlgrey_asic #( assign manual_out_cc2 = 1'b0; assign manual_oe_cc2 = 1'b0; - assign manual_out_flash_test_mode0 = 1'b0; - assign manual_oe_flash_test_mode0 = 1'b0; - assign manual_out_flash_test_mode1 = 1'b0; - assign manual_oe_flash_test_mode1 = 1'b0; - assign manual_out_flash_test_volt = 1'b0; - assign manual_oe_flash_test_volt = 1'b0; assign manual_out_rram_analog = 1'b0; assign manual_oe_rram_analog = 1'b0; @@ -1152,20 +1118,22 @@ module chip_earlgrey_asic #( prim_pad_wrapper_pkg::pad_attr_t [3:0] sensor_ctrl_manual_pad_attr; assign manual_attr_cc1 = sensor_ctrl_manual_pad_attr[0]; assign manual_attr_cc2 = sensor_ctrl_manual_pad_attr[1]; - assign manual_attr_flash_test_mode0 = sensor_ctrl_manual_pad_attr[2]; - assign manual_attr_flash_test_mode1 = sensor_ctrl_manual_pad_attr[3]; + + // Indices 2 and 3 used to map to FLASH_TEST_MODE0/1, which no longer exist + // now that flash_ctrl has been removed from this top. + logic unused_sensor_ctrl_manual_pad_attr; + assign unused_sensor_ctrl_manual_pad_attr = ^{ + sensor_ctrl_manual_pad_attr[2], + sensor_ctrl_manual_pad_attr[3] + }; // These pad attributes are currently tied off permanently (these are supply pads). - assign manual_attr_flash_test_volt = '0; assign manual_attr_rram_analog = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ manual_in_cc2, manual_in_cc1, - manual_in_flash_test_volt, - manual_in_flash_test_mode0, - manual_in_flash_test_mode1, manual_in_rram_analog }; @@ -1288,12 +1256,6 @@ module chip_earlgrey_asic #( .hi_speed_sel_o (hi_speed_sel ), .div_step_down_req_i (div_step_down_req ), .calib_rdy_i (ast_init_done ), - .flash_bist_enable_i (flash_bist_enable ), - .flash_power_down_h_i (flash_power_down_h ), - .flash_power_ready_h_i (flash_power_ready_h ), - .flash_test_mode_a_io ({FLASH_TEST_MODE1, FLASH_TEST_MODE0}), - .flash_test_voltage_h_io (FLASH_TEST_VOLT ), - .flash_obs_o (flash_obs ), .es_rng_enable_o (es_rng_enable ), .es_rng_valid_i (es_rng_valid ), .es_rng_bit_i (es_rng_bit ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv index 32e1db5d5eaa3..f68026a595540 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv @@ -324,7 +324,7 @@ module chip_earlgrey_cw340 #( ///////////////////////// // Only signals going to non-custom pads need to be tied off. - logic [69:0] unused_sig; + logic [66:0] unused_sig; ////////////////////// // Padring Instance // ////////////////////// @@ -744,10 +744,11 @@ module chip_earlgrey_cw340 #( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; + assign flash_obs = '0; // clock bypass req/ack prim_mubi_pkg::mubi4_t io_clk_byp_req; @@ -935,7 +936,7 @@ module chip_earlgrey_cw340 #( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -992,6 +993,7 @@ module chip_earlgrey_cw340 #( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections // Single aggregated request/response struct, driven from the AST's internal @@ -1004,6 +1006,12 @@ module chip_earlgrey_cw340 #( .scan_reset_no ( scan_rst_n ) ); + logic unused_flash_ast_sigs; + assign unused_flash_ast_sigs = ^{ + flash_bist_enable, + flash_power_down_h, + flash_power_ready_h + }; ///////////////////// // Memory Backdoor // @@ -1201,12 +1209,6 @@ module chip_earlgrey_cw340 #( .hi_speed_sel_o (hi_speed_sel ), .div_step_down_req_i (div_step_down_req ), .calib_rdy_i (ast_init_done ), - .flash_bist_enable_i (flash_bist_enable ), - .flash_power_down_h_i (1'b0 ), - .flash_power_ready_h_i (1'b1 ), - .flash_test_mode_a_io ('0 ), - .flash_test_voltage_h_io (1'b0 ), - .flash_obs_o (flash_obs ), .es_rng_enable_o (es_rng_enable ), .es_rng_valid_i (es_rng_valid ), .es_rng_bit_i (es_rng_bit ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv index 7672a3e506bd0..131e8b4fbccf8 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv @@ -297,10 +297,11 @@ module chip_earlgrey_verilator ( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; + assign flash_obs = '0; // clock bypass req/ack prim_mubi_pkg::mubi4_t io_clk_byp_req; @@ -509,7 +510,7 @@ module chip_earlgrey_verilator ( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -566,6 +567,7 @@ module chip_earlgrey_verilator ( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections // Single aggregated request/response struct, driven from the AST's internal @@ -578,6 +580,12 @@ module chip_earlgrey_verilator ( .scan_reset_no ( scan_rst_n ) ); + logic unused_flash_ast_sigs; + assign unused_flash_ast_sigs = ^{ + flash_bist_enable, + flash_power_down_h, + flash_power_ready_h + }; ///////////////////////////////////////////// @@ -656,12 +664,6 @@ module chip_earlgrey_verilator ( .hi_speed_sel_o (hi_speed_sel ), .div_step_down_req_i (div_step_down_req ), .calib_rdy_i (ast_init_done ), - .flash_bist_enable_i (flash_bist_enable ), - .flash_power_down_h_i (flash_power_down_h ), - .flash_power_ready_h_i (flash_power_ready_h ), - .flash_test_mode_a_io ( ), - .flash_test_voltage_h_io ( ), - .flash_obs_o (flash_obs ), .es_rng_enable_o (es_rng_enable ), .es_rng_valid_i (es_rng_valid ), .es_rng_bit_i (es_rng_bit ), diff --git a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv index 3a92471d602f3..4241fbe043e35 100644 --- a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv +++ b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv @@ -39,10 +39,6 @@ module earlgrey_pd_main #( // parameters for pinmux parameter bit SecPinmuxVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, parameter pinmux_pkg::target_cfg_t PinmuxTargetCfg = pinmux_pkg::DefaultTargetCfg, - // parameters for flash_ctrl - parameter bit SecFlashCtrlScrambleEn = 1, - parameter int FlashCtrlProgFifoDepth = 4, - parameter int FlashCtrlRdFifoDepth = 16, // parameters for rram_ctrl parameter bit SecRramCtrlScrambleEn = 1, parameter int RramCtrlWrFifoDepth = 4, @@ -208,12 +204,6 @@ module earlgrey_pd_main #( output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_ram_cfg_rsp_o, input prim_ram_1p_pkg::ram_1p_cfg_req_t [SramCtrlSecNumRamInst-1:0] sram_ctrl_sec_ram_cfg_req_i, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlSecNumRamInst-1:0] sram_ctrl_sec_ram_cfg_rsp_o, - input prim_mubi_pkg::mubi4_t flash_bist_enable_i, - input logic flash_power_down_h_i, - input logic flash_power_ready_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - output logic [7:0] flash_obs_o, output logic es_rng_enable_o, input logic es_rng_valid_i, input logic [EntropySrcRngBusWidth-1:0] es_rng_bit_i, @@ -334,9 +324,9 @@ module earlgrey_pd_main #( localparam bit RvCoreIbexInstructionPipeline = 1'b0; // Signals - logic [59:0] mio_p2d; - logic [64:0] mio_d2p; - logic [64:0] mio_en_d2p; + logic [56:0] mio_p2d; + logic [63:0] mio_d2p; + logic [63:0] mio_en_d2p; logic [15:0] dio_p2d; logic [15:0] dio_d2p; logic [15:0] dio_en_d2p; @@ -417,12 +407,6 @@ module earlgrey_pd_main #( logic cio_usbdev_usb_dn_d2p; logic cio_usbdev_usb_dn_en_d2p; // pinmux - // flash_ctrl - logic cio_flash_ctrl_tck_p2d; - logic cio_flash_ctrl_tms_p2d; - logic cio_flash_ctrl_tdi_p2d; - logic cio_flash_ctrl_tdo_d2p; - logic cio_flash_ctrl_tdo_en_d2p; // rram_ctrl // rram_macro logic cio_rram_macro_tck_p2d; @@ -447,7 +431,7 @@ module earlgrey_pd_main #( // rv_core_ibex - logic [189:0] intr_vector; + logic [183:0] intr_vector; // Interrupt source list logic intr_uart0_tx_watermark; logic intr_uart0_rx_watermark; @@ -568,12 +552,6 @@ module earlgrey_pd_main #( logic intr_usbdev_powered; logic intr_usbdev_link_out_err; logic intr_usbdev_av_setup_empty; - logic intr_flash_ctrl_prog_empty; - logic intr_flash_ctrl_prog_lvl; - logic intr_flash_ctrl_rd_full; - logic intr_flash_ctrl_rd_lvl; - logic intr_flash_ctrl_op_done; - logic intr_flash_ctrl_corr_err; logic intr_rram_ctrl_wr_empty; logic intr_rram_ctrl_wr_lvl; logic intr_rram_ctrl_rd_full; @@ -722,12 +700,6 @@ module earlgrey_pd_main #( tlul_pkg::tl_d2h_t spi_host1_tl_rsp; tlul_pkg::tl_h2d_t usbdev_tl_req; tlul_pkg::tl_d2h_t usbdev_tl_rsp; - tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req; - tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp; - tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req; - tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp; - tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req; - tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp; tlul_pkg::tl_h2d_t rram_ctrl_core_tl_req; tlul_pkg::tl_d2h_t rram_ctrl_core_tl_rsp; tlul_pkg::tl_h2d_t rram_macro_prim_tl_req; @@ -795,8 +767,6 @@ module earlgrey_pd_main #( logic rv_core_ibex_irq_timer; logic [31:0] rv_core_ibex_hart_id; logic [31:0] rv_core_ibex_boot_addr; - otp_ctrl_pkg::nvm_otp_key_req_t flash_ctrl_otp_req; - otp_ctrl_pkg::nvm_otp_key_rsp_t flash_ctrl_otp_rsp; jtag_pkg::jtag_req_t pinmux_dft_jtag_req; jtag_pkg::jtag_rsp_t pinmux_dft_jtag_rsp; otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; @@ -852,12 +822,6 @@ module earlgrey_pd_main #( otp_ctrl_otp_broadcast.hw_cfg1_data.hw_cfg1_digest, otp_ctrl_otp_broadcast.hw_cfg1_data.unallocated }; - // TODO: remove once flash_ctrl is removed - assign flash_ctrl_otp_rsp.data_ack = flash_ctrl_otp_req.data_req; - assign flash_ctrl_otp_rsp.addr_ack = flash_ctrl_otp_req.addr_req; - assign flash_ctrl_otp_rsp.key = '0; - assign flash_ctrl_otp_rsp.rand_key = '0; - assign flash_ctrl_otp_rsp.seed_valid = 1'b0; // Ibex-specific assignments @@ -1892,87 +1856,8 @@ module earlgrey_pd_main #( .dio_in_i ); - flash_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:33]), - .AlertSkewCycles(top_pkg::AlertSkewCycles), - .RndCnstAddrKey(RndCnstFlashCtrlAddrKey), - .RndCnstDataKey(RndCnstFlashCtrlDataKey), - .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds), - .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed), - .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm), - .SecScrambleEn(SecFlashCtrlScrambleEn), - .ProgFifoDepth(FlashCtrlProgFifoDepth), - .RdFifoDepth(FlashCtrlRdFifoDepth) - ) u_flash_ctrl ( - // Clock and reset connections - .clk_i(clkmgr_clocks_i.clk_main_infra), - .clk_otp_i(clkmgr_clocks_i.clk_io_div4_infra), - .rst_shadowed_ni(rstmgr_resets_i.rst_lc_shadowed_n[rstmgr_pkg::DomainMainSel]), - .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), - - // DFT/scan connections - .scanmode_i, - .scan_rst_ni, - .scan_en_i, - - // Interrupts - .intr_prog_empty_o(intr_flash_ctrl_prog_empty), - .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl), - .intr_rd_full_o (intr_flash_ctrl_rd_full), - .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl), - .intr_op_done_o (intr_flash_ctrl_op_done), - .intr_corr_err_o (intr_flash_ctrl_corr_err), - - // alert_handler[33]: recov_err - // alert_handler[34]: fatal_std_err - // alert_handler[35]: fatal_err - // alert_handler[36]: fatal_prim_flash_alert - // alert_handler[37]: recov_prim_flash_alert - .alert_tx_o(alert_tx[37:33]), - .alert_rx_i(alert_rx[37:33]), - - // CIO inputs - .cio_tck_i (cio_flash_ctrl_tck_p2d), - .cio_tms_i (cio_flash_ctrl_tms_p2d), - .cio_tdi_i (cio_flash_ctrl_tdi_p2d), - - // CIO outputs - .cio_tdo_o (cio_flash_ctrl_tdo_d2p), - .cio_tdo_en_o(cio_flash_ctrl_tdo_en_d2p), - - // Inter-module signals - .otp_o(flash_ctrl_otp_req), - .otp_i(flash_ctrl_otp_rsp), - .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), - .flash_bist_enable_i(flash_bist_enable_i), - .flash_power_down_h_i(flash_power_down_h_i), - .flash_power_ready_h_i(flash_power_ready_h_i), - .flash_test_mode_a_io(flash_test_mode_a_io), - .flash_test_voltage_h_io(flash_test_voltage_h_io), - .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), - .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), - .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en), - .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en), - .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), - .lc_escalate_en_i(lc_ctrl_lc_escalate_en), - .rma_req_i(lc_ctrl_lc_nvm_rma_req), - .rma_ack_o(), - .rma_seed_i(lc_ctrl_lc_nvm_rma_seed), - .pwrmgr_o(), - .keymgr_o(), - .obs_ctrl_i(ast_obs_ctrl), - .fla_obs_o(flash_obs_o), - .core_tl_i(flash_ctrl_core_tl_req), - .core_tl_o(flash_ctrl_core_tl_rsp), - .prim_tl_i(flash_ctrl_prim_tl_req), - .prim_tl_o(flash_ctrl_prim_tl_rsp), - .mem_tl_i(flash_ctrl_mem_tl_req), - .mem_tl_o(flash_ctrl_mem_tl_rsp) - ); - rram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:38]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:33]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstAddrKey(RndCnstRramCtrlAddrKey), .RndCnstDataKey(RndCnstRramCtrlDataKey), @@ -1997,13 +1882,13 @@ module earlgrey_pd_main #( .intr_op_done_o (intr_rram_ctrl_op_done), .intr_corr_err_o(intr_rram_ctrl_corr_err), - // alert_handler[38]: recov_err - // alert_handler[39]: fatal_std_err - // alert_handler[40]: fatal_err - // alert_handler[41]: fatal_macro_err - // alert_handler[42]: recov_macro_err - .alert_tx_o(alert_tx[42:38]), - .alert_rx_i(alert_rx[42:38]), + // alert_handler[33]: recov_err + // alert_handler[34]: fatal_std_err + // alert_handler[35]: fatal_err + // alert_handler[36]: fatal_macro_err + // alert_handler[37]: recov_macro_err + .alert_tx_o(alert_tx[37:33]), + .alert_rx_i(alert_rx[37:33]), // Inter-module signals .rram_macro_o(rram_ctrl_rram_macro_req), @@ -2067,7 +1952,7 @@ module earlgrey_pd_main #( ); rv_dm #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .IdcodeValue(RvDmIdcodeValue), .UseDmiInterface(RvDmUseDmiInterface), @@ -2084,9 +1969,9 @@ module earlgrey_pd_main #( .scanmode_i, .scan_rst_ni, - // alert_handler[43]: fatal_fault - .alert_tx_o(alert_tx[43]), - .alert_rx_i(alert_rx[43]), + // alert_handler[38]: fatal_fault + .alert_tx_o(alert_tx[38]), + .alert_rx_i(alert_rx[38]), // Inter-module signals .next_dm_addr_i('0), @@ -2119,16 +2004,16 @@ module earlgrey_pd_main #( ); rv_plic #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_rv_plic ( // Clock and reset connections .clk_i(clkmgr_clocks_i.clk_main_secure), .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[44]: fatal_fault - .alert_tx_o(alert_tx[44]), - .alert_rx_i(alert_rx[44]), + // alert_handler[39]: fatal_fault + .alert_tx_o(alert_tx[39]), + .alert_rx_i(alert_rx[39]), // Inter-module signals .irq_o(rv_plic_irq), @@ -2143,7 +2028,7 @@ module earlgrey_pd_main #( ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .AES192Enable(1'b1), .AESGCMEnable(AesAESGCMEnable), @@ -2165,10 +2050,10 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_edn_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[45]: recov_ctrl_update_err - // alert_handler[46]: fatal_fault - .alert_tx_o(alert_tx[46:45]), - .alert_rx_i(alert_rx[46:45]), + // alert_handler[40]: recov_ctrl_update_err + // alert_handler[41]: fatal_fault + .alert_tx_o(alert_tx[41:40]), + .alert_rx_i(alert_rx[41:40]), // Inter-module signals .idle_o(clkmgr_idle_o[0]), @@ -2183,7 +2068,7 @@ module earlgrey_pd_main #( ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_hmac ( // Clock and reset connections @@ -2195,9 +2080,9 @@ module earlgrey_pd_main #( .intr_fifo_empty_o(intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // alert_handler[47]: fatal_fault - .alert_tx_o(alert_tx[47]), - .alert_rx_i(alert_rx[47]), + // alert_handler[42]: fatal_fault + .alert_tx_o(alert_tx[42]), + .alert_rx_i(alert_rx[42]), // Inter-module signals .idle_o(clkmgr_idle_o[1]), @@ -2206,7 +2091,7 @@ module earlgrey_pd_main #( ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .EnMasking(KmacEnMasking), .SwKeyMasked(KmacSwKeyMasked), @@ -2231,10 +2116,10 @@ module earlgrey_pd_main #( .intr_fifo_empty_o(intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // alert_handler[48]: recov_operation_err - // alert_handler[49]: fatal_fault_err - .alert_tx_o(alert_tx[49:48]), - .alert_rx_i(alert_rx[49:48]), + // alert_handler[43]: recov_operation_err + // alert_handler[44]: fatal_fault_err + .alert_tx_o(alert_tx[44:43]), + .alert_rx_i(alert_rx[44:43]), // Inter-module signals .keymgr_key_i(keymgr_dpe_kmac_key), @@ -2250,7 +2135,7 @@ module earlgrey_pd_main #( ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .Stub(OtbnStub), .RegFile(OtbnRegFile), @@ -2275,10 +2160,10 @@ module earlgrey_pd_main #( // Interrupts .intr_done_o(intr_otbn_done), - // alert_handler[50]: fatal - // alert_handler[51]: recov - .alert_tx_o(alert_tx[51:50]), - .alert_rx_i(alert_rx[51:50]), + // alert_handler[45]: fatal + // alert_handler[46]: recov + .alert_tx_o(alert_tx[46:45]), + .alert_rx_i(alert_rx[46:45]), // Inter-module signals .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), @@ -2303,7 +2188,7 @@ module earlgrey_pd_main #( ); keymgr_dpe #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:52]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .KmacEnMasking(KeymgrDpeKmacEnMasking), .RndCnstLfsrSeed(RndCnstKeymgrDpeLfsrSeed), @@ -2330,10 +2215,10 @@ module earlgrey_pd_main #( // Interrupts .intr_op_done_o(intr_keymgr_dpe_op_done), - // alert_handler[52]: recov_operation_err - // alert_handler[53]: fatal_fault_err - .alert_tx_o(alert_tx[53:52]), - .alert_rx_i(alert_rx[53:52]), + // alert_handler[47]: recov_operation_err + // alert_handler[48]: fatal_fault_err + .alert_tx_o(alert_tx[48:47]), + .alert_rx_i(alert_rx[48:47]), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2356,7 +2241,7 @@ module earlgrey_pd_main #( ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), @@ -2372,10 +2257,10 @@ module earlgrey_pd_main #( .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // alert_handler[54]: recov_alert - // alert_handler[55]: fatal_alert - .alert_tx_o(alert_tx[55:54]), - .alert_rx_i(alert_rx[55:54]), + // alert_handler[49]: recov_alert + // alert_handler[50]: fatal_alert + .alert_tx_o(alert_tx[50:49]), + .alert_rx_i(alert_rx[50:49]), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2389,7 +2274,7 @@ module earlgrey_pd_main #( ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:56]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RngBusWidth(EntropySrcRngBusWidth), .RngBusBitSelWidth(EntropySrcRngBusBitSelWidth), @@ -2408,10 +2293,10 @@ module earlgrey_pd_main #( .intr_es_observe_fifo_ready_o(intr_entropy_src_es_observe_fifo_ready), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // alert_handler[56]: recov_alert - // alert_handler[57]: fatal_alert - .alert_tx_o(alert_tx[57:56]), - .alert_rx_i(alert_rx[57:56]), + // alert_handler[51]: recov_alert + // alert_handler[52]: fatal_alert + .alert_tx_o(alert_tx[52:51]), + .alert_rx_i(alert_rx[52:51]), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2433,7 +2318,7 @@ module earlgrey_pd_main #( ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .NumEndPoints(Edn0NumEndPoints) ) u_edn0 ( @@ -2445,10 +2330,10 @@ module earlgrey_pd_main #( .intr_edn_cmd_req_done_o(intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // alert_handler[58]: recov_alert - // alert_handler[59]: fatal_alert - .alert_tx_o(alert_tx[59:58]), - .alert_rx_i(alert_rx[59:58]), + // alert_handler[53]: recov_alert + // alert_handler[54]: fatal_alert + .alert_tx_o(alert_tx[54:53]), + .alert_rx_i(alert_rx[54:53]), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2460,7 +2345,7 @@ module earlgrey_pd_main #( ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .NumEndPoints(Edn1NumEndPoints) ) u_edn1 ( @@ -2472,10 +2357,10 @@ module earlgrey_pd_main #( .intr_edn_cmd_req_done_o(intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // alert_handler[60]: recov_alert - // alert_handler[61]: fatal_alert - .alert_tx_o(alert_tx[61:60]), - .alert_rx_i(alert_rx[61:60]), + // alert_handler[55]: recov_alert + // alert_handler[56]: fatal_alert + .alert_tx_o(alert_tx[56:55]), + .alert_rx_i(alert_rx[56:55]), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2487,7 +2372,7 @@ module earlgrey_pd_main #( ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), @@ -2507,9 +2392,9 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[62]: fatal_error - .alert_tx_o(alert_tx[62]), - .alert_rx_i(alert_rx[62]), + // alert_handler[57]: fatal_error + .alert_tx_o(alert_tx[57]), + .alert_rx_i(alert_rx[57]), // RACL policies .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), @@ -2532,7 +2417,7 @@ module earlgrey_pd_main #( ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstSramKey(RndCnstSramCtrlSecSramKey), .RndCnstSramNonce(RndCnstSramCtrlSecSramNonce), @@ -2552,9 +2437,9 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[63]: fatal_error - .alert_tx_o(alert_tx[63]), - .alert_rx_i(alert_rx[63]), + // alert_handler[58]: fatal_error + .alert_tx_o(alert_tx[58]), + .alert_rx_i(alert_rx[58]), // RACL policies .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), @@ -2577,7 +2462,7 @@ module earlgrey_pd_main #( ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .BootRomInitFile(RomCtrlBootRomInitFile), .FlopToKmac(RomCtrlFlopToKmac), @@ -2590,9 +2475,9 @@ module earlgrey_pd_main #( .clk_i(clkmgr_clocks_i.clk_main_infra), .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[64]: fatal - .alert_tx_o(alert_tx[64]), - .alert_rx_i(alert_rx[64]), + // alert_handler[59]: fatal + .alert_tx_o(alert_tx[59]), + .alert_rx_i(alert_rx[59]), // Inter-module signals .rom_cfg_i(rom_ctrl_rom_cfg_req_i), @@ -2608,7 +2493,7 @@ module earlgrey_pd_main #( ); rv_core_ibex #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[68:65]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63:60]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed), .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm), @@ -2663,12 +2548,12 @@ module earlgrey_pd_main #( .scanmode_i, .scan_rst_ni, - // alert_handler[65]: fatal_sw_err - // alert_handler[66]: recov_sw_err - // alert_handler[67]: fatal_hw_err - // alert_handler[68]: recov_hw_err - .alert_tx_o(alert_tx[68:65]), - .alert_rx_i(alert_rx[68:65]), + // alert_handler[60]: fatal_sw_err + // alert_handler[61]: recov_sw_err + // alert_handler[62]: fatal_hw_err + // alert_handler[63]: recov_hw_err + .alert_tx_o(alert_tx[63:60]), + .alert_rx_i(alert_rx[63:60]), // Inter-module signals .rst_cpu_n_o(), @@ -2705,38 +2590,32 @@ module earlgrey_pd_main #( // Interrupt assignments assign intr_vector = { - intr_edn1_edn_fatal_err, // ID 189 - intr_edn1_edn_cmd_req_done, // ID 188 - intr_edn0_edn_fatal_err, // ID 187 - intr_edn0_edn_cmd_req_done, // ID 186 - intr_entropy_src_es_fatal_err, // ID 185 - intr_entropy_src_es_observe_fifo_ready, // ID 184 - intr_entropy_src_es_health_test_failed, // ID 183 - intr_entropy_src_es_entropy_valid, // ID 182 - intr_csrng_cs_fatal_err, // ID 181 - intr_csrng_cs_hw_inst_exc, // ID 180 - intr_csrng_cs_entropy_req, // ID 179 - intr_csrng_cs_cmd_req_done, // ID 178 - intr_keymgr_dpe_op_done, // ID 177 - intr_otbn_done, // ID 176 - intr_kmac_kmac_err, // ID 175 - intr_kmac_fifo_empty, // ID 174 - intr_kmac_kmac_done, // ID 173 - intr_hmac_hmac_err, // ID 172 - intr_hmac_fifo_empty, // ID 171 - intr_hmac_hmac_done, // ID 170 - intr_rram_ctrl_corr_err, // ID 169 - intr_rram_ctrl_op_done, // ID 168 - intr_rram_ctrl_rd_lvl, // ID 167 - intr_rram_ctrl_rd_full, // ID 166 - intr_rram_ctrl_wr_lvl, // ID 165 - intr_rram_ctrl_wr_empty, // ID 164 - intr_flash_ctrl_corr_err, // ID 163 - intr_flash_ctrl_op_done, // ID 162 - intr_flash_ctrl_rd_lvl, // ID 161 - intr_flash_ctrl_rd_full, // ID 160 - intr_flash_ctrl_prog_lvl, // ID 159 - intr_flash_ctrl_prog_empty, // ID 158 + intr_edn1_edn_fatal_err, // ID 183 + intr_edn1_edn_cmd_req_done, // ID 182 + intr_edn0_edn_fatal_err, // ID 181 + intr_edn0_edn_cmd_req_done, // ID 180 + intr_entropy_src_es_fatal_err, // ID 179 + intr_entropy_src_es_observe_fifo_ready, // ID 178 + intr_entropy_src_es_health_test_failed, // ID 177 + intr_entropy_src_es_entropy_valid, // ID 176 + intr_csrng_cs_fatal_err, // ID 175 + intr_csrng_cs_hw_inst_exc, // ID 174 + intr_csrng_cs_entropy_req, // ID 173 + intr_csrng_cs_cmd_req_done, // ID 172 + intr_keymgr_dpe_op_done, // ID 171 + intr_otbn_done, // ID 170 + intr_kmac_kmac_err, // ID 169 + intr_kmac_fifo_empty, // ID 168 + intr_kmac_kmac_done, // ID 167 + intr_hmac_hmac_err, // ID 166 + intr_hmac_fifo_empty, // ID 165 + intr_hmac_hmac_done, // ID 164 + intr_rram_ctrl_corr_err, // ID 163 + intr_rram_ctrl_op_done, // ID 162 + intr_rram_ctrl_rd_lvl, // ID 161 + intr_rram_ctrl_rd_full, // ID 160 + intr_rram_ctrl_wr_lvl, // ID 159 + intr_rram_ctrl_wr_empty, // ID 158 intr_vector_pd_aon_i[6], // ID 157 (sensor_ctrl_init_status_change) intr_vector_pd_aon_i[5], // ID 156 (sensor_ctrl_io_status_change) intr_vector_pd_aon_i[4], // ID 155 (aon_timer_wdog_timer_bark) @@ -2923,18 +2802,6 @@ module earlgrey_pd_main #( .tl_usbdev_o(usbdev_tl_req), .tl_usbdev_i(usbdev_tl_rsp), - // port: tl_flash_ctrl__core - .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req), - .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp), - - // port: tl_flash_ctrl__prim - .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req), - .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp), - - // port: tl_flash_ctrl__mem - .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req), - .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp), - // port: tl_rram_ctrl__core .tl_rram_ctrl__core_o(rram_ctrl_core_tl_req), .tl_rram_ctrl__core_i(rram_ctrl_core_tl_rsp), @@ -3167,9 +3034,6 @@ module earlgrey_pd_main #( assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx]; assign cio_uart3_rx_p2d = mio_p2d[MioInUart3Rx]; assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb]; - assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; - assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; - assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; assign cio_rram_macro_tck_p2d = mio_p2d[MioInRramMacroTck]; assign cio_rram_macro_tms_p2d = mio_p2d[MioInRramMacroTms]; assign cio_rram_macro_tdi_p2d = mio_p2d[MioInRramMacroTdi]; @@ -3230,7 +3094,6 @@ module earlgrey_pd_main #( assign mio_d2p[MioOutUart3Tx] = cio_uart3_tx_d2p; assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p; assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p; - assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p; assign mio_d2p[MioOutRramMacroTdo] = cio_rram_macro_tdo_d2p; assign mio_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_d2p_i[0]; assign mio_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_d2p_i[1]; @@ -3297,7 +3160,6 @@ module earlgrey_pd_main #( assign mio_en_d2p[MioOutUart3Tx] = cio_uart3_tx_en_d2p; assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p; assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p; - assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p; assign mio_en_d2p[MioOutRramMacroTdo] = cio_rram_macro_tdo_en_d2p; assign mio_en_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_en_d2p_i[0]; assign mio_en_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_en_d2p_i[1]; diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv index ec17a5e677295..c125c8a7188af 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv @@ -19,17 +19,17 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { - 40'hB8_7118AF11 + 40'hDA_F5141DF1 }; // Compile-time random permutation for LFSR output parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { - 240'h3DA3_8428D1D7_2C69C98E_24203015_5F6E4461_99408565_34800DD2_1695871E + 240'h2D14_0549D5CF_11F0CD25_B04C94E1_E1608664_0A37A09D_54C60145_9A70A8A6 }; // Compile-time random permutation for scrambling key/nonce register reset value parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { - 256'h85BD9A56_EA088D33_FFAA6A11_55AFB016_9AB2DE39_73D027EE_30B8F901_F644EC7C + 256'h0D857783_4CCC6CAA_A63A8E66_04338151_B9A23C08_F9EED04C_A1EBB0BD_D305FFB6 }; // Compile-time scrambling key @@ -237,35 +237,35 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Diversification value used for all invalid life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { - 128'hD3E56C8E_D1EC3873_9F1D0DEB_7C774199 + 128'hC4818054_E0E0EDB0_ACD0B040_FC629EA7 }; // Diversification value used for the TEST_UNLOCKED* life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { - 128'hCF6DD057_F44C13E2_5C7A5877_BC5242E6 + 128'hF8B17FA8_8FEE02E3_F0864223_A2E23A8C }; // Diversification value used for the DEV life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { - 128'hEE63ECDF_458AE659_6E87F9F9_73DB98AA + 128'hC31E2DE5_E578D43D_2DCE49E3_60CFB594 }; // Diversification value used for the PROD/PROD_END life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { - 128'hA293568F_D1F31A01_65939D81_9D151869 + 128'hACDDF170_684F6EAD_2B7FEBFE_895523D7 }; // Diversification value used for the RMA life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { - 128'h0E6473CD_B2479391_635057CA_1045B9E1 + 128'hBC4846A4_85956C7F_904B9EDE_D09B89A7 }; // Compile-time random bits used for invalid tokens in the token mux parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { - 256'h917E1FF0_189B04A4_F7FBA960_FE098A4F_B9D46917_1B950E36_4B0DAC54_69568E66, - 256'h1498FD89_197CCAE8_EA08FF43_EFC2BFB1_C6AB5CC6_3E6F4741_E80F777C_B7FC0504, - 256'h1A1B8963_50C9636D_6814D23E_2F5FF127_5EF19959_AAA8B6A0_04D55749_84DED1CC, - 256'h79BD6787_D6663AA5_E622682A_6525E083_CCDDBD2A_1B008057_C22C884E_D49D87A5 + 256'h5433566F_4963D9DC_27F3ECB1_1CE3B87A_AA7ABC85_920B1881_083AFF7B_DE18EACF, + 256'hF8567945_3DA77D92_A176B871_18AF11CD_BE78D670_60615A20_B9C0740F_07969CCD, + 256'h2D10A1A6_E7988FA5_28AC032E_0A6138CB_8316FF95_C65CD7A1_A768B06E_0106D60E, + 256'hDA0F1BC6_7ADF85BD_9A56EA08_8D33FFAA_6A1155AF_B0169AB2_DE3973D0_27EE30B8 }; //////////////////////////////////////////// @@ -273,12 +273,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { - 32'hB56BA735 + 32'hF901F644 }; // Compile-time random permutation for LFSR output parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { - 160'h48B6F5CC_D4F0C25B_CA307379_FAEB36C7_58041147 + 160'h903E6BA6_C282D992_D49456D1_8F047371_E2DE69FD }; //////////////////////////////////////////// @@ -286,53 +286,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetSramKey = { - 128'hEDECF7B1_7682D2CE_3DB9B12E_1AF4339E + 128'h87F9F973_DB98AAA2_93568FD1_F31A0165 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetSramNonce = { - 128'h1F45164A_418EBC52_210D58DC_65508E86 + 128'h939D819D_1518690E_6473CDB2_47939163 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetLfsrSeed = { - 64'h9AF565C1_B87D687E + 64'h5057CA10_45B9E191 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetLfsrPerm = { - 128'hEEDF1F32_34B462AE_144607AB_F6E0DAFB, - 256'h5DCBA6C8_47A3F995_3806D921_35DD2B14_0290914F_CC1E761A_2C3295CB_D69C437A - }; - - //////////////////////////////////////////// - // flash_ctrl - //////////////////////////////////////////// - // Compile-time random bits for default address key - parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlAddrKey = { - 128'h378405DB_CB5508CD_6CD2CE71_5E7CCEB1 - }; - - // Compile-time random bits for default data key - parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlDataKey = { - 128'hBC1C61B3_D27BB8E8_398E880E_CD252956 - }; - - // Compile-time random bits for default seeds - parameter flash_ctrl_top_specific_pkg::all_seeds_t RndCnstFlashCtrlAllSeeds = { - 256'hBA816163_62B27EAF_B903EC79_BDDF0A4F_7DFF07DB_05DE6391_0E4EE4D8_A2C7D402, - 256'h2F16ED8A_24F80EEB_CF829983_9C103EAE_3C2F18B4_666B5E59_D16C252F_9DB7F094 - }; - - // Compile-time random bits for initial LFSR seed - parameter flash_ctrl_top_specific_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = { - 64'h161D818D_C161FE26 - }; - - // Compile-time random permutation for LFSR output - parameter flash_ctrl_top_specific_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = { - 128'h853EC21A_35348B23_31141F4E_C07B1167, - 256'h998D5AAA_DE24ABC8_F9FDD70D_C82D6BC6_1297AFE8_BA9D4B10_FCE76D09_36755E00 + 128'h92130429_C46B27BB_E752CD20_00F3BAE4, + 256'h8B7E6CBA_1E597DDD_436FF0D7_1663E325_7348D0E5_F456AE4E_2098AA90_661BC1DF }; //////////////////////////////////////////// @@ -340,29 +310,29 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for default address key parameter rram_ctrl_pkg::rram_key_t RndCnstRramCtrlAddrKey = { - 128'h816510C5_35A81649_39D97DF7_421AD4D2 + 128'hF19959AA_A8B6A004_D5574984_DED1CC79 }; // Compile-time random bits for default data key parameter rram_ctrl_pkg::rram_key_t RndCnstRramCtrlDataKey = { - 128'hC18B270D_422EC39C_41F727D1_30ED9B18 + 128'hBD6787D6_663AA5E6_22682A65_25E083CC }; // Compile-time random bits for default seeds parameter rram_ctrl_pkg::all_seeds_t RndCnstRramCtrlAllSeeds = { - 256'hB90E42E4_287F60AD_57D6A551_E78F940B_8AE9F2BB_40621F43_F3ABD8D7_37F8D12D, - 256'h8F43FD16_19FB83E1_A607DCC1_72099339_EF142E02_83257145_13BFDC2A_062C2EB4 + 256'hDDBD2A1B_008057C2_2C884ED4_9D87A5B5_6BA7353C_532142F5_0667E220_C5B724C3, + 256'hFDB6D060_653B42A9_6F88B574_E4D3814F_5116B3E6_F3E331DA_1182DBC2_9C894F18 }; // Compile-time random bits for initial LFSR seed parameter rram_ctrl_pkg::lfsr_seed_t RndCnstRramCtrlLfsrSeed = { - 64'hECDC716A_92861FF7 + 64'h00EDECF7_B17682D2 }; // Compile-time random permutation for LFSR output parameter rram_ctrl_pkg::lfsr_perm_t RndCnstRramCtrlLfsrPerm = { - 128'h359634CC_6AF8FE65_4C8E44BB_1C1E8B3C, - 256'hEA43821B_768825FC_DF1BD015_F7A52807_1D5BDFAA_214A11D6_E9EC4F22_7911A6F0 + 128'h2BBFAB6E_A4E027AA_55FF9797_D65C4192, + 256'h20B700E7_7DD98E34_72D10DA1_A7FC9A1C_B06560C8_52F8D048_54479CC1_8BB2E3F3 }; //////////////////////////////////////////// @@ -370,34 +340,34 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for register clearing. parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { - 64'h8C893A6C_B3FD30A8 + 64'h01E9EE42_0D5B523F }; // Permutation applied to the LFSR of the PRNG used for clearing. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { - 128'hA9B75048_AD734645_E2AD9C13_3C26A197, - 256'hF0777B1B_74A209E9_C95B9CD9_8F8C014F_071B9343_F78B09EA_FECB9A31_0558839F + 128'h83B8A60F_C508664A_AD97D2E7_7714CC43, + 256'h9144A2F4_698CFFF4_6307D771_B0950763_6B87339E_1D2FBA5A_EB3824AD_771B201A }; // Permutation applied to the clearing PRNG output for clearing the second share of registers. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { - 128'h51EDCE57_F6FA0D1E_C8A0F27E_0501B57E, - 256'h994C9C7B_6BF4A90B_D05CA0F3_35AEC381_2F853E5C_8AC363D8_06B19984_9709976A + 128'h07D75E55_0EECC237_EA729932_954DC285, + 256'h334848E2_BABCC611_F07E2DF9_B5976991_BFBAB3C4_9F49A0CC_326214B0_35C68DB9 }; // Default seed of the PRNG used for masking. parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { - 32'h108133B3, - 256'h8A7167F8_2D4B5453_CA029357_90001030_32EED900_BB073D95_19792FAE_CDF66777 + 32'hD7FE6C45, + 256'hD1534FD3_90C7B068_CFE89687_94DE88E8_FF4ADC3D_02EBFA0A_1D5FAA5E_E00CA534 }; // Permutation applied to the output of the PRNG used for masking. parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { - 256'h92489873_56407D76_5D641F23_453F6942_0B041C80_8F5F226F_3B139F84_9534634E, - 256'h5B276675_9A9B0F50_86584F53_8C2B5E65_196A6041_3C050003_7F773991_59512878, - 256'h7B208A44_5A326B4B_062F6E0E_4610476C_37621A54_253A3E07_081B7C29_122C559D, - 256'h1826610A_82174A4D_8D098979_7E97942A_578B0116_7A3D5C43_1167359E_33838593, - 256'h3170361D_96740C52_141E8881_30498E6D_68907121_2D38029C_72872499_4C2E0D15 + 256'h78867A54_4B3E4450_59196D6A_5C759B46_6E246962_8F26809C_488C512B_11025F84, + 256'h3A2F8599_1D4E4F56_5B4D3D66_00072D9F_583C8A4C_71779A33_64326F3F_791F1E25, + 256'h1476633B_2C7E3796_299D8813_0834367C_4361955A_5E709715_09223812_67019E0A, + 256'h1C930492_98035389_0C0B727B_94681B82_6C55210F_31205D74_45054A47_7383526B, + 256'h57607F28_8E0E1830_8D412E90_0D278B1A_427D3949_16351065_812A4087_06231791 }; //////////////////////////////////////////// @@ -405,58 +375,58 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random data for PRNG default seed parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { - 32'h084D95CA, - 256'h06120352_218C90DF_AB74299E_7882F53F_007A8AC1_BC2FDEBB_DB82764E_00B66018 + 32'h50B10232, + 256'hA8B3C33A_6017B970_36561AA2_62310424_04E5EF74_645BE00E_A5B567DB_B5DABAC0 }; // Compile-time random permutation for PRNG output parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { - 64'h04CEE8BE_C2514046, - 256'h12580EA9_7BFCC67F_EAEA09B2_A9CAC4AD_901BC79C_15BA3686_9177092C_56855872, - 256'h356DE28C_4B869CD4_7D6B7861_330F16A6_DD1672C5_421DF86E_EF62F1A4_FA75285E, - 256'hD5D502BC_A7E9EEF5_2614983A_04AA9DA0_613DB9A4_713A0028_0423D861_6DEB8002, - 256'hC092406B_E4B5B830_C0A98919_0D0589D0_6980F4CD_970DCC1C_385E5BA0_50C9F276, - 256'h51507558_A3E2D05E_D34782F8_44F7C0A4_6A00D623_2773FE27_A60E7A12_405C8553, - 256'hA5252190_6C0CE603_4AF25C92_93AE74D4_3BB96F69_A1606F86_E8F2A91E_9AAA76DA, - 256'h4A5C87E8_8311C847_295297ED_88791060_D669BC08_14635B49_F796C056_22677F17, - 256'hA3BE15A4_2FEAD4C2_3C2572CE_7951A321_519A3D69_9AF9F12E_5731ACCA_931387D2, - 256'h940FE3F2_A11967E2_8439EF75_C6336DA4_880C5B1D_61205951_0E50C2E2_1066B2A0, - 256'h52D240FC_A81C1180_E8748776_065A4115_1A6A2483_401008D9_BF1CE995_7E52C0BC, - 256'h46258AA6_490DD821_DFB9CDAC_2F67A24E_A2195932_ECEA77AA_D915867A_CCC2E942, - 256'h198BCA20_CF256ED2_445CC3EB_D42A564D_85B7890C_5915FC75_3A264A65_35A00F56, - 256'hF6310F03_AC8149B5_6FEA5C54_7DA38757_9594160A_41C05712_231BBA33_805CF94D, - 256'hC237036A_78214B06_88E48E7A_82EA5970_7768D53A_A64AA0FA_57144B9D_5B2DCBA2, - 256'hAB9B2AA4_A8E1C4F2_9F0D5051_1A29520E_08B81C63_CE4A4999_9D2DD792_3A058B87, - 256'h19AF80D9_65F214B8_E2B1E123_7D8C85D9_C50CC283_4EB7AC55_BAB1B878_06285916, - 256'h1A8344C2_197E1551_14F49C6F_D1292197_0EB4BCF3_450F2AAE_D98B0D85_507438F1, - 256'h0295A58C_1DB49CCB_29C9C1DA_910B226C_22D51402_52A91884_2365E132_5D08F9C2, - 256'h862DA1FB_E0D199A4_FBE8C7C7_EE85A5C3_7D41F827_17B07137_1DB10830_A3E99B68, - 256'h86D9641E_956C362A_B446DCCB_890D9498_27B08BA0_C7355E17_27D17BAC_4CAFD852, - 256'h2030389E_793623C1_2BB54EE4_0B6CEA15_314011A2_FAA11689_41066B30_1F998DE6, - 256'h35CB2324_262AD678_2A7FC1D5_0C345325_9A75959D_A1D115DE_F38626C0_AC4F6AE2, - 256'h2C495981_C717A1BD_44DFE374_F182E065_FE8B6860_88DEDB05_2389F2E9_19DF3A33, - 256'h197263E0_E563482C_D3FA69C7_011BC45F_3EED7750_1A644238_313F0E0D_29E0CD28, - 256'h8B097AE1_8497D26D_BC5E50B1_349E4ECE_C6D141C0_4F95B66A_1EEA8634_850A4ED5, - 256'h797BB318_0A714A9C_A1D12689_50260BB1_9E3111C6_3AD01647_C9888D92_DE31B171, - 256'hB52B661C_0C4A009C_79220F12_6268DE8D_15A3515C_80B1B74C_A96C144C_62F0ABEE, - 256'hA7C09D92_1EE04903_911349F6_3B2B80A9_74E5056C_F2D26EAC_DB9405C4_04044945, - 256'hFD1014CC_188053D9_29B51242_6C95A947_9DAFB3E0_B709C7E1_FDA81595_DB12425B, - 256'h1A920A54_091A36ED_244E5C05_0DD63F48_A06E612F_ED101DAE_6B489B18_2237EDF8, - 256'hF5E9772F_40C5376D_AF70F8CE_660AD41E_BCB58E19_07006CC0_392A93B7_2B0AE91D + 64'h7C88FA95_BD35ADFA, + 256'hA50F8C25_7AE05F4F_47BC2DFD_52C77BC1_1DBB9712_9C52AC51_0C0EE676_6D81556F, + 256'h5A245B55_B39FE08B_5B066A27_5C42437E_544A5A90_87E4C1BC_2C74E618_622148C7, + 256'h453109A8_8D44F26D_5F7143C8_9327DFB5_E44B781C_04C66830_1BC6DCE2_B7003A48, + 256'h0592EA70_951760D0_2A0DE2B8_E198D0C3_760149C8_8B41CD27_C4EEB44C_DAB157BD, + 256'h6BC63505_3F8F1430_D561A5A2_76157B1F_E7A02037_5E184E63_7A6BA006_775C97F2, + 256'h8D559484_435D7306_CA193D7B_99E8A6D2_B4260859_C1B5191D_EA01437F_C290F066, + 256'h5B196A7E_04803028_A95B5486_B841E492_678362A4_849F77B5_DF6FEBB5_E997BE4E, + 256'h722430BE_DAE5ACFA_25120019_C11B9CF0_5E7E73B1_7942B694_E5D07111_A2582838, + 256'hDE450D06_16419230_0C300E6B_580AB592_9AE94B90_B63050D7_2AF79EDC_61CA653D, + 256'h0CAA209A_76E9A712_3519D451_C45CBA2B_F9F2DD76_91F6687E_01EAB009_CC1A0043, + 256'hC0091302_F70EA13A_2241898C_ACDB8888_B4998AE8_154F2591_549DD22E_14D5D704, + 256'h36E6C0A2_A3500E62_42560F8E_A6517880_6C5832DE_98165045_35B4099B_6912B32E, + 256'h162167B0_6E5489A9_37E82956_9B5180B3_8CF82308_D85CAA7C_0E9770ED_1F71D2DE, + 256'hF6A4549C_79A310D1_E4EF1C0E_A208EB01_371C2498_137D95A4_D02DB808_016B1857, + 256'h5FC8F5EE_031182E9_7057841B_AA444FEB_7C3DFA06_104AA901_7746D78C_324DE936, + 256'h1251B4CC_2B197490_A3351EBD_26E739EA_0FBCC503_127DC562_5BD3094A_A020D4AD, + 256'h2C1EBA9A_86C59F89_396D1F02_E2E6D936_497B8A3F_63A11541_B6C7DA73_FCB108D8, + 256'h7BF8B2BB_57C58713_7261A3F4_E57D0169_90A6AA2F_D666D791_9D64725C_3DDBE15A, + 256'hC70C5810_9AF88283_F4B9AA8A_091A3C47_42B0A3CD_778E5A28_DE23640D_A421C8C1, + 256'hECE58991_B08ECBAE_1CBC627B_26312CDD_43452CAC_2D4210C6_4023C59A_5F8FAB2A, + 256'h56FAB001_EB209E73_5A58B4CC_B10A44E8_78A66DB2_AD1A3D4F_B9C48355_81D324A0, + 256'h57D93320_8AB0E5B1_8C5D1B2A_02B28E0D_CEB8D89C_09EAF13A_2E7CEB50_54769D21, + 256'h621A26B3_ECB419EF_690701FF_1B4E6FC0_7C606C2F_F1140056_46AB9EF2_80D295A5, + 256'h426C58F4_0C2A6291_32A71991_DE602A38_2A11B126_4A33F0E4_B62C9AAE_916DB91A, + 256'h659AF838_1610B592_584658BA_3558091B_2A10191E_5BA3862F_3914175C_AF439545, + 256'h28571781_208B0D86_DBB18538_824BF7A8_FC82E797_42325204_84D8398A_D2F0F42B, + 256'h48481570_A2C48467_469C682E_F3E43B22_2545F9E5_834590D2_6945B088_78A5A159, + 256'h51CC361D_482A0533_4A12B7D6_D2255763_1F052F66_E129AB5B_AB903F11_239AF670, + 256'hC5022CD0_CC511EA0_64923B68_65E71C87_38130874_924C8BBA_5C54674B_E194F6BB, + 256'h0CB1031A_935512D5_9F8A4CE1_08BC0369_8ABA87A7_A1404163_9D99B3BD_53580533, + 256'h4E07A318_99884F72_D3E716CA_699AC9BD_25085D56_781A5AA9_D9028B53_9E713598 }; // Compile-time random data for PRNG buffer default seed parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { - 32'h6289EDD5, - 256'hF001DCD4_095890A2_90A9B632_F0395D11_CAC7F7E9_E764ADD7_EDE232A4_E00DABF1, - 256'hD1D2AD2E_2A5133F6_A12FF2EC_1569BEF1_F0B924C4_70AC5A99_809985DC_415BA1EA, - 256'hCED382D5_4C9E378D_030EA5D3_7665D43A_035F4EA1_E463032A_3A8E24B4_547F8B0D + 32'hE0895D76, + 256'hF862EF81_F419E3C6_CDC8662C_71EAC141_666E443C_6492D9BC_F7A82420_750E5DFC, + 256'h5E3ED4F2_907532E1_79EBEC7E_D7D3A5EF_4982F73E_D91C4B1C_D0C85EC5_E548B401, + 256'h84A69EB1_E5439646_0E36C55C_459EFE9E_43836FE8_78E46433_7EBCAE32_38DCDF7D }; // Compile-time random permutation for LFSR Message output parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { - 128'h0F26D18F_C86EF733_E0574E44_67BD8D0B, - 256'h7306EA64_9EF974E8_50588BB5_061A2AF9_E51D6ADC_3A9238D4_0AB007F7_4991FC6C + 128'h0B325F95_B999ABB7_91AF9530_1B78DA72, + 256'h94E11483_2E8033C7_59061DB3_4F6803F5_F62CDCBE_927F04C5_23B5BCAE_01B558BA }; //////////////////////////////////////////// @@ -464,30 +434,30 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for URND. parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { - 32'hA69F03F5, - 256'hA88525A5_87CEDEA9_0913BBCE_814E6794_DF2BDD99_E66D0780_1B027BD4_E9BF578B + 32'h5A54FF19, + 256'h343CB320_40B34907_68889D27_E0BA8588_D34C05BC_F127DAE5_8B65D6A2_51088099 }; // Compile-time random permutation for URND permutation in BN MAC. parameter otbn_pkg::bn_mac_urnd_perm_t RndCnstOtbnBnMacUrndPerm = { - 256'h04F22173_C8F0BD8B_B254BE88_D77C0EC4_522FE26C_27CB1E12_A13BFA0F_A0A33CDB, - 256'h4F6D8F4A_BCD0C2C6_ED295C91_DD00A202_78153A33_69F5D610_3FFCDA5D_90EE9963, - 256'hFDD5E495_59AB6E25_390942C1_D2F196C0_ACC9B606_CFE85A9A_1BDCDE11_16B708F7, - 256'h74FE9CD8_8E34C3EC_26D420EB_1F8D7E5F_B0EAE1B1_D3184035_984C5176_E3059203, - 256'h2BFBB8B5_8987AE37_F624CD8A_0A720B53_F456F9FF_67137F55_64CE851D_F33E1CAF, - 256'hB39386E6_3D419DDF_C54B0157_BB62842D_941971E7_30D14ECC_7B8070BF_4D17D91A, - 256'h5BA6C78C_9EBA66CA_387DE583_A5F86A2E_AA798197_7A22B948_2AAD2C9B_A407A750, - 256'h5832280D_E0774323_EFA9319F_4765B475_45A84936_E90C6844_5E468260_6B616F14 + 256'hC115938C_D4A11DC9_F317B8B0_72122379_F24D6C4E_C52D8263_7327FDD0_DA53E7A0, + 256'hD764F513_AD461021_3C208899_39EB09BB_A6A4B9E8_A39B140A_E66DD95A_8FF6DDC2, + 256'h45327FB5_1C702C75_7BEE3126_68DBD561_CA57BDC4_36E4CB9F_418D34EA_16BA8E1E, + 256'hB23FE36B_A9F07698_E08719FF_BC80664B_8BED4233_D690F7A5_3E187400_DC11355B, + 256'hC006963D_022F240F_D22BEF77_6037E22A_04B4BE92_8558A7F8_014CE90C_C80B9AE5, + 256'h5469AA28_52C38A1F_AE486F40_7C4FABC7_255D3AFE_D12E945E_FC05FBAC_1B6259AF, + 256'hD367296A_0E55A865_44869EEC_22430D08_DFD8A289_8197B7F1_F43B7E7D_CD38CE56, + 256'h5C6E3091_C67A9D4A_7851FA49_E1509CB6_83BF4784_F9DE035F_951ACFCC_B10771B3 }; // Compile-time random reset value for IMem/DMem scrambling key. parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { - 128'hCACAEA4E_16EF75A4_823EE1BF_100B50C3 + 128'hA4D3D738_71FDAF5A_D0C1DD1E_95F99D71 }; // Compile-time random reset value for IMem/DMem scrambling nonce. parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { - 64'hA2C1BA79_A60BD0D9 + 64'h29CA6861_A4425B9C }; //////////////////////////////////////////// @@ -495,53 +465,53 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrDpeLfsrSeed = { - 64'h47C26D8D_3C3874C6 + 64'hC42EDBA8_8A15B752 }; // Compile-time random permutation for LFSR output parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrDpeLfsrPerm = { - 128'hF901836E_0753A55C_C7F7C8B1_79828835, - 256'h1DD932AC_3B58FD7F_B09D1A7E_BA027259_F2BCBD84_040B7A99_41633B95_E4852E2E + 128'hB63956D3_1AC318F2_3C2C7EDA_DA2E28CB, + 256'h781E5EC0_55CD943F_26100EA9_CF9117D2_9F0B548D_4FAA5B11_D60CBF09_26E6E9D4 }; // Compile-time random permutation for entropy used in share overriding parameter keymgr_pkg::rand_perm_t RndCnstKeymgrDpeRandPerm = { - 160'h38CCA5A1_C161125E_4333F5DF_1EC9BBD7_E9800AD5 + 160'h85E8B7FA_3BFA8A31_0247D131_C9E59672_2A93742D }; // Compile-time random bits for revision seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeRevisionSeed = { - 256'h650A85C3_0237536D_C3E35040_DE9AC1A6_F2B35C99_FB71E1AA_AB3C2083_83ADF503 + 256'h227A9781_79AA2E6A_DC5EA5FD_83777D38_7766BA9E_8C77A65B_1AAD174D_D41ACA70 }; // Compile-time random bits for software generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeSoftOutputSeed = { - 256'h11FF71FD_46921923_A8CD8C6F_F98F9BDF_C2B205D8_690DD355_00E5A51B_BA34A71D + 256'hD3807BA5_4E793023_FA711994_CCF5D2F4_2DAFFA84_621AB157_014B7050_9DA8413D }; // Compile-time random bits for hardware generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeHardOutputSeed = { - 256'h81E9EB87_6B6F1996_B2BE4B58_DFCFB830_B9E25BDA_A3E1AFFA_91806D01_A89BDF50 + 256'hDA43FECD_D6C1A586_93232D1C_3E361D85_6AB2D1DC_6455D87F_13C9A467_1446BEA8 }; // Compile-time random bits for generation seed when aes destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeAesSeed = { - 256'h84C3F043_FE74B4FF_850B4A6D_EA97774B_63EF1E13_CA69B8BB_7DAE3157_B7279A2B + 256'h56D5FBB5_4BB5B253_A70BC372_CFC9BB0A_B38A5EDA_BEE7D224_D1A66837_8437DD24 }; // Compile-time random bits for generation seed when kmac destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeKmacSeed = { - 256'hD0F45178_ADD4099B_463A9BFA_DEB0A249_E67A25FE_EA95E50B_27DEDC68_15C375B4 + 256'h797B602B_068C0A1A_ECA298C9_6A8130AB_336462CE_E1BF8C65_3FDE5A40_A24DF78E }; // Compile-time random bits for generation seed when otbn destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeOtbnSeed = { - 256'hBD85E84A_EB69C3F4_DB751585_B16ED45D_55A6C1FF_D5C92099_CDEEA949_DC968AC7 + 256'h146916DC_55F8CE6D_BFAAD089_10FBE182_2C22A17A_376FA131_5C0CB3C2_9CF4D10A }; // Compile-time random bits for generation seed when no destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeNoneSeed = { - 256'h0991C551_4057A6A1_5FAA5773_95193CDE_4A6705BD_11203330_A927A8CE_1AC88224 + 256'hE5C8F0C7_B034BF23_C9068E30_7D8513B7_734AA78C_C36F947A_2737BBC0_ACD1447B }; //////////////////////////////////////////// @@ -549,14 +519,14 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { - 128'hA441C419_2ABE1DC4_26FEEE2C_9B1C8B34, - 256'hB1A821AF_E522E11C_4049D9B8_5F9DC3C9_9A378685_79B46A84_095EA981_140FF7F0 + 128'hAA83C3FC_818BB3B4_A840AD32_14CEB3F3, + 256'h54CA2E08_9302C3EE_1D695AA6_16283205_DB05CD6C_18888AD0_1FE046EA_FD8BF298 }; // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { - 128'hC4AD73D5_9726774A_37E33560_266D52A2, - 256'hD9C49012_61C19F48_0238C019_7CFA2C90_10EEFDD6_6D4B9172_5B5E1A95_A1411451 + 128'hDB7D5FE0_FD32A296_89A0C154_9C28C210, + 256'hC01FF7E6_E6D20E04_04E7B51D_020AA369_5DF42597_CACAEA4E_16EF75A4_823EE1BF }; //////////////////////////////////////////// @@ -564,23 +534,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { - 128'hC3DA5967_F2CC89F1_B0ECA338_8F277FFA + 128'h100B50C3_A2C1BA79_A60BD0D9_47C26D8D }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { - 128'hE4319B41_44B76B7C_902A9C89_F6F8F885 + 128'h3C3874C6_B8E34A85_925CE73B_8F155098 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { - 64'h6D8B76B9_B8EC2F4F + 64'h5EB503E8_E4071315 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { - 128'h706FB310_EE91C18D_B25CD085_FECA6164, - 256'hC79D0074_08E6EF4F_4CA977D7_C0662F46_A28D4B78_4A856ABD_6824EDFC_499DBAC3 + 128'h548BB3CA_4D68806B_6F35D30E_5BCC0749, + 256'h103B8571_4F8A64EB_07461441_B8F8A99C_43EAC7A9_2BE27769_FF7909CD_A59FF10B }; //////////////////////////////////////////// @@ -588,23 +558,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlSecSramKey = { - 128'hD474657B_77F7EDA1_A07047F9_37051A05 + 128'h025EC695_47062345_C400F5EF_1B06A119 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlSecSramNonce = { - 128'h7461414B_8B3587C6_DE71B922_084EC4EA + 128'h650A85C3_0237536D_C3E35040_DE9AC1A6 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlSecLfsrSeed = { - 64'h31A97E0A_CB1ACB48 + 64'hF2B35C99_FB71E1AA }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlSecLfsrPerm = { - 128'hE2BAB79B_975A58A1_83A4527E_F0BC6EF6, - 256'h507B87F7_33D53B55_60E780D2_C5E73142_02D91652_8EF12440_F7CDC1B8_22E87A32 + 128'h158DED08_E4F2A76F_9E978333_2A8B907D, + 256'h4BE2D5D6_4B257592_9F0EA1EC_7374E550_DA06C9B1_6E3FFD1A_445C100A_FC8083EA }; //////////////////////////////////////////// @@ -612,12 +582,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrlScrNonce = { - 64'h29EE296D_A1850BE6 + 64'hCA69B8BB_7DAE3157 }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrlScrKey = { - 128'hBED073F6_EE870F58_B89FABFE_08C82783 + 128'hB7279A2B_D0F45178_ADD4099B_463A9BFA }; //////////////////////////////////////////// @@ -625,22 +595,22 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for random instructions. parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { - 32'h7C7867EE + 32'hDEB0A249 }; // Permutation applied to the LFSR of the PRNG used for random instructions. parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { - 160'hD1BC70DB_288506AE_7C5DB826_F2912C93_6ABDBA38 + 160'h1FB7401D_1FD454C2_CCCBAE2F_94C2CE13_7A1911FC }; // Default icache scrambling key parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { - 128'hE90CAEAE_11CB84B6_5FDC5C70_2578F9F8 + 128'h57A6A15F_AA577395_193CDE4A_6705BD11 }; // Default icache scrambling nonce parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { - 64'h93C20A28_65EF55E0 + 64'h203330A9_27A8CE1A }; endpackage : top_earlgrey_rnd_cnst_pkg diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core index d8f283206d729..7e2e69a9a551d 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core @@ -12,7 +12,6 @@ filesets: files_rtl: depend: - lowrisc:earlgrey_ip:alert_handler_pkg - - lowrisc:earlgrey_ip:flash_ctrl - lowrisc:earlgrey_ip:otp_ctrl_top_specific_pkg - lowrisc:ibex:ibex_pkg - lowrisc:ip:aes diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 79d4c598746c5..624b1dc8f6328 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -48,10 +48,6 @@ module top_earlgrey #( parameter bit SramCtrlRetInstrExec = 0, parameter int SramCtrlRetNumPrinceRoundsHalf = 3, parameter bit SramCtrlRetEccCorrection = 0, - // parameters for flash_ctrl - parameter bit SecFlashCtrlScrambleEn = 1, - parameter int FlashCtrlProgFifoDepth = 4, - parameter int FlashCtrlRdFifoDepth = 16, // parameters for rram_ctrl parameter bit SecRramCtrlScrambleEn = 1, parameter int RramCtrlWrFifoDepth = 4, @@ -210,12 +206,6 @@ module top_earlgrey #( output prim_mubi_pkg::mubi4_t hi_speed_sel_o, input prim_mubi_pkg::mubi4_t div_step_down_req_i, input prim_mubi_pkg::mubi4_t calib_rdy_i, - input prim_mubi_pkg::mubi4_t flash_bist_enable_i, - input logic flash_power_down_h_i, - input logic flash_power_ready_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - output logic [7:0] flash_obs_o, output logic es_rng_enable_o, input logic es_rng_valid_i, input logic [EntropySrcRngBusWidth-1:0] es_rng_bit_i, @@ -351,9 +341,6 @@ module top_earlgrey #( .UsbdevRcvrWakeTimeUs(UsbdevRcvrWakeTimeUs), .SecPinmuxVolatileRawUnlockEn(SecPinmuxVolatileRawUnlockEn), .PinmuxTargetCfg(PinmuxTargetCfg), - .SecFlashCtrlScrambleEn(SecFlashCtrlScrambleEn), - .FlashCtrlProgFifoDepth(FlashCtrlProgFifoDepth), - .FlashCtrlRdFifoDepth(FlashCtrlRdFifoDepth), .SecRramCtrlScrambleEn(SecRramCtrlScrambleEn), .RramCtrlWrFifoDepth(RramCtrlWrFifoDepth), .RramCtrlRdFifoDepth(RramCtrlRdFifoDepth), @@ -565,12 +552,6 @@ module top_earlgrey #( .sram_ctrl_main_ram_cfg_rsp_o, .sram_ctrl_sec_ram_cfg_req_i, .sram_ctrl_sec_ram_cfg_rsp_o, - .flash_bist_enable_i, - .flash_power_down_h_i, - .flash_power_ready_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .flash_obs_o, .es_rng_enable_o, .es_rng_valid_i, .es_rng_bit_i, diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 747c6f83b5e18..b96912f4998cb 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -269,26 +269,6 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES = 32'h40; - /** - * Peripheral base address for core device on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR = 32'h41000000; - - /** - * Peripheral size in bytes for core device on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES = 32'h200; - - /** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR = 32'h41008000; - - /** - * Peripheral size in bytes for prim device on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80; - /** * Peripheral base address for core device on rram_ctrl in top earlgrey. */ @@ -479,16 +459,6 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES = 32'h1000; - /** - * Memory base address for mem memory on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR = 32'h20000000; - - /** - * Memory size for mem memory on flash_ctrl in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES = 32'h100000; - /** * Memory base address for host memory on rram_ctrl in top earlgrey. */ @@ -556,23 +526,22 @@ package top_earlgrey_pkg; TopEarlgreyAlertPeripheralAonTimer = 21, TopEarlgreyAlertPeripheralSensorCtrl = 22, TopEarlgreyAlertPeripheralSramCtrlRet = 23, - TopEarlgreyAlertPeripheralFlashCtrl = 24, - TopEarlgreyAlertPeripheralRramCtrl = 25, - TopEarlgreyAlertPeripheralRvDm = 26, - TopEarlgreyAlertPeripheralRvPlic = 27, - TopEarlgreyAlertPeripheralAes = 28, - TopEarlgreyAlertPeripheralHmac = 29, - TopEarlgreyAlertPeripheralKmac = 30, - TopEarlgreyAlertPeripheralOtbn = 31, - TopEarlgreyAlertPeripheralKeymgrDpe = 32, - TopEarlgreyAlertPeripheralCsrng = 33, - TopEarlgreyAlertPeripheralEntropySrc = 34, - TopEarlgreyAlertPeripheralEdn0 = 35, - TopEarlgreyAlertPeripheralEdn1 = 36, - TopEarlgreyAlertPeripheralSramCtrlMain = 37, - TopEarlgreyAlertPeripheralSramCtrlSec = 38, - TopEarlgreyAlertPeripheralRomCtrl = 39, - TopEarlgreyAlertPeripheralRvCoreIbex = 40, + TopEarlgreyAlertPeripheralRramCtrl = 24, + TopEarlgreyAlertPeripheralRvDm = 25, + TopEarlgreyAlertPeripheralRvPlic = 26, + TopEarlgreyAlertPeripheralAes = 27, + TopEarlgreyAlertPeripheralHmac = 28, + TopEarlgreyAlertPeripheralKmac = 29, + TopEarlgreyAlertPeripheralOtbn = 30, + TopEarlgreyAlertPeripheralKeymgrDpe = 31, + TopEarlgreyAlertPeripheralCsrng = 32, + TopEarlgreyAlertPeripheralEntropySrc = 33, + TopEarlgreyAlertPeripheralEdn0 = 34, + TopEarlgreyAlertPeripheralEdn1 = 35, + TopEarlgreyAlertPeripheralSramCtrlMain = 36, + TopEarlgreyAlertPeripheralSramCtrlSec = 37, + TopEarlgreyAlertPeripheralRomCtrl = 38, + TopEarlgreyAlertPeripheralRvCoreIbex = 39, TopEarlgreyAlertPeripheralCount } alert_peripheral_e; @@ -611,42 +580,37 @@ package top_earlgrey_pkg; TopEarlgreyAlertIdSensorCtrlRecovAlert = 30, TopEarlgreyAlertIdSensorCtrlFatalAlert = 31, TopEarlgreyAlertIdSramCtrlRetFatalError = 32, - TopEarlgreyAlertIdFlashCtrlRecovErr = 33, - TopEarlgreyAlertIdFlashCtrlFatalStdErr = 34, - TopEarlgreyAlertIdFlashCtrlFatalErr = 35, - TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 36, - TopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 37, - TopEarlgreyAlertIdRramCtrlRecovErr = 38, - TopEarlgreyAlertIdRramCtrlFatalStdErr = 39, - TopEarlgreyAlertIdRramCtrlFatalErr = 40, - TopEarlgreyAlertIdRramCtrlFatalMacroErr = 41, - TopEarlgreyAlertIdRramCtrlRecovMacroErr = 42, - TopEarlgreyAlertIdRvDmFatalFault = 43, - TopEarlgreyAlertIdRvPlicFatalFault = 44, - TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 45, - TopEarlgreyAlertIdAesFatalFault = 46, - TopEarlgreyAlertIdHmacFatalFault = 47, - TopEarlgreyAlertIdKmacRecovOperationErr = 48, - TopEarlgreyAlertIdKmacFatalFaultErr = 49, - TopEarlgreyAlertIdOtbnFatal = 50, - TopEarlgreyAlertIdOtbnRecov = 51, - TopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 52, - TopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 53, - TopEarlgreyAlertIdCsrngRecovAlert = 54, - TopEarlgreyAlertIdCsrngFatalAlert = 55, - TopEarlgreyAlertIdEntropySrcRecovAlert = 56, - TopEarlgreyAlertIdEntropySrcFatalAlert = 57, - TopEarlgreyAlertIdEdn0RecovAlert = 58, - TopEarlgreyAlertIdEdn0FatalAlert = 59, - TopEarlgreyAlertIdEdn1RecovAlert = 60, - TopEarlgreyAlertIdEdn1FatalAlert = 61, - TopEarlgreyAlertIdSramCtrlMainFatalError = 62, - TopEarlgreyAlertIdSramCtrlSecFatalError = 63, - TopEarlgreyAlertIdRomCtrlFatal = 64, - TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 65, - TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 66, - TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 67, - TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 68, + TopEarlgreyAlertIdRramCtrlRecovErr = 33, + TopEarlgreyAlertIdRramCtrlFatalStdErr = 34, + TopEarlgreyAlertIdRramCtrlFatalErr = 35, + TopEarlgreyAlertIdRramCtrlFatalMacroErr = 36, + TopEarlgreyAlertIdRramCtrlRecovMacroErr = 37, + TopEarlgreyAlertIdRvDmFatalFault = 38, + TopEarlgreyAlertIdRvPlicFatalFault = 39, + TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 40, + TopEarlgreyAlertIdAesFatalFault = 41, + TopEarlgreyAlertIdHmacFatalFault = 42, + TopEarlgreyAlertIdKmacRecovOperationErr = 43, + TopEarlgreyAlertIdKmacFatalFaultErr = 44, + TopEarlgreyAlertIdOtbnFatal = 45, + TopEarlgreyAlertIdOtbnRecov = 46, + TopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 47, + TopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 48, + TopEarlgreyAlertIdCsrngRecovAlert = 49, + TopEarlgreyAlertIdCsrngFatalAlert = 50, + TopEarlgreyAlertIdEntropySrcRecovAlert = 51, + TopEarlgreyAlertIdEntropySrcFatalAlert = 52, + TopEarlgreyAlertIdEdn0RecovAlert = 53, + TopEarlgreyAlertIdEdn0FatalAlert = 54, + TopEarlgreyAlertIdEdn1RecovAlert = 55, + TopEarlgreyAlertIdEdn1FatalAlert = 56, + TopEarlgreyAlertIdSramCtrlMainFatalError = 57, + TopEarlgreyAlertIdSramCtrlSecFatalError = 58, + TopEarlgreyAlertIdRomCtrlFatal = 59, + TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 60, + TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 61, + TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 62, + TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 63, TopEarlgreyAlertIdCount } alert_id_e; @@ -810,38 +774,32 @@ package top_earlgrey_pkg; TopEarlgreyPlicIrqIdAonTimerWdogTimerBark = 155, TopEarlgreyPlicIrqIdSensorCtrlIoStatusChange = 156, TopEarlgreyPlicIrqIdSensorCtrlInitStatusChange = 157, - TopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 158, - TopEarlgreyPlicIrqIdFlashCtrlProgLvl = 159, - TopEarlgreyPlicIrqIdFlashCtrlRdFull = 160, - TopEarlgreyPlicIrqIdFlashCtrlRdLvl = 161, - TopEarlgreyPlicIrqIdFlashCtrlOpDone = 162, - TopEarlgreyPlicIrqIdFlashCtrlCorrErr = 163, - TopEarlgreyPlicIrqIdRramCtrlWrEmpty = 164, - TopEarlgreyPlicIrqIdRramCtrlWrLvl = 165, - TopEarlgreyPlicIrqIdRramCtrlRdFull = 166, - TopEarlgreyPlicIrqIdRramCtrlRdLvl = 167, - TopEarlgreyPlicIrqIdRramCtrlOpDone = 168, - TopEarlgreyPlicIrqIdRramCtrlCorrErr = 169, - TopEarlgreyPlicIrqIdHmacHmacDone = 170, - TopEarlgreyPlicIrqIdHmacFifoEmpty = 171, - TopEarlgreyPlicIrqIdHmacHmacErr = 172, - TopEarlgreyPlicIrqIdKmacKmacDone = 173, - TopEarlgreyPlicIrqIdKmacFifoEmpty = 174, - TopEarlgreyPlicIrqIdKmacKmacErr = 175, - TopEarlgreyPlicIrqIdOtbnDone = 176, - TopEarlgreyPlicIrqIdKeymgrDpeOpDone = 177, - TopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 178, - TopEarlgreyPlicIrqIdCsrngCsEntropyReq = 179, - TopEarlgreyPlicIrqIdCsrngCsHwInstExc = 180, - TopEarlgreyPlicIrqIdCsrngCsFatalErr = 181, - TopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 182, - TopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 183, - TopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 184, - TopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 185, - TopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 186, - TopEarlgreyPlicIrqIdEdn0EdnFatalErr = 187, - TopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 188, - TopEarlgreyPlicIrqIdEdn1EdnFatalErr = 189, + TopEarlgreyPlicIrqIdRramCtrlWrEmpty = 158, + TopEarlgreyPlicIrqIdRramCtrlWrLvl = 159, + TopEarlgreyPlicIrqIdRramCtrlRdFull = 160, + TopEarlgreyPlicIrqIdRramCtrlRdLvl = 161, + TopEarlgreyPlicIrqIdRramCtrlOpDone = 162, + TopEarlgreyPlicIrqIdRramCtrlCorrErr = 163, + TopEarlgreyPlicIrqIdHmacHmacDone = 164, + TopEarlgreyPlicIrqIdHmacFifoEmpty = 165, + TopEarlgreyPlicIrqIdHmacHmacErr = 166, + TopEarlgreyPlicIrqIdKmacKmacDone = 167, + TopEarlgreyPlicIrqIdKmacFifoEmpty = 168, + TopEarlgreyPlicIrqIdKmacKmacErr = 169, + TopEarlgreyPlicIrqIdOtbnDone = 170, + TopEarlgreyPlicIrqIdKeymgrDpeOpDone = 171, + TopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 172, + TopEarlgreyPlicIrqIdCsrngCsEntropyReq = 173, + TopEarlgreyPlicIrqIdCsrngCsHwInstExc = 174, + TopEarlgreyPlicIrqIdCsrngCsFatalErr = 175, + TopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 176, + TopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 177, + TopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 178, + TopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 179, + TopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 180, + TopEarlgreyPlicIrqIdEdn0EdnFatalErr = 181, + TopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 182, + TopEarlgreyPlicIrqIdEdn1EdnFatalErr = 183, TopEarlgreyPlicIrqIdCount } interrupt_rv_plic_id_e; @@ -905,20 +863,17 @@ package top_earlgrey_pkg; MioInUart2Rx = 44, MioInUart3Rx = 45, MioInSpiDeviceTpmCsb = 46, - MioInFlashCtrlTck = 47, - MioInFlashCtrlTms = 48, - MioInFlashCtrlTdi = 49, - MioInRramMacroTck = 50, - MioInRramMacroTms = 51, - MioInRramMacroTdi = 52, - MioInSysrstCtrlAcPresent = 53, - MioInSysrstCtrlKey0In = 54, - MioInSysrstCtrlKey1In = 55, - MioInSysrstCtrlKey2In = 56, - MioInSysrstCtrlPwrbIn = 57, - MioInSysrstCtrlLidOpen = 58, - MioInUsbdevSense = 59, - MioInCount = 60 + MioInRramMacroTck = 47, + MioInRramMacroTms = 48, + MioInRramMacroTdi = 49, + MioInSysrstCtrlAcPresent = 50, + MioInSysrstCtrlKey0In = 51, + MioInSysrstCtrlKey1In = 52, + MioInSysrstCtrlKey2In = 53, + MioInSysrstCtrlPwrbIn = 54, + MioInSysrstCtrlLidOpen = 55, + MioInUsbdevSense = 56, + MioInCount = 57 } mio_in_e; typedef enum { @@ -970,24 +925,23 @@ package top_earlgrey_pkg; MioOutUart3Tx = 45, MioOutSpiHost1Sck = 46, MioOutSpiHost1Csb = 47, - MioOutFlashCtrlTdo = 48, - MioOutRramMacroTdo = 49, - MioOutSensorCtrlAstDebugOut0 = 50, - MioOutSensorCtrlAstDebugOut1 = 51, - MioOutSensorCtrlAstDebugOut2 = 52, - MioOutSensorCtrlAstDebugOut3 = 53, - MioOutSensorCtrlAstDebugOut4 = 54, - MioOutSensorCtrlAstDebugOut5 = 55, - MioOutSensorCtrlAstDebugOut6 = 56, - MioOutSensorCtrlAstDebugOut7 = 57, - MioOutSensorCtrlAstDebugOut8 = 58, - MioOutSysrstCtrlBatDisable = 59, - MioOutSysrstCtrlKey0Out = 60, - MioOutSysrstCtrlKey1Out = 61, - MioOutSysrstCtrlKey2Out = 62, - MioOutSysrstCtrlPwrbOut = 63, - MioOutSysrstCtrlZ3Wakeup = 64, - MioOutCount = 65 + MioOutRramMacroTdo = 48, + MioOutSensorCtrlAstDebugOut0 = 49, + MioOutSensorCtrlAstDebugOut1 = 50, + MioOutSensorCtrlAstDebugOut2 = 51, + MioOutSensorCtrlAstDebugOut3 = 52, + MioOutSensorCtrlAstDebugOut4 = 53, + MioOutSensorCtrlAstDebugOut5 = 54, + MioOutSensorCtrlAstDebugOut6 = 55, + MioOutSensorCtrlAstDebugOut7 = 56, + MioOutSensorCtrlAstDebugOut8 = 57, + MioOutSysrstCtrlBatDisable = 58, + MioOutSysrstCtrlKey0Out = 59, + MioOutSysrstCtrlKey1Out = 60, + MioOutSysrstCtrlKey2Out = 61, + MioOutSysrstCtrlPwrbOut = 62, + MioOutSysrstCtrlZ3Wakeup = 63, + MioOutCount = 64 } mio_out_e; // Enumeration for DIO signals, used on both the top and chip-levels. @@ -1077,24 +1031,21 @@ package top_earlgrey_pkg; DioPadUsbN = 2, DioPadCc1 = 3, DioPadCc2 = 4, - DioPadFlashTestVolt = 5, - DioPadFlashTestMode0 = 6, - DioPadFlashTestMode1 = 7, - DioPadRramAnalog = 8, - DioPadSpiHostD0 = 9, - DioPadSpiHostD1 = 10, - DioPadSpiHostD2 = 11, - DioPadSpiHostD3 = 12, - DioPadSpiHostClk = 13, - DioPadSpiHostCsL = 14, - DioPadSpiDevD0 = 15, - DioPadSpiDevD1 = 16, - DioPadSpiDevD2 = 17, - DioPadSpiDevD3 = 18, - DioPadSpiDevClk = 19, - DioPadSpiDevCsL = 20, - DioPadIor8 = 21, - DioPadIor9 = 22, + DioPadRramAnalog = 5, + DioPadSpiHostD0 = 6, + DioPadSpiHostD1 = 7, + DioPadSpiHostD2 = 8, + DioPadSpiHostD3 = 9, + DioPadSpiHostClk = 10, + DioPadSpiHostCsL = 11, + DioPadSpiDevD0 = 12, + DioPadSpiDevD1 = 13, + DioPadSpiDevD2 = 14, + DioPadSpiDevD3 = 15, + DioPadSpiDevClk = 16, + DioPadSpiDevCsL = 17, + DioPadIor8 = 18, + DioPadIor9 = 19, DioPadCount } dio_pad_e; @@ -1110,7 +1061,6 @@ package top_earlgrey_pkg; PeripheralEdn0, PeripheralEdn1, PeripheralEntropySrc, - PeripheralFlashCtrl, PeripheralGpio, PeripheralHmac, PeripheralI2c0, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index c32c49aa8d0d5..7baddec9bd2f6 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -385,34 +385,6 @@ pub const SRAM_CTRL_RET_REGS_BASE_ADDR: usize = 0x40500000; /// `SRAM_CTRL_RET_REGS_BASE_ADDR + SRAM_CTRL_RET_REGS_SIZE_BYTES`. pub const SRAM_CTRL_RET_REGS_SIZE_BYTES: usize = 0x40; -/// Peripheral base address for core device on flash_ctrl in top earlgrey. -/// -/// This should be used with #mmio_region_from_addr to access the memory-mapped -/// registers associated with the peripheral (usually via a DIF). -pub const FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000; - -/// Peripheral size for core device on flash_ctrl in top earlgrey. -/// -/// This is the size (in bytes) of the peripheral's reserved memory area. All -/// memory-mapped registers associated with this peripheral should have an -/// address between #FLASH_CTRL_CORE_BASE_ADDR and -/// `FLASH_CTRL_CORE_BASE_ADDR + FLASH_CTRL_CORE_SIZE_BYTES`. -pub const FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200; - -/// Peripheral base address for prim device on flash_ctrl in top earlgrey. -/// -/// This should be used with #mmio_region_from_addr to access the memory-mapped -/// registers associated with the peripheral (usually via a DIF). -pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000; - -/// Peripheral size for prim device on flash_ctrl in top earlgrey. -/// -/// This is the size (in bytes) of the peripheral's reserved memory area. All -/// memory-mapped registers associated with this peripheral should have an -/// address between #FLASH_CTRL_PRIM_BASE_ADDR and -/// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`. -pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80; - /// Peripheral base address for core device on rram_ctrl in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -671,12 +643,6 @@ pub const SRAM_CTRL_RET_RAM_BASE_ADDR: usize = 0x40600000; /// Memory size for ram memory on sram_ctrl_ret in top earlgrey. pub const SRAM_CTRL_RET_RAM_SIZE_BYTES: usize = 0x1000; -/// Memory base address for mem memory on flash_ctrl in top earlgrey. -pub const FLASH_CTRL_MEM_BASE_ADDR: usize = 0x20000000; - -/// Memory size for mem memory on flash_ctrl in top earlgrey. -pub const FLASH_CTRL_MEM_SIZE_BYTES: usize = 0x100000; - /// Memory base address for host memory on rram_ctrl in top earlgrey. pub const RRAM_CTRL_HOST_BASE_ADDR: usize = 0x30000000; @@ -750,26 +716,24 @@ pub enum PlicPeripheral { AonTimer = 19, /// sensor_ctrl SensorCtrl = 20, - /// flash_ctrl - FlashCtrl = 21, /// rram_ctrl - RramCtrl = 22, + RramCtrl = 21, /// hmac - Hmac = 23, + Hmac = 22, /// kmac - Kmac = 24, + Kmac = 23, /// otbn - Otbn = 25, + Otbn = 24, /// keymgr_dpe - KeymgrDpe = 26, + KeymgrDpe = 25, /// csrng - Csrng = 27, + Csrng = 26, /// entropy_src - EntropySrc = 28, + EntropySrc = 27, /// edn0 - Edn0 = 29, + Edn0 = 28, /// edn1 - Edn1 = 30, + Edn1 = 29, } impl TryFrom for PlicPeripheral { @@ -797,16 +761,15 @@ impl TryFrom for PlicPeripheral { 18 => Ok(Self::AdcCtrl), 19 => Ok(Self::AonTimer), 20 => Ok(Self::SensorCtrl), - 21 => Ok(Self::FlashCtrl), - 22 => Ok(Self::RramCtrl), - 23 => Ok(Self::Hmac), - 24 => Ok(Self::Kmac), - 25 => Ok(Self::Otbn), - 26 => Ok(Self::KeymgrDpe), - 27 => Ok(Self::Csrng), - 28 => Ok(Self::EntropySrc), - 29 => Ok(Self::Edn0), - 30 => Ok(Self::Edn1), + 21 => Ok(Self::RramCtrl), + 22 => Ok(Self::Hmac), + 23 => Ok(Self::Kmac), + 24 => Ok(Self::Otbn), + 25 => Ok(Self::KeymgrDpe), + 26 => Ok(Self::Csrng), + 27 => Ok(Self::EntropySrc), + 28 => Ok(Self::Edn0), + 29 => Ok(Self::Edn1), _ => Err(val), } } @@ -1135,70 +1098,58 @@ pub enum PlicIrqId { SensorCtrlIoStatusChange = 156, /// sensor_ctrl_init_status_change SensorCtrlInitStatusChange = 157, - /// flash_ctrl_prog_empty - FlashCtrlProgEmpty = 158, - /// flash_ctrl_prog_lvl - FlashCtrlProgLvl = 159, - /// flash_ctrl_rd_full - FlashCtrlRdFull = 160, - /// flash_ctrl_rd_lvl - FlashCtrlRdLvl = 161, - /// flash_ctrl_op_done - FlashCtrlOpDone = 162, - /// flash_ctrl_corr_err - FlashCtrlCorrErr = 163, /// rram_ctrl_wr_empty - RramCtrlWrEmpty = 164, + RramCtrlWrEmpty = 158, /// rram_ctrl_wr_lvl - RramCtrlWrLvl = 165, + RramCtrlWrLvl = 159, /// rram_ctrl_rd_full - RramCtrlRdFull = 166, + RramCtrlRdFull = 160, /// rram_ctrl_rd_lvl - RramCtrlRdLvl = 167, + RramCtrlRdLvl = 161, /// rram_ctrl_op_done - RramCtrlOpDone = 168, + RramCtrlOpDone = 162, /// rram_ctrl_corr_err - RramCtrlCorrErr = 169, + RramCtrlCorrErr = 163, /// hmac_hmac_done - HmacHmacDone = 170, + HmacHmacDone = 164, /// hmac_fifo_empty - HmacFifoEmpty = 171, + HmacFifoEmpty = 165, /// hmac_hmac_err - HmacHmacErr = 172, + HmacHmacErr = 166, /// kmac_kmac_done - KmacKmacDone = 173, + KmacKmacDone = 167, /// kmac_fifo_empty - KmacFifoEmpty = 174, + KmacFifoEmpty = 168, /// kmac_kmac_err - KmacKmacErr = 175, + KmacKmacErr = 169, /// otbn_done - OtbnDone = 176, + OtbnDone = 170, /// keymgr_dpe_op_done - KeymgrDpeOpDone = 177, + KeymgrDpeOpDone = 171, /// csrng_cs_cmd_req_done - CsrngCsCmdReqDone = 178, + CsrngCsCmdReqDone = 172, /// csrng_cs_entropy_req - CsrngCsEntropyReq = 179, + CsrngCsEntropyReq = 173, /// csrng_cs_hw_inst_exc - CsrngCsHwInstExc = 180, + CsrngCsHwInstExc = 174, /// csrng_cs_fatal_err - CsrngCsFatalErr = 181, + CsrngCsFatalErr = 175, /// entropy_src_es_entropy_valid - EntropySrcEsEntropyValid = 182, + EntropySrcEsEntropyValid = 176, /// entropy_src_es_health_test_failed - EntropySrcEsHealthTestFailed = 183, + EntropySrcEsHealthTestFailed = 177, /// entropy_src_es_observe_fifo_ready - EntropySrcEsObserveFifoReady = 184, + EntropySrcEsObserveFifoReady = 178, /// entropy_src_es_fatal_err - EntropySrcEsFatalErr = 185, + EntropySrcEsFatalErr = 179, /// edn0_edn_cmd_req_done - Edn0EdnCmdReqDone = 186, + Edn0EdnCmdReqDone = 180, /// edn0_edn_fatal_err - Edn0EdnFatalErr = 187, + Edn0EdnFatalErr = 181, /// edn1_edn_cmd_req_done - Edn1EdnCmdReqDone = 188, + Edn1EdnCmdReqDone = 182, /// edn1_edn_fatal_err - Edn1EdnFatalErr = 189, + Edn1EdnFatalErr = 183, } impl TryFrom for PlicIrqId { @@ -1363,38 +1314,32 @@ impl TryFrom for PlicIrqId { 155 => Ok(Self::AonTimerWdogTimerBark), 156 => Ok(Self::SensorCtrlIoStatusChange), 157 => Ok(Self::SensorCtrlInitStatusChange), - 158 => Ok(Self::FlashCtrlProgEmpty), - 159 => Ok(Self::FlashCtrlProgLvl), - 160 => Ok(Self::FlashCtrlRdFull), - 161 => Ok(Self::FlashCtrlRdLvl), - 162 => Ok(Self::FlashCtrlOpDone), - 163 => Ok(Self::FlashCtrlCorrErr), - 164 => Ok(Self::RramCtrlWrEmpty), - 165 => Ok(Self::RramCtrlWrLvl), - 166 => Ok(Self::RramCtrlRdFull), - 167 => Ok(Self::RramCtrlRdLvl), - 168 => Ok(Self::RramCtrlOpDone), - 169 => Ok(Self::RramCtrlCorrErr), - 170 => Ok(Self::HmacHmacDone), - 171 => Ok(Self::HmacFifoEmpty), - 172 => Ok(Self::HmacHmacErr), - 173 => Ok(Self::KmacKmacDone), - 174 => Ok(Self::KmacFifoEmpty), - 175 => Ok(Self::KmacKmacErr), - 176 => Ok(Self::OtbnDone), - 177 => Ok(Self::KeymgrDpeOpDone), - 178 => Ok(Self::CsrngCsCmdReqDone), - 179 => Ok(Self::CsrngCsEntropyReq), - 180 => Ok(Self::CsrngCsHwInstExc), - 181 => Ok(Self::CsrngCsFatalErr), - 182 => Ok(Self::EntropySrcEsEntropyValid), - 183 => Ok(Self::EntropySrcEsHealthTestFailed), - 184 => Ok(Self::EntropySrcEsObserveFifoReady), - 185 => Ok(Self::EntropySrcEsFatalErr), - 186 => Ok(Self::Edn0EdnCmdReqDone), - 187 => Ok(Self::Edn0EdnFatalErr), - 188 => Ok(Self::Edn1EdnCmdReqDone), - 189 => Ok(Self::Edn1EdnFatalErr), + 158 => Ok(Self::RramCtrlWrEmpty), + 159 => Ok(Self::RramCtrlWrLvl), + 160 => Ok(Self::RramCtrlRdFull), + 161 => Ok(Self::RramCtrlRdLvl), + 162 => Ok(Self::RramCtrlOpDone), + 163 => Ok(Self::RramCtrlCorrErr), + 164 => Ok(Self::HmacHmacDone), + 165 => Ok(Self::HmacFifoEmpty), + 166 => Ok(Self::HmacHmacErr), + 167 => Ok(Self::KmacKmacDone), + 168 => Ok(Self::KmacFifoEmpty), + 169 => Ok(Self::KmacKmacErr), + 170 => Ok(Self::OtbnDone), + 171 => Ok(Self::KeymgrDpeOpDone), + 172 => Ok(Self::CsrngCsCmdReqDone), + 173 => Ok(Self::CsrngCsEntropyReq), + 174 => Ok(Self::CsrngCsHwInstExc), + 175 => Ok(Self::CsrngCsFatalErr), + 176 => Ok(Self::EntropySrcEsEntropyValid), + 177 => Ok(Self::EntropySrcEsHealthTestFailed), + 178 => Ok(Self::EntropySrcEsObserveFifoReady), + 179 => Ok(Self::EntropySrcEsFatalErr), + 180 => Ok(Self::Edn0EdnCmdReqDone), + 181 => Ok(Self::Edn0EdnFatalErr), + 182 => Ok(Self::Edn1EdnCmdReqDone), + 183 => Ok(Self::Edn1EdnFatalErr), _ => Err(val), } } @@ -1415,7 +1360,7 @@ pub enum PlicTarget { /// /// This array is a mapping from `PlicIrqId` to /// `PlicPeripheral`. -pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 190] = [ +pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 184] = [ // None -> PlicPeripheral::Unknown PlicPeripheral::Unknown, // Uart0TxWatermark -> PlicPeripheral::Uart0 @@ -1732,18 +1677,6 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 190] = [ PlicPeripheral::SensorCtrl, // SensorCtrlInitStatusChange -> PlicPeripheral::SensorCtrl PlicPeripheral::SensorCtrl, - // FlashCtrlProgEmpty -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, - // FlashCtrlProgLvl -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, - // FlashCtrlRdFull -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, - // FlashCtrlRdLvl -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, - // FlashCtrlOpDone -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, - // FlashCtrlCorrErr -> PlicPeripheral::FlashCtrl - PlicPeripheral::FlashCtrl, // RramCtrlWrEmpty -> PlicPeripheral::RramCtrl PlicPeripheral::RramCtrl, // RramCtrlWrLvl -> PlicPeripheral::RramCtrl @@ -1855,40 +1788,38 @@ pub enum AlertPeripheral { SensorCtrl = 23, /// sram_ctrl_ret SramCtrlRet = 24, - /// flash_ctrl - FlashCtrl = 25, /// rram_ctrl - RramCtrl = 26, + RramCtrl = 25, /// rv_dm - RvDm = 27, + RvDm = 26, /// rv_plic - RvPlic = 28, + RvPlic = 27, /// aes - Aes = 29, + Aes = 28, /// hmac - Hmac = 30, + Hmac = 29, /// kmac - Kmac = 31, + Kmac = 30, /// otbn - Otbn = 32, + Otbn = 31, /// keymgr_dpe - KeymgrDpe = 33, + KeymgrDpe = 32, /// csrng - Csrng = 34, + Csrng = 33, /// entropy_src - EntropySrc = 35, + EntropySrc = 34, /// edn0 - Edn0 = 36, + Edn0 = 35, /// edn1 - Edn1 = 37, + Edn1 = 36, /// sram_ctrl_main - SramCtrlMain = 38, + SramCtrlMain = 37, /// sram_ctrl_sec - SramCtrlSec = 39, + SramCtrlSec = 38, /// rom_ctrl - RomCtrl = 40, + RomCtrl = 39, /// rv_core_ibex - RvCoreIbex = 41, + RvCoreIbex = 40, } /// Alert Handler Alert Source. @@ -1964,78 +1895,68 @@ pub enum AlertId { SensorCtrlFatalAlert = 31, /// sram_ctrl_ret_fatal_error SramCtrlRetFatalError = 32, - /// flash_ctrl_recov_err - FlashCtrlRecovErr = 33, - /// flash_ctrl_fatal_std_err - FlashCtrlFatalStdErr = 34, - /// flash_ctrl_fatal_err - FlashCtrlFatalErr = 35, - /// flash_ctrl_fatal_prim_flash_alert - FlashCtrlFatalPrimFlashAlert = 36, - /// flash_ctrl_recov_prim_flash_alert - FlashCtrlRecovPrimFlashAlert = 37, /// rram_ctrl_recov_err - RramCtrlRecovErr = 38, + RramCtrlRecovErr = 33, /// rram_ctrl_fatal_std_err - RramCtrlFatalStdErr = 39, + RramCtrlFatalStdErr = 34, /// rram_ctrl_fatal_err - RramCtrlFatalErr = 40, + RramCtrlFatalErr = 35, /// rram_ctrl_fatal_macro_err - RramCtrlFatalMacroErr = 41, + RramCtrlFatalMacroErr = 36, /// rram_ctrl_recov_macro_err - RramCtrlRecovMacroErr = 42, + RramCtrlRecovMacroErr = 37, /// rv_dm_fatal_fault - RvDmFatalFault = 43, + RvDmFatalFault = 38, /// rv_plic_fatal_fault - RvPlicFatalFault = 44, + RvPlicFatalFault = 39, /// aes_recov_ctrl_update_err - AesRecovCtrlUpdateErr = 45, + AesRecovCtrlUpdateErr = 40, /// aes_fatal_fault - AesFatalFault = 46, + AesFatalFault = 41, /// hmac_fatal_fault - HmacFatalFault = 47, + HmacFatalFault = 42, /// kmac_recov_operation_err - KmacRecovOperationErr = 48, + KmacRecovOperationErr = 43, /// kmac_fatal_fault_err - KmacFatalFaultErr = 49, + KmacFatalFaultErr = 44, /// otbn_fatal - OtbnFatal = 50, + OtbnFatal = 45, /// otbn_recov - OtbnRecov = 51, + OtbnRecov = 46, /// keymgr_dpe_recov_operation_err - KeymgrDpeRecovOperationErr = 52, + KeymgrDpeRecovOperationErr = 47, /// keymgr_dpe_fatal_fault_err - KeymgrDpeFatalFaultErr = 53, + KeymgrDpeFatalFaultErr = 48, /// csrng_recov_alert - CsrngRecovAlert = 54, + CsrngRecovAlert = 49, /// csrng_fatal_alert - CsrngFatalAlert = 55, + CsrngFatalAlert = 50, /// entropy_src_recov_alert - EntropySrcRecovAlert = 56, + EntropySrcRecovAlert = 51, /// entropy_src_fatal_alert - EntropySrcFatalAlert = 57, + EntropySrcFatalAlert = 52, /// edn0_recov_alert - Edn0RecovAlert = 58, + Edn0RecovAlert = 53, /// edn0_fatal_alert - Edn0FatalAlert = 59, + Edn0FatalAlert = 54, /// edn1_recov_alert - Edn1RecovAlert = 60, + Edn1RecovAlert = 55, /// edn1_fatal_alert - Edn1FatalAlert = 61, + Edn1FatalAlert = 56, /// sram_ctrl_main_fatal_error - SramCtrlMainFatalError = 62, + SramCtrlMainFatalError = 57, /// sram_ctrl_sec_fatal_error - SramCtrlSecFatalError = 63, + SramCtrlSecFatalError = 58, /// rom_ctrl_fatal - RomCtrlFatal = 64, + RomCtrlFatal = 59, /// rv_core_ibex_fatal_sw_err - RvCoreIbexFatalSwErr = 65, + RvCoreIbexFatalSwErr = 60, /// rv_core_ibex_recov_sw_err - RvCoreIbexRecovSwErr = 66, + RvCoreIbexRecovSwErr = 61, /// rv_core_ibex_fatal_hw_err - RvCoreIbexFatalHwErr = 67, + RvCoreIbexFatalHwErr = 62, /// rv_core_ibex_recov_hw_err - RvCoreIbexRecovHwErr = 68, + RvCoreIbexRecovHwErr = 63, } impl TryFrom for AlertId { @@ -2075,42 +1996,37 @@ impl TryFrom for AlertId { 30 => Ok(Self::SensorCtrlRecovAlert), 31 => Ok(Self::SensorCtrlFatalAlert), 32 => Ok(Self::SramCtrlRetFatalError), - 33 => Ok(Self::FlashCtrlRecovErr), - 34 => Ok(Self::FlashCtrlFatalStdErr), - 35 => Ok(Self::FlashCtrlFatalErr), - 36 => Ok(Self::FlashCtrlFatalPrimFlashAlert), - 37 => Ok(Self::FlashCtrlRecovPrimFlashAlert), - 38 => Ok(Self::RramCtrlRecovErr), - 39 => Ok(Self::RramCtrlFatalStdErr), - 40 => Ok(Self::RramCtrlFatalErr), - 41 => Ok(Self::RramCtrlFatalMacroErr), - 42 => Ok(Self::RramCtrlRecovMacroErr), - 43 => Ok(Self::RvDmFatalFault), - 44 => Ok(Self::RvPlicFatalFault), - 45 => Ok(Self::AesRecovCtrlUpdateErr), - 46 => Ok(Self::AesFatalFault), - 47 => Ok(Self::HmacFatalFault), - 48 => Ok(Self::KmacRecovOperationErr), - 49 => Ok(Self::KmacFatalFaultErr), - 50 => Ok(Self::OtbnFatal), - 51 => Ok(Self::OtbnRecov), - 52 => Ok(Self::KeymgrDpeRecovOperationErr), - 53 => Ok(Self::KeymgrDpeFatalFaultErr), - 54 => Ok(Self::CsrngRecovAlert), - 55 => Ok(Self::CsrngFatalAlert), - 56 => Ok(Self::EntropySrcRecovAlert), - 57 => Ok(Self::EntropySrcFatalAlert), - 58 => Ok(Self::Edn0RecovAlert), - 59 => Ok(Self::Edn0FatalAlert), - 60 => Ok(Self::Edn1RecovAlert), - 61 => Ok(Self::Edn1FatalAlert), - 62 => Ok(Self::SramCtrlMainFatalError), - 63 => Ok(Self::SramCtrlSecFatalError), - 64 => Ok(Self::RomCtrlFatal), - 65 => Ok(Self::RvCoreIbexFatalSwErr), - 66 => Ok(Self::RvCoreIbexRecovSwErr), - 67 => Ok(Self::RvCoreIbexFatalHwErr), - 68 => Ok(Self::RvCoreIbexRecovHwErr), + 33 => Ok(Self::RramCtrlRecovErr), + 34 => Ok(Self::RramCtrlFatalStdErr), + 35 => Ok(Self::RramCtrlFatalErr), + 36 => Ok(Self::RramCtrlFatalMacroErr), + 37 => Ok(Self::RramCtrlRecovMacroErr), + 38 => Ok(Self::RvDmFatalFault), + 39 => Ok(Self::RvPlicFatalFault), + 40 => Ok(Self::AesRecovCtrlUpdateErr), + 41 => Ok(Self::AesFatalFault), + 42 => Ok(Self::HmacFatalFault), + 43 => Ok(Self::KmacRecovOperationErr), + 44 => Ok(Self::KmacFatalFaultErr), + 45 => Ok(Self::OtbnFatal), + 46 => Ok(Self::OtbnRecov), + 47 => Ok(Self::KeymgrDpeRecovOperationErr), + 48 => Ok(Self::KeymgrDpeFatalFaultErr), + 49 => Ok(Self::CsrngRecovAlert), + 50 => Ok(Self::CsrngFatalAlert), + 51 => Ok(Self::EntropySrcRecovAlert), + 52 => Ok(Self::EntropySrcFatalAlert), + 53 => Ok(Self::Edn0RecovAlert), + 54 => Ok(Self::Edn0FatalAlert), + 55 => Ok(Self::Edn1RecovAlert), + 56 => Ok(Self::Edn1FatalAlert), + 57 => Ok(Self::SramCtrlMainFatalError), + 58 => Ok(Self::SramCtrlSecFatalError), + 59 => Ok(Self::RomCtrlFatal), + 60 => Ok(Self::RvCoreIbexFatalSwErr), + 61 => Ok(Self::RvCoreIbexRecovSwErr), + 62 => Ok(Self::RvCoreIbexFatalHwErr), + 63 => Ok(Self::RvCoreIbexRecovHwErr), _ => Err(val), } } @@ -2120,7 +2036,7 @@ impl TryFrom for AlertId { /// /// This array is a mapping from `AlertId` to /// `AlertPeripheral`. -pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 69] = [ +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 64] = [ // Uart0FatalFault -> AlertPeripheral::Uart0 AlertPeripheral::Uart0, // Uart1FatalFault -> AlertPeripheral::Uart1 @@ -2187,16 +2103,6 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 69] = [ AlertPeripheral::SensorCtrl, // SramCtrlRetFatalError -> AlertPeripheral::SramCtrlRet AlertPeripheral::SramCtrlRet, - // FlashCtrlRecovErr -> AlertPeripheral::FlashCtrl - AlertPeripheral::FlashCtrl, - // FlashCtrlFatalStdErr -> AlertPeripheral::FlashCtrl - AlertPeripheral::FlashCtrl, - // FlashCtrlFatalErr -> AlertPeripheral::FlashCtrl - AlertPeripheral::FlashCtrl, - // FlashCtrlFatalPrimFlashAlert -> AlertPeripheral::FlashCtrl - AlertPeripheral::FlashCtrl, - // FlashCtrlRecovPrimFlashAlert -> AlertPeripheral::FlashCtrl - AlertPeripheral::FlashCtrl, // RramCtrlRecovErr -> AlertPeripheral::RramCtrl AlertPeripheral::RramCtrl, // RramCtrlFatalStdErr -> AlertPeripheral::RramCtrl @@ -2368,31 +2274,25 @@ pub enum PinmuxPeripheralIn { /// Peripheral Input 46 SpiDeviceTpmCsb = 46, /// Peripheral Input 47 - FlashCtrlTck = 47, + RramMacroTck = 47, /// Peripheral Input 48 - FlashCtrlTms = 48, + RramMacroTms = 48, /// Peripheral Input 49 - FlashCtrlTdi = 49, + RramMacroTdi = 49, /// Peripheral Input 50 - RramMacroTck = 50, + SysrstCtrlAcPresent = 50, /// Peripheral Input 51 - RramMacroTms = 51, + SysrstCtrlKey0In = 51, /// Peripheral Input 52 - RramMacroTdi = 52, + SysrstCtrlKey1In = 52, /// Peripheral Input 53 - SysrstCtrlAcPresent = 53, + SysrstCtrlKey2In = 53, /// Peripheral Input 54 - SysrstCtrlKey0In = 54, + SysrstCtrlPwrbIn = 54, /// Peripheral Input 55 - SysrstCtrlKey1In = 55, + SysrstCtrlLidOpen = 55, /// Peripheral Input 56 - SysrstCtrlKey2In = 56, - /// Peripheral Input 57 - SysrstCtrlPwrbIn = 57, - /// Peripheral Input 58 - SysrstCtrlLidOpen = 58, - /// Peripheral Input 59 - UsbdevSense = 59, + UsbdevSense = 56, } impl TryFrom for PinmuxPeripheralIn { @@ -2446,19 +2346,16 @@ impl TryFrom for PinmuxPeripheralIn { 44 => Ok(Self::Uart2Rx), 45 => Ok(Self::Uart3Rx), 46 => Ok(Self::SpiDeviceTpmCsb), - 47 => Ok(Self::FlashCtrlTck), - 48 => Ok(Self::FlashCtrlTms), - 49 => Ok(Self::FlashCtrlTdi), - 50 => Ok(Self::RramMacroTck), - 51 => Ok(Self::RramMacroTms), - 52 => Ok(Self::RramMacroTdi), - 53 => Ok(Self::SysrstCtrlAcPresent), - 54 => Ok(Self::SysrstCtrlKey0In), - 55 => Ok(Self::SysrstCtrlKey1In), - 56 => Ok(Self::SysrstCtrlKey2In), - 57 => Ok(Self::SysrstCtrlPwrbIn), - 58 => Ok(Self::SysrstCtrlLidOpen), - 59 => Ok(Self::UsbdevSense), + 47 => Ok(Self::RramMacroTck), + 48 => Ok(Self::RramMacroTms), + 49 => Ok(Self::RramMacroTdi), + 50 => Ok(Self::SysrstCtrlAcPresent), + 51 => Ok(Self::SysrstCtrlKey0In), + 52 => Ok(Self::SysrstCtrlKey1In), + 53 => Ok(Self::SysrstCtrlKey2In), + 54 => Ok(Self::SysrstCtrlPwrbIn), + 55 => Ok(Self::SysrstCtrlLidOpen), + 56 => Ok(Self::UsbdevSense), _ => Err(val), } } @@ -2889,39 +2786,37 @@ pub enum PinmuxOutsel { /// Peripheral Output 47 SpiHost1Csb = 50, /// Peripheral Output 48 - FlashCtrlTdo = 51, + RramMacroTdo = 51, /// Peripheral Output 49 - RramMacroTdo = 52, + SensorCtrlAstDebugOut0 = 52, /// Peripheral Output 50 - SensorCtrlAstDebugOut0 = 53, + SensorCtrlAstDebugOut1 = 53, /// Peripheral Output 51 - SensorCtrlAstDebugOut1 = 54, + SensorCtrlAstDebugOut2 = 54, /// Peripheral Output 52 - SensorCtrlAstDebugOut2 = 55, + SensorCtrlAstDebugOut3 = 55, /// Peripheral Output 53 - SensorCtrlAstDebugOut3 = 56, + SensorCtrlAstDebugOut4 = 56, /// Peripheral Output 54 - SensorCtrlAstDebugOut4 = 57, + SensorCtrlAstDebugOut5 = 57, /// Peripheral Output 55 - SensorCtrlAstDebugOut5 = 58, + SensorCtrlAstDebugOut6 = 58, /// Peripheral Output 56 - SensorCtrlAstDebugOut6 = 59, + SensorCtrlAstDebugOut7 = 59, /// Peripheral Output 57 - SensorCtrlAstDebugOut7 = 60, + SensorCtrlAstDebugOut8 = 60, /// Peripheral Output 58 - SensorCtrlAstDebugOut8 = 61, + SysrstCtrlBatDisable = 61, /// Peripheral Output 59 - SysrstCtrlBatDisable = 62, + SysrstCtrlKey0Out = 62, /// Peripheral Output 60 - SysrstCtrlKey0Out = 63, + SysrstCtrlKey1Out = 63, /// Peripheral Output 61 - SysrstCtrlKey1Out = 64, + SysrstCtrlKey2Out = 64, /// Peripheral Output 62 - SysrstCtrlKey2Out = 65, + SysrstCtrlPwrbOut = 65, /// Peripheral Output 63 - SysrstCtrlPwrbOut = 66, - /// Peripheral Output 64 - SysrstCtrlZ3Wakeup = 67, + SysrstCtrlZ3Wakeup = 66, } impl TryFrom for PinmuxOutsel { @@ -2979,23 +2874,22 @@ impl TryFrom for PinmuxOutsel { 48 => Ok(Self::Uart3Tx), 49 => Ok(Self::SpiHost1Sck), 50 => Ok(Self::SpiHost1Csb), - 51 => Ok(Self::FlashCtrlTdo), - 52 => Ok(Self::RramMacroTdo), - 53 => Ok(Self::SensorCtrlAstDebugOut0), - 54 => Ok(Self::SensorCtrlAstDebugOut1), - 55 => Ok(Self::SensorCtrlAstDebugOut2), - 56 => Ok(Self::SensorCtrlAstDebugOut3), - 57 => Ok(Self::SensorCtrlAstDebugOut4), - 58 => Ok(Self::SensorCtrlAstDebugOut5), - 59 => Ok(Self::SensorCtrlAstDebugOut6), - 60 => Ok(Self::SensorCtrlAstDebugOut7), - 61 => Ok(Self::SensorCtrlAstDebugOut8), - 62 => Ok(Self::SysrstCtrlBatDisable), - 63 => Ok(Self::SysrstCtrlKey0Out), - 64 => Ok(Self::SysrstCtrlKey1Out), - 65 => Ok(Self::SysrstCtrlKey2Out), - 66 => Ok(Self::SysrstCtrlPwrbOut), - 67 => Ok(Self::SysrstCtrlZ3Wakeup), + 51 => Ok(Self::RramMacroTdo), + 52 => Ok(Self::SensorCtrlAstDebugOut0), + 53 => Ok(Self::SensorCtrlAstDebugOut1), + 54 => Ok(Self::SensorCtrlAstDebugOut2), + 55 => Ok(Self::SensorCtrlAstDebugOut3), + 56 => Ok(Self::SensorCtrlAstDebugOut4), + 57 => Ok(Self::SensorCtrlAstDebugOut5), + 58 => Ok(Self::SensorCtrlAstDebugOut6), + 59 => Ok(Self::SensorCtrlAstDebugOut7), + 60 => Ok(Self::SensorCtrlAstDebugOut8), + 61 => Ok(Self::SysrstCtrlBatDisable), + 62 => Ok(Self::SysrstCtrlKey0Out), + 63 => Ok(Self::SysrstCtrlKey1Out), + 64 => Ok(Self::SysrstCtrlKey2Out), + 65 => Ok(Self::SysrstCtrlPwrbOut), + 66 => Ok(Self::SysrstCtrlZ3Wakeup), _ => Err(val), } } @@ -3227,7 +3121,7 @@ pub enum HintableClocks { /// MMIO Region /// /// MMIO region excludes any memory that is separate from the module -/// configuration space, i.e. ROM, main SRAM, and flash are excluded but +/// configuration space, i.e. ROM, main SRAM, and RRAM are excluded but /// retention SRAM, spi_device memory, or usbdev memory are included. pub const TOP_EARLGREY_MMIO_BASE_ADDR: usize = 0x40000000; pub const TOP_EARLGREY_MMIO_SIZE_BYTES: usize = 0x10000000; diff --git a/hw/top_earlgrey/sw/autogen/tests/BUILD b/hw/top_earlgrey/sw/autogen/tests/BUILD index 3e318702a17d3..2977f265b4e36 100644 --- a/hw/top_earlgrey/sw/autogen/tests/BUILD +++ b/hw/top_earlgrey/sw/autogen/tests/BUILD @@ -66,7 +66,6 @@ NR_IRQ_PERIPH_TESTS = 3 "//sw/device/lib/dif/autogen:csrng", "//sw/device/lib/dif/autogen:edn", "//sw/device/lib/dif/autogen:entropy_src", - "//sw/device/lib/dif/autogen:flash_ctrl", "//sw/device/lib/dif/autogen:gpio", "//sw/device/lib/dif/autogen:hmac", "//sw/device/lib/dif/autogen:i2c", @@ -126,7 +125,6 @@ opentitan_test( "//sw/device/lib/dif/autogen:csrng", "//sw/device/lib/dif/autogen:edn", "//sw/device/lib/dif/autogen:entropy_src", - "//sw/device/lib/dif/autogen:flash_ctrl", "//sw/device/lib/dif/autogen:gpio", "//sw/device/lib/dif/autogen:hmac", "//sw/device/lib/dif/autogen:i2c", diff --git a/hw/top_earlgrey/sw/autogen/tests/alert_test.c b/hw/top_earlgrey/sw/autogen/tests/alert_test.c index dc5bb2ad134e0..6082ad64bd0d4 100644 --- a/hw/top_earlgrey/sw/autogen/tests/alert_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/alert_test.c @@ -18,7 +18,6 @@ #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" #include "sw/device/lib/dif/autogen/dif_edn_autogen.h" #include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h" -#include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_gpio_autogen.h" #include "sw/device/lib/dif/autogen/dif_hmac_autogen.h" #include "sw/device/lib/dif/autogen/dif_i2c_autogen.h" @@ -61,7 +60,6 @@ static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_entropy_src_t entropy_src; -static dif_flash_ctrl_t flash_ctrl; static dif_gpio_t gpio; static dif_hmac_t hmac; static dif_i2c_t i2c0; @@ -126,9 +124,6 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR); CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); - CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); @@ -400,21 +395,6 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } - // Write flash_ctrl's alert_test reg and check alert_cause. - for (dif_flash_ctrl_alert_t i = 0; i < 5; ++i) { - CHECK_DIF_OK(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr + i)); - - // Verify that alert handler received it. - exp_alert = (int)kTopEarlgreyAlertIdFlashCtrlRecovErr + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - // Write gpio's alert_test reg and check alert_cause. for (dif_gpio_alert_t i = 0; i < 1; ++i) { CHECK_DIF_OK(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault + i)); diff --git a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c index f1c96dcb14d3b..320dc62748eed 100644 --- a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c @@ -22,7 +22,7 @@ #endif #ifndef TEST_MAX_IRQ_PERIPHERAL -#define TEST_MAX_IRQ_PERIPHERAL 23 +#define TEST_MAX_IRQ_PERIPHERAL 22 #endif #include "sw/device/lib/arch/boot_stage.h" @@ -34,7 +34,6 @@ #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" #include "sw/device/lib/dif/autogen/dif_edn_autogen.h" #include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h" -#include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_gpio_autogen.h" #include "sw/device/lib/dif/autogen/dif_hmac_autogen.h" #include "sw/device/lib/dif/autogen/dif_i2c_autogen.h" @@ -91,94 +90,90 @@ static dif_entropy_src_t entropy_src; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL -static dif_flash_ctrl_t flash_ctrl; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static dif_gpio_t gpio; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static dif_hmac_t hmac; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c2; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static dif_keymgr_dpe_t keymgr_dpe; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static dif_kmac_t kmac; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL static dif_otbn_t otbn; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_otp_ctrl_t otp_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL static dif_pwrmgr_t pwrmgr; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL static dif_rram_ctrl_t rram_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL static dif_rv_timer_t rv_timer; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL static dif_sensor_ctrl_t sensor_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_device_t spi_device; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_host_t spi_host0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_host_t spi_host1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL static dif_sysrst_ctrl_t sysrst_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart2; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart3; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static dif_usbdev_t usbdev; #endif @@ -232,86 +227,81 @@ static volatile dif_entropy_src_irq_t entropy_src_irq_serviced; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_expected; -static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_serviced; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_gpio_irq_t gpio_irq_expected; static volatile dif_gpio_irq_t gpio_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_hmac_irq_t hmac_irq_expected; static volatile dif_hmac_irq_t hmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_i2c_irq_t i2c_irq_expected; static volatile dif_i2c_irq_t i2c_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_expected; static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_kmac_irq_t kmac_irq_expected; static volatile dif_kmac_irq_t kmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_otbn_irq_t otbn_irq_expected; static volatile dif_otbn_irq_t otbn_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected; static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_pwrmgr_irq_t pwrmgr_irq_expected; static volatile dif_pwrmgr_irq_t pwrmgr_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_rram_ctrl_irq_t rram_ctrl_irq_expected; static volatile dif_rram_ctrl_irq_t rram_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_rv_timer_irq_t rv_timer_irq_expected; static volatile dif_rv_timer_irq_t rv_timer_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_expected; static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_device_irq_t spi_device_irq_expected; static volatile dif_spi_device_irq_t spi_device_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_host_irq_t spi_host_irq_expected; static volatile dif_spi_host_irq_t spi_host_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_expected; static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_uart_irq_t uart_irq_expected; static volatile dif_uart_irq_t uart_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_usbdev_irq_t usbdev_irq_expected; static volatile dif_usbdev_irq_t usbdev_irq_serviced; #endif @@ -515,42 +505,6 @@ void ottf_external_isr(uint32_t *exc_info) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralFlashCtrl: { - dif_flash_ctrl_irq_t irq = - (dif_flash_ctrl_irq_t)(plic_irq_id - - (dif_rv_plic_irq_id_t) - kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty); - CHECK(irq == flash_ctrl_irq_expected, - "Incorrect flash_ctrl IRQ triggered: exp = %d, obs = %d", - flash_ctrl_irq_expected, irq); - flash_ctrl_irq_serviced = irq; - - dif_flash_ctrl_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_flash_ctrl_irq_get_state(&flash_ctrl, &snapshot)); - CHECK(snapshot == (dif_flash_ctrl_irq_state_snapshot_t)((1 << irq) | 0x3), - "Expected flash_ctrl interrupt status %x. Actual interrupt " - "status = %x", - (1 << irq) | 0x3, snapshot); - - if (0xf & (1 << irq)) { - // We do not acknowledge status type interrupt at the IP side, but we - // need to clear the test force register. - CHECK_DIF_OK(dif_flash_ctrl_irq_force(&flash_ctrl, irq, false)); - // In case this status interrupt is asserted by default, we also - // disable it at this point so that it does not interfere with the - // rest of the test. - if ((0x3 & (1 << irq))) { - CHECK_DIF_OK(dif_flash_ctrl_irq_set_enabled(&flash_ctrl, irq, false)); - } - } else { - // We acknowledge event type interrupt. - CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge(&flash_ctrl, irq)); - } - break; - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralGpio: { dif_gpio_irq_t irq = (dif_gpio_irq_t)(plic_irq_id - @@ -573,7 +527,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralHmac: { dif_hmac_irq_t irq = (dif_hmac_irq_t)(plic_irq_id - @@ -609,7 +563,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c0: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -645,7 +599,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c1: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -681,7 +635,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c2: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -717,7 +671,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralKeymgrDpe: { dif_keymgr_dpe_irq_t irq = (dif_keymgr_dpe_irq_t)(plic_irq_id - @@ -740,7 +694,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralKmac: { dif_kmac_irq_t irq = (dif_kmac_irq_t)(plic_irq_id - @@ -776,7 +730,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralOtbn: { dif_otbn_irq_t irq = (dif_otbn_irq_t)(plic_irq_id - @@ -799,7 +753,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralOtpCtrl: { dif_otp_ctrl_irq_t irq = (dif_otp_ctrl_irq_t)(plic_irq_id - @@ -822,7 +776,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralPwrmgr: { dif_pwrmgr_irq_t irq = (dif_pwrmgr_irq_t)(plic_irq_id - @@ -845,7 +799,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralRramCtrl: { dif_rram_ctrl_irq_t irq = (dif_rram_ctrl_irq_t)(plic_irq_id - @@ -881,7 +835,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralRvTimer: { dif_rv_timer_irq_t irq = (dif_rv_timer_irq_t)(plic_irq_id - @@ -904,7 +858,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSensorCtrl: { dif_sensor_ctrl_irq_t irq = (dif_sensor_ctrl_irq_t)(plic_irq_id - @@ -927,7 +881,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiDevice: { dif_spi_device_irq_t irq = (dif_spi_device_irq_t)(plic_irq_id - @@ -963,7 +917,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiHost0: { dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(plic_irq_id - @@ -999,7 +953,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiHost1: { dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(plic_irq_id - @@ -1035,7 +989,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSysrstCtrl: { dif_sysrst_ctrl_irq_t irq = (dif_sysrst_ctrl_irq_t)(plic_irq_id - @@ -1071,7 +1025,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart0: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1107,7 +1061,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart1: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1143,7 +1097,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart2: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1179,7 +1133,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart3: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1215,7 +1169,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUsbdev: { dif_usbdev_irq_t irq = (dif_usbdev_irq_t)(plic_irq_id - @@ -1301,116 +1255,111 @@ static void peripherals_init(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); - CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR); CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C0_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR); CHECK_DIF_OK(dif_keymgr_dpe_init(base_addr, &keymgr_dpe)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR); CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_PWRMGR_BASE_ADDR); CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_rram_ctrl_init(base_addr, &rram_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR); CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR); CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR); CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST0_BASE_ADDR); CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR); CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR); CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART2_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART3_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_USBDEV_BASE_ADDR); CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev)); #endif @@ -1452,96 +1401,92 @@ static void peripheral_irqs_clear(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_keymgr_dpe_irq_acknowledge_all(&keymgr_dpe)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL if (kBootStage != kBootStageOwner) { CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl)); } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge_all(&rram_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer, kHart)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge_all(&sensor_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev)); #endif } @@ -1576,55 +1521,46 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - // Note: this peripheral contains status interrupts that are asserted by - // default. Therefore, not all interrupts are enabled here, since that - // would interfere with this test. Instead, these interrupts are enabled on - // demand once they are being tested. - dif_flash_ctrl_irq_state_snapshot_t flash_ctrl_irqs = - (dif_flash_ctrl_irq_state_snapshot_t)0xfffffffc; -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL dif_gpio_irq_state_snapshot_t gpio_irqs = (dif_gpio_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL dif_hmac_irq_state_snapshot_t hmac_irqs = (dif_hmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL dif_i2c_irq_state_snapshot_t i2c_irqs = (dif_i2c_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL dif_keymgr_dpe_irq_state_snapshot_t keymgr_dpe_irqs = (dif_keymgr_dpe_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL dif_kmac_irq_state_snapshot_t kmac_irqs = (dif_kmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL dif_otbn_irq_state_snapshot_t otbn_irqs = (dif_otbn_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs = (dif_otp_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL dif_pwrmgr_irq_state_snapshot_t pwrmgr_irqs = (dif_pwrmgr_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL // Note: this peripheral contains status interrupts that are asserted by // default. Therefore, not all interrupts are enabled here, since that // would interfere with this test. Instead, these interrupts are enabled on @@ -1633,32 +1569,32 @@ static void peripheral_irqs_enable(void) { (dif_rram_ctrl_irq_state_snapshot_t)0xfffffffc; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL dif_rv_timer_irq_state_snapshot_t rv_timer_irqs = (dif_rv_timer_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL dif_sensor_ctrl_irq_state_snapshot_t sensor_ctrl_irqs = (dif_sensor_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL dif_spi_device_irq_state_snapshot_t spi_device_irqs = (dif_spi_device_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL dif_spi_host_irq_state_snapshot_t spi_host_irqs = (dif_spi_host_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL dif_sysrst_ctrl_irq_state_snapshot_t sysrst_ctrl_irqs = (dif_sysrst_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL // Note: this peripheral contains status interrupts that are asserted by // default. Therefore, not all interrupts are enabled here, since that // would interfere with this test. Instead, these interrupts are enabled on @@ -1667,7 +1603,7 @@ static void peripheral_irqs_enable(void) { (dif_uart_irq_state_snapshot_t)0xfffffefe; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL dif_usbdev_irq_state_snapshot_t usbdev_irqs = (dif_usbdev_irq_state_snapshot_t)0xffffffff; #endif @@ -1697,80 +1633,76 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_flash_ctrl_irq_restore_all(&flash_ctrl, &flash_ctrl_irqs)); -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_restore_all(&hmac, &hmac_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c0, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c1, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c2, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_keymgr_dpe_irq_restore_all(&keymgr_dpe, &keymgr_dpe_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_otbn_irq_restore_all(&otbn, &otbn_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL if (kBootStage != kBootStageOwner) { CHECK_DIF_OK(dif_otp_ctrl_irq_restore_all(&otp_ctrl, &otp_ctrl_irqs)); } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_pwrmgr_irq_restore_all(&pwrmgr, &pwrmgr_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_rram_ctrl_irq_restore_all(&rram_ctrl, &rram_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_rv_timer_irq_restore_all(&rv_timer, kHart, &rv_timer_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sensor_ctrl_irq_restore_all(&sensor_ctrl, &sensor_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_restore_all(&spi_host0, &spi_host_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_restore_all(&spi_host1, &spi_host_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl, &sysrst_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. if (kDeviceType == kDeviceSimDV) { @@ -1778,19 +1710,19 @@ static void peripheral_irqs_enable(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart1, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart2, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart3, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_usbdev_irq_restore_all(&usbdev, &usbdev_irqs)); #endif } @@ -1932,30 +1864,6 @@ static void peripheral_irqs_trigger(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralFlashCtrl; - status_default_mask = 0x3; - for (dif_flash_ctrl_irq_t irq = kDifFlashCtrlIrqProgEmpty; irq <= kDifFlashCtrlIrqCorrErr; - ++irq) { - flash_ctrl_irq_expected = irq; - LOG_INFO("Triggering flash_ctrl IRQ %d.", irq); - CHECK_DIF_OK(dif_flash_ctrl_irq_force(&flash_ctrl, irq, true)); - - // In this case, the interrupt has not been enabled yet because that would - // interfere with testing other interrupts. We enable it here and let the - // interrupt handler disable it again. - if ((status_default_mask & 0x1)) { - CHECK_DIF_OK(dif_flash_ctrl_irq_set_enabled(&flash_ctrl, irq, true)); - } - status_default_mask >>= 1; - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(flash_ctrl_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from flash_ctrl is serviced.", irq); - } -#endif - -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralGpio; for (dif_gpio_irq_t irq = kDifGpioIrqGpio0; irq <= kDifGpioIrqGpio31; ++irq) { @@ -1970,7 +1878,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralHmac; status_default_mask = 0x0; for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone; irq <= kDifHmacIrqHmacErr; @@ -1994,7 +1902,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c0; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2018,7 +1926,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c1; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2042,7 +1950,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c2; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2066,7 +1974,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralKeymgrDpe; for (dif_keymgr_dpe_irq_t irq = kDifKeymgrDpeIrqOpDone; irq <= kDifKeymgrDpeIrqOpDone; ++irq) { @@ -2081,7 +1989,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralKmac; status_default_mask = 0x0; for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone; irq <= kDifKmacIrqKmacErr; @@ -2105,7 +2013,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralOtbn; for (dif_otbn_irq_t irq = kDifOtbnIrqDone; irq <= kDifOtbnIrqDone; ++irq) { @@ -2120,7 +2028,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL // Skip OTP_CTRL in boot stage owner since ROM_EXT configures all accesses // to OTP_CTRL and AST to be illegal. if (kBootStage != kBootStageOwner) { @@ -2139,7 +2047,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralPwrmgr; for (dif_pwrmgr_irq_t irq = kDifPwrmgrIrqWakeup; irq <= kDifPwrmgrIrqWakeup; ++irq) { @@ -2154,7 +2062,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralRramCtrl; status_default_mask = 0x3; for (dif_rram_ctrl_irq_t irq = kDifRramCtrlIrqWrEmpty; irq <= kDifRramCtrlIrqCorrErr; @@ -2178,7 +2086,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralRvTimer; for (dif_rv_timer_irq_t irq = kDifRvTimerIrqTimerExpiredHart0Timer0; irq <= kDifRvTimerIrqTimerExpiredHart0Timer0; ++irq) { @@ -2193,7 +2101,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSensorCtrl; for (dif_sensor_ctrl_irq_t irq = kDifSensorCtrlIrqIoStatusChange; irq <= kDifSensorCtrlIrqInitStatusChange; ++irq) { @@ -2208,7 +2116,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiDevice; status_default_mask = 0x0; for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqUploadCmdfifoNotEmpty; irq <= kDifSpiDeviceIrqTpmRdfifoDrop; @@ -2232,7 +2140,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost0; status_default_mask = 0x0; for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; @@ -2256,7 +2164,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost1; status_default_mask = 0x0; for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; @@ -2280,7 +2188,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSysrstCtrl; status_default_mask = 0x0; for (dif_sysrst_ctrl_irq_t irq = kDifSysrstCtrlIrqEventDetected; irq <= kDifSysrstCtrlIrqEventDetected; @@ -2304,7 +2212,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. @@ -2335,7 +2243,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart1; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2359,7 +2267,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart2; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2383,7 +2291,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart3; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2407,7 +2315,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUsbdev; status_default_mask = 0x0; for (dif_usbdev_irq_t irq = kDifUsbdevIrqPktReceived; irq <= kDifUsbdevIrqAvSetupEmpty; diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index cbf5c16f3b616..99ff2b4ddf046 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -16,7 +16,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[69] = { + top_earlgrey_alert_for_peripheral[64] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -50,11 +50,6 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdSensorCtrlRecovAlert] = kTopEarlgreyAlertPeripheralSensorCtrl, [kTopEarlgreyAlertIdSensorCtrlFatalAlert] = kTopEarlgreyAlertPeripheralSensorCtrl, [kTopEarlgreyAlertIdSramCtrlRetFatalError] = kTopEarlgreyAlertPeripheralSramCtrlRet, - [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl, - [kTopEarlgreyAlertIdFlashCtrlFatalStdErr] = kTopEarlgreyAlertPeripheralFlashCtrl, - [kTopEarlgreyAlertIdFlashCtrlFatalErr] = kTopEarlgreyAlertPeripheralFlashCtrl, - [kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl, - [kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdRramCtrlRecovErr] = kTopEarlgreyAlertPeripheralRramCtrl, [kTopEarlgreyAlertIdRramCtrlFatalStdErr] = kTopEarlgreyAlertPeripheralRramCtrl, [kTopEarlgreyAlertIdRramCtrlFatalErr] = kTopEarlgreyAlertPeripheralRramCtrl, @@ -95,7 +90,7 @@ const top_earlgrey_alert_peripheral_t * `top_earlgrey_plic_peripheral_t`. */ const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[190] = { + top_earlgrey_plic_interrupt_for_peripheral[184] = { [kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown, [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0, [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0, @@ -254,12 +249,6 @@ const top_earlgrey_plic_peripheral_t [kTopEarlgreyPlicIrqIdAonTimerWdogTimerBark] = kTopEarlgreyPlicPeripheralAonTimer, [kTopEarlgreyPlicIrqIdSensorCtrlIoStatusChange] = kTopEarlgreyPlicPeripheralSensorCtrl, [kTopEarlgreyPlicIrqIdSensorCtrlInitStatusChange] = kTopEarlgreyPlicPeripheralSensorCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty] = kTopEarlgreyPlicPeripheralFlashCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlProgLvl] = kTopEarlgreyPlicPeripheralFlashCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlRdFull] = kTopEarlgreyPlicPeripheralFlashCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl, - [kTopEarlgreyPlicIrqIdFlashCtrlCorrErr] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdRramCtrlWrEmpty] = kTopEarlgreyPlicPeripheralRramCtrl, [kTopEarlgreyPlicIrqIdRramCtrlWrLvl] = kTopEarlgreyPlicPeripheralRramCtrl, [kTopEarlgreyPlicIrqIdRramCtrlRdFull] = kTopEarlgreyPlicPeripheralRramCtrl, diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 70d8d6a1b968c..55210eead79b1 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -498,42 +498,6 @@ extern "C" { */ #define TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES 0x40u -/** - * Peripheral base address for core device on flash_ctrl in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u - -/** - * Peripheral size for core device on flash_ctrl in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES`. - */ -#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u - -/** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u - -/** - * Peripheral size for prim device on flash_ctrl in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`. - */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u - /** * Peripheral base address for core device on rram_ctrl in top earlgrey. * @@ -869,16 +833,6 @@ extern "C" { */ #define TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES 0x1000u -/** - * Memory base address for mem memory on flash_ctrl in top earlgrey. - */ -#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u - -/** - * Memory size for mem memory on flash_ctrl in top earlgrey. - */ -#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u - /** * Memory base address for host memory on rram_ctrl in top earlgrey. */ @@ -948,17 +902,16 @@ typedef enum top_earlgrey_plic_peripheral { kTopEarlgreyPlicPeripheralAdcCtrl = 18, /**< adc_ctrl */ kTopEarlgreyPlicPeripheralAonTimer = 19, /**< aon_timer */ kTopEarlgreyPlicPeripheralSensorCtrl = 20, /**< sensor_ctrl */ - kTopEarlgreyPlicPeripheralFlashCtrl = 21, /**< flash_ctrl */ - kTopEarlgreyPlicPeripheralRramCtrl = 22, /**< rram_ctrl */ - kTopEarlgreyPlicPeripheralHmac = 23, /**< hmac */ - kTopEarlgreyPlicPeripheralKmac = 24, /**< kmac */ - kTopEarlgreyPlicPeripheralOtbn = 25, /**< otbn */ - kTopEarlgreyPlicPeripheralKeymgrDpe = 26, /**< keymgr_dpe */ - kTopEarlgreyPlicPeripheralCsrng = 27, /**< csrng */ - kTopEarlgreyPlicPeripheralEntropySrc = 28, /**< entropy_src */ - kTopEarlgreyPlicPeripheralEdn0 = 29, /**< edn0 */ - kTopEarlgreyPlicPeripheralEdn1 = 30, /**< edn1 */ - kTopEarlgreyPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */ + kTopEarlgreyPlicPeripheralRramCtrl = 21, /**< rram_ctrl */ + kTopEarlgreyPlicPeripheralHmac = 22, /**< hmac */ + kTopEarlgreyPlicPeripheralKmac = 23, /**< kmac */ + kTopEarlgreyPlicPeripheralOtbn = 24, /**< otbn */ + kTopEarlgreyPlicPeripheralKeymgrDpe = 25, /**< keymgr_dpe */ + kTopEarlgreyPlicPeripheralCsrng = 26, /**< csrng */ + kTopEarlgreyPlicPeripheralEntropySrc = 27, /**< entropy_src */ + kTopEarlgreyPlicPeripheralEdn0 = 28, /**< edn0 */ + kTopEarlgreyPlicPeripheralEdn1 = 29, /**< edn1 */ + kTopEarlgreyPlicPeripheralLast = 29, /**< \internal Final PLIC peripheral */ } top_earlgrey_plic_peripheral_t; /** @@ -1126,39 +1079,33 @@ typedef enum top_earlgrey_plic_irq_id { kTopEarlgreyPlicIrqIdAonTimerWdogTimerBark = 155, /**< aon_timer_wdog_timer_bark */ kTopEarlgreyPlicIrqIdSensorCtrlIoStatusChange = 156, /**< sensor_ctrl_io_status_change */ kTopEarlgreyPlicIrqIdSensorCtrlInitStatusChange = 157, /**< sensor_ctrl_init_status_change */ - kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 158, /**< flash_ctrl_prog_empty */ - kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 159, /**< flash_ctrl_prog_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 160, /**< flash_ctrl_rd_full */ - kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 161, /**< flash_ctrl_rd_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 162, /**< flash_ctrl_op_done */ - kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 163, /**< flash_ctrl_corr_err */ - kTopEarlgreyPlicIrqIdRramCtrlWrEmpty = 164, /**< rram_ctrl_wr_empty */ - kTopEarlgreyPlicIrqIdRramCtrlWrLvl = 165, /**< rram_ctrl_wr_lvl */ - kTopEarlgreyPlicIrqIdRramCtrlRdFull = 166, /**< rram_ctrl_rd_full */ - kTopEarlgreyPlicIrqIdRramCtrlRdLvl = 167, /**< rram_ctrl_rd_lvl */ - kTopEarlgreyPlicIrqIdRramCtrlOpDone = 168, /**< rram_ctrl_op_done */ - kTopEarlgreyPlicIrqIdRramCtrlCorrErr = 169, /**< rram_ctrl_corr_err */ - kTopEarlgreyPlicIrqIdHmacHmacDone = 170, /**< hmac_hmac_done */ - kTopEarlgreyPlicIrqIdHmacFifoEmpty = 171, /**< hmac_fifo_empty */ - kTopEarlgreyPlicIrqIdHmacHmacErr = 172, /**< hmac_hmac_err */ - kTopEarlgreyPlicIrqIdKmacKmacDone = 173, /**< kmac_kmac_done */ - kTopEarlgreyPlicIrqIdKmacFifoEmpty = 174, /**< kmac_fifo_empty */ - kTopEarlgreyPlicIrqIdKmacKmacErr = 175, /**< kmac_kmac_err */ - kTopEarlgreyPlicIrqIdOtbnDone = 176, /**< otbn_done */ - kTopEarlgreyPlicIrqIdKeymgrDpeOpDone = 177, /**< keymgr_dpe_op_done */ - kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 178, /**< csrng_cs_cmd_req_done */ - kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 179, /**< csrng_cs_entropy_req */ - kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 180, /**< csrng_cs_hw_inst_exc */ - kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 181, /**< csrng_cs_fatal_err */ - kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 182, /**< entropy_src_es_entropy_valid */ - kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 183, /**< entropy_src_es_health_test_failed */ - kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 184, /**< entropy_src_es_observe_fifo_ready */ - kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 185, /**< entropy_src_es_fatal_err */ - kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 186, /**< edn0_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 187, /**< edn0_edn_fatal_err */ - kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 188, /**< edn1_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 189, /**< edn1_edn_fatal_err */ - kTopEarlgreyPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */ + kTopEarlgreyPlicIrqIdRramCtrlWrEmpty = 158, /**< rram_ctrl_wr_empty */ + kTopEarlgreyPlicIrqIdRramCtrlWrLvl = 159, /**< rram_ctrl_wr_lvl */ + kTopEarlgreyPlicIrqIdRramCtrlRdFull = 160, /**< rram_ctrl_rd_full */ + kTopEarlgreyPlicIrqIdRramCtrlRdLvl = 161, /**< rram_ctrl_rd_lvl */ + kTopEarlgreyPlicIrqIdRramCtrlOpDone = 162, /**< rram_ctrl_op_done */ + kTopEarlgreyPlicIrqIdRramCtrlCorrErr = 163, /**< rram_ctrl_corr_err */ + kTopEarlgreyPlicIrqIdHmacHmacDone = 164, /**< hmac_hmac_done */ + kTopEarlgreyPlicIrqIdHmacFifoEmpty = 165, /**< hmac_fifo_empty */ + kTopEarlgreyPlicIrqIdHmacHmacErr = 166, /**< hmac_hmac_err */ + kTopEarlgreyPlicIrqIdKmacKmacDone = 167, /**< kmac_kmac_done */ + kTopEarlgreyPlicIrqIdKmacFifoEmpty = 168, /**< kmac_fifo_empty */ + kTopEarlgreyPlicIrqIdKmacKmacErr = 169, /**< kmac_kmac_err */ + kTopEarlgreyPlicIrqIdOtbnDone = 170, /**< otbn_done */ + kTopEarlgreyPlicIrqIdKeymgrDpeOpDone = 171, /**< keymgr_dpe_op_done */ + kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 172, /**< csrng_cs_cmd_req_done */ + kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 173, /**< csrng_cs_entropy_req */ + kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 174, /**< csrng_cs_hw_inst_exc */ + kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 175, /**< csrng_cs_fatal_err */ + kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 176, /**< entropy_src_es_entropy_valid */ + kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 177, /**< entropy_src_es_health_test_failed */ + kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 178, /**< entropy_src_es_observe_fifo_ready */ + kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 179, /**< entropy_src_es_fatal_err */ + kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 180, /**< edn0_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 181, /**< edn0_edn_fatal_err */ + kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 182, /**< edn1_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 183, /**< edn1_edn_fatal_err */ + kTopEarlgreyPlicIrqIdLast = 183, /**< \internal The Last Valid Interrupt ID. */ } top_earlgrey_plic_irq_id_t; /** @@ -1168,7 +1115,7 @@ typedef enum top_earlgrey_plic_irq_id { * `top_earlgrey_plic_peripheral_t`. */ extern const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[190]; + top_earlgrey_plic_interrupt_for_peripheral[184]; /** * PLIC Interrupt Target. @@ -1214,24 +1161,23 @@ typedef enum top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralAonTimer = 22, /**< aon_timer */ kTopEarlgreyAlertPeripheralSensorCtrl = 23, /**< sensor_ctrl */ kTopEarlgreyAlertPeripheralSramCtrlRet = 24, /**< sram_ctrl_ret */ - kTopEarlgreyAlertPeripheralFlashCtrl = 25, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralRramCtrl = 26, /**< rram_ctrl */ - kTopEarlgreyAlertPeripheralRvDm = 27, /**< rv_dm */ - kTopEarlgreyAlertPeripheralRvPlic = 28, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 29, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 30, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 31, /**< kmac */ - kTopEarlgreyAlertPeripheralOtbn = 32, /**< otbn */ - kTopEarlgreyAlertPeripheralKeymgrDpe = 33, /**< keymgr_dpe */ - kTopEarlgreyAlertPeripheralCsrng = 34, /**< csrng */ - kTopEarlgreyAlertPeripheralEntropySrc = 35, /**< entropy_src */ - kTopEarlgreyAlertPeripheralEdn0 = 36, /**< edn0 */ - kTopEarlgreyAlertPeripheralEdn1 = 37, /**< edn1 */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralSramCtrlSec = 39, /**< sram_ctrl_sec */ - kTopEarlgreyAlertPeripheralRomCtrl = 40, /**< rom_ctrl */ - kTopEarlgreyAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */ - kTopEarlgreyAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralRramCtrl = 25, /**< rram_ctrl */ + kTopEarlgreyAlertPeripheralRvDm = 26, /**< rv_dm */ + kTopEarlgreyAlertPeripheralRvPlic = 27, /**< rv_plic */ + kTopEarlgreyAlertPeripheralAes = 28, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 29, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 30, /**< kmac */ + kTopEarlgreyAlertPeripheralOtbn = 31, /**< otbn */ + kTopEarlgreyAlertPeripheralKeymgrDpe = 32, /**< keymgr_dpe */ + kTopEarlgreyAlertPeripheralCsrng = 33, /**< csrng */ + kTopEarlgreyAlertPeripheralEntropySrc = 34, /**< entropy_src */ + kTopEarlgreyAlertPeripheralEdn0 = 35, /**< edn0 */ + kTopEarlgreyAlertPeripheralEdn1 = 36, /**< edn1 */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 37, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralSramCtrlSec = 38, /**< sram_ctrl_sec */ + kTopEarlgreyAlertPeripheralRomCtrl = 39, /**< rom_ctrl */ + kTopEarlgreyAlertPeripheralRvCoreIbex = 40, /**< rv_core_ibex */ + kTopEarlgreyAlertPeripheralLast = 40, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1274,43 +1220,38 @@ typedef enum top_earlgrey_alert_id { kTopEarlgreyAlertIdSensorCtrlRecovAlert = 30, /**< sensor_ctrl_recov_alert */ kTopEarlgreyAlertIdSensorCtrlFatalAlert = 31, /**< sensor_ctrl_fatal_alert */ kTopEarlgreyAlertIdSramCtrlRetFatalError = 32, /**< sram_ctrl_ret_fatal_error */ - kTopEarlgreyAlertIdFlashCtrlRecovErr = 33, /**< flash_ctrl_recov_err */ - kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 34, /**< flash_ctrl_fatal_std_err */ - kTopEarlgreyAlertIdFlashCtrlFatalErr = 35, /**< flash_ctrl_fatal_err */ - kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 36, /**< flash_ctrl_fatal_prim_flash_alert */ - kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 37, /**< flash_ctrl_recov_prim_flash_alert */ - kTopEarlgreyAlertIdRramCtrlRecovErr = 38, /**< rram_ctrl_recov_err */ - kTopEarlgreyAlertIdRramCtrlFatalStdErr = 39, /**< rram_ctrl_fatal_std_err */ - kTopEarlgreyAlertIdRramCtrlFatalErr = 40, /**< rram_ctrl_fatal_err */ - kTopEarlgreyAlertIdRramCtrlFatalMacroErr = 41, /**< rram_ctrl_fatal_macro_err */ - kTopEarlgreyAlertIdRramCtrlRecovMacroErr = 42, /**< rram_ctrl_recov_macro_err */ - kTopEarlgreyAlertIdRvDmFatalFault = 43, /**< rv_dm_fatal_fault */ - kTopEarlgreyAlertIdRvPlicFatalFault = 44, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 45, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 46, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 47, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacRecovOperationErr = 48, /**< kmac_recov_operation_err */ - kTopEarlgreyAlertIdKmacFatalFaultErr = 49, /**< kmac_fatal_fault_err */ - kTopEarlgreyAlertIdOtbnFatal = 50, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 51, /**< otbn_recov */ - kTopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 52, /**< keymgr_dpe_recov_operation_err */ - kTopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 53, /**< keymgr_dpe_fatal_fault_err */ - kTopEarlgreyAlertIdCsrngRecovAlert = 54, /**< csrng_recov_alert */ - kTopEarlgreyAlertIdCsrngFatalAlert = 55, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 56, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 57, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0RecovAlert = 58, /**< edn0_recov_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 59, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1RecovAlert = 60, /**< edn1_recov_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 61, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalError = 62, /**< sram_ctrl_main_fatal_error */ - kTopEarlgreyAlertIdSramCtrlSecFatalError = 63, /**< sram_ctrl_sec_fatal_error */ - kTopEarlgreyAlertIdRomCtrlFatal = 64, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 65, /**< rv_core_ibex_fatal_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 66, /**< rv_core_ibex_recov_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 67, /**< rv_core_ibex_fatal_hw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 68, /**< rv_core_ibex_recov_hw_err */ - kTopEarlgreyAlertIdLast = 68, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdRramCtrlRecovErr = 33, /**< rram_ctrl_recov_err */ + kTopEarlgreyAlertIdRramCtrlFatalStdErr = 34, /**< rram_ctrl_fatal_std_err */ + kTopEarlgreyAlertIdRramCtrlFatalErr = 35, /**< rram_ctrl_fatal_err */ + kTopEarlgreyAlertIdRramCtrlFatalMacroErr = 36, /**< rram_ctrl_fatal_macro_err */ + kTopEarlgreyAlertIdRramCtrlRecovMacroErr = 37, /**< rram_ctrl_recov_macro_err */ + kTopEarlgreyAlertIdRvDmFatalFault = 38, /**< rv_dm_fatal_fault */ + kTopEarlgreyAlertIdRvPlicFatalFault = 39, /**< rv_plic_fatal_fault */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 40, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 41, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 42, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacRecovOperationErr = 43, /**< kmac_recov_operation_err */ + kTopEarlgreyAlertIdKmacFatalFaultErr = 44, /**< kmac_fatal_fault_err */ + kTopEarlgreyAlertIdOtbnFatal = 45, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 46, /**< otbn_recov */ + kTopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 47, /**< keymgr_dpe_recov_operation_err */ + kTopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 48, /**< keymgr_dpe_fatal_fault_err */ + kTopEarlgreyAlertIdCsrngRecovAlert = 49, /**< csrng_recov_alert */ + kTopEarlgreyAlertIdCsrngFatalAlert = 50, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 51, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 52, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0RecovAlert = 53, /**< edn0_recov_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 54, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1RecovAlert = 55, /**< edn1_recov_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 56, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalError = 57, /**< sram_ctrl_main_fatal_error */ + kTopEarlgreyAlertIdSramCtrlSecFatalError = 58, /**< sram_ctrl_sec_fatal_error */ + kTopEarlgreyAlertIdRomCtrlFatal = 59, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 60, /**< rv_core_ibex_fatal_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 61, /**< rv_core_ibex_recov_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 62, /**< rv_core_ibex_fatal_hw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 63, /**< rv_core_ibex_recov_hw_err */ + kTopEarlgreyAlertIdLast = 63, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1320,7 +1261,7 @@ typedef enum top_earlgrey_alert_id { * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[69]; + top_earlgrey_alert_for_peripheral[64]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 @@ -1382,20 +1323,17 @@ typedef enum top_earlgrey_pinmux_peripheral_in { kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */ kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */ kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 46, /**< Peripheral Input 46 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */ - kTopEarlgreyPinmuxPeripheralInRramMacroTck = 50, /**< Peripheral Input 50 */ - kTopEarlgreyPinmuxPeripheralInRramMacroTms = 51, /**< Peripheral Input 51 */ - kTopEarlgreyPinmuxPeripheralInRramMacroTdi = 52, /**< Peripheral Input 52 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 53, /**< Peripheral Input 53 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 54, /**< Peripheral Input 54 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 55, /**< Peripheral Input 55 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 56, /**< Peripheral Input 56 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 57, /**< Peripheral Input 57 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 58, /**< Peripheral Input 58 */ - kTopEarlgreyPinmuxPeripheralInUsbdevSense = 59, /**< Peripheral Input 59 */ - kTopEarlgreyPinmuxPeripheralInLast = 59, /**< \internal Last valid peripheral input */ + kTopEarlgreyPinmuxPeripheralInRramMacroTck = 47, /**< Peripheral Input 47 */ + kTopEarlgreyPinmuxPeripheralInRramMacroTms = 48, /**< Peripheral Input 48 */ + kTopEarlgreyPinmuxPeripheralInRramMacroTdi = 49, /**< Peripheral Input 49 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 50, /**< Peripheral Input 50 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 51, /**< Peripheral Input 51 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 52, /**< Peripheral Input 52 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 53, /**< Peripheral Input 53 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 54, /**< Peripheral Input 54 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 55, /**< Peripheral Input 55 */ + kTopEarlgreyPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */ + kTopEarlgreyPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */ } top_earlgrey_pinmux_peripheral_in_t; /** @@ -1563,24 +1501,23 @@ typedef enum top_earlgrey_pinmux_outsel { kTopEarlgreyPinmuxOutselUart3Tx = 48, /**< Peripheral Output 45 */ kTopEarlgreyPinmuxOutselSpiHost1Sck = 49, /**< Peripheral Output 46 */ kTopEarlgreyPinmuxOutselSpiHost1Csb = 50, /**< Peripheral Output 47 */ - kTopEarlgreyPinmuxOutselFlashCtrlTdo = 51, /**< Peripheral Output 48 */ - kTopEarlgreyPinmuxOutselRramMacroTdo = 52, /**< Peripheral Output 49 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 53, /**< Peripheral Output 50 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 54, /**< Peripheral Output 51 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 55, /**< Peripheral Output 52 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 56, /**< Peripheral Output 53 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 57, /**< Peripheral Output 54 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 58, /**< Peripheral Output 55 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 59, /**< Peripheral Output 56 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 60, /**< Peripheral Output 57 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 61, /**< Peripheral Output 58 */ - kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 62, /**< Peripheral Output 59 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 63, /**< Peripheral Output 60 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 64, /**< Peripheral Output 61 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 65, /**< Peripheral Output 62 */ - kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 66, /**< Peripheral Output 63 */ - kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 67, /**< Peripheral Output 64 */ - kTopEarlgreyPinmuxOutselLast = 67, /**< \internal Last valid outsel value */ + kTopEarlgreyPinmuxOutselRramMacroTdo = 51, /**< Peripheral Output 48 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 52, /**< Peripheral Output 49 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 53, /**< Peripheral Output 50 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 54, /**< Peripheral Output 51 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 55, /**< Peripheral Output 52 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 56, /**< Peripheral Output 53 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 57, /**< Peripheral Output 54 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 58, /**< Peripheral Output 55 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 59, /**< Peripheral Output 56 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 60, /**< Peripheral Output 57 */ + kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 61, /**< Peripheral Output 58 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 62, /**< Peripheral Output 59 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 63, /**< Peripheral Output 60 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 64, /**< Peripheral Output 61 */ + kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 65, /**< Peripheral Output 62 */ + kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 66, /**< Peripheral Output 63 */ + kTopEarlgreyPinmuxOutselLast = 66, /**< \internal Last valid outsel value */ } top_earlgrey_pinmux_outsel_t; /** @@ -1728,8 +1665,8 @@ typedef enum top_earlgrey_hintable_clocks { * MMIO Region * * MMIO region excludes any memory that is separate from the module - * configuration space, i.e. ROM, main SRAM, and flash are excluded but - * retention SRAM, spi_device memory, or usbdev memory are included. + * configuration space, i.e. ROM, main SRAM, and RRAM are excluded but retention + * SRAM, spi_device memory, or usbdev memory are included. */ #define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u #define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000u diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index 21bb13d3e97fe..ecbcdd22c852a 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -35,16 +35,6 @@ */ #define TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES 0x1000 -/** - * Memory base for mem memory on flash_ctrl in top earlgrey. - */ -#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000 - -/** - * Memory size for mem memory on flash_ctrl in top earlgrey. - */ -#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000 - /** * Memory base for host memory on rram_ctrl in top earlgrey. */ @@ -528,40 +518,6 @@ * `TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES`. */ #define TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES 0x40 -/** - * Peripheral base address for core device on flash_ctrl in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000 - -/** - * Peripheral size for core device on flash_ctrl in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES`. - */ -#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200 -/** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000 - -/** - * Peripheral size for prim device on flash_ctrl in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`. - */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80 /** * Peripheral base address for core device on rram_ctrl in top earlgrey. * @@ -873,8 +829,8 @@ * MMIO Region * * MMIO region excludes any memory that is separate from the module - * configuration space, i.e. ROM, main SRAM, and flash are excluded but - * retention SRAM, spi_device memory, or usbdev memory are included. + * configuration space, i.e. ROM, main SRAM, and RRAM are excluded but retention + * SRAM, spi_device memory, or usbdev memory are included. */ #define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000 #define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000 diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld index ad47e753e98a7..04d43ce4701b9 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld @@ -15,7 +15,6 @@ */ MEMORY { ram_ret_aon(rwx) : ORIGIN = 0x40600000, LENGTH = 0x1000 - eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 rram(rx) : ORIGIN = 0x30000000, LENGTH = 0x200000 ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 ram_secondary(rwx) : ORIGIN = 0x10020000, LENGTH = 0x10000 diff --git a/hw/top_earlgrey/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl index 9cea2020f0286..850963dcd978a 100644 --- a/hw/top_earlgrey/templates/chiplevel.sv.tpl +++ b/hw/top_earlgrey/templates/chiplevel.sv.tpl @@ -1032,6 +1032,14 @@ module chip_${top["name"]}_${target["name"]} #( assign manual_attr_cc1 = sensor_ctrl_manual_pad_attr[0]; assign manual_attr_cc2 = sensor_ctrl_manual_pad_attr[1]; + // Indices 2 and 3 used to map to FLASH_TEST_MODE0/1, which no longer exist + // now that flash_ctrl has been removed from this top. + logic unused_sensor_ctrl_manual_pad_attr; + assign unused_sensor_ctrl_manual_pad_attr = ^{ + sensor_ctrl_manual_pad_attr[2], + sensor_ctrl_manual_pad_attr[3] + }; + // These pad attributes are currently tied off permanently (these are supply pads). assign manual_attr_rram_analog = '0; diff --git a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv index be488fb3982c5..aead9884db923 100644 --- a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv +++ b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv @@ -646,7 +646,7 @@ module chip_englishbreakfast_cw305 #( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; @@ -786,7 +786,7 @@ module chip_englishbreakfast_cw305 #( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -843,6 +843,7 @@ module chip_englishbreakfast_cw305 #( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections // englishbreakfast does not use the AST SRAM configuration: leave the cfg diff --git a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_verilator.sv index 8bfa235b39984..54f9357ea3b94 100644 --- a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_verilator.sv +++ b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_verilator.sv @@ -293,7 +293,7 @@ module chip_englishbreakfast_verilator ( ast_pkg::ast_alert_rsp_t ast_alert_rsp; ast_pkg::ast_alert_req_t ast_alert_req; - // Flash connections + // Flash connections (only for englishbreakfast). prim_mubi_pkg::mubi4_t flash_bist_enable; logic flash_power_down_h; logic flash_power_ready_h; @@ -455,7 +455,7 @@ module chip_englishbreakfast_verilator ( .main_env_iso_en_i ( pwrmgr_ast_req.pwr_clamp_env ), .main_pd_ni ( pwrmgr_ast_req.main_pd_n ), // pdm control (flash) - .flash_power_down_h_o ( flash_power_down_h ), + .flash_power_down_h_o ( flash_power_down_h ), .flash_power_ready_h_o ( flash_power_ready_h ), .otp_power_seq_i ( '0 ), .otp_power_seq_h_o ( ), @@ -512,6 +512,7 @@ module chip_englishbreakfast_verilator ( .all_clk_byp_ack_o ( all_clk_byp_ack ), .io_clk_byp_req_i ( io_clk_byp_req ), .io_clk_byp_ack_o ( io_clk_byp_ack ), + // bist enable (flash) .flash_bist_en_o ( flash_bist_enable ), // Memory configuration connections // englishbreakfast does not use the AST SRAM configuration: leave the cfg diff --git a/sw/host/ot_hal/src/top/autogen/earlgrey.rs b/sw/host/ot_hal/src/top/autogen/earlgrey.rs index 27d45433f5aab..8ac81f0e5e860 100644 --- a/sw/host/ot_hal/src/top/autogen/earlgrey.rs +++ b/sw/host/ot_hal/src/top/autogen/earlgrey.rs @@ -60,20 +60,17 @@ with_unknown! { Uart2Rx = 44, Uart3Rx = 45, SpiDeviceTpmCsb = 46, - FlashCtrlTck = 47, - FlashCtrlTms = 48, - FlashCtrlTdi = 49, - RramMacroTck = 50, - RramMacroTms = 51, - RramMacroTdi = 52, - SysrstCtrlAcPresent = 53, - SysrstCtrlKey0In = 54, - SysrstCtrlKey1In = 55, - SysrstCtrlKey2In = 56, - SysrstCtrlPwrbIn = 57, - SysrstCtrlLidOpen = 58, - UsbdevSense = 59, - End = 60, + RramMacroTck = 47, + RramMacroTms = 48, + RramMacroTdi = 49, + SysrstCtrlAcPresent = 50, + SysrstCtrlKey0In = 51, + SysrstCtrlKey1In = 52, + SysrstCtrlKey2In = 53, + SysrstCtrlPwrbIn = 54, + SysrstCtrlLidOpen = 55, + UsbdevSense = 56, + End = 57, } pub enum PinmuxInsel: u32 [default = Self::End] { @@ -232,24 +229,23 @@ with_unknown! { Uart3Tx = 48, SpiHost1Sck = 49, SpiHost1Csb = 50, - FlashCtrlTdo = 51, - RramMacroTdo = 52, - SensorCtrlAstDebugOut0 = 53, - SensorCtrlAstDebugOut1 = 54, - SensorCtrlAstDebugOut2 = 55, - SensorCtrlAstDebugOut3 = 56, - SensorCtrlAstDebugOut4 = 57, - SensorCtrlAstDebugOut5 = 58, - SensorCtrlAstDebugOut6 = 59, - SensorCtrlAstDebugOut7 = 60, - SensorCtrlAstDebugOut8 = 61, - SysrstCtrlBatDisable = 62, - SysrstCtrlKey0Out = 63, - SysrstCtrlKey1Out = 64, - SysrstCtrlKey2Out = 65, - SysrstCtrlPwrbOut = 66, - SysrstCtrlZ3Wakeup = 67, - End = 68, + RramMacroTdo = 51, + SensorCtrlAstDebugOut0 = 52, + SensorCtrlAstDebugOut1 = 53, + SensorCtrlAstDebugOut2 = 54, + SensorCtrlAstDebugOut3 = 55, + SensorCtrlAstDebugOut4 = 56, + SensorCtrlAstDebugOut5 = 57, + SensorCtrlAstDebugOut6 = 58, + SensorCtrlAstDebugOut7 = 59, + SensorCtrlAstDebugOut8 = 60, + SysrstCtrlBatDisable = 61, + SysrstCtrlKey0Out = 62, + SysrstCtrlKey1Out = 63, + SysrstCtrlKey2Out = 64, + SysrstCtrlPwrbOut = 65, + SysrstCtrlZ3Wakeup = 66, + End = 67, } pub enum DirectPads: u32 [default = Self::End] { From f56e21633e21a2c97b8f53a1c423bb7058dbd27e Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 14:28:06 +0200 Subject: [PATCH 05/24] [dv,earlgrey] exclude flash specific tests This commit cleans up testplans after flash_ctrl removal. RRAM will need similar tests (see #31028) to verify the full functionality of RRAM in Earl Grey. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/chip_testplan.hjson | 29 -- .../data/ip/chip_clkmgr_testplan.hjson | 7 - .../data/ip/chip_flash_ctrl_testplan.hjson | 357 ---------------- .../data/ip/chip_lc_ctrl_testplan.hjson | 3 - .../data/ip/chip_otp_ctrl_testplan.hjson | 26 +- hw/top_earlgrey/dv/chip_sim_cfg.hjson | 168 +------- .../cov/conn_flash_ctrl_ast_obs_test_volt.el | 54 --- hw/top_earlgrey/dv/env/chip_env.core | 3 - .../dv/env/flash_ctrl_host_gnt_fault_if.sv | 48 --- .../env/seq_lib/chip_prim_tl_access_vseq.sv | 134 ------ .../chip_sw_flash_ctrl_lc_rw_en_vseq.sv | 14 +- .../dv/env/seq_lib/chip_sw_flash_init_vseq.sv | 382 ------------------ .../chip_sw_inject_scramble_seed_vseq.sv | 89 ---- .../seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv | 4 +- .../dv/env/seq_lib/chip_vseq_list.sv | 5 - .../formal/top_earlgrey_fpv_sec_cm_cfgs.hjson | 9 - sw/device/tests/BUILD | 8 +- 17 files changed, 23 insertions(+), 1317 deletions(-) delete mode 100644 hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson delete mode 100644 hw/top_earlgrey/dv/cov/conn_flash_ctrl_ast_obs_test_volt.el delete mode 100644 hw/top_earlgrey/dv/env/flash_ctrl_host_gnt_fault_if.sv delete mode 100644 hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv delete mode 100644 hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_init_vseq.sv delete mode 100644 hw/top_earlgrey/dv/env/seq_lib/chip_sw_inject_scramble_seed_vseq.sv diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson index 0256b04c521b7..23ddb3679f1bf 100644 --- a/hw/top_earlgrey/data/chip_testplan.hjson +++ b/hw/top_earlgrey/data/chip_testplan.hjson @@ -30,7 +30,6 @@ "hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson", "hw/top_earlgrey/data/ip/chip_edn_testplan.hjson", "hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson", - "hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson", "hw/top_earlgrey/data/ip/chip_gpio_testplan.hjson", "hw/top_earlgrey/data/ip/chip_hmac_testplan.hjson", "hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson" @@ -319,8 +318,6 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_clkmgr_jitter", - "chip_sw_flash_ctrl_ops_jitter_en", - "chip_sw_flash_ctrl_access_jitter_en", "chip_sw_otbn_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", @@ -416,7 +413,6 @@ stage: V1 si_stage: NA tests: ["chip_sw_example_rom", - "chip_sw_example_flash", "chip_sw_example_manufacturer", "chip_sw_example_concurrency" ] @@ -448,7 +444,6 @@ "chip_sw_rstmgr_smoketest", "chip_sw_sram_ctrl_smoketest", "chip_sw_uart_smoketest", - #"chip_sw_flash_scrambling_smoketest", TODO: Replace with RRAM test ] bazel: [ "//sw/device/tests:aes_smoketest", @@ -695,29 +690,5 @@ tests: ["chip_sw_exit_test_unlocked_bootstrap"] } - { - name: chip_sw_inject_scramble_seed - desc: '''End to end test to ensure boot strap can succeed after injecting scramble seeds. - - - Pre-load the device into PROD, PROD_END or DEV state. - - Backdoor load an unscrambled value into flash isolated partition. - - In the test program, populate the scramble seeds (flash / sram). - - In the test program, populate OTP entries to inform ROM to scramble flash upon next boot. - - Reboot the device and perform boot strap of the same test image, ROM should now program - the flash image with scramble enabled. - - Upon successful boot strap, ROM jumps to the newly programmed image and de-scrambles the - instructions. - - In the test program, check whether the OTP partition containing the scramble seeds is - locked. Also check that the unscrambled value programmed into flash isolated partition - can be correctly read back when the region is set to scramble disable. - - If either of the above checks is incorrect, return error. - - - X-ref'ed with manuf_ft_sku_individualization from manufacturing test plan. - ''' - stage: V2 - si_stage: NA - tests: ["chip_sw_inject_scramble_seed"] - } ] } diff --git a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson index f1a40bc0b8c0c..864788777f6eb 100644 --- a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson @@ -198,8 +198,6 @@ si_stage: SV3 tests: [ "chip_sw_clkmgr_jitter", - "chip_sw_flash_ctrl_ops_jitter_en", - "chip_sw_flash_ctrl_access_jitter_en", "chip_sw_otbn_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", @@ -260,8 +258,6 @@ Test the following functionalities with reduced clock: - - flash_ctrl initialization - - flash_ctrl program, read and erase operations - AES, HMAC, KMAC and OTBN operations - Keymgr key derivation - Scramble-enabled access from the main SRAM @@ -274,15 +270,12 @@ si_stage: NA tests: [ "chip_sw_clkmgr_jitter_reduced_freq", - "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq", - "chip_sw_flash_ctrl_access_jitter_en_reduced_freq", "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq", "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq", "chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq", - "chip_sw_flash_init_reduced_freq", "chip_sw_csrng_edn_concurrency_reduced_freq", ] } diff --git a/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson deleted file mode 100644 index cf60bb92a92a6..0000000000000 --- a/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson +++ /dev/null @@ -1,357 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - name: flash_ctrl - testpoints: [ - // FLASH integration tests - { - name: chip_sw_flash_init - desc: '''Verify that flash initialization routine works correctly. - - - Initialize the flash ctrl by writing 1 to the INIT register. - - Poll the status register for the initialization to complete. - - Verify that during the init process, the flash ctrl requested keys from OTP. Verify - with different sets of key values programmed in OTP. - - Verify the flash ctrl can read seeds when lc_seed_hw_rd_en is set, otherwise all 1s. - - Verify that the flash ctrl sent the creator and owner seeds to keymgr. Verify with - different seed values. - - - This test needs to execute as a boot rom image. - - In silicon, this will be covered by manuf_ft_provision_rma_token_and_personalization. - ''' - features: ["FLASH_CTRL.INIT.SCRAMBLING_KEYS", "FLASH_CTRL.INIT.ROOT_SEEDS", - "FLASH_CTRL.INFO.CREATOR_PARTITION", "FLASH_CTRL.INFO.OWNER_PARTITION"] - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_init"] - bazel: ["//sw/device/tests:flash_ctrl_test"] - } - { - name: chip_sw_flash_host_access - desc: '''Verify that the flash memory contents can be read by the CPU. - - Nothing extra to do here - most SW based tests fetch code from flash. - ''' - features: ["FLASH_CTRL.OP.HOST_READ"] - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_ctrl_access", - "chip_sw_flash_ctrl_access_jitter_en"] - bazel: ["//sw/device/tests:flash_ctrl_ops_test", "//sw/device/tests:flash_ctrl_test"] - } - { - name: chip_sw_flash_ctrl_ops - desc: '''Verify the SW can initiate flash operations via the controller. - - Verify that the CPU can read / program and erase the flash mem. Pick an operation on - all data and info partitions. Erase both, bank and page. SW validates the reception of - prog empty, prog level, rd full, rd level and op done interrupts. - ''' - features: ["FLASH_CTRL.OP.PROTOCOL_CTRL"] - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_ctrl_ops", "chip_sw_flash_ctrl_ops_jitter_en"] - bazel: ["//sw/device/tests:flash_ctrl_ops_test"] - } - { - name: chip_sw_flash_memory_protection - desc: '''Extend chip_sw_flash_ctrl_access test to over following features. - Perform READ/ PROGRAM/ ERASE operations over protected regions and pages of data and - info partitions. - Use set and reset values of corresponding read, program and erase enable bits. - Test boundary values of regions. Test overlap of regions in which lower - region wins arbitration. - ''' - features: ["FLASH_CTRL.MEM_PROTECTION"] - stage: V3 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_ctrl_mem_protection"] - bazel: ["//sw/device/tests:flash_ctrl_mem_protection_test"] - } - { - name: chip_sw_flash_rma_unlocked - desc: '''Verify the flash memory contents can be accessed after in RMA unlock. - - - Provision an RMA_UNLOCK token in OTP. - - Repeat the following a few times: - - Randomize the otp contents for device id, manufacturing state and RMA_UNLOCK token. - - Reset the chip. - - Ensure chip revision, device id and manufacturing state can be read through the LC JTAG. - - Enable RMA mode, and verify that the SW can access the flash after RMA completion. - - - RMA entry should be done through the JTAG interface. - - - X-ref'ed with manuf_ft_provision_rma_token_and_personalization from the manufacturing - testplan. - ''' - features: ["FLASH_CTRL.RMA"] - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_rma_unlocked"] - bazel: [] - } - { - name: chip_sw_flash_scramble - desc: '''Verify flash scrambling via the controller. - - - Extends the chip_flash_init test. - - Verify flash scrambling with different key values programmed in OTP. - - Verify read of scrambled contents via both, controller and direct host read. - - - Program a new scramble key in OTP and reboot - this time we need to backdoor load the - flash with new test image that is re-scrambled with the new key. - - Need to understand the bootstrapping requirements. - ''' - features: ["FLASH_CTRL.INIT.SCRAMBLING_KEYS", "FLASH_CTRL.OP.PROTOCOL_CTRL"] - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_init"] - bazel: ["//sw/device/tests:flash_ctrl_test"] - } - { - name: chip_sw_flash_idle_low_power - desc: '''Verify flash_idle signaling to pwrmgr. - - - Initiate flash program or erase over the controller. - - Program the pwrmgr to go into deep sleep. - - Issue a WFI. - - Ensure that the low power entry does not happen due to the ongoing flash operation. - ''' - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_ctrl_idle_low_power"] - bazel: ["//sw/device/tests:flash_ctrl_idle_low_power_test"] - } - { - name: chip_sw_flash_keymgr_seeds - desc: '''Verify the creator and owner seeds are read on flash init provided lc_hw_seed_rd_en - is set. - - X-ref'ed with keymgr dpe test. - ''' - features: ["FLASH_CTRL.INIT.ROOT_SEEDS", "FLASH_CTRL.INFO.CREATOR_PARTITION", "FLASH_CTRL.INFO.OWNER_PARTITION"] - stage: V2 - si_stage: NA - lc_states: ["PROD"] - tests: ["chip_sw_keymgr_dpe_key_derivation"] - } - { - name: chip_sw_flash_lc_creator_seed_sw_rw_en - desc: '''Verify the lc_creator_seed_sw_rw_en signal from LC ctrl. - - - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify - that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW - accessibility of the corresponding partition depending on the signal value. - - In silicon, we cannot transition the chip or check this signal. The - accessibility of the partition should still be checked in each of - the relevant LC states. - ''' - features: ["FLASH_CTRL.INFO.CREATOR_PARTITION"] - stage: V2 - si_stage: SV3 - lc_states: ["TEST_LOCKED", "DEV", "PROD", "SCRAP"] - boot_stages: ["rom_ext"] - tests: ["chip_sw_flash_ctrl_lc_rw_en"] - bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_dev", - "//sw/device/tests:flash_ctrl_info_access_lc_prod", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_end", - "//sw/device/tests:flash_ctrl_info_access_lc_rma", - "//sw/device/tests:flash_ctrl_info_access_lc_test_unlocked0", - "//sw/device/tests:flash_ctrl_info_access_lc_dev_personalized", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_personalized", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_end_personalized"] - - } - { - name: chip_sw_flash_creator_seed_wipe_on_rma - desc: '''Verify that the creator seed is wiped by the flash ctrl on RMA entry. - ''' - features: ["FLASH_CTRL.RMA"] - stage: V2 - si_stage: SV3 - lc_states: ["RMA"] - tests: ["chip_sw_flash_rma_unlocked"] - bazel: ["//sw/device/tests:flash_ctrl_rma_test"] - } - { - name: chip_sw_flash_lc_owner_seed_sw_rw_en - desc: '''Verify the lc_owner_seed_sw_rw_en signal from LC ctrl. - - - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify - that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW - accessibility of the corresponding partition depending on the signal value. - - In silicon, we cannot transition the chip or check this signal. The - accessibility of the partition should still be checked in each of - the relevant LC states. - ''' - features: ["FLASH_CTRL.INFO.OWNER_PARTITION"] - stage: V2 - si_stage: SV3 - lc_states: ["TEST_LOCKED", "DEV", "PROD", "SCRAP"] - tests: ["chip_sw_flash_ctrl_lc_rw_en"] - boot_stages: ["rom_ext"] - bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_dev", - "//sw/device/tests:flash_ctrl_info_access_lc_prod", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_end", - "//sw/device/tests:flash_ctrl_info_access_lc_rma", - "//sw/device/tests:flash_ctrl_info_access_lc_test_unlocked0"] - } - { - name: chip_sw_flash_lc_iso_part_sw_rd_en - desc: '''Verify the lc_iso_part_sw_rd_en signal from LC ctrl. - - - Transition from DEV or PROD to ESCALATION/SCRAP state via OTP and verify - that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW - accessibility of the corresponding partition depending on the signal value. - - In silicon, we cannot transition the chip or check this signal. The - accessibility of the partition should still be checked in each of - the relevant LC states. - ''' - features: ["FLASH_CTRL.INFO.ISOLATED_PARTITION"] - stage: V2 - si_stage: SV3 - lc_states: ["DEV", "PROD", "SCRAP"] - tests: ["chip_sw_flash_ctrl_lc_rw_en"] - boot_stages: ["rom_ext"] - bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_dev", - "//sw/device/tests:flash_ctrl_info_access_lc_prod", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_end", - "//sw/device/tests:flash_ctrl_info_access_lc_rma", - "//sw/device/tests:flash_ctrl_info_access_lc_test_unlocked0"] - } - { - name: chip_sw_flash_lc_iso_part_sw_wr_en - desc: '''Verify the lc_creator_seed_sw_wr_en signal from LC ctrl. - - - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify - that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW - accessibility of the corresponding partition depending on the signal value. - - In silicon, we cannot transition the chip or check this signal. The - accessibility of the partition should still be checked in each of - the relevant LC states. - ''' - features: ["FLASH_CTRL.INFO.ISOLATED_PARTITION"] - stage: V2 - si_stage: SV3 - lc_states: ["TEST_LOCKED", "DEV", "PROD", "SCRAP"] - tests: ["chip_sw_flash_ctrl_lc_rw_en"] - boot_stages: ["rom_ext"] - bazel: ["//sw/device/tests:flash_ctrl_info_access_lc_dev", - "//sw/device/tests:flash_ctrl_info_access_lc_prod", - "//sw/device/tests:flash_ctrl_info_access_lc_prod_end", - "//sw/device/tests:flash_ctrl_info_access_lc_rma", - "//sw/device/tests:flash_ctrl_info_access_lc_test_unlocked0"] - } - { - name: chip_sw_flash_lc_seed_hw_rd_en - desc: '''Verify the lc_seed_hw_rd_en signal from LC ctrl. - - - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify - that this LC signal transitions from 0 to 1 and back to 0. Verify that the flash ctrl - does (or does not) read the creator and owner partitions to fetch the seeds for the - keymgr. - - In silicon, this will be covered by manuf_ft_provision_rma_token_and_personalization. - ''' - features: ["FLASH_CTRL.INIT.ROOT_SEEDS"] - stage: V2 - si_stage: SV3 - lc_states: ["DEV", "PROD", "PROD_END", "RMA"] - boot_stages: ["rom_ext"] - tests: ["chip_sw_flash_ctrl_lc_rw_en"] - bazel: [] - } - { - name: chip_sw_flash_lc_escalate_en - desc: '''Verify the lc_escalate_en signal from LC ctrl. - - - Trigger an LC escalation signal by generating an alert. - - Verify that all flash accesses are disabled when the escalation kicks in. - - Confirm flash accesses are disabled by erroring if the device executes the ISR. - - Use assertion based connectivity check to prove that this signal is connected to the - flash ctrl. - - X-ref with chip_sw_all_escalation_resets. - ''' - features: ["FLASH_CTRL.ESCALATION"] - stage: V2 - si_stage: NA - tests: ["chip_sw_all_escalation_resets"] - } - { - name: chip_sw_flash_prim_tl_access - desc: '''Verify that the SW can read / write the prim tlul interface in flash phy. - - - The prim tlul interface is a open source placeholder for the closed source CSRs that - will be implemented in a translation 'shim'. - - Verify that this region can be read / written to by the SW in any LC state. - ''' - stage: V2 - si_stage: NA - tests: ["chip_prim_tl_access"] - } - { - name: chip_sw_flash_ctrl_clock_freqs - desc: '''Verify flash program and erase operations over the ctrl over a range of clock freqs. - - - Enable jitter on the clock while performing erase, write and read operations - to the flash. - - This sets the test for closed source where the flash access timing matters. - ''' - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_ctrl_clock_freqs"] - bazel: ["//sw/device/tests:flash_ctrl_clock_freqs_test"] - } - { - name: chip_sw_flash_ctrl_escalation_reset - desc: '''Verify the flash ctrl fatal error does not disturb escalation process - and operation of ibex core. - - Trigger an internal fatal fault (host_gnt_err) from flash_ctrl - and let it escalate to reset. Upon alert escalation reset, - the internal status should be clean and should not send out more alerts. - ''' - stage: V2 - si_stage: NA - tests: ["chip_sw_flash_crash_alert"] - } - { - name: chip_sw_flash_ctrl_write_clear - desc: '''Verify the flash is able to process a second write to clear all bits - when ECC is enabled. - - Configure memory protected entries to override the default flash configuration as follows: - 1. ECC enabled, scrambling and high endurance disabled. - 2. ECC and high endurance enabled, scrambling disabled. - - Test the following sequence: - - Set one of the configuration options above. - - Erase target page. - - Write and verify intermediate value, different than all 1s or 0s. - - Write and verify all 0s. - - The flash should not throw any errors on the second write. - - Note: The hardware does not support this behavior when scrambling is enabled. - ''' - stage: V2 - si_stage: SV3 - lc_states: ["PROD"] - tests: ["chip_sw_flash_crash_alert"] - bazel: ["//sw/device/tests:flash_ctrl_write_clear_test"] - } - ] -} diff --git a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson index d694231634be5..ad1087c9363fc 100644 --- a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson @@ -182,7 +182,6 @@ stage: V2 si_stage: NA tests: [ - "chip_prim_tl_access", // lc_dft_en_o: otp_ctrl "chip_tap_straps_dev", // lc_dft_en_o, lc_hw_debug_en_o: pinmux "chip_tap_straps_prod", // lc_dft_en_o, lc_hw_debug_en_o: pinmux "chip_tap_straps_rma", // lc_dft_en_o, lc_hw_debug_en_o: pinmux @@ -197,9 +196,7 @@ "chip_rv_dm_lc_disabled" // lc_hw_debug_en_o: rv_dm "chip_sw_keymgr_dpe_key_derivation", // lc_keymgr_en_o: keymgr_dpe "chip_sw_clkmgr_external_clk_src_for_lc", // lc_clk_byp_req_o: clkmgr - "chip_sw_flash_rma_unlocked", // lc_nvm_rma_req_o, lc_nvm_rma_seed_o: flash_ctrl "chip_sw_lc_ctrl_transition", // lc_check_byp_en_o: otp_ctrl - "chip_sw_flash_ctrl_lc_rw_en", // lc_creator*, lc_seed*, lc_owner*, lc_iso*: flash_ctrl "chip_sw_otp_ctrl_lc_signals_test_unlocked0", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_otp_ctrl_lc_signals_dev", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_otp_ctrl_lc_signals_prod", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl diff --git a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson index d021d7e7b0ed1..78bbdd1cda587 100644 --- a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson @@ -24,14 +24,13 @@ name: chip_sw_otp_ctrl_keys desc: '''Verify the proliferation of keys to security peripherals. - - Verify the correctness of keys provided to SRAM ctrl (main & ret), flash ctrl, + - Verify the correctness of keys provided to SRAM ctrl (main & ret), rram ctrl, keymgr dpe (note that keymgr dpe does not have handshake). - Ensure that the test requests a new key and verifies the previously written data to an address now returns a garbage value. X-ref'ed with the following IP tests that consume these signals: - chip_sw_sram_scrambled_access - - chip_sw_flash_scramble - chip_sw_keymgr_dpe_key_derivation - chip_sw_otbn_mem_scramble For sival, this test can be done by @@ -44,7 +43,6 @@ lc_states: ["PROD"] tests: [// Verifies both, main and retention SRAM scrambling. "chip_sw_sram_ctrl_scrambled_access", - "chip_sw_flash_init", "chip_sw_keymgr_dpe_key_derivation", "chip_sw_otbn_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] @@ -65,7 +63,6 @@ si_stage: SV1 lc_states: ["PROD"] tests: ["chip_sw_sram_ctrl_scrambled_access", - "chip_sw_flash_init", "chip_sw_keymgr_dpe_key_derivation", "chip_sw_otbn_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] @@ -104,7 +101,7 @@ fatal program error as expected. - Allow escalation to go through reset. - Use the rstmgr alert info and the fault CSRs to check the alert cause is right. - - Keep state across resets in flash to check that no NMI or regular ISR interrupt run + - Keep state across resets in NVM to check that no NMI or regular ISR interrupt run for kTopEarlgreyAlertIdLcCtrlFatalProgError. - Verify that, after escalation reset, the alert handler cause and the fault register are cleared. - Verify after the escalation reset that the alert info captured the correct alert. @@ -157,8 +154,6 @@ stage: V2 si_stage: NA tests: [ - // lc_dft_en_i - "chip_prim_tl_access", // lc_check_byp_en_i "chip_sw_lc_ctrl_transition", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, also checks lc_keymgr_en_i since it uses @@ -169,23 +164,6 @@ "chip_sw_otp_ctrl_lc_signals_rma", ] } - { - name: chip_sw_otp_prim_tl_access - desc: '''Verify that the SW can read / write the prim tlul interface. - - - The prim tlul interface is a open source placeholder for the closed source CSRs that - will be implemented in a translation 'shim'. - - Verify that when `lc_dft_en_i` is On, this region can be read / written to by the SW. - When `lc_dft_en_i` is Off, accessing this region will result in a TLUL error. - - For sival, this test can only run on open-source RTL in test_unlocked or rma state. - Do random csr write and read back for RW type registers. - ''' - stage: V2 - si_stage: SV3 - lc_states: ["TEST_UNLOCKED", "RMA"] - tests: ["chip_prim_tl_access"] - bazel: [] - } { name: chip_sw_otp_ctrl_escalation desc: '''Verify escalation from otp_ctrl macro fatal error. diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index e0c52702b667f..9cd98f2902dd4 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -122,7 +122,6 @@ // exclusion files vcs_cov_excl_files: ["{top_dv_path}/cov/chip_top_unr_tied_off.el", "{top_dv_path}/cov/conn_ast_mem_cfg.el", - "{top_dv_path}/cov/conn_flash_ctrl_ast_obs_test_volt.el", "{top_dv_path}/cov/conn_otp_ctrl_ast_obs_ext_volt.el", "{top_dv_path}/cov/edn1_unr_tied_off_ports.el", "{top_dv_path}/cov/entropy_src_tied_off_xht_port.el", @@ -501,12 +500,6 @@ run_timeout_mins: 120 run_opts: ["+test_timeout_ns=120_000_000"] } - { - name: chip_sw_example_flash - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:example_test_from_flash:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - } { name: chip_sw_example_rom uvm_test_seq: chip_sw_base_vseq @@ -525,16 +518,6 @@ sw_images: ["//sw/device/tests:example_concurrency_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } - { - name: chip_sival_flash_info_access - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_info_access_lc:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - // Following run opt can be alternatively selected. - // +use_otp_image=OtpTypeLcStDev - // +use_otp_image=OtpTypeLcStProd - run_opts: ["+use_otp_image=OtpTypeLcStTestUnlocked0"] - } { name: chip_sw_all_escalation_resets uvm_test_seq: chip_sw_all_escalation_resets_vseq @@ -696,20 +679,12 @@ run_opts: ["+uart_idx=0", "+calibrate_usb_clk=1"] reseed: 1 } - { - name: chip_sw_inject_scramble_seed - uvm_test_seq: chip_sw_inject_scramble_seed_vseq - sw_images: ["//sw/device/tests/sim_dv:inject_scramble_seed:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+lc_at_prod=1", "+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"] - run_timeout_mins: 300 - } { name: chip_sw_exit_test_unlocked_bootstrap uvm_test_seq: chip_sw_exit_test_unlocked_bootstrap_vseq sw_images: ["//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"] + run_opts: ["+sw_test_timeout_ns=150_000_000"] run_timeout_mins: 220 } { @@ -803,67 +778,6 @@ sw_images: ["//sw/device/tests/sim_dv:gpio_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } - { - name: chip_sw_flash_ctrl_ops - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+sw_test_timeout_ns=50_000_000"] - } - { - name: chip_sw_flash_ctrl_ops_jitter_en - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+sw_test_timeout_ns=50_000_000", "+en_jitter=1"] - } - { - name: chip_sw_flash_ctrl_lc_rw_en - uvm_test_seq: chip_sw_flash_ctrl_lc_rw_en_vseq - sw_images: ["//sw/device/tests/sim_dv:flash_ctrl_lc_rw_en_test:1:new_rules"] - run_opts: ["+bypass_alert_ready_to_end_check=1"] - en_run_modes: ["sw_test_mode_test_rom"] - } - { - name: chip_sw_flash_ctrl_access - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - } - { - name: chip_sw_flash_ctrl_access_jitter_en - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+en_jitter=1"] - } - { - name: chip_sw_flash_ctrl_idle_low_power - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_idle_low_power_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - } - { - name: chip_sw_flash_init - uvm_test_seq: chip_sw_flash_init_vseq - sw_images: ["//sw/device/tests/sim_dv:flash_init_test:0:test_in_rom:new_rules"] - en_run_modes: ["sw_test_mode_common"] - run_opts: ["+sw_test_timeout_ns=25_000_000"] - } - { - name: chip_sw_flash_rma_unlocked - uvm_test_seq: chip_sw_flash_rma_unlocked_vseq - sw_images: ["//sw/device/tests/sim_dv:flash_rma_unlocked_test:0:test_in_rom:new_rules"] - en_run_modes: ["sw_test_mode_common"] - run_opts: ["+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"] - run_timeout_mins: 200 - } - { - name: chip_sw_flash_ctrl_clock_freqs - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_clock_freqs_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - } { name: chip_sw_kmac_entropy uvm_test_seq: chip_sw_base_vseq @@ -1006,8 +920,7 @@ uvm_test_seq: chip_sw_lc_walkthrough_vseq sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+flash_program_latency=5", - "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStDev", + run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStDev", // The test takes long time because it will transit to RMA state "+sw_test_timeout_ns=200_000_000"] run_timeout_mins: 240 @@ -1017,8 +930,7 @@ uvm_test_seq: chip_sw_lc_walkthrough_vseq sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+flash_program_latency=5", - "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProd", + run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProd", // The test takes long time because it will transit to RMA state "+sw_test_timeout_ns=200_000_000"] run_timeout_mins: 240 @@ -1028,8 +940,7 @@ uvm_test_seq: chip_sw_lc_walkthrough_vseq sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+flash_program_latency=5", - "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProdEnd"] + run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProdEnd"] } { name: chip_sw_lc_ctrl_volatile_raw_unlock @@ -1062,7 +973,6 @@ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStRma", - "+flash_program_latency=5", // The test takes long time because it will transit to RMA state "+sw_test_timeout_ns=200_000_000"] run_timeout_mins: 240 @@ -1418,7 +1328,7 @@ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=3000_000_000", "+bypass_alert_ready_to_end_check=1", - "+avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs,otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err"] + "+avoid_inject_fatal_error_for_ips=sram_ctrl_main,rram_ctrl,lc_ctrl*state_regs,otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err"] run_timeout_mins: 240 reseed: 90 } @@ -1772,13 +1682,6 @@ en_run_modes: ["stub_cpu_mode"] reseed: 30 } - { - name: chip_prim_tl_access - build_mode: "cover_reg_top" - uvm_test_seq: "chip_prim_tl_access_vseq" - en_run_modes: ["stub_cpu_mode"] - run_opts: ["+en_scb=0", "+en_scb_tl_err_chk=0"] - } { name: chip_plic_all_irqs_0 uvm_test_seq: chip_sw_base_vseq @@ -2086,20 +1989,6 @@ run_opts: ["+usb_max_drift=1", "+usb_fast_sof=1"] reseed: 1 } - { - name: chip_sw_flash_crash_alert - uvm_test_seq: chip_sw_flash_host_gnt_err_inj_vseq - sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+test_timeout_ns=8_000_000", "+bypass_alert_ready_to_end_check=1"] - } - { - name: chip_sw_flash_ctrl_write_clear - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_write_clear_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+test_timeout_ns=8_000_000"] - } { name: chip_padctrl_attributes build_mode: "pad_ctrl_test_mode" @@ -2116,20 +2005,6 @@ en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+cal_sys_clk_70mhz=1"] } - { - name: chip_sw_flash_ctrl_ops_jitter_en_reduced_freq - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+sw_test_timeout_ns=50_000_000", "+en_jitter=1", "+cal_sys_clk_70mhz=1"] - } - { - name: chip_sw_flash_ctrl_access_jitter_en_reduced_freq - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+en_jitter=1", "+cal_sys_clk_70mhz=1"] - } { name: chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq uvm_test_seq: chip_sw_base_vseq @@ -2175,13 +2050,6 @@ "+sw_test_timeout_ns=12_000_000", "+bypass_alert_ready_to_end_check=1", "+en_jitter=1", "+en_scb_tl_err_chk=0", "+cal_sys_clk_70mhz=1"] } - { - name: chip_sw_flash_init_reduced_freq - uvm_test_seq: chip_sw_flash_init_vseq - sw_images: ["//sw/device/tests/sim_dv:flash_init_test:0:test_in_rom:new_rules"] - en_run_modes: ["sw_test_mode_common"] - run_opts: ["+sw_test_timeout_ns=25_000_000", "+cal_sys_clk_70mhz=1"] - } { name: chip_sw_csrng_edn_concurrency_reduced_freq uvm_test_seq: chip_sw_base_vseq @@ -2227,22 +2095,6 @@ ] run_timeout_mins: 300 } - { - name: chip_sw_flash_scrambling_smoketest - uvm_test_seq: chip_sw_base_vseq - sw_images: [ - "//sw/device/tests:flash_scrambling_smoketest:1:new_rules", - "//sw/device/tests:flash_scrambling_smoketest_otp_img_rma:4", - ] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+use_otp_image=OtpTypeCustom"] - } - { - name: chip_sw_flash_ctrl_mem_protection - uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:flash_ctrl_mem_protection_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - } ] // List of regressions. @@ -2263,12 +2115,9 @@ "chip_sw_spi_device_pass_through", "chip_sw_i2c_host_tx_rx", "chip_sw_i2c_device_tx_rx", - # "chip_sw_flash_scrambling_smoketest", TODO: port to RRAM - # https://github.com/lowRISC/opentitan/issues/30900 "chip_plic_all_irqs_0", "chip_plic_all_irqs_10", "chip_plic_all_irqs_20", - "chip_sw_example_flash", "chip_sw_example_rom", "chip_sw_example_manufacturer", "chip_sw_example_concurrency"] @@ -2277,8 +2126,6 @@ { name: jitter tests: ["chip_sw_clkmgr_jitter", - "chip_sw_flash_ctrl_ops_jitter_en", - "chip_sw_flash_ctrl_access_jitter_en", "chip_sw_otbn_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", @@ -2289,15 +2136,12 @@ { name: jitter_reduced_freq tests: ["chip_sw_clkmgr_jitter_reduced_freq", - "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq", - "chip_sw_flash_ctrl_access_jitter_en_reduced_freq", "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq", "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq", "chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq", - "chip_sw_flash_init_reduced_freq", "chip_sw_csrng_edn_concurrency_reduced_freq"] } { @@ -2326,7 +2170,7 @@ // "chip_sw_lc_walkthrough_prodend", // "chip_sw_lc_walkthrough_rma", // "chip_sw_lc_walkthrough_testunlocks", - "chip_prim_tl_access"] + ] } { name: xcelium_ci_1 diff --git a/hw/top_earlgrey/dv/cov/conn_flash_ctrl_ast_obs_test_volt.el b/hw/top_earlgrey/dv/cov/conn_flash_ctrl_ast_obs_test_volt.el deleted file mode 100644 index 837f336a45385..0000000000000 --- a/hw/top_earlgrey/dv/cov/conn_flash_ctrl_ast_obs_test_volt.el +++ /dev/null @@ -1,54 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -//================================================== -// This file contains the Excluded objects -// Generated By User: root -// Format Version: 2 -// Date: Fri Nov 11 21:51:07 2022 -// ExclMode: default -//================================================== -CHECKSUM: "4159415449 2721317761" -INSTANCE: tb.dut.u_ast -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_o.obmen "logic obs_ctrl_o.obmen[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_o.obgsl "logic obs_ctrl_o.obgsl[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_o.obmsl "logic obs_ctrl_o.obmsl[3:0]" -CHECKSUM: "4211070719 3495537513" -INSTANCE: tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle flash_test_mode_a_io "net flash_test_mode_a_io[1:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle cio_tdo_o "logic cio_tdo_o" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle cio_tdo_en_o "logic cio_tdo_en_o" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obmsl "logic obs_ctrl_i.obmsl[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obmen "logic obs_ctrl_i.obmen[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obgsl "logic obs_ctrl_i.obgsl[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle flash_test_voltage_h_io "net flash_test_voltage_h_io" -CHECKSUM: "1202717726 1014860158" -INSTANCE: tb.dut.top_earlgrey -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle flash_test_mode_a_io "net flash_test_mode_a_io[1:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obmsl "logic obs_ctrl_i.obmsl[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obmen "logic obs_ctrl_i.obmen[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle obs_ctrl_i.obgsl "logic obs_ctrl_i.obgsl[3:0]" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle flash_test_voltage_h_io "net flash_test_voltage_h_io" -CHECKSUM: "2197777849 2875308652" -INSTANCE: tb.dut -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle FLASH_TEST_MODE0 "net FLASH_TEST_MODE0" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle FLASH_TEST_VOLT "net FLASH_TEST_VOLT" -ANNOTATION: "[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV." -Toggle FLASH_TEST_MODE1 "net FLASH_TEST_MODE1" diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index c799e57fdbc0f..9c587da6cd02f 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -51,7 +51,6 @@ filesets: - seq_lib/chip_common_vseq.sv: {is_include_file: true} - seq_lib/chip_jtag_csr_rw_vseq.sv: {is_include_file: true} - seq_lib/chip_jtag_mem_vseq.sv: {is_include_file: true} - - seq_lib/chip_prim_tl_access_vseq.sv: {is_include_file: true} - seq_lib/chip_tap_straps_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_base_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_uart_tx_vseq.sv: {is_include_file: true} @@ -88,9 +87,7 @@ filesets: - seq_lib/chip_sw_gpio_smoke_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_gpio_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv: {is_include_file: true} - - seq_lib/chip_sw_flash_init_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_flash_rma_unlocked_vseq.sv: {is_include_file: true} - - seq_lib/chip_sw_inject_scramble_seed_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_transition_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/dv/env/flash_ctrl_host_gnt_fault_if.sv b/hw/top_earlgrey/dv/env/flash_ctrl_host_gnt_fault_if.sv deleted file mode 100644 index 3175a8d7872df..0000000000000 --- a/hw/top_earlgrey/dv/env/flash_ctrl_host_gnt_fault_if.sv +++ /dev/null @@ -1,48 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// This interface allows injection of flash_ctrl fatal alert. - -interface flash_ctrl_host_gnt_fault_if ( - input clk_i, - input rst_ni -); - `include "dv_macros.svh" - `include "uvm_macros.svh" - - string msg_id = $sformatf("%m"); - string path = dv_utils_pkg::get_parent_hier($sformatf("%m")); - string signal_forced = $sformatf("%s.muxed_part", path); - - class flash_ctrl_host_gnt_if_proxy extends sec_cm_pkg::sec_cm_base_if_proxy; - `uvm_object_new - - // This injects the fault via force and releases it after a few cycles. - virtual task automatic inject_fault(); - @(negedge clk_i); - `DV_CHECK(uvm_hdl_force(signal_forced, 1'b1)) - `uvm_info(msg_id, $sformatf("Injecting fault by forcing %0s high", signal_forced), UVM_MEDIUM) - repeat (300) @(negedge clk_i); - `DV_CHECK(uvm_hdl_release(signal_forced)) - endtask - - virtual task automatic restore_fault(); - endtask - endclass - - flash_ctrl_host_gnt_if_proxy if_proxy; - - initial begin - `DV_CHECK_FATAL(uvm_hdl_check_path(signal_forced), , msg_id) - - // Store the proxy object for TB to use - if_proxy = new("if_proxy"); - // The sec_cm_type is bogus. - if_proxy.sec_cm_type = sec_cm_pkg::SecCmPrimSparseFsmFlop; - if_proxy.path = path; - sec_cm_pkg::sec_cm_if_proxy_q.push_back(if_proxy); - - `uvm_info(msg_id, $sformatf("Interface proxy class is added for %s", path), UVM_HIGH) - end -endinterface diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv deleted file mode 100644 index e5a734005658e..0000000000000 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv +++ /dev/null @@ -1,134 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// The prim_tlul register spaces are placeholders in open source environment. -// This sequence access prim_tlul access with randomly backdoor-loaded LC state. -// If the LC state gates the prim_tlul interface, we are expecting to see a TLUL d_error. -// In current chip-level design, only otp_ctrl's prim_tl_i/o will be gated by lc_dft_en_i. -class chip_prim_tl_access_vseq extends chip_stub_cpu_base_vseq; - `uvm_object_utils(chip_prim_tl_access_vseq) - - `uvm_object_new - - rand lc_state_e lc_state; - - typedef enum bit [3:0] { - NormalResponse = 0, - ZeroResponse = 1, - ErrorResponse = 2 - } response_mode_e; - - constraint num_trans_c { - num_trans inside {[2:10]}; - } - - // Add constraint to avoid lc_escalate_en being broadcasted and causes fatal alerts. - constraint lc_state_c { - lc_state != LcStScrap; - } - - virtual function void backdoor_override_otp(); - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(lc_state) - `uvm_info(`gfn, $sformatf("Configuring via backdoor OTP: lc_state %0s", lc_state.name), - UVM_LOW) - otp_write_lc_partition_state(cfg.mem_bkdr_util_h[Otp], lc_state); - endfunction - - virtual function void initialize_otp_lc_state(); - backdoor_override_otp(); - super.initialize_otp_lc_state(); - endfunction - - function response_mode_e get_response_mode(bit using_prims); - // If the CPU is disabled, the lc gate will respond with all zeros. - if (cfg.chip_vif.get_lc_ctrl_enable_signal(LcCtrlSignalCpuEn) != lc_ctrl_pkg::On) begin - return ZeroResponse; - end - - // If the CPU is enabled, but we have put lc_ctrl in a state that won't allow TL access to - // prims, we expect errors when we use prims. - if (using_prims && - !(lc_state inside {LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, - LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, - LcStTestUnlocked6, LcStTestUnlocked7, LcStRma})) begin - return ErrorResponse; - end - - // Otherwise, we expect a normal response (not an error and not all zero) - return NormalResponse; - endfunction - - task rw_csr_addr_with_gating(uvm_reg csr, response_mode_e rsp_mode); - bit [TL_AW-1:0] addr = csr.get_address(); - bit [TL_DW-1:0] data = $urandom(); - bit [TL_DW-1:0] exp_data, fake_rdata; - bit expect_errors, writes_work, use_fake_rdata; - - csr_excl_item csr_excl = get_excl_item(csr); - - case (rsp_mode) - NormalResponse: begin - writes_work = 1; - expect_errors = 0; - use_fake_rdata = 0; - end - ZeroResponse: begin - writes_work = 0; - expect_errors = 0; - use_fake_rdata = 1; - fake_rdata = '0; - end - ErrorResponse: begin - writes_work = 0; - expect_errors = 1; - use_fake_rdata = 1; - fake_rdata = '1; - end - default: ; - endcase - - // Apply CsrExclWrite - if (!csr_excl.is_excl(csr, CsrExclWrite, CsrAllTests)) begin - tl_access(.addr(addr), .write(1), .data(data), .exp_err_rsp(expect_errors)); - if (writes_work) begin - void'(csr.predict(.value(data), .kind(UVM_PREDICT_WRITE))); - end - end - - tl_access(.addr(addr), .write(1), .data(data), .exp_err_rsp(expect_errors)); - if (writes_work) begin - void'(csr.predict(.value(data), .kind(UVM_PREDICT_WRITE))); - end - - exp_data = use_fake_rdata ? fake_rdata : `gmv(csr); - `uvm_info(`gfn, - $sformatf("Write addr %0h, write adata %0h, expect data %0h", addr, data, exp_data), - UVM_HIGH); - tl_access(.addr(addr), .write(0), .data(data), .exp_err_rsp(expect_errors), .check_exp_data(1), - .exp_data(exp_data)); - endtask - - task rand_rw_prim_regs(uvm_reg prim_regs[$], response_mode_e rsp_mode); - `DV_CHECK_NE(prim_regs.size(), 0) - prim_regs.shuffle(); - foreach (prim_regs[i]) rw_csr_addr_with_gating(prim_regs[i], rsp_mode); - endtask - - task body(); - for (int trans_i = 1; trans_i <= num_trans; trans_i++) begin - uvm_reg flash_prim_regs[$]; - - if (trans_i > 1 && $urandom_range(0, 4)) dut_init(); - `uvm_info(`gfn, $sformatf("Run iterations %0d/%0d with lc_state %0s", trans_i, num_trans, - lc_state.name), UVM_LOW) - - if ($urandom_range(0, 1)) begin - `uvm_info(`gfn, "Check FLASH_CTRL prim_tl access", UVM_HIGH) - ral.flash_ctrl_prim.get_registers(flash_prim_regs); - rand_rw_prim_regs(flash_prim_regs, get_response_mode(1'b0)); - end - end - endtask : body - -endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv index c7becb6e667d5..9ac11e218c644 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv @@ -7,13 +7,13 @@ class chip_sw_flash_ctrl_lc_rw_en_vseq extends chip_sw_base_vseq; `uvm_object_new - localparam string FLASH_CTRL_HDL_PATH = "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl"; + localparam string RRAM_CTRL_HDL_PATH = "tb.dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl"; localparam string RW_EN_PATHS[5] = '{ - {FLASH_CTRL_HDL_PATH, ".lc_creator_seed_sw_rw_en_i"}, - {FLASH_CTRL_HDL_PATH, ".lc_owner_seed_sw_rw_en_i"}, - {FLASH_CTRL_HDL_PATH, ".lc_iso_part_sw_wr_en_i"}, - {FLASH_CTRL_HDL_PATH, ".lc_iso_part_sw_rd_en_i"}, - {FLASH_CTRL_HDL_PATH, ".lc_seed_hw_rd_en_i"} + {RRAM_CTRL_HDL_PATH, ".lc_creator_seed_sw_rw_en_i"}, + {RRAM_CTRL_HDL_PATH, ".lc_owner_seed_sw_rw_en_i"}, + {RRAM_CTRL_HDL_PATH, ".lc_iso_part_sw_wr_en_i"}, + {RRAM_CTRL_HDL_PATH, ".lc_iso_part_sw_rd_en_i"}, + {RRAM_CTRL_HDL_PATH, ".lc_seed_hw_rd_en_i"} }; virtual task dut_init(string reset_kind = "HARD"); @@ -37,7 +37,7 @@ class chip_sw_flash_ctrl_lc_rw_en_vseq extends chip_sw_base_vseq; // Starting LC state is TestLocked2. This state disables // CPU execution so we check the values by directly reading - // the signals from the flash_ctrl inputs. + // the signals from the rram_ctrl inputs. for (int i = 0; i < 5; i++) begin `DV_CHECK_EQ_FATAL(get_rw_en_signals(i), lc_ctrl_pkg::Off, diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_init_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_init_vseq.sv deleted file mode 100644 index 9fb6d2aa21291..0000000000000 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_init_vseq.sv +++ /dev/null @@ -1,382 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -class chip_sw_flash_init_vseq extends chip_sw_base_vseq; - `uvm_object_utils(chip_sw_flash_init_vseq) - - `uvm_object_new - - localparam string NVM_DATA_KEY_PATH = - "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_flash_hw_if.data_key_o"; - localparam string NVM_ADDR_KEY_PATH = - "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_flash_hw_if.addr_key_o"; - localparam string FLASH_INIT_BUSY_PATH = - "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_flash_hw_if.init_busy_o"; - localparam string KEYMGR_SEEDS_PATH = "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_flash_hw_if.seeds_o"; - localparam string FLASH_LC_SEED_HW_RD_EN_PATH = - "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.lc_seed_hw_rd_en_i"; - - localparam string SRAM_CTRL_RET_HDL_PATH = - "tb.dut.top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr"; - localparam string SRAM_CTRL_RET_NONCE_PATH = {SRAM_CTRL_RET_HDL_PATH, ".nonce_i"}; - localparam string SRAM_CTRL_RET_KEY_PATH = {SRAM_CTRL_RET_HDL_PATH, ".key_i"}; - - localparam uint KeyWidthAddrBits = otp_ctrl_reg_pkg::NvmAddrKeySeedSize * 8; - localparam uint KeyWidthAddrBytes = KeyWidthAddrBits / 8; - localparam uint KeyWidthDataBits = otp_ctrl_reg_pkg::NvmDataKeySeedSize * 8; - localparam uint KeyWidthDataBytes = KeyWidthDataBits / 8; - localparam uint KeyWidthSramBits = otp_ctrl_reg_pkg::SramDataKeySeedSize * 8; - localparam uint KeyWidthSramBytes = KeyWidthSramBits / 8; - - localparam uint SEED_WIDTH = flash_ctrl_pkg::SeedWidth; - localparam uint FLASH_PAGE_SIZE_BYTES = flash_ctrl_reg_pkg::BytesPerPage; - localparam uint FLASH_PAGES_PER_BANK = flash_ctrl_reg_pkg::RegPagesPerBank; - localparam uint CREATOR_SECRET_PAGE_ID = flash_ctrl_top_specific_pkg::CreatorInfoPage; - localparam uint OWNER_SECRET_PAGE_ID = flash_ctrl_top_specific_pkg::OwnerInfoPage; - localparam uint ISO_PART_PAGE_ID = flash_ctrl_top_specific_pkg::IsolatedInfoPage; - localparam uint FLASH_DATA_BYTE_WIDTH = flash_ctrl_top_specific_pkg::DataByteWidth; - - localparam uint NUM_TEST_WORDS = 16; - typedef enum { - UnscrambledTest[0:2], - ScrambledTest[0:1], - BackdoorTest[0:1], - KeyMgrPrep, - KeyMgrTest[0:1], - LastPhase - } test_phases_e; - - bit [sram_scrambler_pkg::SRAM_BLOCK_WIDTH-1:0] sram_ret_nonce; - bit [sram_scrambler_pkg::SRAM_KEY_WIDTH-1:0] sram_ret_key; - - rand bit [7:0] secret_nvm_addr_key[KeyWidthAddrBytes]; - rand bit [7:0] secret_nvm_data_key[KeyWidthDataBytes]; - rand bit [7:0] secret_sram_key[KeyWidthSramBytes]; - - rand bit [31:0] creator_secret_data[NUM_TEST_WORDS]; - rand bit [31:0] owner_secret_data[NUM_TEST_WORDS]; - rand bit [31:0] iso_part_data[NUM_TEST_WORDS]; - rand bit [31:0] bank0_page0_data[NUM_TEST_WORDS]; - rand bit [31:0] bank1_page0_data[NUM_TEST_WORDS]; - rand bit [otp_ctrl_reg_pkg::CreatorRootKeyShare0Size*8-1:0] root_key0; - rand bit [otp_ctrl_reg_pkg::CreatorRootKeyShare0Size*8-1:0] root_key1; - bit [NvmKeyWidth-1:0] nvm_data_key; - bit [NvmKeyWidth-1:0] nvm_addr_key; - - bit write_scrambled; - bit do_keymgr_check; - - event init_done_event; - - typedef enum int { - DV_EXP_RMA, - DV_EXP_PROD - } exp_lc_st_e; - - exp_lc_st_e exp_lc_st; - virtual task ret_backdoor_data_write(); - `DV_CHECK(uvm_hdl_read(SRAM_CTRL_RET_NONCE_PATH, sram_ret_nonce)); - `DV_CHECK(uvm_hdl_read(SRAM_CTRL_RET_KEY_PATH, sram_ret_key)); - for (int i = 0; i < NUM_TEST_WORDS; i++) begin - ret_sram_bkdr_write32((i * 4), creator_secret_data[i], sram_ret_key, sram_ret_nonce); - ret_sram_bkdr_write32((NUM_TEST_WORDS * 4) + (i * 4), owner_secret_data[i], sram_ret_key, - sram_ret_nonce); - ret_sram_bkdr_write32((NUM_TEST_WORDS * 8) + (i * 4), iso_part_data[i], sram_ret_key, - sram_ret_nonce); - ret_sram_bkdr_write32((NUM_TEST_WORDS * 12) + (i * 4), bank0_page0_data[i], sram_ret_key, - sram_ret_nonce); - ret_sram_bkdr_write32((NUM_TEST_WORDS * 16) + (i * 4), bank1_page0_data[i], sram_ret_key, - sram_ret_nonce); - end - endtask - - virtual task randomize_data(); - `DV_CHECK_STD_RANDOMIZE_FATAL(creator_secret_data) - `DV_CHECK_STD_RANDOMIZE_FATAL(owner_secret_data) - `DV_CHECK_STD_RANDOMIZE_FATAL(iso_part_data) - `DV_CHECK_STD_RANDOMIZE_FATAL(bank0_page0_data) - `DV_CHECK_STD_RANDOMIZE_FATAL(bank1_page0_data) - `DV_CHECK_STD_RANDOMIZE_FATAL(root_key0) - `DV_CHECK_STD_RANDOMIZE_FATAL(root_key1) - endtask - - virtual function bit [KeyWidthAddrBits-1:0] get_flash_otp_key( - bit [7:0] key_in[KeyWidthAddrBytes]); - bit [kmac_pkg::AppDigestW-1:0] digest_bits; - bit [7:0] dpi_digest[kmac_pkg::AppDigestW/8]; - - digestpp_dpi_pkg::c_dpi_cshake128(key_in, "", "FLASH_CTRL", KeyWidthAddrBytes, - kmac_pkg::AppDigestW / 8, dpi_digest); - digest_bits = {<> FLASH_DATA_BYTE_WIDTH) * FLASH_PAGES_PER_BANK; - data1.flash_write_scrambled( - {bank1_page0_data[(i*2)+1], bank1_page0_data[i*2]}, base_addr_words + i, - nvm_addr_key, nvm_data_key); - base_addr_words = (FLASH_PAGE_SIZE_BYTES >> FLASH_DATA_BYTE_WIDTH) * CREATOR_SECRET_PAGE_ID; - info0.flash_write_scrambled( - {creator_secret_data[(i*2)+1], creator_secret_data[i*2]}, base_addr_words + i, - nvm_addr_key, nvm_data_key); - base_addr_words = (FLASH_PAGE_SIZE_BYTES >> FLASH_DATA_BYTE_WIDTH) * OWNER_SECRET_PAGE_ID; - info0.flash_write_scrambled( - {owner_secret_data[(i*2)+1], owner_secret_data[i*2]}, base_addr_words + i, - nvm_addr_key, nvm_data_key); - base_addr_words = (FLASH_PAGE_SIZE_BYTES >> FLASH_DATA_BYTE_WIDTH) * ISO_PART_PAGE_ID; - info0.flash_write_scrambled( - {iso_part_data[(i*2)+1], iso_part_data[i*2]}, base_addr_words + i, nvm_addr_key, - nvm_data_key); - end - endtask - - virtual task check_hdl_paths(); - int retval; - retval = uvm_hdl_check_path(NVM_DATA_KEY_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", NVM_DATA_KEY_PATH)) - retval = uvm_hdl_check_path(NVM_ADDR_KEY_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", NVM_ADDR_KEY_PATH)) - retval = uvm_hdl_check_path(FLASH_INIT_BUSY_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", FLASH_INIT_BUSY_PATH)) - retval = uvm_hdl_check_path(KEYMGR_SEEDS_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", KEYMGR_SEEDS_PATH)) - retval = uvm_hdl_check_path(FLASH_LC_SEED_HW_RD_EN_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", FLASH_LC_SEED_HW_RD_EN_PATH)) - retval = uvm_hdl_check_path(SRAM_CTRL_RET_NONCE_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", SRAM_CTRL_RET_NONCE_PATH)) - retval = uvm_hdl_check_path(SRAM_CTRL_RET_KEY_PATH); - `DV_CHECK_EQ_FATAL(retval, 1, $sformatf( - "Hierarchical path %0s appears to be invalid.", SRAM_CTRL_RET_KEY_PATH)) - endtask - - virtual task wait_init_done(); - int retval; - bit init_busy; - bit init_busy_last_value; - forever begin - init_busy_last_value = init_busy; - retval = uvm_hdl_read(FLASH_INIT_BUSY_PATH, init_busy); - `DV_CHECK_EQ(retval, 1, $sformatf("uvm_hdl_read failed for %0s", FLASH_INIT_BUSY_PATH)) - if (init_busy == 0 && init_busy_last_value == 1) begin - ->init_done_event; - end - // Use top level clock to advance time between samples. - cfg.clk_rst_vif.wait_clks(1); - end - endtask - - virtual task get_keys(); - int retval; - forever begin - @(init_done_event); - if (write_scrambled == 1) begin - retval = uvm_hdl_read(NVM_DATA_KEY_PATH, nvm_data_key); - `DV_CHECK_EQ(retval, 1, $sformatf("uvm_hdl_read failed for %0s", NVM_DATA_KEY_PATH)) - retval = uvm_hdl_read(NVM_ADDR_KEY_PATH, nvm_addr_key); - `DV_CHECK_EQ(retval, 1, $sformatf("uvm_hdl_read failed for %0s", NVM_ADDR_KEY_PATH)) - calculate_and_write_scrambled(); - end - end - endtask - - virtual task check_keymgr_seeds(); - int retval; - bit [(SEED_WIDTH*2)-1:0] seeds; - bit [SEED_WIDTH-1:0] owner_seed; - bit [SEED_WIDTH-1:0] creator_seed; - bit [(SEED_WIDTH*2)-1:0] expected_owner_seed; - bit [(SEED_WIDTH*2)-1:0] expected_creator_seed; - bit [lc_ctrl_pkg::TxWidth-1:0] lc_seed_hw_rd_en; - bit [(DecLcStateNumRep*DecLcStateWidth)-1:0] lc_state; - dec_lc_state_e dec_lc_state; - forever begin - @(init_done_event); - if (do_keymgr_check == 1) begin - expected_owner_seed = {<<32{owner_secret_data}}; - expected_creator_seed = {<<32{creator_secret_data}}; - retval = uvm_hdl_read(FLASH_LC_SEED_HW_RD_EN_PATH, lc_seed_hw_rd_en); - `DV_CHECK_EQ(retval, 1, $sformatf("uvm_hdl_read failed for %0s", FLASH_LC_SEED_HW_RD_EN_PATH - )) - retval = uvm_hdl_read(KEYMGR_SEEDS_PATH, seeds); - `DV_CHECK_EQ(retval, 1, $sformatf("uvm_hdl_read failed for %0s", KEYMGR_SEEDS_PATH)) - owner_seed = seeds[(SEED_WIDTH*flash_ctrl_pkg::OwnerSeedIdx)+:SEED_WIDTH]; - creator_seed = seeds[(SEED_WIDTH*flash_ctrl_pkg::CreatorSeedIdx)+:SEED_WIDTH]; - - // Check 'lc_seed_hw_rd_en' - // This can be set to 'on' only if - // 1. lc_state = RMA or - // 2. otp.secret0_digest != 0 && otp.secret2_digest != 0. - // and lc state should be one of {DEV, PROD, PROD_END} - `uvm_info("SEQ", $sformatf("EXP LC STATE: %s", exp_lc_st.name), UVM_MEDIUM) - - if (exp_lc_st == DV_EXP_RMA) begin - `DV_CHECK(lc_seed_hw_rd_en, lc_ctrl_pkg::On) - end else begin - bit [63:0] secret0_digest, secret2_digest; - secret0_digest = {csr_peek(ral.otp_ctrl_core.secret0_digest[1]), - csr_peek(ral.otp_ctrl_core.secret0_digest[0])}; - secret2_digest = {csr_peek(ral.otp_ctrl_core.secret2_digest[1]), - csr_peek(ral.otp_ctrl_core.secret2_digest[0])}; - `uvm_info("SEQ", $sformatf("read secret digest: digest0:0x%16x digest2:0x%16x", - secret0_digest, secret2_digest), UVM_MEDIUM) - if (secret0_digest == 0 || secret2_digest == 0) begin - `DV_CHECK_NE(lc_seed_hw_rd_en, lc_ctrl_pkg::On) - end else begin - `DV_CHECK_EQ(lc_seed_hw_rd_en, lc_ctrl_pkg::On) - end - end - - // If 'lc_seed_hw_rd_en' is off, creator/owner seed cannot be updated and - // retains the default value. - // Make sure your bus is the right size cause - // full 64bit bus might contain x's. - if (lc_seed_hw_rd_en == lc_ctrl_pkg::Off) begin - `DV_CHECK_EQ(creator_seed, - top_earlgrey_rnd_cnst_pkg::RndCnstFlashCtrlAllSeeds[SEED_WIDTH-1:0]); - `DV_CHECK_EQ(owner_seed, - top_earlgrey_rnd_cnst_pkg::RndCnstFlashCtrlAllSeeds[SEED_WIDTH +: SEED_WIDTH]); - end else begin - `DV_CHECK_EQ(creator_seed, expected_creator_seed[SEED_WIDTH-1:0]); - `DV_CHECK_EQ(owner_seed, expected_owner_seed[SEED_WIDTH-1:0]); - end - end - end - endtask - - virtual task body(); - bit [7:0] array_data[1]; - bit random_data = 0; - super.body(); - check_hdl_paths(); - - cfg.disable_d_user_data_intg_check_for_passthru_mem = 1; - cfg.en_scb_mem_chk = 0; - // Write randomly generated data to retention SRAM for use in SW. - ret_backdoor_data_write(); - - // Fork the tasks for monitoring the key updates and - // checking the keymgr seed update where applicable. - fork - wait_init_done(); - get_keys(); - check_keymgr_seeds(); - join_none - - // Allow most test phases to write seed partition, but do not allow hardware to read - otp_write_lc_partition_state(cfg.mem_bkdr_util_h[Otp], LcStProd); - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::Secret2DigestOffset, 0); - - // Looping through all test phases. - for (int current_phase = UnscrambledTest0; current_phase <= LastPhase; current_phase++) begin - // Backdoor overwrite the SW variable for the test phase. - array_data[0] = current_phase; - sw_symbol_backdoor_overwrite("kTestPhase", array_data, SwTypeRom); - `uvm_info(`gfn, $sformatf("Testing %d", current_phase), UVM_LOW) - - if (current_phase < LastPhase) begin - do_keymgr_check = 0; - write_scrambled = 0; - random_data = 0; - case (current_phase) - UnscrambledTest0, UnscrambledTest1, UnscrambledTest2, - ScrambledTest0, ScrambledTest1: begin - random_data = 1; - end - - BackdoorTest0, BackdoorTest1: begin - write_scrambled = 1; - random_data = 1; - end - - KeyMgrPrep: begin - write_scrambled = 1; - end - - KeyMgrTest0: begin - do_keymgr_check = 1; - `uvm_info(`gfn, $sformatf("Lock OTP secret2 partition and enable seed reading"), - UVM_LOW) - - // The actual data is irrelevant as long as the partition becomes locked. - otp_write_secret2_partition( - .mem_bkdr_util_h(cfg.mem_bkdr_util_h[Otp]), - .rma_token('0), .creator_root_key_share0('0), .creator_root_key_share1('0)); - end - - KeyMgrTest1: begin - `uvm_info(`gfn, $sformatf("Zero secret2 partition and disable seed reading"), - UVM_LOW) - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::Secret2DigestOffset, 0); - do_keymgr_check = 1; - end - - default:; - - endcase // case (current_phase) - - // Wait for the test to start and enter the WFI state, - `uvm_info(`gfn, $sformatf("Wating to be in test"), UVM_MEDIUM) - `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest) - `uvm_info(`gfn, $sformatf("Wating to be see WFI"), UVM_MEDIUM) - `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInWfi) - - // Randomize the data and keys for the next test phase. - if (random_data) begin - randomize_data(); - randomize_keys(); - ret_backdoor_data_write(); - end - - apply_reset(); - cfg.clk_rst_vif.wait_clks(1000); - end else begin - // final phase cleanup. - disable fork; - end - end - endtask - -endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_inject_scramble_seed_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_inject_scramble_seed_vseq.sv deleted file mode 100644 index aab5fc8a2cb52..0000000000000 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_inject_scramble_seed_vseq.sv +++ /dev/null @@ -1,89 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -class chip_sw_inject_scramble_seed_vseq extends chip_sw_base_vseq; - `uvm_object_utils(chip_sw_inject_scramble_seed_vseq) - - `uvm_object_new - - localparam uint ISO_PART_SIZE = 8 * flash_phy_pkg::DataWidth/8; - localparam uint ISO_PART_ADDR = flash_ctrl_top_specific_pkg::IsolatedInfoPage * - (flash_ctrl_top_specific_pkg::WordsPerPage * - (flash_ctrl_top_specific_pkg::DataWidth / 8)); - rand bit [7:0] iso_part_data [ISO_PART_SIZE]; - - virtual task dut_init(string reset_kind = "HARD"); - super.dut_init(reset_kind); - - // make sure it is unlocked and empty to start - for (int i = 0; i < 4; i++) begin - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::NvmAddrKeySeedOffset + i*8, - '0); - - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::NvmDataKeySeedOffset + i*8, - '0); - - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::SramDataKeySeedOffset + i*8, - '0); - end - - - cfg.mem_bkdr_util_h[Otp].write64(otp_ctrl_reg_pkg::Secret1DigestOffset, - '0); - - - // make sure we are in prod state - otp_write_lc_partition_state(cfg.mem_bkdr_util_h[Otp], LcStProd); - - // Randomize the expected data and write it into flash. - `DV_CHECK_STD_RANDOMIZE_FATAL(iso_part_data); - for (int i = 0; i < ISO_PART_SIZE; i++) begin - // write some data into isolated partition - cfg.mem_bkdr_util_h[FlashBank0Info].write8(ISO_PART_ADDR + i, iso_part_data[i]); - end - - endtask // dut_init - - virtual task cpu_init(); - super.cpu_init(); - sw_symbol_backdoor_overwrite("kIsoPartExpData", iso_part_data); - endtask - - - virtual task body(); - super.body(); - - `DV_SPINWAIT(wait(cfg.sw_logger_vif.printed_log == - "Completed first phase, wait for reset");, - "timeout waiting for C side acknowledgement", - cfg.sw_test_timeout_ns) - - `uvm_info(`gfn, "Received C side acknowledgement", UVM_LOW) - - // setup triggers to bootstrap during the second run - cfg.use_spi_load_bootstrap = 1'b1; - - `DV_SPINWAIT(wait(cfg.sw_logger_vif.printed_log == - "Boot strap requested");, - "timeout waiting for C side acknowledgement", - cfg.sw_test_timeout_ns) - - `uvm_info(`gfn, "Received C side acknowledgement", UVM_LOW) - - spi_device_load_bootstrap({cfg.sw_images[SwTypeTestSlotA], ".64.scr.vmem"}); - cfg.use_spi_load_bootstrap = 1'b0; - - // After bootstrap, we need to write the expected values again, - // since the boot-strap process wiped out the previous version. - sw_symbol_backdoor_overwrite("kIsoPartExpData", iso_part_data); - - `DV_SPINWAIT(wait(cfg.sw_logger_vif.printed_log == "Hello World");, - "timeout waiting for Hello World", - cfg.sw_test_timeout_ns) - - endtask - - - -endclass : chip_sw_inject_scramble_seed_vseq diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv index 059ce956e0b4b..55c6516e44651 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv @@ -141,8 +141,8 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq; `DV_CHECK((cfg.chip_vif.pmp_addr[0] < cfg.chip_vif.pmp_addr[1]) && (cfg.chip_vif.pmp_addr[1] <= cfg.chip_vif.pmp_addr[2])) `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[5], - epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, - top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES)) + epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR, + top_earlgrey_pkg::TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES)) `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[10], epmp_addr_tor(MMIO_START_ADDRESS)) `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[11], epmp_addr_tor(MMIO_END_ADDRESS)) `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[12], diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv index b4188a8dc0afb..3c322543aafa6 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv @@ -14,7 +14,6 @@ `include "chip_sw_lc_base_vseq.sv" `include "chip_sw_uart_smoke_vseq.sv" `include "chip_jtag_base_vseq.sv" -`include "chip_prim_tl_access_vseq.sv" `include "chip_sw_all_escalation_resets_vseq.sv" `include "chip_sw_fault_base_vseq.sv" `include "chip_sw_rstmgr_cnsty_fault_vseq.sv" @@ -36,9 +35,6 @@ `include "chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv" `include "chip_sw_gpio_smoke_vseq.sv" `include "chip_sw_gpio_vseq.sv" -`include "chip_sw_flash_ctrl_lc_rw_en_vseq.sv" -`include "chip_sw_flash_init_vseq.sv" -`include "chip_sw_flash_rma_unlocked_vseq.sv" `include "chip_sw_lc_ctrl_transition_vseq.sv" `include "chip_sw_lc_ctrl_scrap_vseq.sv" `include "chip_sw_lc_raw_unlock_vseq.sv" @@ -87,7 +83,6 @@ `include "chip_sw_i2c_device_tx_rx_vseq.sv" `include "chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv" `include "chip_sw_rv_core_ibex_icache_invalidate_vseq.sv" -`include "chip_sw_inject_scramble_seed_vseq.sv" `include "chip_sw_exit_test_unlocked_bootstrap_vseq.sv" `include "chip_sw_spi_device_tpm_vseq.sv" `include "chip_sw_aes_masking_off_vseq.sv" diff --git a/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson b/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson index 90609a39f872e..a294d8c2c0e6a 100644 --- a/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson +++ b/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson @@ -85,15 +85,6 @@ stopats: ["*u_state_regs.state_o"] task: "FpvSecCm" } - { - name: flash_ctrl_sec_cm - dut: flash_ctrl - fusesoc_core: lowrisc:earlgrey_dv:flash_ctrl_sva - import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/{sub_flow}/{tool}" - stopats: ["*u_state_regs.state_o", "*u_rma_state_regs.state_o"] - task: "FpvSecCm" - } { name: keymgr_sec_cm dut: keymgr diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 40db2f907b763..0cc42fd3b47bf 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -2029,10 +2029,14 @@ opentitan_test( "//hw/top_earlgrey:silicon_creator": None, }, ), - # No longer relevant on RRAM; exclude all FPGA variants from CI entirely. + # No longer relevant on RRAM; exclude all FPGA and verilator variants from + # CI entirely. # https://github.com/lowRISC/opentitan/issues/30897 fpga = fpga_params(tags = ["skip_in_ci"]), - verilator = verilator_params(timeout = "long"), + verilator = verilator_params( + timeout = "long", + tags = ["skip_in_ci"], + ), deps = [ "//hw/top/dt", "//hw/top_earlgrey/sw/autogen:top_earlgrey", From 94a23463fb8059f06eb38548a8f2ba822a067516 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 15:33:37 +0200 Subject: [PATCH 06/24] [sw,rram_ctrl] port remaining tests to rram_ctrl This includes: - sleep_pin_wake_test - rv_dm_ndm_reset_req - modify_digest - irq_asm - spi_device_unittest Signed-off-by: Michael Gautschi --- sw/device/lib/testing/json/pinmux.h | 8 ++++---- sw/device/silicon_creator/lib/BUILD | 7 ++++++- sw/device/silicon_creator/lib/drivers/BUILD | 1 + .../lib/drivers/spi_device_unittest.cc | 7 +++---- sw/device/silicon_creator/lib/irq_asm.S | 10 +++++----- .../rom_ext/e2e/dice_chain/modify_digest.c | 7 +++---- sw/device/tests/BUILD | 2 +- sw/device/tests/rv_dm_ndm_reset_req.c | 16 ++++++++-------- sw/device/tests/sleep_pin_wake_test.c | 6 +++--- 9 files changed, 34 insertions(+), 30 deletions(-) diff --git a/sw/device/lib/testing/json/pinmux.h b/sw/device/lib/testing/json/pinmux.h index 57a425034779c..92369e7725974 100644 --- a/sw/device/lib/testing/json/pinmux.h +++ b/sw/device/lib/testing/json/pinmux.h @@ -67,9 +67,9 @@ extern "C" { value(_, Uart2Rx, kTopEarlgreyPinmuxPeripheralInUart2Rx) \ value(_, Uart3Rx, kTopEarlgreyPinmuxPeripheralInUart3Rx) \ value(_, SpiDeviceTpmCsb, kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb) \ - value(_, FlashCtrlTck, kTopEarlgreyPinmuxPeripheralInFlashCtrlTck) \ - value(_, FlashCtrlTms, kTopEarlgreyPinmuxPeripheralInFlashCtrlTms) \ - value(_, FlashCtrlTdi, kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi) \ + value(_, RramMacroTck, kTopEarlgreyPinmuxPeripheralInRramMacroTck) \ + value(_, RramMacroTms, kTopEarlgreyPinmuxPeripheralInRramMacroTms) \ + value(_, RramMacroTdi, kTopEarlgreyPinmuxPeripheralInRramMacroTdi) \ value(_, SysrstCtrlAcPresent, kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent) \ value(_, SysrstCtrlKey0In, kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In) \ value(_, SysrstCtrlKey1In, kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In) \ @@ -236,7 +236,7 @@ C_ONLY(UJSON_SERDE_ENUM(PinmuxMioOut, pinmux_mio_out_t, TOP_EARLGREY_PINMUX_MIO_ value(_, Uart3Tx, kTopEarlgreyPinmuxOutselUart3Tx) \ value(_, SpiHost1Sck, kTopEarlgreyPinmuxOutselSpiHost1Sck) \ value(_, SpiHost1Csb, kTopEarlgreyPinmuxOutselSpiHost1Csb) \ - value(_, FlashCtrlTdo, kTopEarlgreyPinmuxOutselFlashCtrlTdo) \ + value(_, RramMacroTdo, kTopEarlgreyPinmuxOutselRramMacroTdo) \ value(_, SensorCtrlAstDebugOut0, kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0) \ value(_, SensorCtrlAstDebugOut1, kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1) \ value(_, SensorCtrlAstDebugOut2, kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2) \ diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index 97fd0310016cb..a7b592ff68ba9 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -147,6 +147,11 @@ filegroup( srcs = ["flash_exc_handler.S"], ) +filegroup( + name = "rram_exc_handler", + srcs = ["rram_exc_handler.S"], +) + cc_library( name = "epmp_defs", hdrs = [ @@ -221,8 +226,8 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ "//hw/top:aon_timer_c_regs", - "//hw/top:flash_ctrl_c_regs", "//hw/top:pwrmgr_c_regs", + "//hw/top:rram_ctrl_c_regs", "//hw/top:rstmgr_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:multibits", diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD index dc0fe9c1939b1..92f6809fe0ce1 100644 --- a/sw/device/silicon_creator/lib/drivers/BUILD +++ b/sw/device/silicon_creator/lib/drivers/BUILD @@ -967,6 +967,7 @@ cc_test( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:abs_mmio", "//sw/device/silicon_creator/lib:error", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/testing:rom_test", "@googletest//:gtest_main", ], diff --git a/sw/device/silicon_creator/lib/drivers/spi_device_unittest.cc b/sw/device/silicon_creator/lib/drivers/spi_device_unittest.cc index 5211c7ffbdcf6..8bf1f35ac1396 100644 --- a/sw/device/silicon_creator/lib/drivers/spi_device_unittest.cc +++ b/sw/device/silicon_creator/lib/drivers/spi_device_unittest.cc @@ -12,9 +12,9 @@ #include "sw/device/lib/base/mock_abs_mmio.h" #include "sw/device/silicon_creator/lib/drivers/mock_lifecycle.h" #include "sw/device/silicon_creator/lib/error.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" #include "sw/device/silicon_creator/testing/rom_test.h" -#include "hw/top/flash_ctrl_regs.h" #include "hw/top/spi_device_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -63,9 +63,8 @@ TEST_F(InitTest, Init) { {SPI_DEVICE_DEV_ID_ROM_BOOTSTRAP_BIT, 1}, {SPI_DEVICE_DEV_ID_CHIP_GEN_FIELD.index, hw_rev.product_id}, {SPI_DEVICE_DEV_ID_DENSITY_FIELD.index, - (uint32_t)bitfield_count_trailing_zeroes32( - FLASH_CTRL_PARAM_REG_NUM_BANKS * - FLASH_CTRL_PARAM_BYTES_PER_BANK)}, + (uint32_t)bitfield_count_trailing_zeroes32(NVM_BYTES_PER_BANK * + NVM_NUM_BANKS)}, {SPI_DEVICE_JEDEC_ID_MF_OFFSET, kSpiDeviceJedecManufId}, }); diff --git a/sw/device/silicon_creator/lib/irq_asm.S b/sw/device/silicon_creator/lib/irq_asm.S index 5d0ad2e4f1592..24fd5914ae42f 100644 --- a/sw/device/silicon_creator/lib/irq_asm.S +++ b/sw/device/silicon_creator/lib/irq_asm.S @@ -4,7 +4,7 @@ #include "sw/device/lib/base/multibits_asm.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h" -#include "hw/top/flash_ctrl_regs.h" +#include "hw/top/rram_ctrl_regs.h" #include "hw/top/rstmgr_regs.h" // Place this code into the .crt section to be able to call it early in @@ -30,12 +30,12 @@ _asm_exception_handler: li t1, MULTIBIT_ASM_BOOL4_TRUE sw t1, RSTMGR_RESET_REQ_REG_OFFSET(t0) - // Disable access to flash. + // Disable access to RRAM. // // This is done after requesting a reset so that this function will - // work even if it is in flash. - li t0, TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR - sw zero, FLASH_CTRL_DIS_REG_OFFSET(t0) + // work even if it is executing from RRAM. + li t0, TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + sw zero, RRAM_CTRL_DIS_REG_OFFSET(t0) wfi j .L_exception_loop diff --git a/sw/device/silicon_creator/rom_ext/e2e/dice_chain/modify_digest.c b/sw/device/silicon_creator/rom_ext/e2e/dice_chain/modify_digest.c index 9f80cb6b500a1..071218f17484a 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/dice_chain/modify_digest.c +++ b/sw/device/silicon_creator/rom_ext/e2e/dice_chain/modify_digest.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "hw/top/dt/flash_ctrl.h" +#include "hw/top/dt/rram_ctrl.h" #include "sw/device/lib/base/status.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/test_framework/ottf_alerts.h" @@ -43,9 +43,8 @@ static status_t modify_digest_test(void) { bool test_main(void) { // This test intentionally creates an invalid digest triggering recoverable // errors. Ignore the alert in OTTF. - CHECK_STATUS_OK( - ottf_alerts_expect_alert_start(dt_flash_ctrl_alert_to_alert_id( - kDtFlashCtrlFirst, kDtFlashCtrlAlertRecovErr))); + CHECK_STATUS_OK(ottf_alerts_expect_alert_start(dt_rram_ctrl_alert_to_alert_id( + kDtRramCtrlFirst, kDtRramCtrlAlertRecovErr))); status_t sts = modify_digest_test(); if (status_err(sts)) { diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 0cc42fd3b47bf..2b86fe98f2648 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -6352,8 +6352,8 @@ test_suite( }, [ "//hw/top:adc_ctrl_c_regs", - "//hw/top:flash_ctrl_c_regs", "//hw/top:keymgr_dpe_c_regs", + "//hw/top:rram_ctrl_c_regs", "//hw/top:sysrst_ctrl_c_regs", ], ), diff --git a/sw/device/tests/rv_dm_ndm_reset_req.c b/sw/device/tests/rv_dm_ndm_reset_req.c index 473ad136c7ff0..19d6d2912b87f 100644 --- a/sw/device/tests/rv_dm_ndm_reset_req.c +++ b/sw/device/tests/rv_dm_ndm_reset_req.c @@ -17,11 +17,11 @@ #if defined(OPENTITAN_IS_EARLGREY) #include "hw/top/dt/adc_ctrl.h" // Generated -#include "hw/top/dt/flash_ctrl.h" // Generated +#include "hw/top/dt/rram_ctrl.h" // Generated #include "hw/top/dt/sysrst_ctrl.h" // Generated #include "hw/top/adc_ctrl_regs.h" -#include "hw/top/flash_ctrl_regs.h" +#include "hw/top/rram_ctrl_regs.h" #include "hw/top/sysrst_ctrl_regs.h" #elif defined(OPENTITAN_IS_DARJEELING) #else @@ -54,7 +54,7 @@ RESET PRGM (ARBITRARY VALUE) ADC_CTRL.ADC_SAMPLE_CTL 0x9B 0x37 SYSRST_CTRL.EC_RST_CTL 0x7D0 0x567 - FLASH_CTRL.SCRATCH 0x0 0x3927 + RRAM_CTRL.SCRATCH 0x0 0x5252_414D After programming csrs, the test assert NDM reset from RV_DM and de-assert. Read programmed csr to check all Group2 keep programmed value while group 3 @@ -153,11 +153,11 @@ bool test_main(void) { }, { - .name = "FLASH_CTRL", - .base = dt_flash_ctrl_primary_reg_block(kDtFlashCtrl), - .offset = FLASH_CTRL_SCRATCH_REG_OFFSET, - .write_val = 0x3927, - .exp_read_val = FLASH_CTRL_SCRATCH_REG_RESVAL, + .name = "RRAM_CTRL", + .base = dt_rram_ctrl_primary_reg_block(kDtRramCtrl), + .offset = RRAM_CTRL_SCRATCH_REG_OFFSET, + .write_val = 0x5252414D, + .exp_read_val = RRAM_CTRL_SCRATCH_REG_RESVAL, }, #elif defined(OPENTITAN_IS_DARJEELING) #else diff --git a/sw/device/tests/sleep_pin_wake_test.c b/sw/device/tests/sleep_pin_wake_test.c index 9bf61f2461996..903e9331ef78e 100644 --- a/sw/device/tests/sleep_pin_wake_test.c +++ b/sw/device/tests/sleep_pin_wake_test.c @@ -108,9 +108,9 @@ bool test_main(void) { wakeup_detector_selected = rand_testutils_gen32_range(0, PINMUX_PARAM_N_WKUP_DETECT - 1); if (kDeviceType == kDeviceSimDV) { - CHECK(nvm_ctrl_data_write((uint32_t)(&wakeup_detector_idx) - - TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, - 1, &wakeup_detector_selected) == kErrorOk); + CHECK(nvm_ctrl_data_write( + (uint32_t)(&wakeup_detector_idx) - NVM_DATA_BASE_ADDR, 1, + &wakeup_detector_selected) == kErrorOk); } LOG_INFO("detector %d is selected", wakeup_detector_selected); // TODO(lowrisc/opentitan#15889): The weak pull on IOC3 needs to be From 3d270b340d1b96c97acb4da334a25ea2076eab5b Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 15:34:47 +0200 Subject: [PATCH 07/24] [rram,flash,sw] remove stale flash dependencies There were a few tests that actually do not have a dependency on flash, but still had flash_ctrl in its dependency tree. spi_device was ported to use nvm_ctrl instead of flash_ctrl Signed-off-by: Michael Gautschi --- sw/device/lib/testing/BUILD | 1 - sw/device/lib/testing/nvm_testutils.c | 8 ++++---- sw/device/lib/testing/test_rom/BUILD | 15 ++++++--------- sw/device/silicon_creator/lib/BUILD | 1 - sw/device/silicon_creator/lib/drivers/BUILD | 2 +- .../silicon_creator/lib/drivers/spi_device.c | 13 ++++++------- sw/device/silicon_creator/lib/ownership/BUILD | 1 - sw/device/silicon_creator/manuf/base/BUILD | 9 --------- .../manuf/extensions/BUILD.bazel | 1 - sw/device/silicon_creator/manuf/lib/BUILD | 18 ++++++------------ sw/device/silicon_creator/manuf/tests/BUILD | 6 ++---- .../rom/e2e/rom_ext_upgrade_interrupt/BUILD | 1 - .../rom_ext_upgrade_interrupt.c | 1 - .../silicon_creator/rom_ext/e2e/isfb/BUILD | 1 - sw/device/tests/BUILD | 15 +-------------- sw/device/tests/crypto/BUILD | 1 - sw/device/tests/sim_dv/BUILD | 6 ------ sw/host/ot_hal/bindgen/BUILD | 4 ++-- sw/host/ot_hal/bindgen/difs.h | 2 +- sw/host/tests/chip/rv_dm/src/csr_rw.rs | 10 +++++----- .../tests/rom/e2e_bootstrap_entry/src/main.rs | 10 +++++----- 21 files changed, 39 insertions(+), 87 deletions(-) diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 49fdea3371fec..85c1223ab2552 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD @@ -330,7 +330,6 @@ cc_library( { "earlgrey": [ ":nvm_testutils", - "//sw/device/lib/dif:flash_ctrl", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/silicon_creator/lib/drivers:retention_sram", ], diff --git a/sw/device/lib/testing/nvm_testutils.c b/sw/device/lib/testing/nvm_testutils.c index c4bb38225d00c..e3e8f5405bcde 100644 --- a/sw/device/lib/testing/nvm_testutils.c +++ b/sw/device/lib/testing/nvm_testutils.c @@ -11,7 +11,6 @@ #include "sw/device/lib/base/mmio.h" #include "sw/device/lib/base/multibits.h" #include "sw/device/lib/testing/test_framework/check.h" -#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #if defined(USE_RRAM) #include "sw/device/lib/dif/dif_rram_ctrl.h" @@ -21,6 +20,7 @@ #else #include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/testing/flash_ctrl_testutils.h" +#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #if defined(OPENTITAN_IS_EARLGREY) #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #elif defined(OPENTITAN_IS_ENGLISHBREAKFAST) @@ -88,12 +88,12 @@ status_t nvm_testutils_rom_init(uint32_t otp_nvm_default_cfg) { TRY(dif_rram_ctrl_get_default_region_properties(&rram, &props)); props.rd_en = kMultiBitBool4True; if (otp_nvm_default_cfg != 0) { - // RRAM has no high-endurance concept, so FLASH_CTRL_OTP_FIELD_HE is not + // RRAM has no high-endurance concept, so RRAM_CTRL_OTP_FIELD_HE is not // applied here. props.scramble_en = bitfield_field32_read(otp_nvm_default_cfg, - FLASH_CTRL_OTP_FIELD_SCRAMBLING); + RRAM_CTRL_OTP_FIELD_SCRAMBLING); props.ecc_en = - bitfield_field32_read(otp_nvm_default_cfg, FLASH_CTRL_OTP_FIELD_ECC); + bitfield_field32_read(otp_nvm_default_cfg, RRAM_CTRL_OTP_FIELD_ECC); } TRY(dif_rram_ctrl_set_default_region_properties(&rram, props)); TRY(dif_rram_ctrl_set_rram_enablement(&rram, kDifToggleEnabled)); diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD index 3c532f332d913..880675bae8109 100644 --- a/sw/device/lib/testing/test_rom/BUILD +++ b/sw/device/lib/testing/test_rom/BUILD @@ -111,7 +111,6 @@ cc_library( name = "earl_grey_test_rom_lib", deps = [ "//sw/device/lib/dif:rstmgr", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:retention_sram", "//sw/device/silicon_creator/rom:bootstrap", ], @@ -233,14 +232,6 @@ cc_library( "edn", ["//hw/top:edn_c_regs"], [], - ) + opentitan_if_ip( - "flash_ctrl", - [ - "//sw/device/lib/dif:flash_ctrl", - "//sw/device/lib/testing:flash_ctrl_testutils", - "//sw/device/lib/testing:nvm_testutils", - ], - [], ) + opentitan_if_ip( "sensor_ctrl", ["//hw/top:sensor_ctrl_c_regs"], @@ -252,6 +243,12 @@ cc_library( "//hw/top/dt:otp_ctrl", ], [], + ) + opentitan_select_top( + { + "earlgrey": ["//sw/device/lib/testing:nvm_testutils"], + "englishbreakfast": ["//sw/device/lib/testing:nvm_testutils"], + }, + [], ), ) diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index a7b592ff68ba9..bc0143b43920f 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -612,7 +612,6 @@ cc_library( "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib/base:sec_mmio", "//sw/device/silicon_creator/lib/base:util", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:hmac", "//sw/device/silicon_creator/lib/drivers:keymgr_dpe", "//sw/device/silicon_creator/lib/drivers:otbn", diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD index 92f6809fe0ce1..a94d4378444ce 100644 --- a/sw/device/silicon_creator/lib/drivers/BUILD +++ b/sw/device/silicon_creator/lib/drivers/BUILD @@ -938,9 +938,9 @@ dual_cc_library( ], deps = dual_inputs( device = [ - "//hw/top:flash_ctrl_c_regs", "//hw/top:spi_device_c_regs", "//hw/top/dt", + "//sw/device/silicon_creator/lib:nvm_ctrl", ], host = [ "//sw/device/lib/base:global_mock", diff --git a/sw/device/silicon_creator/lib/drivers/spi_device.c b/sw/device/silicon_creator/lib/drivers/spi_device.c index 6ef9a5564b7f8..f220e661cc4f8 100644 --- a/sw/device/silicon_creator/lib/drivers/spi_device.c +++ b/sw/device/silicon_creator/lib/drivers/spi_device.c @@ -11,8 +11,8 @@ #include "sw/device/silicon_creator/lib/drivers/lifecycle.h" #include "sw/device/silicon_creator/lib/drivers/spi_device_bfpt.h" #include "sw/device/silicon_creator/lib/error.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" -#include "hw/top/flash_ctrl_regs.h" #include "hw/top/spi_device_regs.h" static const dt_spi_device_t kSpiDeviceDt = kDtSpiDevice; @@ -36,10 +36,9 @@ enum { kSfdpAreaEndOff = SPI_DEVICE_EGRESS_BUFFER_REG_OFFSET + kSpiDeviceSfdpAreaOffset + kSpiDeviceSfdpAreaNumBytes, /** - * Flash data partition size in bits. + * NVM data partition size in bits. */ - kFlashBitCount = - FLASH_CTRL_PARAM_REG_NUM_BANKS * FLASH_CTRL_PARAM_BYTES_PER_BANK * 8, + kNvmBitCount = NVM_BYTES_PER_BANK * NVM_NUM_BANKS * 8, /** * 32-bit SFDP signature that indicates the presence of a SFDP table * (JESD216F 6.2.1). @@ -48,9 +47,9 @@ enum { /** * LSB of the 2-byte device ID. * - * Density is expressed as log2(flash size in bytes). + * Density is expressed as log2(NVM size in bytes). */ - kSpiDeviceJedecDensity = 20, + kSpiDeviceJedecDensity = __builtin_ctz(NVM_BYTES_PER_BANK * NVM_NUM_BANKS), /** * Size of the SFDP table in words. */ @@ -145,7 +144,7 @@ static_assert(kBfptTablePointer % sizeof(uint32_t) == 0, */ #define BFPT_WORD_2(X) \ X(31, 31, 0x0) & \ - X(30, 0, kFlashBitCount - 1) + X(30, 0, kNvmBitCount - 1) /** * BFPT 3rd Word diff --git a/sw/device/silicon_creator/lib/ownership/BUILD b/sw/device/silicon_creator/lib/ownership/BUILD index 0f8bf13174afc..6c3b6e6f224bf 100644 --- a/sw/device/silicon_creator/lib/ownership/BUILD +++ b/sw/device/silicon_creator/lib/ownership/BUILD @@ -183,7 +183,6 @@ cc_library( "//sw/device/silicon_creator/lib:boot_data", "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib/boot_svc:boot_svc_msg", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:hmac", "//sw/device/silicon_creator/lib/drivers:lifecycle", "//sw/device/silicon_creator/lib/sigverify:flash_exec", diff --git a/sw/device/silicon_creator/manuf/base/BUILD b/sw/device/silicon_creator/manuf/base/BUILD index c6a4a5e900b45..db89a6dfb3505 100644 --- a/sw/device/silicon_creator/manuf/base/BUILD +++ b/sw/device/silicon_creator/manuf/base/BUILD @@ -59,11 +59,9 @@ opentitan_binary( "//sw/device/lib/base:crc32", "//sw/device/lib/base:macros", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:lc_ctrl_testutils", "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", @@ -99,13 +97,11 @@ opentitan_binary( "//sw/device/lib/base:crc32", "//sw/device/lib/base:macros", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:lc_ctrl_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing/json:provisioning_data", @@ -179,7 +175,6 @@ opentitan_test( "//sw/device/lib/base:crc32", "//sw/device/lib/base:macros", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", @@ -223,7 +218,6 @@ cc_library( hdrs = ["personalize_ext.h"], deps = [ "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/testing/json:provisioning_data", "//sw/device/silicon_creator/lib/cert", "//sw/device/silicon_creator/lib/sigverify:ecdsa_p256_key", @@ -318,14 +312,12 @@ manifest(d = { ":personalize_ext", "//hw/top:otp_ctrl_c_regs", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:lc_ctrl_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:pinmux_testutils", @@ -346,7 +338,6 @@ manifest(d = { "//sw/device/silicon_creator/lib/cert:cdi_1_template_library", "//sw/device/silicon_creator/lib/cert:dice_chain", "//sw/device/silicon_creator/lib/cert:uds_template_library", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:hmac", "//sw/device/silicon_creator/lib/drivers:keymgr_dpe", "//sw/device/silicon_creator/lib/drivers:kmac", diff --git a/sw/device/silicon_creator/manuf/extensions/BUILD.bazel b/sw/device/silicon_creator/manuf/extensions/BUILD.bazel index 2aa9f0c334887..cac4afd1a86a6 100644 --- a/sw/device/silicon_creator/manuf/extensions/BUILD.bazel +++ b/sw/device/silicon_creator/manuf/extensions/BUILD.bazel @@ -10,7 +10,6 @@ cc_library( name = "default_perso_fw_ext", srcs = ["default_personalize_ext.c"], deps = [ - "@//sw/device/lib/dif:flash_ctrl", "@//sw/device/lib/testing/json:provisioning_data", "@//sw/device/lib/testing/test_framework:status", "@//sw/device/lib/testing/test_framework:ujson_ottf", diff --git a/sw/device/silicon_creator/manuf/lib/BUILD b/sw/device/silicon_creator/manuf/lib/BUILD index 1060ba9c6e555..2c3633089c19c 100644 --- a/sw/device/silicon_creator/manuf/lib/BUILD +++ b/sw/device/silicon_creator/manuf/lib/BUILD @@ -127,11 +127,10 @@ cc_library( "//sw/device/lib/base:status", "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/crypto/include:datatypes", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:lc_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing/json:provisioning_data", "//sw/device/lib/testing/test_framework:check", @@ -155,12 +154,11 @@ opentitan_test( ":otp_fields", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:rstmgr", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:lc_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing/json:provisioning_data", @@ -178,7 +176,6 @@ cc_library( ":nvm_info_field", ":otp_img_types", ":util", - "//hw/top:flash_ctrl_c_regs", "//hw/top:otp_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:macros", @@ -227,12 +224,11 @@ opentitan_test( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:status", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/runtime:hart", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing/test_framework:ottf_main", @@ -285,15 +281,14 @@ opentitan_test( deps = [ ":nvm_info_field", ":personalize", - "//hw/top:flash_ctrl_c_regs", "//hw/top:lc_ctrl_c_regs", "//hw/top:otp_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:rstmgr", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing/json:command", "//sw/device/lib/testing/json:provisioning_data", @@ -311,11 +306,11 @@ cc_library( ":nvm_info_field", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print_uart", + "//sw/device/lib/testing:nvm_testutils", ], ) @@ -339,12 +334,11 @@ opentitan_test( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:crc32", "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print_uart", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing/test_framework:ottf_main", ], ) diff --git a/sw/device/silicon_creator/manuf/tests/BUILD b/sw/device/silicon_creator/manuf/tests/BUILD index d4ae290383dfa..fb04393ca6c07 100644 --- a/sw/device/silicon_creator/manuf/tests/BUILD +++ b/sw/device/silicon_creator/manuf/tests/BUILD @@ -308,12 +308,11 @@ opentitan_binary( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/arch:device", "//sw/device/lib/base:macros", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing/test_framework:check", @@ -366,10 +365,9 @@ opentitan_binary( ), deps = [ ":test_wafer_auth_secret", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/manuf/lib:nvm_info_field", ], diff --git a/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/BUILD b/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/BUILD index 3d5547db5c9b8..719dfcc1181d3 100644 --- a/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/BUILD +++ b/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/BUILD @@ -74,7 +74,6 @@ otp_json( ), manifest = ":manifest_rom_ext_upgrade_interrupt", deps = [ - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:nv_counter_testutils", "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing/test_framework:check", diff --git a/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/rom_ext_upgrade_interrupt.c b/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/rom_ext_upgrade_interrupt.c index c308e326803a1..810e2771269bc 100644 --- a/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/rom_ext_upgrade_interrupt.c +++ b/sw/device/silicon_creator/rom/e2e/rom_ext_upgrade_interrupt/rom_ext_upgrade_interrupt.c @@ -5,7 +5,6 @@ #include #include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/flash_ctrl_testutils.h" #include "sw/device/lib/testing/nv_counter_testutils.h" #include "sw/device/lib/testing/nvm_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" diff --git a/sw/device/silicon_creator/rom_ext/e2e/isfb/BUILD b/sw/device/silicon_creator/rom_ext/e2e/isfb/BUILD index 2f2445be29d03..db8064b0d8159 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/isfb/BUILD +++ b/sw/device/silicon_creator/rom_ext/e2e/isfb/BUILD @@ -240,7 +240,6 @@ _ISFB_CONTRAINT_TESTS = { "//sw/device/lib/base:status", "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/lib:boot_log", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:retention_sram", "//sw/device/silicon_creator/lib/ownership:datatypes", ], diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 2b86fe98f2648..0faaee460e2d3 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -3355,7 +3355,6 @@ cc_library( "//sw/device/lib/base:mmio", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", @@ -4513,13 +4512,11 @@ cc_library( deps = [ "//sw/device/lib/base:mmio", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/runtime:irq", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:aon_timer_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:pwrmgr_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing:rv_plic_testutils", @@ -5666,15 +5663,7 @@ opentitan_test( "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - ] + opentitan_select_top( - { - "earlgrey": [ - "//sw/device/lib/dif:flash_ctrl", - "//sw/device/lib/testing:flash_ctrl_testutils", - ], - }, - [], - ), + ], ) opentitan_test( @@ -6524,7 +6513,6 @@ test_suite( "//sw/device/lib/base:mmio", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", @@ -6535,7 +6523,6 @@ test_suite( "//sw/device/lib/runtime:log", "//sw/device/lib/testing:alert_handler_testutils", "//sw/device/lib/testing:aon_timer_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing:pwrmgr_testutils", "//sw/device/lib/testing:rstmgr_testutils", diff --git a/sw/device/tests/crypto/BUILD b/sw/device/tests/crypto/BUILD index 8dc567497479c..375352a174630 100644 --- a/sw/device/tests/crypto/BUILD +++ b/sw/device/tests/crypto/BUILD @@ -289,7 +289,6 @@ opentitan_test( "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/lib/base:util", "//sw/device/silicon_creator/lib/cert:dice_keys", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/manuf/base:perso_tlv_data", "//sw/device/silicon_creator/manuf/lib:nvm_info_field", ], diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index bd29f8335fb21..c6e160f1df97f 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -435,14 +435,12 @@ opentitan_test( "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:mmio", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:sysrst_ctrl", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:aon_timer_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:nv_counter_testutils", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing:pwrmgr_testutils", @@ -462,7 +460,6 @@ opentitan_test( "//sw/device/lib/base:mmio", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:aon_timer", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", @@ -472,7 +469,6 @@ opentitan_test( "//sw/device/lib/runtime:log", "//sw/device/lib/testing:alert_handler_testutils", "//sw/device/lib/testing:aon_timer_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:nv_counter_testutils", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing:pwrmgr_testutils", @@ -597,14 +593,12 @@ opentitan_test( "//hw/top:aon_timer_c_regs", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:sysrst_ctrl", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:aon_timer_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:nv_counter_testutils", "//sw/device/lib/testing:pwrmgr_testutils", "//sw/device/lib/testing:rstmgr_testutils", diff --git a/sw/host/ot_hal/bindgen/BUILD b/sw/host/ot_hal/bindgen/BUILD index 85596f58c9022..6e850223933cd 100644 --- a/sw/host/ot_hal/bindgen/BUILD +++ b/sw/host/ot_hal/bindgen/BUILD @@ -29,7 +29,6 @@ _EARLGREY_DEPS = [ "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:i2c", @@ -40,6 +39,7 @@ _EARLGREY_DEPS = [ "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwrmgr", + "//sw/device/lib/dif:rram_ctrl", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:rv_timer", "//sw/device/lib/dif:sensor_ctrl", @@ -91,7 +91,6 @@ rust_bindgen_library( "--allowlist-type=dif_lc_ctrl_token", "--allowlist-var=EDN_.*_REG_OFFSET", "--allowlist-var=ENTROPY_SRC_.*_REG_OFFSET", - "--allowlist-var=FLASH_CTRL_.*_REG_OFFSET", "--allowlist-var=GPIO_.*_REG_OFFSET", "--allowlist-var=HMAC_.*_REG_OFFSET", "--allowlist-var=I2C_.*_REG_OFFSET", @@ -107,6 +106,7 @@ rust_bindgen_library( "--allowlist-var=PINMUX_.*_REG_OFFSET", "--allowlist-var=PINMUX_.*_BIT", "--allowlist-var=PWRMGR_.*_REG_OFFSET", + "--allowlist-var=RRAM_CTRL_.*_REG_OFFSET", "--allowlist-type=dif_rstmgr_reset_info", "--allowlist-var=RSTMGR_.*_OFFSET", "--allowlist-var=RSTMGR_.*_BIT", diff --git a/sw/host/ot_hal/bindgen/difs.h b/sw/host/ot_hal/bindgen/difs.h index 590be237d3fee..1419cc549658b 100644 --- a/sw/host/ot_hal/bindgen/difs.h +++ b/sw/host/ot_hal/bindgen/difs.h @@ -29,7 +29,6 @@ #include "hw/top/csrng_regs.h" // Generated. #include "hw/top/edn_regs.h" // Generated. #include "hw/top/entropy_src_regs.h" // Generated. -#include "hw/top/flash_ctrl_regs.h" // Generated. #include "hw/top/gpio_regs.h" // Generated. #include "hw/top/hmac_regs.h" // Generated. #include "hw/top/i2c_regs.h" // Generated. @@ -40,6 +39,7 @@ #include "hw/top/otp_ctrl_regs.h" // Generated. #include "hw/top/pinmux_regs.h" // Generated. #include "hw/top/pwrmgr_regs.h" // Generated. +#include "hw/top/rram_ctrl_regs.h" // Generated. #include "hw/top/rstmgr_regs.h" // Generated. #include "hw/top/rv_timer_regs.h" // Generated. #include "hw/top/sensor_ctrl_regs.h" // Generated. diff --git a/sw/host/tests/chip/rv_dm/src/csr_rw.rs b/sw/host/tests/chip/rv_dm/src/csr_rw.rs index 480b712e4bc61..cde3ec511f52e 100644 --- a/sw/host/tests/chip/rv_dm/src/csr_rw.rs +++ b/sw/host/tests/chip/rv_dm/src/csr_rw.rs @@ -114,11 +114,6 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> { top_earlgrey::ENTROPY_SRC_BASE_ADDR, dif::ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, ), - ( - "flash_ctrl", - top_earlgrey::FLASH_CTRL_CORE_BASE_ADDR, - dif::FLASH_CTRL_INTR_ENABLE_REG_OFFSET, - ), ( "gpio", top_earlgrey::GPIO_BASE_ADDR, @@ -175,6 +170,11 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> { dif::PWRMGR_INTR_ENABLE_REG_OFFSET, ), // Skip ROM_CTRL which does not have RW registers + ( + "rram_ctrl", + top_earlgrey::RRAM_CTRL_CORE_BASE_ADDR, + dif::RRAM_CTRL_INTR_ENABLE_REG_OFFSET, + ), ( "rstmgr", top_earlgrey::RSTMGR_BASE_ADDR, diff --git a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs index 7a5a0dbbcf9f0..98a208964e59d 100644 --- a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs +++ b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs @@ -47,9 +47,9 @@ struct Opts { #[arg(long, value_parser = u8::from_str, default_value = "0x09")] jedec_product: u8, - /// Size of the internal flash. - #[arg(long, value_parser = u32::from_str, default_value = "0x100000")] - flash_size: u32, + /// Size of the internal NVM. + #[arg(long, value_parser = u32::from_str, default_value = "0x200000")] + nvm_size: u32, } /// A struct for isolating individual test points. @@ -172,7 +172,7 @@ fn test_jedec_id(opts: &Opts, transport: &TransportWrapper) -> Result<()> { assert_eq!(page, opts.jedec_page); assert_eq!(manufacturer, opts.jedec_id); assert_eq!(product, opts.jedec_product); - assert_eq!(1u32 << density, opts.flash_size); + assert_eq!(1u32 << density, opts.nvm_size); Ok(()) } @@ -234,7 +234,7 @@ fn test_sfdp(opts: &Opts, transport: &TransportWrapper) -> Result<()> { assert_eq!(sfdp.jedec.support_fast_read_114, false); assert_eq!(sfdp.jedec.support_fast_read_222, false); assert_eq!(sfdp.jedec.support_fast_read_444, false); - assert_eq!(sfdp.jedec.density, opts.flash_size); + assert_eq!(sfdp.jedec.density, opts.nvm_size); assert_eq!(sfdp.jedec.erase[0].size, 4096); assert_eq!(sfdp.jedec.erase[0].opcode, 0x20); From 71ad8a89383bf3d2701c44dd635eff6da3bdf652 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 16:15:07 +0200 Subject: [PATCH 08/24] [sw,alert] manual alert/interrupt changes Removing flash_ctrl removes 5 alerts and 6 interrupts. Signed-off-by: Michael Gautschi --- .../lib/dif/dif_alert_handler_unittest.cc | 2 +- sw/device/lib/dif/dif_rv_plic_unittest.cc | 6 +- .../json/pentest_lib_commands.h | 2 +- sw/host/opentitanlib/src/otp/alert_handler.rs | 12 +- .../src/otp/alert_handler_regs.rs | 627 ++++++++---------- .../python/util/common_library.py | 32 - .../testvectors/data/fi_asym_cryptolib.json | 4 +- .../testvectors/data/fi_crypto.json | 4 +- .../testvectors/data/fi_ibex.json | 12 +- .../testvectors/data/fi_lc_ctrl.json | 4 +- .../testvectors/data/fi_otbn.json | 4 +- .../testvectors/data/fi_otp.json | 4 +- .../testvectors/data/fi_rng.json | 16 +- .../testvectors/data/fi_rom.json | 4 +- .../testvectors/data/fi_sym_cryptolib.json | 4 +- 15 files changed, 320 insertions(+), 417 deletions(-) diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc index 6e7893623fd7f..629a1f41ec0f2 100644 --- a/sw/device/lib/dif/dif_alert_handler_unittest.cc +++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc @@ -30,7 +30,7 @@ using ::testing::Return; // so if the number of alerts change, the digest will be changed // as well. This process is not yet automated, so the user // must be aware on how to update the value. -static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 69, +static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 64, "The number of alerts have changed."); constexpr int kAlerts = ALERT_HANDLER_PARAM_N_ALERTS; diff --git a/sw/device/lib/dif/dif_rv_plic_unittest.cc b/sw/device/lib/dif/dif_rv_plic_unittest.cc index 59924a8b8271b..a9fcd2c83651d 100644 --- a/sw/device/lib/dif/dif_rv_plic_unittest.cc +++ b/sw/device/lib/dif/dif_rv_plic_unittest.cc @@ -21,7 +21,7 @@ using testing::Test; // If either of these static assertions fail, then the unit-tests for related // API should be revisited. -static_assert(RV_PLIC_PARAM_NUM_SRC == 190, +static_assert(RV_PLIC_PARAM_NUM_SRC == 184, "PLIC instantiation parameters have changed."); static_assert(RV_PLIC_PARAM_NUM_TARGET == 1, "PLIC instantiation parameters have changed."); @@ -100,7 +100,7 @@ class IrqTest : public PlicTest { {RV_PLIC_IE0_2_REG_OFFSET, RV_PLIC_IE0_2_E_95_BIT}, {RV_PLIC_IE0_3_REG_OFFSET, RV_PLIC_IE0_3_E_127_BIT}, {RV_PLIC_IE0_4_REG_OFFSET, RV_PLIC_IE0_4_E_159_BIT}, - {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_189_BIT}, + {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_183_BIT}, }}; static constexpr std::array kPendingRegisters{{ @@ -109,7 +109,7 @@ class IrqTest : public PlicTest { {RV_PLIC_IP_2_REG_OFFSET, RV_PLIC_IP_2_P_95_BIT}, {RV_PLIC_IP_3_REG_OFFSET, RV_PLIC_IP_3_P_127_BIT}, {RV_PLIC_IP_4_REG_OFFSET, RV_PLIC_IP_4_P_159_BIT}, - {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_189_BIT}, + {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_183_BIT}, }}; // Set enable/disable multireg expectations, one bit per call. diff --git a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h index 7bbae67c10338..b42f61ba03da1 100644 --- a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h +++ b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h @@ -14,7 +14,7 @@ extern "C" { #define MODULE_ID MAKE_MODULE_ID('j', 'p', 'c') -#define ALERT_HANDLER_PARAM_N_ALERTS 69 +#define ALERT_HANDLER_PARAM_N_ALERTS 64 #define ALERT_HANDLER_PARAM_N_CLASSES 4 #define SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS 11 #define ALERT_HANDLER_PARAM_N_PHASES 4 diff --git a/sw/host/opentitanlib/src/otp/alert_handler.rs b/sw/host/opentitanlib/src/otp/alert_handler.rs index 17b7074454a42..a0b66d725fbed 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler.rs @@ -373,7 +373,7 @@ mod test { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, - 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, ], en: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -385,7 +385,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, ], class: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -397,7 +397,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, ], loc_regwen: [ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, @@ -512,7 +512,7 @@ mod test { #[test] fn test_crc_from_regs() { - assert_eq!(TEST_REGS.crc32(), 0x3d61fdac); + assert_eq!(TEST_REGS.crc32(), 0x1391a65e); } #[test] @@ -529,7 +529,7 @@ mod test { AlertRegs::try_new(LcStateVal::Dev, &TestOtpAlertsDisabled {}) .unwrap() .crc32(), - 0x3d61fdac + 0x1391a65e ); } @@ -539,7 +539,7 @@ mod test { AlertRegs::try_new(LcStateVal::Dev, &TestOtpAlertsEnabled {}) .unwrap() .crc32(), - 0x921b579a + 0xbceb0c68 ); } } diff --git a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs index a7cd8797aac90..22cff2b2ab4cf 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs @@ -7,7 +7,7 @@ /* automatically generated by rust-bindgen 0.72.1 */ -pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 69; +pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 64; pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 24; pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5; pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32; @@ -61,7 +61,7 @@ pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 69; +pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 64; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; @@ -254,233 +254,203 @@ pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: u32 = 276; pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280; -pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET: u32 = 284; -pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_REGWEN_66_REG_OFFSET: u32 = 288; -pub const ALERT_HANDLER_ALERT_REGWEN_66_REG_RESVAL: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_66_EN_66_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_REGWEN_67_REG_OFFSET: u32 = 292; -pub const ALERT_HANDLER_ALERT_REGWEN_67_REG_RESVAL: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_67_EN_67_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_REGWEN_68_REG_OFFSET: u32 = 296; -pub const ALERT_HANDLER_ALERT_REGWEN_68_REG_RESVAL: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_68_EN_68_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 69; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 300; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 64; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 280; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 304; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 284; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 308; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 288; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 312; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 292; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 316; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 296; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 320; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 300; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 324; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 304; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 328; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 308; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 332; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 312; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 336; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 316; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 340; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 320; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 344; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 324; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 348; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 328; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 352; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 332; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 356; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 336; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 360; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 340; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 364; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 344; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 368; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 348; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 372; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 352; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 376; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 356; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 380; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 360; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 384; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 364; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 388; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 368; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 392; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 372; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 396; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 376; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 400; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 380; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 404; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 384; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 408; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 388; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 412; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 392; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 416; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 396; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 420; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 400; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 424; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 404; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 428; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 408; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 432; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 412; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 436; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 416; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 440; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 420; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 444; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 424; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 448; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 428; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 452; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 432; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 456; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 436; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 460; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 440; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 464; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 444; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 468; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 448; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 472; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 452; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 476; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 456; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 480; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 460; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 484; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 464; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 488; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 468; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 492; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 472; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 496; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 476; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 500; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 480; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 504; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 484; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 508; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 488; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 512; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 492; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 516; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 496; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 520; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 500; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 524; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 504; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 528; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 508; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 532; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 512; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 536; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 516; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 540; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 520; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 544; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 524; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 548; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 528; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 552; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 532; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 556; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET: u32 = 560; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_OFFSET: u32 = 564; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_EN_A_66_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_OFFSET: u32 = 568; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_EN_A_67_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_OFFSET: u32 = 572; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_EN_A_68_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 69; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 576; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 64; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 536; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0; @@ -488,536 +458,501 @@ pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 580; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 540; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 584; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 544; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 588; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 548; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 592; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 552; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 596; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 556; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 600; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 560; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 604; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 564; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 608; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 568; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 612; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 572; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 616; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 576; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 620; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 580; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 624; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 584; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 628; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 588; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 632; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 592; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 636; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 596; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 640; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 600; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 644; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 604; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 648; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 608; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 652; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 612; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 656; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 616; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 660; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 620; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 664; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 624; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 668; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 628; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 672; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 632; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 676; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 636; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 680; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 640; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 684; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 644; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 688; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 648; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 692; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 652; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 696; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 656; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 700; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 660; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 704; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 664; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 708; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 668; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 712; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 672; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 716; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 676; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 720; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 680; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 724; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 684; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 728; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 688; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 732; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 692; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 736; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 696; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 740; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 700; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 744; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 704; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 748; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 708; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 752; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 712; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 756; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 716; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 760; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 720; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 764; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 724; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 768; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 728; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 772; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 732; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 776; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 736; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 780; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 740; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 784; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 744; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 788; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 748; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 792; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 752; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 796; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 756; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 800; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 760; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 804; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 764; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 808; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 768; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 812; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 772; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 816; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 776; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 820; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 780; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 824; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 784; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 828; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 788; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 832; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET: u32 = 836; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_OFFSET: u32 = 840; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_OFFSET: u32 = 844; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_OFFSET: u32 = 848; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 69; -pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 852; +pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 64; +pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 792; pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 856; +pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 796; pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 860; +pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 800; pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 864; +pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 804; pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 868; +pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 808; pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 872; +pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 812; pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 876; +pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 816; pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 880; +pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 820; pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 884; +pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 824; pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 888; +pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 828; pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 892; +pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 832; pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 896; +pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 836; pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 900; +pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 840; pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 904; +pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 844; pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 908; +pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 848; pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 912; +pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 852; pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 916; +pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 856; pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 920; +pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 860; pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 924; +pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 864; pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 928; +pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 868; pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 932; +pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 872; pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 936; +pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 876; pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 940; +pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 880; pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 944; +pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 884; pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 948; +pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 888; pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 952; +pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 892; pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 956; +pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 896; pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 960; +pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 900; pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 964; +pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 904; pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 968; +pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 908; pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 972; +pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 912; pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 976; +pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 916; pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 980; +pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 920; pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 984; +pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 924; pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 988; +pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 928; pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 992; +pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 932; pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 996; +pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 936; pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 1000; +pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 940; pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 1004; +pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 944; pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 1008; +pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 948; pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 1012; +pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 952; pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 1016; +pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 956; pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 1020; +pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 960; pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 1024; +pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 964; pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 1028; +pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 968; pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 1032; +pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 972; pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 1036; +pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 976; pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 1040; +pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 980; pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 1044; +pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 984; pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1048; +pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 988; pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1052; +pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 992; pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1056; +pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 996; pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1060; +pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1000; pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1064; +pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1004; pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1068; +pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1008; pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1072; +pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1012; pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1076; +pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1016; pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1080; +pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1020; pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1084; +pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1024; pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1088; +pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1028; pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1092; +pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1032; pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1096; +pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1036; pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1100; +pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1040; pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1104; +pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1044; pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1108; -pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET: u32 = 1112; -pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_66_REG_OFFSET: u32 = 1116; -pub const ALERT_HANDLER_ALERT_CAUSE_66_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_66_A_66_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_67_REG_OFFSET: u32 = 1120; -pub const ALERT_HANDLER_ALERT_CAUSE_67_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_67_A_67_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_68_REG_OFFSET: u32 = 1124; -pub const ALERT_HANDLER_ALERT_CAUSE_68_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_68_A_68_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1128; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1048; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1132; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1052; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1136; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1056; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1140; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1060; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1144; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1064; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1148; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1068; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1152; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1072; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1156; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1076; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1160; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1080; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1164; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1084; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1168; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1088; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1172; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1092; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1176; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1096; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1180; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1100; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1184; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1104; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0; @@ -1025,57 +960,57 @@ pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1188; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1108; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1192; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1112; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1196; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1116; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1200; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1120; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1204; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1124; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1208; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1128; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1212; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1132; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1216; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1136; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1220; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1140; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1224; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1144; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1228; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1148; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1232; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1152; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1236; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1156; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1240; +pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1160; pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1244; +pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1164; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1091,38 +1026,38 @@ pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1248; +pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1168; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1252; +pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1172; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1256; +pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1176; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1260; +pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1180; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1264; +pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1184; pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1268; +pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1188; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1272; +pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1192; pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1276; +pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1196; pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1280; +pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1200; pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1284; +pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1204; pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1288; +pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1208; pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1292; +pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1212; pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0; @@ -1134,10 +1069,10 @@ pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1296; +pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1216; pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1300; +pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1220; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1153,38 +1088,38 @@ pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1304; +pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1224; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1308; +pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1228; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1312; +pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1232; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1316; +pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1236; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1320; +pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1240; pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1324; +pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1244; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1328; +pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1248; pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1332; +pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1252; pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1336; +pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1256; pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1340; +pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1260; pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1344; +pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1264; pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1348; +pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1268; pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0; @@ -1196,10 +1131,10 @@ pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1352; +pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1272; pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1356; +pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1276; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1215,38 +1150,38 @@ pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1360; +pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1280; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1364; +pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1284; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1368; +pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1288; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1372; +pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1292; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1376; +pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1296; pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1380; +pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1300; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1384; +pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1304; pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1388; +pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1308; pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1392; +pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1312; pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1396; +pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1316; pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1400; +pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1320; pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1404; +pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1324; pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0; @@ -1258,10 +1193,10 @@ pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1408; +pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1328; pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1412; +pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1332; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1277,38 +1212,38 @@ pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1416; +pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1336; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1420; +pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1340; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1424; +pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1344; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1428; +pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1348; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1432; +pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1352; pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1436; +pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1356; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1440; +pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1360; pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1444; +pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1364; pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1448; +pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1368; pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1452; +pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1372; pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1456; +pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1376; pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1460; +pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1380; pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0; diff --git a/sw/host/penetrationtests/python/util/common_library.py b/sw/host/penetrationtests/python/util/common_library.py index 2f1c6b5f73cbb..8f479d1d2d358 100644 --- a/sw/host/penetrationtests/python/util/common_library.py +++ b/sw/host/penetrationtests/python/util/common_library.py @@ -61,11 +61,6 @@ 1, # "sensor_ctrl_recov_alert", 0, # "sensor_ctrl_fatal_alert", 0, # "sram_ctrl_ret_fatal_error", - 1, # "flash_ctrl_recov_err", - 0, # "flash_ctrl_fatal_std_err", - 0, # "flash_ctrl_fatal_err", - 0, # "flash_ctrl_fatal_prim_flash_alert", - 1, # "flash_ctrl_recov_prim_flash_alert", 1, # "rram_ctrl_recov_err", 0, # "rram_ctrl_fatal_std_err", 0, # "rram_ctrl_fatal_err", @@ -141,11 +136,6 @@ True, # "sensor_ctrl_recov_alert", True, # "sensor_ctrl_fatal_alert", True, # "sram_ctrl_ret_fatal_error", - True, # "flash_ctrl_recov_err", - True, # "flash_ctrl_fatal_std_err", - True, # "flash_ctrl_fatal_err", - True, # "flash_ctrl_fatal_prim_flash_alert", - True, # "flash_ctrl_recov_prim_flash_alert", True, # "rram_ctrl_recov_err", True, # "rram_ctrl_fatal_std_err", True, # "rram_ctrl_fatal_err", @@ -220,11 +210,6 @@ 1, # "sensor_ctrl_recov_alert", 0, # "sensor_ctrl_fatal_alert", 0, # "sram_ctrl_ret_fatal_error", - 1, # "flash_ctrl_recov_err", - 0, # "flash_ctrl_fatal_std_err", - 0, # "flash_ctrl_fatal_err", - 0, # "flash_ctrl_fatal_prim_flash_alert", - 1, # "flash_ctrl_recov_prim_flash_alert", 1, # "rram_ctrl_recov_err", 0, # "rram_ctrl_fatal_std_err", 0, # "rram_ctrl_fatal_err", @@ -291,12 +276,6 @@ True, # "sensor_ctrl_recov_alert", True, # "sensor_ctrl_fatal_alert", True, # "sram_ctrl_ret_fatal_error", - True, # "flash_ctrl_recov_err", - True, # "flash_ctrl_fatal_std_err", - # On FPGA, this alert always raised, so leave it off - False, # "flash_ctrl_fatal_err", - True, # "flash_ctrl_fatal_prim_flash_alert", - True, # "flash_ctrl_recov_prim_flash_alert", True, # "rram_ctrl_recov_err", True, # "rram_ctrl_fatal_std_err", True, # "rram_ctrl_fatal_err", @@ -380,11 +359,6 @@ 1, # "sensor_ctrl_recov_alert", 0, # "sensor_ctrl_fatal_alert", 0, # "sram_ctrl_ret_fatal_error", - 1, # "flash_ctrl_recov_err", - 0, # "flash_ctrl_fatal_std_err", - 0, # "flash_ctrl_fatal_err", - 0, # "flash_ctrl_fatal_prim_flash_alert", - 1, # "flash_ctrl_recov_prim_flash_alert", 1, # "rram_ctrl_recov_err", 0, # "rram_ctrl_fatal_std_err", 0, # "rram_ctrl_fatal_err", @@ -451,12 +425,6 @@ True, # "sensor_ctrl_recov_alert", True, # "sensor_ctrl_fatal_alert", True, # "sram_ctrl_ret_fatal_error", - True, # "flash_ctrl_recov_err", - True, # "flash_ctrl_fatal_std_err", - # On FPGA, this alert always raised, so leave it off - False, # "flash_ctrl_fatal_err", - True, # "flash_ctrl_fatal_prim_flash_alert", - True, # "flash_ctrl_recov_prim_flash_alert", True, # "rram_ctrl_recov_err", True, # "rram_ctrl_fatal_std_err", True, # "rram_ctrl_fatal_err", diff --git a/sw/host/penetrationtests/testvectors/data/fi_asym_cryptolib.json b/sw/host/penetrationtests/testvectors/data/fi_asym_cryptolib.json index 7b037614f204e..d3273cf4f458c 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_asym_cryptolib.json +++ b/sw/host/penetrationtests/testvectors/data/fi_asym_cryptolib.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_crypto.json b/sw/host/penetrationtests/testvectors/data/fi_crypto.json index addcb947fc6a8..d57f0b23a1b24 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_crypto.json +++ b/sw/host/penetrationtests/testvectors/data/fi_crypto.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_ibex.json b/sw/host/penetrationtests/testvectors/data/fi_ibex.json index 23f5e5d0868e4..c122a9b2a4bf0 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_ibex.json +++ b/sw/host/penetrationtests/testvectors/data/fi_ibex.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", @@ -203,11 +203,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", @@ -229,11 +229,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_lc_ctrl.json b/sw/host/penetrationtests/testvectors/data/fi_lc_ctrl.json index f7a4da70dd0a4..109084fe3b55c 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_lc_ctrl.json +++ b/sw/host/penetrationtests/testvectors/data/fi_lc_ctrl.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_otbn.json b/sw/host/penetrationtests/testvectors/data/fi_otbn.json index c307b242407dd..0cde401306173 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_otbn.json +++ b/sw/host/penetrationtests/testvectors/data/fi_otbn.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_otp.json b/sw/host/penetrationtests/testvectors/data/fi_otp.json index 9e6fba250ebbd..4b46bd1c3cbda 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_otp.json +++ b/sw/host/penetrationtests/testvectors/data/fi_otp.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_rng.json b/sw/host/penetrationtests/testvectors/data/fi_rng.json index 42559e200df31..c12da44f4ec8d 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_rng.json +++ b/sw/host/penetrationtests/testvectors/data/fi_rng.json @@ -4,11 +4,11 @@ "command": "CsrngInit", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", @@ -30,11 +30,11 @@ "command": "EdnInit", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", @@ -60,11 +60,11 @@ "command": "EdnInit", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", @@ -86,11 +86,11 @@ "command": "EdnInit", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_rom.json b/sw/host/penetrationtests/testvectors/data/fi_rom.json index c367fad84806a..3cb1302d04064 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_rom.json +++ b/sw/host/penetrationtests/testvectors/data/fi_rom.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", diff --git a/sw/host/penetrationtests/testvectors/data/fi_sym_cryptolib.json b/sw/host/penetrationtests/testvectors/data/fi_sym_cryptolib.json index 7cc7d1152e14c..b55722b87f182 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_sym_cryptolib.json +++ b/sw/host/penetrationtests/testvectors/data/fi_sym_cryptolib.json @@ -4,11 +4,11 @@ "command": "Init", "input": "{\"enable_icache\": true,\"enable_dummy_instr\": true,\"dummy_instr_count\": 3,\"enable_jittery_clock\": true,\"enable_sram_readback\": true, \"enable_data_ind_timing\": true}", "sensors": "{\"sensor_ctrl_enable\": true, \"sensor_ctrl_en_fatal\": [false, false, false, false, false, false, false, false, false, false, false]}", - "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,false,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", + "alerts":"{\"alert_classes\":[2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"enable_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enable_loc_alerts\": [true, true, true, true, true, true, true], \"enable_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"signals\": [4294967295, 0, 2, 3], \"duration_cycles\": [0, 2400000,48,48], \"ping_timeout\": 1200}", "expected_output": [ "{\"device_id\":[0,0,0,0,0,0,0,0],\"icache_en\":true,\"dummy_instr_en\":true,\"clock_jitter_locked\":false,\"clock_jitter_en\":true,\"sram_main_readback_locked\":false,\"sram_main_readback_en\":true,\"sram_ret_readback_locked\":false,\"sram_ret_readback_en\":true, \"data_ind_timing_en\": true}", "{\"sensor_ctrl_en\": [true,true,true,true,true,true,true,true,true,true,true], \"sensor_ctrl_fatal\": [false,false,false,false,false,false,false,false,false,false,false]}", - "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,2,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", + "{\"alert_classes\": [2,2,2,2,0,0,2,2,2,0,0,0,0,0,1,0,0,0,2,2,2,0,0,0,1,0,2,2,2,0,1,0,0,1,0,0,0,1,0,0,1,0,0,1,0,0,1,1,0,1,0,1,0,1,0,1,0,0,0,0,0,1,0,1], \"loc_alert_classes\": [0,0,0,0,0,0,0], \"enabled_alerts\": [true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true,true], \"enabled_loc_alerts\": [true, true, true, true, true, true, true], \"enabled_classes\": [true,true,false,false], \"accumulation_thresholds\": [2,2,2,2], \"duration_cycles\": [0, 2400000,48,48], \"escalation_signals_en\": [true,false,true,true], \"escalation_signals_map\": [1, 0, 2, 3]}", "{\"config_version\":1,\"sram_exec_mode\":0,\"ownership_key_alg\":0,\"update_mode\":0,\"min_security_version_bl0\":0,\"lock_constraint\":0}", "{\"digest\":[0,0,0,0,0,0,0,0],\"identifier\":0,\"scm_revision_low\":0,\"scm_revision_high\":0,\"rom_ext_slot\":0,\"rom_ext_major\":0,\"rom_ext_minor\":1,\"rom_ext_size\":0,\"bl0_slot\":0,\"ownership_state\":0,\"ownership_transfers\":0,\"rom_ext_min_sec_ver\":0,\"bl0_min_sec_ver\":0,\"primary_bl0_slot\":16000078145,\"retention_ram_initialized\":0}", "{\"bl0\":[0,0,0,0,0,0,0,0],\"rom_ext\":[0,0,0,0,0,0,0,0]}", From 813d98083d7396e5c1c1f392a7cf30b0cfa46914 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 16:38:40 +0200 Subject: [PATCH 09/24] [dv,earlgrey] port functionality from flash to RRAM Signed-off-by: Michael Gautschi --- hw/top_earlgrey/dv/env/chip_env_pkg.sv | 9 ++--- .../dv/env/seq_lib/chip_base_vseq.sv | 3 +- .../chip_sw_ate_bootstrap_disjoint_vseq.sv | 33 +++++-------------- .../chip_sw_ate_bootstrap_flash_erase_vseq.sv | 2 +- .../chip_sw_ate_bootstrap_one_frame_vseq.sv | 6 ++-- .../dv/env/seq_lib/chip_sw_base_vseq.sv | 21 +++++------- .../seq_lib/chip_sw_lc_walkthrough_vseq.sv | 4 +-- ...ip_sw_rv_core_ibex_lockstep_glitch_vseq.sv | 2 +- 8 files changed, 27 insertions(+), 53 deletions(-) diff --git a/hw/top_earlgrey/dv/env/chip_env_pkg.sv b/hw/top_earlgrey/dv/env/chip_env_pkg.sv index a025e4e104d51..70ff0458fa320 100644 --- a/hw/top_earlgrey/dv/env/chip_env_pkg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_pkg.sv @@ -19,7 +19,6 @@ package chip_env_pkg; import dv_base_reg_pkg::*; import dv_lib_pkg::*; import dv_utils_pkg::*; - import flash_ctrl_pkg::*; import jtag_pkg::*; import jtag_agent_pkg::*; import jtag_riscv_agent_pkg::*; @@ -79,10 +78,6 @@ package chip_env_pkg; // RAM instances have support for up to 16 tiles. Actual number of tiles in use in the design is a // runtime setting in chip_env_cfg. typedef enum { - FlashBank0Data, - FlashBank1Data, - FlashBank0Info, - FlashBank1Info, RramData, RramInfo, ICacheWay0Tag, @@ -104,8 +99,8 @@ package chip_env_pkg; // Note: If this enum is updated, then also update the file `build_sw_collateral_for_sim.py`. typedef enum { SwTypeRom = 0, // Ibex SW - first stage boot ROM. - SwTypeTestSlotA = 1, // Ibex SW - test SW in (flash) slot A. - SwTypeTestSlotB = 2, // Ibex SW - test SW in (flash) slot B. + SwTypeTestSlotA = 1, // Ibex SW - test SW in (NVM) slot A. + SwTypeTestSlotB = 2, // Ibex SW - test SW in (NVM) slot B. SwTypeOtbn = 3, // Otbn SW SwTypeOtp = 4, // Customized OTP image SwTypeDebug = 5 // Debug SW - injected into SRAM. diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv index 4a05fa675542b..a228f458ef54c 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv @@ -157,8 +157,7 @@ class chip_base_vseq #( cfg.chip_vif.enable_spi_host = 1; // Initialize all memories via backdoor. - cfg.mem_bkdr_util_h[FlashBank0Info].set_mem(); - cfg.mem_bkdr_util_h[FlashBank1Info].set_mem(); + cfg.mem_bkdr_util_h[RramInfo].clear_mem(); // Backdoor load the OTP image. cfg.mem_bkdr_util_h[Otp].load_mem_from_file(cfg.otp_images[cfg.use_otp_image]); // Plusargs to selectively clear the provisioning state of some of the OTP partitions. diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv index e5933eadfbdf3..3224ed3ee01b8 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv @@ -119,34 +119,17 @@ class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; end endfunction - // Extract a SW flash address into a bank index and address within the bank - // - // The address is from the SW point of view, which is actually governed by the rom_ext slot - // addresses in ../../../defs.bzl. That mapping is replicated here, and we expect: - // - // - Slot A addresses 0x00000 - 0x7ffff - // - Slot B addresses 0x80000 - 0xfffff + // Extract a SW flash address into a relative address within RRAM's (single, unified) data + // partition. // + // Unlike flash, which backed slots A and B with two separate physical banks, RRAM backs both + // slots with one contiguous region, so the SW address maps onto it directly with no per-slot + // offset. The out-of-range case is handled by the depth check at the call site below. local function bit expand_flash_address(int unsigned address, output int unsigned rel_address, output chip_mem_e mem_idx); - // Do we fit in slot A? - if (address < 'h80000) begin - rel_address = address; - mem_idx = FlashBank0Data; - return 1'b1; - end - - // We didn't fit in slot A. Do we fit in slot B? - if (address < 'hfffff) begin - rel_address = address - 'h80000; - mem_idx = FlashBank1Data; - return 1'b1; - end - - // We have run out of slots. Set the indices to something invalid and return 0. - rel_address = '1; - mem_idx = chip_mem_e'('1); - return 1'b0; + mem_idx = RramData; + rel_address = address; + return 1'b1; endfunction endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv index bf9eb41e4d518..3c5992b669ba1 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv @@ -16,7 +16,7 @@ class chip_sw_ate_bootstrap_flash_erase_vseq extends chip_sw_base_vseq; local function automatic void _check_flash_data_page(input int unsigned address, input bit [31:0] expected); logic [TL_DW-1:0] actual; - actual = cfg.mem_bkdr_util_h[FlashBank0Data].read32(address); + actual = cfg.mem_bkdr_util_h[RramData].read32(address); `DV_CHECK_EQ(actual, expected) endfunction diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv index 68a8f0987c27d..7b9e4898192c5 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv @@ -13,7 +13,7 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; local function automatic void _check_flash_data_page(input integer address, input integer expected); logic [TL_DW-1:0] actual; - actual = cfg.mem_bkdr_util_h[FlashBank0Data].read32(address); + actual = cfg.mem_bkdr_util_h[RramData].read32(address); `DV_CHECK_EQ(actual, expected) endfunction @@ -69,13 +69,13 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; // mismatch, generate a uvm_error describing the mismatch and return false. // local function bit check_flash_word_32(int unsigned address, bit [31:0] expected); - logic [31:0] actual = cfg.mem_bkdr_util_h[FlashBank0Data].read32(address); + logic [31:0] actual = cfg.mem_bkdr_util_h[RramData].read32(address); if (actual === expected) begin return 1'b1; end else begin `uvm_error(get_name(), - $sformatf({"Flash data mismatch at 0x%0h (in FlashBank0Data). ", + $sformatf({"Flash data mismatch at 0x%0h (in RramData). ", "We expected 0x%0h but saw 0x%0h."}, address, expected, actual)) return 1'b0; diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv index e60bd7f283537..2f30576460fd0 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv @@ -90,11 +90,6 @@ class chip_sw_base_vseq extends chip_base_vseq; main_sram_bkdr_write32(addr, rand_val); end - // Initialize the data partition in all flash banks to all 1s. - `uvm_info(`gfn, "Initializing flash banks (data partition only)", UVM_MEDIUM) - cfg.mem_bkdr_util_h[FlashBank0Data].set_mem(); - cfg.mem_bkdr_util_h[FlashBank1Data].set_mem(); - // Initialize the info and data partition of the RRAM to all 0s. cfg.mem_bkdr_util_h[RramInfo].clear_mem(); cfg.mem_bkdr_util_h[RramData].clear_mem(); @@ -714,7 +709,7 @@ class chip_sw_base_vseq extends chip_base_vseq; // Infer mem from address. `DV_CHECK(cfg.get_mem_from_addr(addr, mem)) - `DV_CHECK_FATAL(mem inside {Rom, [RamMain0:RamMain15], RramData, FlashBank0Data, FlashBank1Data}, + `DV_CHECK_FATAL(mem inside {Rom, [RamMain0:RamMain15], RramData}, $sformatf("SW symbol %0s is not expected to appear in %0s mem", symbol, mem)) addr_mask = (2**$clog2(cfg.mem_bkdr_util_h[mem].get_size_bytes()))-1; @@ -1302,21 +1297,23 @@ class chip_sw_base_vseq extends chip_base_vseq; endtask : push_button // This task can be called, when rma is requested by lc_ctrl. - // Before rma wipe for data partition started (256 pages), - // this task force total page to 9 pages. So rma process is completed faster. + // Before rma wipe for the data partition starts (4091 pages -- see the last entry of + // rram_ctrl_pkg::RmaWipeEntries), this task forces the wipe's end_page down to 2 pages, so the + // rma process completes faster. virtual task enable_small_rma(); - string path = "tb.dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_flash_hw_if"; + string path = "tb.dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl.u_rram_ctrl_lcmgr"; string mypath; - logic [2:0] rma_wipe_idx; + logic [1:0] rma_wipe_idx; logic [3:0] rma_ack; - // Wait for data partition rma. + // Wait for the data-partition entry -- the last of the 4 RmaWipeEntries (info pages are + // entries 0-2; the data partition, the big one, is entry 3 == MaxWipeEntry). mypath = {path, ".rma_wipe_idx"}; `DV_SPINWAIT( do begin @(cfg.clk_rst_vif.cb); `DV_CHECK_EQ(uvm_hdl_read(mypath, rma_wipe_idx), 1, "hdl read failure") - end while (rma_wipe_idx != 3'h3);, + end while (rma_wipe_idx != 2'h3);, "waiting for rma index = 3", 100_000_000 ) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_walkthrough_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_walkthrough_vseq.sv index 2e17808ce255f..329a844e172f4 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_walkthrough_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_walkthrough_vseq.sv @@ -104,8 +104,8 @@ class chip_sw_lc_walkthrough_vseq extends chip_sw_base_vseq; virtual task reload_flash_after_rma_transfer(); bit [7:0] selected_dest_state[]; selected_dest_state = {dest_dec_state}; - cfg.mem_bkdr_util_h[FlashBank0Data].load_mem_from_file( - {cfg.sw_images[SwTypeTestSlotA], ".64.scr.vmem"}); + cfg.mem_bkdr_util_h[RramData].load_mem_from_file( + {cfg.sw_images[SwTypeTestSlotA], ".128.scr.vmem"}); sw_symbol_backdoor_overwrite("kDestState", selected_dest_state); endtask endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv index ae3a377de516d..5a70ae92c166c 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv @@ -571,7 +571,7 @@ class chip_sw_rv_core_ibex_lockstep_glitch_vseq extends chip_sw_base_vseq; $assertoff(0, "tb.dut.top_earlgrey.earlgrey_pd_main.u_xbar_main.tlul_assert_device_sram_ctrl_main__ram.gen_host"); $assertoff(0, - "tb.dut.top_earlgrey.earlgrey_pd_main.u_xbar_main.tlul_assert_device_flash_ctrl__mem.gen_host"); + "tb.dut.top_earlgrey.earlgrey_pd_main.u_xbar_main.tlul_assert_device_rram_ctrl__host.gen_host"); end "data_req_o", "data_we_o", From 17f46196c65b7750b71d85907c36900f19e2a842 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 18:38:18 +0200 Subject: [PATCH 10/24] [sw,host,unittests] Disable unittests that depend on mock_flash_ctrl These tests need to be ported to use mock_rram_ctrl instead of mock_flash_ctrl. With flash_ctrl removed, they don't build anymore. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/BUILD | 21 ++++++++++++------- sw/device/silicon_creator/lib/ownership/BUILD | 8 +++++++ sw/device/silicon_creator/lib/rescue/BUILD | 3 +++ sw/device/silicon_creator/lib/sigverify/BUILD | 2 ++ sw/device/silicon_creator/rom/BUILD | 3 +++ sw/device/silicon_creator/rom_ext/BUILD | 4 +++- 6 files changed, 32 insertions(+), 9 deletions(-) diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index bc0143b43920f..7d64d0ea4955c 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -6,7 +6,7 @@ load( "@bazel_skylib//lib:dicts.bzl", "dicts", ) -load("//hw/top:defs.bzl", "ALL_IP_NAMES", "opentitan_alias_top_attr", "opentitan_if_ip", "opentitan_select_top") +load("//hw/top:defs.bzl", "ALL_IP_NAMES", "opentitan_alias_top_attr", "opentitan_if_ip", "opentitan_require_ip", "opentitan_select_top") load("//rules:autogen.bzl", "autogen_build_info") load("//rules:cross_platform.bzl", "dual_cc_device_library_of", "dual_cc_library", "dual_inputs") load("//rules/opentitan:defs.bzl", "OPENTITAN_CPU") @@ -73,6 +73,8 @@ dual_cc_library( cc_test( name = "boot_data_unittest", srcs = ["boot_data_unittest.cc"], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ dual_cc_device_library_of(":boot_data"), "@googletest//:gtest_main", @@ -452,6 +454,8 @@ dual_cc_library( cc_test( name = "shutdown_unittest", srcs = ["shutdown_unittest.cc"], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ dual_cc_device_library_of(":shutdown"), "//hw/top:flash_ctrl_c_regs", @@ -489,6 +493,7 @@ cc_library( name = "bootstrap_fuzzer_util", srcs = ["bootstrap_fuzzer_util.cc"], hdrs = ["bootstrap_fuzzer_util.h"], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:hardened", @@ -505,6 +510,7 @@ cc_library( name = "bootstrap_unittest_util", srcs = ["bootstrap_unittest_util.cc"], hdrs = ["bootstrap_unittest_util.h"], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":bootstrap", "//hw/top:flash_ctrl_c_regs", @@ -547,14 +553,13 @@ dual_cc_library( }, [], ), - # Host tests always build against the flash backend, independent of - # the selected top: existing unit tests (boot_data_unittest, - # flash_ctrl_unittest, rescue_xmodem_unittest, ownership tests, ...) - # mock flash_ctrl directly and predate RRAM support. This keeps them - # passing but means nvm_ctrl.c's RRAM branch has no host unit test - # coverage; it's only exercised by on-device functests/DV. # TODO(#30967): port the silicon_creator host test suite to RRAM. - host = ["USE_FLASH"], + host = opentitan_select_top( + { + "earlgrey": ["USE_RRAM"], + }, + ["USE_FLASH"], + ), ), deps = dual_inputs( # Links whichever backend driver(s) the top actually has, matching diff --git a/sw/device/silicon_creator/lib/ownership/BUILD b/sw/device/silicon_creator/lib/ownership/BUILD index 6c3b6e6f224bf..d03f16eb71c7c 100644 --- a/sw/device/silicon_creator/lib/ownership/BUILD +++ b/sw/device/silicon_creator/lib/ownership/BUILD @@ -2,6 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +load("//hw/top:defs.bzl", "opentitan_require_ip") load( "//rules:cross_platform.bzl", "dual_cc_library", @@ -51,6 +52,7 @@ cc_test( srcs = [ "isfb_unittest.cc", ], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":datatypes", ":isfb", @@ -123,6 +125,8 @@ cc_test( srcs = [ "ownership_unittest.cc", ], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":datatypes", ":ownership", @@ -160,6 +164,8 @@ cc_test( "owner_block_unittest.cc", "testdata/basic_owner_testdata.h", ], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":datatypes", ":owner_block", @@ -232,6 +238,8 @@ cc_test( srcs = [ "ownership_activate_unittest.cc", ], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":datatypes", ":ownership_activate", diff --git a/sw/device/silicon_creator/lib/rescue/BUILD b/sw/device/silicon_creator/lib/rescue/BUILD index 7e041a10107c0..9dd7145fbe795 100644 --- a/sw/device/silicon_creator/lib/rescue/BUILD +++ b/sw/device/silicon_creator/lib/rescue/BUILD @@ -6,6 +6,7 @@ load( "@bazel_skylib//lib:dicts.bzl", "dicts", ) +load("//hw/top:defs.bzl", "opentitan_require_ip") load("//rules:cross_platform.bzl", "dual_cc_device_library_of", "dual_cc_library", "dual_inputs") load( "//rules/opentitan:defs.bzl", @@ -67,6 +68,8 @@ cc_test( "rescue_xmodem.c", "rescue_xmodem_unittest.cc", ], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":rescue", ":xmodem", diff --git a/sw/device/silicon_creator/lib/sigverify/BUILD b/sw/device/silicon_creator/lib/sigverify/BUILD index f927fc614a13e..65a86010f1ac3 100644 --- a/sw/device/silicon_creator/lib/sigverify/BUILD +++ b/sw/device/silicon_creator/lib/sigverify/BUILD @@ -20,6 +20,7 @@ load( "@bazel_skylib//lib:dicts.bzl", "dicts", ) +load("//hw/top:defs.bzl", "opentitan_require_ip") package(default_visibility = ["//visibility:public"]) @@ -247,6 +248,7 @@ cc_library( cc_test( name = "flash_exec_unittest", srcs = ["flash_exec_unittest.cc"], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":flash_exec", ":rsa_verify", diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD index d040916734a42..03428b1159d3a 100644 --- a/sw/device/silicon_creator/rom/BUILD +++ b/sw/device/silicon_creator/rom/BUILD @@ -7,6 +7,7 @@ load("@rules_pkg//pkg:mappings.bzl", "pkg_files") load("//rules:cross_platform.bzl", "dual_cc_library", "dual_inputs") load("//rules:files.bzl", "output_groups") load("//rules:linker.bzl", "ld_library") +load("//hw/top:defs.bzl", "opentitan_require_ip", "opentitan_select_top") load( "//rules/opentitan:defs.bzl", "OPENTITAN_CPU", @@ -387,6 +388,7 @@ cc_library( cc_test( name = "bootstrap_unittest", srcs = ["bootstrap_unittest.cc"], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":bootstrap", "//hw/top:flash_ctrl_c_regs", @@ -406,6 +408,7 @@ cc_fuzz_test( "fuzzer", "manual", ], + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":bootstrap", "//sw/device/silicon_creator/lib:bootstrap_fuzzer_util", diff --git a/sw/device/silicon_creator/rom_ext/BUILD b/sw/device/silicon_creator/rom_ext/BUILD index 37ba385cf3473..17b27addf6153 100644 --- a/sw/device/silicon_creator/rom_ext/BUILD +++ b/sw/device/silicon_creator/rom_ext/BUILD @@ -6,7 +6,7 @@ load("@opentitan_signing_infra//signing:defs.bzl", "signature_test") load("@rules_pkg//pkg:mappings.bzl", "pkg_filegroup", "pkg_files") load("//rules:files.bzl", "output_groups") load("//rules:const.bzl", "CONST", "hex") -load("//hw/top:defs.bzl", "opentitan_select_top") +load("//hw/top:defs.bzl", "opentitan_require_ip", "opentitan_select_top") load("//rules:cross_platform.bzl", "dual_cc_device_library_of", "dual_cc_library", "dual_inputs") load("//rules:linker.bzl", "ld_library") load("//rules:manifest.bzl", "manifest") @@ -149,6 +149,8 @@ cc_library( cc_test( name = "rom_ext_boot_services_unittest", srcs = ["rom_ext_boot_services_unittest.cc"], + # Mocks flash_ctrl directly and predates RRAM support (TODO(#30967)). + target_compatible_with = opentitan_require_ip("flash_ctrl"), deps = [ ":rom_ext_boot_services", dual_cc_device_library_of("//sw/device/silicon_creator/lib/boot_svc:boot_svc_header"), From 91ea042eb258431c22184295af66b622a51dad5b Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 20:50:41 +0200 Subject: [PATCH 11/24] [rtl,bkdr_loader] remove flash targets Flash has been removed for earlgrey. It can no longer be accessed by the bkdr loader. Signed-off-by: Michael Gautschi --- hw/ip/bkdr_loader/data/bkdr_loader.hjson | 2 +- hw/ip/bkdr_loader/doc/registers.md | 128 +- hw/ip/bkdr_loader/rtl/bkdr_loader.svh | 40 +- hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv | 30 +- hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv | 238 +--- .../rtl/bkdr_loader_regs_reg_top.sv | 1194 ++--------------- 6 files changed, 232 insertions(+), 1400 deletions(-) diff --git a/hw/ip/bkdr_loader/data/bkdr_loader.hjson b/hw/ip/bkdr_loader/data/bkdr_loader.hjson index 6ba694c0605d8..1a33b3a350825 100644 --- a/hw/ip/bkdr_loader/data/bkdr_loader.hjson +++ b/hw/ip/bkdr_loader/data/bkdr_loader.hjson @@ -41,7 +41,7 @@ { name: "NumBkdrTgts", desc: "Number of RAM Targets", type: "int unsigned", - default: "14", + default: "6", } { name: "MaxWordWidthDiv32", desc: "Max bit width of a word / 32", diff --git a/hw/ip/bkdr_loader/doc/registers.md b/hw/ip/bkdr_loader/doc/registers.md index 99871f3e2c15b..d1dda059c098e 100644 --- a/hw/ip/bkdr_loader/doc/registers.md +++ b/hw/ip/bkdr_loader/doc/registers.md @@ -16,42 +16,18 @@ | bkdr_loader.[`TARGET_INFO_3`](#target_info) | 0x10c | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`TARGET_INFO_4`](#target_info) | 0x110 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`TARGET_INFO_5`](#target_info) | 0x114 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_6`](#target_info) | 0x118 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_7`](#target_info) | 0x11c | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_8`](#target_info) | 0x120 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_9`](#target_info) | 0x124 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_10`](#target_info) | 0x128 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_11`](#target_info) | 0x12c | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_12`](#target_info) | 0x130 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | -| bkdr_loader.[`TARGET_INFO_13`](#target_info) | 0x134 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_0`](#width_info) | 0x200 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_1`](#width_info) | 0x204 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_2`](#width_info) | 0x208 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_3`](#width_info) | 0x20c | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_4`](#width_info) | 0x210 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_5`](#width_info) | 0x214 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_6`](#width_info) | 0x218 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_7`](#width_info) | 0x21c | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_8`](#width_info) | 0x220 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_9`](#width_info) | 0x224 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_10`](#width_info) | 0x228 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_11`](#width_info) | 0x22c | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_12`](#width_info) | 0x230 | 4 | The SRAM word width of a given bkdr target memory. | -| bkdr_loader.[`WIDTH_INFO_13`](#width_info) | 0x234 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_0`](#depth_info) | 0x300 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_1`](#depth_info) | 0x304 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_2`](#depth_info) | 0x308 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_3`](#depth_info) | 0x30c | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_4`](#depth_info) | 0x310 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_5`](#depth_info) | 0x314 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_6`](#depth_info) | 0x318 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_7`](#depth_info) | 0x31c | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_8`](#depth_info) | 0x320 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_9`](#depth_info) | 0x324 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_10`](#depth_info) | 0x328 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_11`](#depth_info) | 0x32c | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_12`](#depth_info) | 0x330 | 4 | The number of SRAM words of a given bkdr target memory. | -| bkdr_loader.[`DEPTH_INFO_13`](#depth_info) | 0x334 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`READ_DATA_0`](#read_data) | 0x400 | 4 | Value to be read from the target memory at the current `INDEX`. If | | bkdr_loader.[`READ_DATA_1`](#read_data) | 0x404 | 4 | Value to be read from the target memory at the current `INDEX`. If | | bkdr_loader.[`READ_DATA_2`](#read_data) | 0x408 | 4 | Value to be read from the target memory at the current `INDEX`. If | @@ -75,14 +51,6 @@ | bkdr_loader.[`HASH_LAST_LOADED_3`](#hash_last_loaded) | 0x70c | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | | bkdr_loader.[`HASH_LAST_LOADED_4`](#hash_last_loaded) | 0x710 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | | bkdr_loader.[`HASH_LAST_LOADED_5`](#hash_last_loaded) | 0x714 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_6`](#hash_last_loaded) | 0x718 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_7`](#hash_last_loaded) | 0x71c | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_8`](#hash_last_loaded) | 0x720 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_9`](#hash_last_loaded) | 0x724 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_10`](#hash_last_loaded) | 0x728 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_11`](#hash_last_loaded) | 0x72c | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_12`](#hash_last_loaded) | 0x730 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | -| bkdr_loader.[`HASH_LAST_LOADED_13`](#hash_last_loaded) | 0x734 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | ## STATUS Status register @@ -217,22 +185,14 @@ ASCII 4-character string values (big endian) identifying each bkdr target memory ### Instances -| Name | Offset | -|:---------------|:---------| -| TARGET_INFO_0 | 0x100 | -| TARGET_INFO_1 | 0x104 | -| TARGET_INFO_2 | 0x108 | -| TARGET_INFO_3 | 0x10c | -| TARGET_INFO_4 | 0x110 | -| TARGET_INFO_5 | 0x114 | -| TARGET_INFO_6 | 0x118 | -| TARGET_INFO_7 | 0x11c | -| TARGET_INFO_8 | 0x120 | -| TARGET_INFO_9 | 0x124 | -| TARGET_INFO_10 | 0x128 | -| TARGET_INFO_11 | 0x12c | -| TARGET_INFO_12 | 0x130 | -| TARGET_INFO_13 | 0x134 | +| Name | Offset | +|:--------------|:---------| +| TARGET_INFO_0 | 0x100 | +| TARGET_INFO_1 | 0x104 | +| TARGET_INFO_2 | 0x108 | +| TARGET_INFO_3 | 0x10c | +| TARGET_INFO_4 | 0x110 | +| TARGET_INFO_5 | 0x114 | ### Fields @@ -252,22 +212,14 @@ The SRAM word width of a given bkdr target memory. ### Instances -| Name | Offset | -|:--------------|:---------| -| WIDTH_INFO_0 | 0x200 | -| WIDTH_INFO_1 | 0x204 | -| WIDTH_INFO_2 | 0x208 | -| WIDTH_INFO_3 | 0x20c | -| WIDTH_INFO_4 | 0x210 | -| WIDTH_INFO_5 | 0x214 | -| WIDTH_INFO_6 | 0x218 | -| WIDTH_INFO_7 | 0x21c | -| WIDTH_INFO_8 | 0x220 | -| WIDTH_INFO_9 | 0x224 | -| WIDTH_INFO_10 | 0x228 | -| WIDTH_INFO_11 | 0x22c | -| WIDTH_INFO_12 | 0x230 | -| WIDTH_INFO_13 | 0x234 | +| Name | Offset | +|:-------------|:---------| +| WIDTH_INFO_0 | 0x200 | +| WIDTH_INFO_1 | 0x204 | +| WIDTH_INFO_2 | 0x208 | +| WIDTH_INFO_3 | 0x20c | +| WIDTH_INFO_4 | 0x210 | +| WIDTH_INFO_5 | 0x214 | ### Fields @@ -287,22 +239,14 @@ The number of SRAM words of a given bkdr target memory. ### Instances -| Name | Offset | -|:--------------|:---------| -| DEPTH_INFO_0 | 0x300 | -| DEPTH_INFO_1 | 0x304 | -| DEPTH_INFO_2 | 0x308 | -| DEPTH_INFO_3 | 0x30c | -| DEPTH_INFO_4 | 0x310 | -| DEPTH_INFO_5 | 0x314 | -| DEPTH_INFO_6 | 0x318 | -| DEPTH_INFO_7 | 0x31c | -| DEPTH_INFO_8 | 0x320 | -| DEPTH_INFO_9 | 0x324 | -| DEPTH_INFO_10 | 0x328 | -| DEPTH_INFO_11 | 0x32c | -| DEPTH_INFO_12 | 0x330 | -| DEPTH_INFO_13 | 0x334 | +| Name | Offset | +|:-------------|:---------| +| DEPTH_INFO_0 | 0x300 | +| DEPTH_INFO_1 | 0x304 | +| DEPTH_INFO_2 | 0x308 | +| DEPTH_INFO_3 | 0x30c | +| DEPTH_INFO_4 | 0x310 | +| DEPTH_INFO_5 | 0x314 | ### Fields @@ -410,22 +354,14 @@ the same memory file is already loaded and a preload can be skipped. ### Instances -| Name | Offset | -|:--------------------|:---------| -| HASH_LAST_LOADED_0 | 0x700 | -| HASH_LAST_LOADED_1 | 0x704 | -| HASH_LAST_LOADED_2 | 0x708 | -| HASH_LAST_LOADED_3 | 0x70c | -| HASH_LAST_LOADED_4 | 0x710 | -| HASH_LAST_LOADED_5 | 0x714 | -| HASH_LAST_LOADED_6 | 0x718 | -| HASH_LAST_LOADED_7 | 0x71c | -| HASH_LAST_LOADED_8 | 0x720 | -| HASH_LAST_LOADED_9 | 0x724 | -| HASH_LAST_LOADED_10 | 0x728 | -| HASH_LAST_LOADED_11 | 0x72c | -| HASH_LAST_LOADED_12 | 0x730 | -| HASH_LAST_LOADED_13 | 0x734 | +| Name | Offset | +|:-------------------|:---------| +| HASH_LAST_LOADED_0 | 0x700 | +| HASH_LAST_LOADED_1 | 0x704 | +| HASH_LAST_LOADED_2 | 0x708 | +| HASH_LAST_LOADED_3 | 0x70c | +| HASH_LAST_LOADED_4 | 0x710 | +| HASH_LAST_LOADED_5 | 0x714 | ### Fields diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader.svh b/hw/ip/bkdr_loader/rtl/bkdr_loader.svh index 9e9b01f7d2799..2b1ef72260595 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader.svh +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader.svh @@ -6,35 +6,19 @@ `define BKDR_LOADER_SVH `define BKDR_LOADER_CONNECT_REQS \ - assign top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrAon]; \ - assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramInfo]; \ - assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramData]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I2]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I1]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I0]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I2]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I1]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I0]; \ - assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0]; \ - assign top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSram]; \ - assign top_earlgrey.earlgrey_pd_main.u_sram_ctrl_sec.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSramSec]; \ - assign top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRom]; + assign top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrAon]; \ + assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramInfo]; \ + assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramData]; \ + assign top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSram]; \ + assign top_earlgrey.earlgrey_pd_main.u_sram_ctrl_sec.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSramSec]; \ + assign top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRom]; `define BKDR_LOADER_CONNECT_RSPS \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrAon] = top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrRramInfo] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrRramData] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I2] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I2] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrSram] = top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrSramSec] = top_earlgrey.earlgrey_pd_main.u_sram_ctrl_sec.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ - assign bkdr_rsp[bkdr_loader_pkg::BkdrRom] = top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_rsp; + assign bkdr_rsp[bkdr_loader_pkg::BkdrAon] = top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrRramInfo] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrRramData] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrSram] = top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrSramSec] = top_earlgrey.earlgrey_pd_main.u_sram_ctrl_sec.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrRom] = top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_rsp; `endif diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv index 1497ab7b1431c..e479f79b28164 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv @@ -33,17 +33,9 @@ package bkdr_loader_pkg; // Target indices typedef enum logic [TargetIdxWidth-1:0] { - BkdrRramInfo = 'd13, - BkdrRramData = 'd12, - BkdrAon = 'd11, - BkdrFlashB1I2 = 'd10, - BkdrFlashB1I1 = 'd9, - BkdrFlashB1I0 = 'd8, - BkdrFlashB1 = 'd7, - BkdrFlashB0I2 = 'd6, - BkdrFlashB0I1 = 'd5, - BkdrFlashB0I0 = 'd4, - BkdrFlashB0 = 'd3, + BkdrRramInfo = 'd5, + BkdrRramData = 'd4, + BkdrAon = 'd3, BkdrSramSec = 'd2, BkdrSram = 'd1, BkdrRom = 'd0 @@ -54,14 +46,6 @@ package bkdr_loader_pkg; BkdrRramInfo, BkdrRramData, BkdrAon, - BkdrFlashB1I2, - BkdrFlashB1I1, - BkdrFlashB1I0, - BkdrFlashB1, - BkdrFlashB0I2, - BkdrFlashB0I1, - BkdrFlashB0I0, - BkdrFlashB0, BkdrSramSec, BkdrSram, BkdrRom @@ -72,14 +56,6 @@ package bkdr_loader_pkg; "RRIN", "RRDA", "AON ", - "FI12", - "FI11", - "FI10", - "FB1 ", - "FI02", - "FI01", - "FI00", - "FB0 ", "SRM2", "SRAM", "ROM " diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv index 35272eb33c0d3..c7954e98c0c34 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv @@ -7,7 +7,7 @@ package bkdr_loader_reg_pkg; // Param list - parameter int unsigned NumBkdrTgts = 14; + parameter int unsigned NumBkdrTgts = 6; parameter int unsigned MaxWordWidthDiv32 = 8; parameter int unsigned TargetIdxWidth = 8; @@ -15,7 +15,7 @@ package bkdr_loader_reg_pkg; parameter int RegsAw = 11; // Number of registers for every interface - parameter int NumRegsRegs = 78; + parameter int NumRegsRegs = 46; /////////////////////////////////////////////// // Typedefs for registers for regs interface // @@ -119,26 +119,26 @@ package bkdr_loader_reg_pkg; // Register -> HW type for regs interface typedef struct packed { - bkdr_loader_reg2hw_control_reg_t control; // [1071:1055] - bkdr_loader_reg2hw_mission_mode_switch_delay_reg_t mission_mode_switch_delay; // [1054:1023] - bkdr_loader_reg2hw_read_data_mreg_t [7:0] read_data; // [1022:759] - bkdr_loader_reg2hw_write_data_mreg_t [7:0] write_data; // [758:495] - bkdr_loader_reg2hw_index_reg_t index; // [494:462] - bkdr_loader_reg2hw_hash_last_loaded_mreg_t [13:0] hash_last_loaded; // [461:0] + bkdr_loader_reg2hw_control_reg_t control; // [807:791] + bkdr_loader_reg2hw_mission_mode_switch_delay_reg_t mission_mode_switch_delay; // [790:759] + bkdr_loader_reg2hw_read_data_mreg_t [7:0] read_data; // [758:495] + bkdr_loader_reg2hw_write_data_mreg_t [7:0] write_data; // [494:231] + bkdr_loader_reg2hw_index_reg_t index; // [230:198] + bkdr_loader_reg2hw_hash_last_loaded_mreg_t [5:0] hash_last_loaded; // [197:0] } bkdr_loader_regs_reg2hw_t; // HW -> register type for regs interface typedef struct packed { - bkdr_loader_hw2reg_status_reg_t status; // [2148:2147] - bkdr_loader_hw2reg_control_reg_t control; // [2146:2145] - bkdr_loader_hw2reg_num_bkdr_targets_reg_t num_bkdr_targets; // [2144:2113] - bkdr_loader_hw2reg_usr_access_timestamp_reg_t usr_access_timestamp; // [2112:2081] - bkdr_loader_hw2reg_target_info_mreg_t [13:0] target_info; // [2080:1633] - bkdr_loader_hw2reg_width_info_mreg_t [13:0] width_info; // [1632:1185] - bkdr_loader_hw2reg_depth_info_mreg_t [13:0] depth_info; // [1184:737] - bkdr_loader_hw2reg_read_data_mreg_t [7:0] read_data; // [736:481] - bkdr_loader_hw2reg_index_reg_t index; // [480:448] - bkdr_loader_hw2reg_hash_last_loaded_mreg_t [13:0] hash_last_loaded; // [447:0] + bkdr_loader_hw2reg_status_reg_t status; // [1124:1123] + bkdr_loader_hw2reg_control_reg_t control; // [1122:1121] + bkdr_loader_hw2reg_num_bkdr_targets_reg_t num_bkdr_targets; // [1120:1089] + bkdr_loader_hw2reg_usr_access_timestamp_reg_t usr_access_timestamp; // [1088:1057] + bkdr_loader_hw2reg_target_info_mreg_t [5:0] target_info; // [1056:865] + bkdr_loader_hw2reg_width_info_mreg_t [5:0] width_info; // [864:673] + bkdr_loader_hw2reg_depth_info_mreg_t [5:0] depth_info; // [672:481] + bkdr_loader_hw2reg_read_data_mreg_t [7:0] read_data; // [480:225] + bkdr_loader_hw2reg_index_reg_t index; // [224:192] + bkdr_loader_hw2reg_hash_last_loaded_mreg_t [5:0] hash_last_loaded; // [191:0] } bkdr_loader_regs_hw2reg_t; // Register offsets for regs interface @@ -153,42 +153,18 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_3_OFFSET = 11'h 10c; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_4_OFFSET = 11'h 110; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_5_OFFSET = 11'h 114; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_6_OFFSET = 11'h 118; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_7_OFFSET = 11'h 11c; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_8_OFFSET = 11'h 120; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_9_OFFSET = 11'h 124; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_10_OFFSET = 11'h 128; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_11_OFFSET = 11'h 12c; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_12_OFFSET = 11'h 130; - parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_13_OFFSET = 11'h 134; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_0_OFFSET = 11'h 200; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_1_OFFSET = 11'h 204; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_2_OFFSET = 11'h 208; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_3_OFFSET = 11'h 20c; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_4_OFFSET = 11'h 210; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_5_OFFSET = 11'h 214; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_6_OFFSET = 11'h 218; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_7_OFFSET = 11'h 21c; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_8_OFFSET = 11'h 220; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_9_OFFSET = 11'h 224; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_10_OFFSET = 11'h 228; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_11_OFFSET = 11'h 22c; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_12_OFFSET = 11'h 230; - parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_13_OFFSET = 11'h 234; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_0_OFFSET = 11'h 300; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_1_OFFSET = 11'h 304; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_2_OFFSET = 11'h 308; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_3_OFFSET = 11'h 30c; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_4_OFFSET = 11'h 310; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_5_OFFSET = 11'h 314; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_6_OFFSET = 11'h 318; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_7_OFFSET = 11'h 31c; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_8_OFFSET = 11'h 320; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_9_OFFSET = 11'h 324; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_10_OFFSET = 11'h 328; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_11_OFFSET = 11'h 32c; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_12_OFFSET = 11'h 330; - parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_13_OFFSET = 11'h 334; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_0_OFFSET = 11'h 400; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_1_OFFSET = 11'h 404; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_2_OFFSET = 11'h 408; @@ -212,14 +188,6 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_3_OFFSET = 11'h 70c; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_4_OFFSET = 11'h 710; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_5_OFFSET = 11'h 714; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_6_OFFSET = 11'h 718; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_7_OFFSET = 11'h 71c; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_8_OFFSET = 11'h 720; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_9_OFFSET = 11'h 724; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_10_OFFSET = 11'h 728; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_11_OFFSET = 11'h 72c; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_12_OFFSET = 11'h 730; - parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_13_OFFSET = 11'h 734; // Reset values for hwext registers and their fields for regs interface parameter logic [1:0] BKDR_LOADER_STATUS_RESVAL = 2'h 0; @@ -231,42 +199,18 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_3_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_4_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_5_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_6_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_7_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_8_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_9_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_10_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_11_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_12_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_TARGET_INFO_13_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_1_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_2_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_3_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_4_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_5_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_6_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_7_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_8_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_9_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_10_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_11_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_12_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_13_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_1_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_2_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_3_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_4_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_5_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_6_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_7_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_8_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_9_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_10_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_11_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_12_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_13_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_0_VAL_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_1_RESVAL = 32'h 0; @@ -289,14 +233,6 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_3_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_4_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_5_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_6_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_7_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_8_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_9_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_10_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_11_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_12_RESVAL = 32'h 0; - parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_13_RESVAL = 32'h 0; // Register index for regs interface typedef enum int { @@ -311,42 +247,18 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_TARGET_INFO_3, BKDR_LOADER_TARGET_INFO_4, BKDR_LOADER_TARGET_INFO_5, - BKDR_LOADER_TARGET_INFO_6, - BKDR_LOADER_TARGET_INFO_7, - BKDR_LOADER_TARGET_INFO_8, - BKDR_LOADER_TARGET_INFO_9, - BKDR_LOADER_TARGET_INFO_10, - BKDR_LOADER_TARGET_INFO_11, - BKDR_LOADER_TARGET_INFO_12, - BKDR_LOADER_TARGET_INFO_13, BKDR_LOADER_WIDTH_INFO_0, BKDR_LOADER_WIDTH_INFO_1, BKDR_LOADER_WIDTH_INFO_2, BKDR_LOADER_WIDTH_INFO_3, BKDR_LOADER_WIDTH_INFO_4, BKDR_LOADER_WIDTH_INFO_5, - BKDR_LOADER_WIDTH_INFO_6, - BKDR_LOADER_WIDTH_INFO_7, - BKDR_LOADER_WIDTH_INFO_8, - BKDR_LOADER_WIDTH_INFO_9, - BKDR_LOADER_WIDTH_INFO_10, - BKDR_LOADER_WIDTH_INFO_11, - BKDR_LOADER_WIDTH_INFO_12, - BKDR_LOADER_WIDTH_INFO_13, BKDR_LOADER_DEPTH_INFO_0, BKDR_LOADER_DEPTH_INFO_1, BKDR_LOADER_DEPTH_INFO_2, BKDR_LOADER_DEPTH_INFO_3, BKDR_LOADER_DEPTH_INFO_4, BKDR_LOADER_DEPTH_INFO_5, - BKDR_LOADER_DEPTH_INFO_6, - BKDR_LOADER_DEPTH_INFO_7, - BKDR_LOADER_DEPTH_INFO_8, - BKDR_LOADER_DEPTH_INFO_9, - BKDR_LOADER_DEPTH_INFO_10, - BKDR_LOADER_DEPTH_INFO_11, - BKDR_LOADER_DEPTH_INFO_12, - BKDR_LOADER_DEPTH_INFO_13, BKDR_LOADER_READ_DATA_0, BKDR_LOADER_READ_DATA_1, BKDR_LOADER_READ_DATA_2, @@ -369,19 +281,11 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_HASH_LAST_LOADED_2, BKDR_LOADER_HASH_LAST_LOADED_3, BKDR_LOADER_HASH_LAST_LOADED_4, - BKDR_LOADER_HASH_LAST_LOADED_5, - BKDR_LOADER_HASH_LAST_LOADED_6, - BKDR_LOADER_HASH_LAST_LOADED_7, - BKDR_LOADER_HASH_LAST_LOADED_8, - BKDR_LOADER_HASH_LAST_LOADED_9, - BKDR_LOADER_HASH_LAST_LOADED_10, - BKDR_LOADER_HASH_LAST_LOADED_11, - BKDR_LOADER_HASH_LAST_LOADED_12, - BKDR_LOADER_HASH_LAST_LOADED_13 + BKDR_LOADER_HASH_LAST_LOADED_5 } bkdr_loader_regs_id_e; // Register width information to check illegal writes for regs interface - parameter logic [3:0] BKDR_LOADER_REGS_PERMIT [78] = '{ + parameter logic [3:0] BKDR_LOADER_REGS_PERMIT [46] = '{ 4'b 0001, // index[ 0] BKDR_LOADER_STATUS 4'b 0011, // index[ 1] BKDR_LOADER_CONTROL 4'b 1111, // index[ 2] BKDR_LOADER_NUM_BKDR_TARGETS @@ -393,73 +297,41 @@ package bkdr_loader_reg_pkg; 4'b 1111, // index[ 8] BKDR_LOADER_TARGET_INFO_3 4'b 1111, // index[ 9] BKDR_LOADER_TARGET_INFO_4 4'b 1111, // index[10] BKDR_LOADER_TARGET_INFO_5 - 4'b 1111, // index[11] BKDR_LOADER_TARGET_INFO_6 - 4'b 1111, // index[12] BKDR_LOADER_TARGET_INFO_7 - 4'b 1111, // index[13] BKDR_LOADER_TARGET_INFO_8 - 4'b 1111, // index[14] BKDR_LOADER_TARGET_INFO_9 - 4'b 1111, // index[15] BKDR_LOADER_TARGET_INFO_10 - 4'b 1111, // index[16] BKDR_LOADER_TARGET_INFO_11 - 4'b 1111, // index[17] BKDR_LOADER_TARGET_INFO_12 - 4'b 1111, // index[18] BKDR_LOADER_TARGET_INFO_13 - 4'b 1111, // index[19] BKDR_LOADER_WIDTH_INFO_0 - 4'b 1111, // index[20] BKDR_LOADER_WIDTH_INFO_1 - 4'b 1111, // index[21] BKDR_LOADER_WIDTH_INFO_2 - 4'b 1111, // index[22] BKDR_LOADER_WIDTH_INFO_3 - 4'b 1111, // index[23] BKDR_LOADER_WIDTH_INFO_4 - 4'b 1111, // index[24] BKDR_LOADER_WIDTH_INFO_5 - 4'b 1111, // index[25] BKDR_LOADER_WIDTH_INFO_6 - 4'b 1111, // index[26] BKDR_LOADER_WIDTH_INFO_7 - 4'b 1111, // index[27] BKDR_LOADER_WIDTH_INFO_8 - 4'b 1111, // index[28] BKDR_LOADER_WIDTH_INFO_9 - 4'b 1111, // index[29] BKDR_LOADER_WIDTH_INFO_10 - 4'b 1111, // index[30] BKDR_LOADER_WIDTH_INFO_11 - 4'b 1111, // index[31] BKDR_LOADER_WIDTH_INFO_12 - 4'b 1111, // index[32] BKDR_LOADER_WIDTH_INFO_13 - 4'b 1111, // index[33] BKDR_LOADER_DEPTH_INFO_0 - 4'b 1111, // index[34] BKDR_LOADER_DEPTH_INFO_1 - 4'b 1111, // index[35] BKDR_LOADER_DEPTH_INFO_2 - 4'b 1111, // index[36] BKDR_LOADER_DEPTH_INFO_3 - 4'b 1111, // index[37] BKDR_LOADER_DEPTH_INFO_4 - 4'b 1111, // index[38] BKDR_LOADER_DEPTH_INFO_5 - 4'b 1111, // index[39] BKDR_LOADER_DEPTH_INFO_6 - 4'b 1111, // index[40] BKDR_LOADER_DEPTH_INFO_7 - 4'b 1111, // index[41] BKDR_LOADER_DEPTH_INFO_8 - 4'b 1111, // index[42] BKDR_LOADER_DEPTH_INFO_9 - 4'b 1111, // index[43] BKDR_LOADER_DEPTH_INFO_10 - 4'b 1111, // index[44] BKDR_LOADER_DEPTH_INFO_11 - 4'b 1111, // index[45] BKDR_LOADER_DEPTH_INFO_12 - 4'b 1111, // index[46] BKDR_LOADER_DEPTH_INFO_13 - 4'b 1111, // index[47] BKDR_LOADER_READ_DATA_0 - 4'b 1111, // index[48] BKDR_LOADER_READ_DATA_1 - 4'b 1111, // index[49] BKDR_LOADER_READ_DATA_2 - 4'b 1111, // index[50] BKDR_LOADER_READ_DATA_3 - 4'b 1111, // index[51] BKDR_LOADER_READ_DATA_4 - 4'b 1111, // index[52] BKDR_LOADER_READ_DATA_5 - 4'b 1111, // index[53] BKDR_LOADER_READ_DATA_6 - 4'b 1111, // index[54] BKDR_LOADER_READ_DATA_7 - 4'b 1111, // index[55] BKDR_LOADER_WRITE_DATA_0 - 4'b 1111, // index[56] BKDR_LOADER_WRITE_DATA_1 - 4'b 1111, // index[57] BKDR_LOADER_WRITE_DATA_2 - 4'b 1111, // index[58] BKDR_LOADER_WRITE_DATA_3 - 4'b 1111, // index[59] BKDR_LOADER_WRITE_DATA_4 - 4'b 1111, // index[60] BKDR_LOADER_WRITE_DATA_5 - 4'b 1111, // index[61] BKDR_LOADER_WRITE_DATA_6 - 4'b 1111, // index[62] BKDR_LOADER_WRITE_DATA_7 - 4'b 1111, // index[63] BKDR_LOADER_INDEX - 4'b 1111, // index[64] BKDR_LOADER_HASH_LAST_LOADED_0 - 4'b 1111, // index[65] BKDR_LOADER_HASH_LAST_LOADED_1 - 4'b 1111, // index[66] BKDR_LOADER_HASH_LAST_LOADED_2 - 4'b 1111, // index[67] BKDR_LOADER_HASH_LAST_LOADED_3 - 4'b 1111, // index[68] BKDR_LOADER_HASH_LAST_LOADED_4 - 4'b 1111, // index[69] BKDR_LOADER_HASH_LAST_LOADED_5 - 4'b 1111, // index[70] BKDR_LOADER_HASH_LAST_LOADED_6 - 4'b 1111, // index[71] BKDR_LOADER_HASH_LAST_LOADED_7 - 4'b 1111, // index[72] BKDR_LOADER_HASH_LAST_LOADED_8 - 4'b 1111, // index[73] BKDR_LOADER_HASH_LAST_LOADED_9 - 4'b 1111, // index[74] BKDR_LOADER_HASH_LAST_LOADED_10 - 4'b 1111, // index[75] BKDR_LOADER_HASH_LAST_LOADED_11 - 4'b 1111, // index[76] BKDR_LOADER_HASH_LAST_LOADED_12 - 4'b 1111 // index[77] BKDR_LOADER_HASH_LAST_LOADED_13 + 4'b 1111, // index[11] BKDR_LOADER_WIDTH_INFO_0 + 4'b 1111, // index[12] BKDR_LOADER_WIDTH_INFO_1 + 4'b 1111, // index[13] BKDR_LOADER_WIDTH_INFO_2 + 4'b 1111, // index[14] BKDR_LOADER_WIDTH_INFO_3 + 4'b 1111, // index[15] BKDR_LOADER_WIDTH_INFO_4 + 4'b 1111, // index[16] BKDR_LOADER_WIDTH_INFO_5 + 4'b 1111, // index[17] BKDR_LOADER_DEPTH_INFO_0 + 4'b 1111, // index[18] BKDR_LOADER_DEPTH_INFO_1 + 4'b 1111, // index[19] BKDR_LOADER_DEPTH_INFO_2 + 4'b 1111, // index[20] BKDR_LOADER_DEPTH_INFO_3 + 4'b 1111, // index[21] BKDR_LOADER_DEPTH_INFO_4 + 4'b 1111, // index[22] BKDR_LOADER_DEPTH_INFO_5 + 4'b 1111, // index[23] BKDR_LOADER_READ_DATA_0 + 4'b 1111, // index[24] BKDR_LOADER_READ_DATA_1 + 4'b 1111, // index[25] BKDR_LOADER_READ_DATA_2 + 4'b 1111, // index[26] BKDR_LOADER_READ_DATA_3 + 4'b 1111, // index[27] BKDR_LOADER_READ_DATA_4 + 4'b 1111, // index[28] BKDR_LOADER_READ_DATA_5 + 4'b 1111, // index[29] BKDR_LOADER_READ_DATA_6 + 4'b 1111, // index[30] BKDR_LOADER_READ_DATA_7 + 4'b 1111, // index[31] BKDR_LOADER_WRITE_DATA_0 + 4'b 1111, // index[32] BKDR_LOADER_WRITE_DATA_1 + 4'b 1111, // index[33] BKDR_LOADER_WRITE_DATA_2 + 4'b 1111, // index[34] BKDR_LOADER_WRITE_DATA_3 + 4'b 1111, // index[35] BKDR_LOADER_WRITE_DATA_4 + 4'b 1111, // index[36] BKDR_LOADER_WRITE_DATA_5 + 4'b 1111, // index[37] BKDR_LOADER_WRITE_DATA_6 + 4'b 1111, // index[38] BKDR_LOADER_WRITE_DATA_7 + 4'b 1111, // index[39] BKDR_LOADER_INDEX + 4'b 1111, // index[40] BKDR_LOADER_HASH_LAST_LOADED_0 + 4'b 1111, // index[41] BKDR_LOADER_HASH_LAST_LOADED_1 + 4'b 1111, // index[42] BKDR_LOADER_HASH_LAST_LOADED_2 + 4'b 1111, // index[43] BKDR_LOADER_HASH_LAST_LOADED_3 + 4'b 1111, // index[44] BKDR_LOADER_HASH_LAST_LOADED_4 + 4'b 1111 // index[45] BKDR_LOADER_HASH_LAST_LOADED_5 }; endpackage diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv index 491576b11bded..f6cbe172eebe5 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv @@ -52,9 +52,9 @@ module bkdr_loader_regs_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [77:0] reg_we_check; + logic [45:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(78) + .OneHotWidth(46) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -154,22 +154,6 @@ module bkdr_loader_regs_reg_top ( logic [31:0] target_info_4_qs; logic target_info_5_re; logic [31:0] target_info_5_qs; - logic target_info_6_re; - logic [31:0] target_info_6_qs; - logic target_info_7_re; - logic [31:0] target_info_7_qs; - logic target_info_8_re; - logic [31:0] target_info_8_qs; - logic target_info_9_re; - logic [31:0] target_info_9_qs; - logic target_info_10_re; - logic [31:0] target_info_10_qs; - logic target_info_11_re; - logic [31:0] target_info_11_qs; - logic target_info_12_re; - logic [31:0] target_info_12_qs; - logic target_info_13_re; - logic [31:0] target_info_13_qs; logic width_info_0_re; logic [31:0] width_info_0_qs; logic width_info_1_re; @@ -182,22 +166,6 @@ module bkdr_loader_regs_reg_top ( logic [31:0] width_info_4_qs; logic width_info_5_re; logic [31:0] width_info_5_qs; - logic width_info_6_re; - logic [31:0] width_info_6_qs; - logic width_info_7_re; - logic [31:0] width_info_7_qs; - logic width_info_8_re; - logic [31:0] width_info_8_qs; - logic width_info_9_re; - logic [31:0] width_info_9_qs; - logic width_info_10_re; - logic [31:0] width_info_10_qs; - logic width_info_11_re; - logic [31:0] width_info_11_qs; - logic width_info_12_re; - logic [31:0] width_info_12_qs; - logic width_info_13_re; - logic [31:0] width_info_13_qs; logic depth_info_0_re; logic [31:0] depth_info_0_qs; logic depth_info_1_re; @@ -210,22 +178,6 @@ module bkdr_loader_regs_reg_top ( logic [31:0] depth_info_4_qs; logic depth_info_5_re; logic [31:0] depth_info_5_qs; - logic depth_info_6_re; - logic [31:0] depth_info_6_qs; - logic depth_info_7_re; - logic [31:0] depth_info_7_qs; - logic depth_info_8_re; - logic [31:0] depth_info_8_qs; - logic depth_info_9_re; - logic [31:0] depth_info_9_qs; - logic depth_info_10_re; - logic [31:0] depth_info_10_qs; - logic depth_info_11_re; - logic [31:0] depth_info_11_qs; - logic depth_info_12_re; - logic [31:0] depth_info_12_qs; - logic depth_info_13_re; - logic [31:0] depth_info_13_qs; logic read_data_0_re; logic [31:0] read_data_0_qs; logic read_data_1_re; @@ -293,38 +245,6 @@ module bkdr_loader_regs_reg_top ( logic hash_last_loaded_5_we; logic [31:0] hash_last_loaded_5_qs; logic [31:0] hash_last_loaded_5_wd; - logic hash_last_loaded_6_re; - logic hash_last_loaded_6_we; - logic [31:0] hash_last_loaded_6_qs; - logic [31:0] hash_last_loaded_6_wd; - logic hash_last_loaded_7_re; - logic hash_last_loaded_7_we; - logic [31:0] hash_last_loaded_7_qs; - logic [31:0] hash_last_loaded_7_wd; - logic hash_last_loaded_8_re; - logic hash_last_loaded_8_we; - logic [31:0] hash_last_loaded_8_qs; - logic [31:0] hash_last_loaded_8_wd; - logic hash_last_loaded_9_re; - logic hash_last_loaded_9_we; - logic [31:0] hash_last_loaded_9_qs; - logic [31:0] hash_last_loaded_9_wd; - logic hash_last_loaded_10_re; - logic hash_last_loaded_10_we; - logic [31:0] hash_last_loaded_10_qs; - logic [31:0] hash_last_loaded_10_wd; - logic hash_last_loaded_11_re; - logic hash_last_loaded_11_we; - logic [31:0] hash_last_loaded_11_qs; - logic [31:0] hash_last_loaded_11_wd; - logic hash_last_loaded_12_re; - logic hash_last_loaded_12_we; - logic [31:0] hash_last_loaded_12_qs; - logic [31:0] hash_last_loaded_12_wd; - logic hash_last_loaded_13_re; - logic hash_last_loaded_13_we; - logic [31:0] hash_last_loaded_13_qs; - logic [31:0] hash_last_loaded_13_wd; // Register instances // R[status]: V(True) @@ -678,142 +598,6 @@ module bkdr_loader_regs_reg_top ( ); - // Subregister 6 of Multireg target_info - // R[target_info_6]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_6 ( - .re (target_info_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[6].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_6_qs) - ); - - - // Subregister 7 of Multireg target_info - // R[target_info_7]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_7 ( - .re (target_info_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[7].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_7_qs) - ); - - - // Subregister 8 of Multireg target_info - // R[target_info_8]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_8 ( - .re (target_info_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[8].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_8_qs) - ); - - - // Subregister 9 of Multireg target_info - // R[target_info_9]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_9 ( - .re (target_info_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[9].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_9_qs) - ); - - - // Subregister 10 of Multireg target_info - // R[target_info_10]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_10 ( - .re (target_info_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[10].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_10_qs) - ); - - - // Subregister 11 of Multireg target_info - // R[target_info_11]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_11 ( - .re (target_info_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[11].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_11_qs) - ); - - - // Subregister 12 of Multireg target_info - // R[target_info_12]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_12 ( - .re (target_info_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[12].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_12_qs) - ); - - - // Subregister 13 of Multireg target_info - // R[target_info_13]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_target_info_13 ( - .re (target_info_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.target_info[13].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (target_info_13_qs) - ); - - // Subregister 0 of Multireg width_info // R[width_info_0]: V(True) prim_subreg_ext #( @@ -916,142 +700,6 @@ module bkdr_loader_regs_reg_top ( ); - // Subregister 6 of Multireg width_info - // R[width_info_6]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_6 ( - .re (width_info_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[6].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_6_qs) - ); - - - // Subregister 7 of Multireg width_info - // R[width_info_7]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_7 ( - .re (width_info_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[7].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_7_qs) - ); - - - // Subregister 8 of Multireg width_info - // R[width_info_8]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_8 ( - .re (width_info_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[8].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_8_qs) - ); - - - // Subregister 9 of Multireg width_info - // R[width_info_9]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_9 ( - .re (width_info_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[9].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_9_qs) - ); - - - // Subregister 10 of Multireg width_info - // R[width_info_10]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_10 ( - .re (width_info_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[10].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_10_qs) - ); - - - // Subregister 11 of Multireg width_info - // R[width_info_11]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_11 ( - .re (width_info_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[11].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_11_qs) - ); - - - // Subregister 12 of Multireg width_info - // R[width_info_12]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_12 ( - .re (width_info_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[12].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_12_qs) - ); - - - // Subregister 13 of Multireg width_info - // R[width_info_13]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_width_info_13 ( - .re (width_info_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.width_info[13].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (width_info_13_qs) - ); - - // Subregister 0 of Multireg depth_info // R[depth_info_0]: V(True) prim_subreg_ext #( @@ -1154,142 +802,6 @@ module bkdr_loader_regs_reg_top ( ); - // Subregister 6 of Multireg depth_info - // R[depth_info_6]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_6 ( - .re (depth_info_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[6].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_6_qs) - ); - - - // Subregister 7 of Multireg depth_info - // R[depth_info_7]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_7 ( - .re (depth_info_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[7].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_7_qs) - ); - - - // Subregister 8 of Multireg depth_info - // R[depth_info_8]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_8 ( - .re (depth_info_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[8].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_8_qs) - ); - - - // Subregister 9 of Multireg depth_info - // R[depth_info_9]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_9 ( - .re (depth_info_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[9].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_9_qs) - ); - - - // Subregister 10 of Multireg depth_info - // R[depth_info_10]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_10 ( - .re (depth_info_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[10].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_10_qs) - ); - - - // Subregister 11 of Multireg depth_info - // R[depth_info_11]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_11 ( - .re (depth_info_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[11].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_11_qs) - ); - - - // Subregister 12 of Multireg depth_info - // R[depth_info_12]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_12 ( - .re (depth_info_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[12].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_12_qs) - ); - - - // Subregister 13 of Multireg depth_info - // R[depth_info_13]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_depth_info_13 ( - .re (depth_info_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.depth_info[13].d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (depth_info_13_qs) - ); - - // Subregister 0 of Multireg read_data // R[read_data_0]: V(True) prim_subreg_ext #( @@ -1920,176 +1432,8 @@ module bkdr_loader_regs_reg_top ( assign reg2hw.hash_last_loaded[5].qe = hash_last_loaded_5_qe; - // Subregister 6 of Multireg hash_last_loaded - // R[hash_last_loaded_6]: V(True) - logic hash_last_loaded_6_qe; - logic [0:0] hash_last_loaded_6_flds_we; - assign hash_last_loaded_6_qe = &hash_last_loaded_6_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_6 ( - .re (hash_last_loaded_6_re), - .we (hash_last_loaded_6_we), - .wd (hash_last_loaded_6_wd), - .d (hw2reg.hash_last_loaded[6].d), - .qre (), - .qe (hash_last_loaded_6_flds_we[0]), - .q (reg2hw.hash_last_loaded[6].q), - .ds (), - .qs (hash_last_loaded_6_qs) - ); - assign reg2hw.hash_last_loaded[6].qe = hash_last_loaded_6_qe; - - // Subregister 7 of Multireg hash_last_loaded - // R[hash_last_loaded_7]: V(True) - logic hash_last_loaded_7_qe; - logic [0:0] hash_last_loaded_7_flds_we; - assign hash_last_loaded_7_qe = &hash_last_loaded_7_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_7 ( - .re (hash_last_loaded_7_re), - .we (hash_last_loaded_7_we), - .wd (hash_last_loaded_7_wd), - .d (hw2reg.hash_last_loaded[7].d), - .qre (), - .qe (hash_last_loaded_7_flds_we[0]), - .q (reg2hw.hash_last_loaded[7].q), - .ds (), - .qs (hash_last_loaded_7_qs) - ); - assign reg2hw.hash_last_loaded[7].qe = hash_last_loaded_7_qe; - - - // Subregister 8 of Multireg hash_last_loaded - // R[hash_last_loaded_8]: V(True) - logic hash_last_loaded_8_qe; - logic [0:0] hash_last_loaded_8_flds_we; - assign hash_last_loaded_8_qe = &hash_last_loaded_8_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_8 ( - .re (hash_last_loaded_8_re), - .we (hash_last_loaded_8_we), - .wd (hash_last_loaded_8_wd), - .d (hw2reg.hash_last_loaded[8].d), - .qre (), - .qe (hash_last_loaded_8_flds_we[0]), - .q (reg2hw.hash_last_loaded[8].q), - .ds (), - .qs (hash_last_loaded_8_qs) - ); - assign reg2hw.hash_last_loaded[8].qe = hash_last_loaded_8_qe; - - - // Subregister 9 of Multireg hash_last_loaded - // R[hash_last_loaded_9]: V(True) - logic hash_last_loaded_9_qe; - logic [0:0] hash_last_loaded_9_flds_we; - assign hash_last_loaded_9_qe = &hash_last_loaded_9_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_9 ( - .re (hash_last_loaded_9_re), - .we (hash_last_loaded_9_we), - .wd (hash_last_loaded_9_wd), - .d (hw2reg.hash_last_loaded[9].d), - .qre (), - .qe (hash_last_loaded_9_flds_we[0]), - .q (reg2hw.hash_last_loaded[9].q), - .ds (), - .qs (hash_last_loaded_9_qs) - ); - assign reg2hw.hash_last_loaded[9].qe = hash_last_loaded_9_qe; - - - // Subregister 10 of Multireg hash_last_loaded - // R[hash_last_loaded_10]: V(True) - logic hash_last_loaded_10_qe; - logic [0:0] hash_last_loaded_10_flds_we; - assign hash_last_loaded_10_qe = &hash_last_loaded_10_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_10 ( - .re (hash_last_loaded_10_re), - .we (hash_last_loaded_10_we), - .wd (hash_last_loaded_10_wd), - .d (hw2reg.hash_last_loaded[10].d), - .qre (), - .qe (hash_last_loaded_10_flds_we[0]), - .q (reg2hw.hash_last_loaded[10].q), - .ds (), - .qs (hash_last_loaded_10_qs) - ); - assign reg2hw.hash_last_loaded[10].qe = hash_last_loaded_10_qe; - - - // Subregister 11 of Multireg hash_last_loaded - // R[hash_last_loaded_11]: V(True) - logic hash_last_loaded_11_qe; - logic [0:0] hash_last_loaded_11_flds_we; - assign hash_last_loaded_11_qe = &hash_last_loaded_11_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_11 ( - .re (hash_last_loaded_11_re), - .we (hash_last_loaded_11_we), - .wd (hash_last_loaded_11_wd), - .d (hw2reg.hash_last_loaded[11].d), - .qre (), - .qe (hash_last_loaded_11_flds_we[0]), - .q (reg2hw.hash_last_loaded[11].q), - .ds (), - .qs (hash_last_loaded_11_qs) - ); - assign reg2hw.hash_last_loaded[11].qe = hash_last_loaded_11_qe; - - - // Subregister 12 of Multireg hash_last_loaded - // R[hash_last_loaded_12]: V(True) - logic hash_last_loaded_12_qe; - logic [0:0] hash_last_loaded_12_flds_we; - assign hash_last_loaded_12_qe = &hash_last_loaded_12_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_12 ( - .re (hash_last_loaded_12_re), - .we (hash_last_loaded_12_we), - .wd (hash_last_loaded_12_wd), - .d (hw2reg.hash_last_loaded[12].d), - .qre (), - .qe (hash_last_loaded_12_flds_we[0]), - .q (reg2hw.hash_last_loaded[12].q), - .ds (), - .qs (hash_last_loaded_12_qs) - ); - assign reg2hw.hash_last_loaded[12].qe = hash_last_loaded_12_qe; - - - // Subregister 13 of Multireg hash_last_loaded - // R[hash_last_loaded_13]: V(True) - logic hash_last_loaded_13_qe; - logic [0:0] hash_last_loaded_13_flds_we; - assign hash_last_loaded_13_qe = &hash_last_loaded_13_flds_we; - prim_subreg_ext #( - .DW (32) - ) u_hash_last_loaded_13 ( - .re (hash_last_loaded_13_re), - .we (hash_last_loaded_13_we), - .wd (hash_last_loaded_13_wd), - .d (hw2reg.hash_last_loaded[13].d), - .qre (), - .qe (hash_last_loaded_13_flds_we[0]), - .q (reg2hw.hash_last_loaded[13].q), - .ds (), - .qs (hash_last_loaded_13_qs) - ); - assign reg2hw.hash_last_loaded[13].qe = hash_last_loaded_13_qe; - - - - logic [77:0] addr_hit; + logic [45:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == BKDR_LOADER_STATUS_OFFSET); addr_hit[ 1] = (reg_addr == BKDR_LOADER_CONTROL_OFFSET); @@ -2102,73 +1446,41 @@ module bkdr_loader_regs_reg_top ( addr_hit[ 8] = (reg_addr == BKDR_LOADER_TARGET_INFO_3_OFFSET); addr_hit[ 9] = (reg_addr == BKDR_LOADER_TARGET_INFO_4_OFFSET); addr_hit[10] = (reg_addr == BKDR_LOADER_TARGET_INFO_5_OFFSET); - addr_hit[11] = (reg_addr == BKDR_LOADER_TARGET_INFO_6_OFFSET); - addr_hit[12] = (reg_addr == BKDR_LOADER_TARGET_INFO_7_OFFSET); - addr_hit[13] = (reg_addr == BKDR_LOADER_TARGET_INFO_8_OFFSET); - addr_hit[14] = (reg_addr == BKDR_LOADER_TARGET_INFO_9_OFFSET); - addr_hit[15] = (reg_addr == BKDR_LOADER_TARGET_INFO_10_OFFSET); - addr_hit[16] = (reg_addr == BKDR_LOADER_TARGET_INFO_11_OFFSET); - addr_hit[17] = (reg_addr == BKDR_LOADER_TARGET_INFO_12_OFFSET); - addr_hit[18] = (reg_addr == BKDR_LOADER_TARGET_INFO_13_OFFSET); - addr_hit[19] = (reg_addr == BKDR_LOADER_WIDTH_INFO_0_OFFSET); - addr_hit[20] = (reg_addr == BKDR_LOADER_WIDTH_INFO_1_OFFSET); - addr_hit[21] = (reg_addr == BKDR_LOADER_WIDTH_INFO_2_OFFSET); - addr_hit[22] = (reg_addr == BKDR_LOADER_WIDTH_INFO_3_OFFSET); - addr_hit[23] = (reg_addr == BKDR_LOADER_WIDTH_INFO_4_OFFSET); - addr_hit[24] = (reg_addr == BKDR_LOADER_WIDTH_INFO_5_OFFSET); - addr_hit[25] = (reg_addr == BKDR_LOADER_WIDTH_INFO_6_OFFSET); - addr_hit[26] = (reg_addr == BKDR_LOADER_WIDTH_INFO_7_OFFSET); - addr_hit[27] = (reg_addr == BKDR_LOADER_WIDTH_INFO_8_OFFSET); - addr_hit[28] = (reg_addr == BKDR_LOADER_WIDTH_INFO_9_OFFSET); - addr_hit[29] = (reg_addr == BKDR_LOADER_WIDTH_INFO_10_OFFSET); - addr_hit[30] = (reg_addr == BKDR_LOADER_WIDTH_INFO_11_OFFSET); - addr_hit[31] = (reg_addr == BKDR_LOADER_WIDTH_INFO_12_OFFSET); - addr_hit[32] = (reg_addr == BKDR_LOADER_WIDTH_INFO_13_OFFSET); - addr_hit[33] = (reg_addr == BKDR_LOADER_DEPTH_INFO_0_OFFSET); - addr_hit[34] = (reg_addr == BKDR_LOADER_DEPTH_INFO_1_OFFSET); - addr_hit[35] = (reg_addr == BKDR_LOADER_DEPTH_INFO_2_OFFSET); - addr_hit[36] = (reg_addr == BKDR_LOADER_DEPTH_INFO_3_OFFSET); - addr_hit[37] = (reg_addr == BKDR_LOADER_DEPTH_INFO_4_OFFSET); - addr_hit[38] = (reg_addr == BKDR_LOADER_DEPTH_INFO_5_OFFSET); - addr_hit[39] = (reg_addr == BKDR_LOADER_DEPTH_INFO_6_OFFSET); - addr_hit[40] = (reg_addr == BKDR_LOADER_DEPTH_INFO_7_OFFSET); - addr_hit[41] = (reg_addr == BKDR_LOADER_DEPTH_INFO_8_OFFSET); - addr_hit[42] = (reg_addr == BKDR_LOADER_DEPTH_INFO_9_OFFSET); - addr_hit[43] = (reg_addr == BKDR_LOADER_DEPTH_INFO_10_OFFSET); - addr_hit[44] = (reg_addr == BKDR_LOADER_DEPTH_INFO_11_OFFSET); - addr_hit[45] = (reg_addr == BKDR_LOADER_DEPTH_INFO_12_OFFSET); - addr_hit[46] = (reg_addr == BKDR_LOADER_DEPTH_INFO_13_OFFSET); - addr_hit[47] = (reg_addr == BKDR_LOADER_READ_DATA_0_OFFSET); - addr_hit[48] = (reg_addr == BKDR_LOADER_READ_DATA_1_OFFSET); - addr_hit[49] = (reg_addr == BKDR_LOADER_READ_DATA_2_OFFSET); - addr_hit[50] = (reg_addr == BKDR_LOADER_READ_DATA_3_OFFSET); - addr_hit[51] = (reg_addr == BKDR_LOADER_READ_DATA_4_OFFSET); - addr_hit[52] = (reg_addr == BKDR_LOADER_READ_DATA_5_OFFSET); - addr_hit[53] = (reg_addr == BKDR_LOADER_READ_DATA_6_OFFSET); - addr_hit[54] = (reg_addr == BKDR_LOADER_READ_DATA_7_OFFSET); - addr_hit[55] = (reg_addr == BKDR_LOADER_WRITE_DATA_0_OFFSET); - addr_hit[56] = (reg_addr == BKDR_LOADER_WRITE_DATA_1_OFFSET); - addr_hit[57] = (reg_addr == BKDR_LOADER_WRITE_DATA_2_OFFSET); - addr_hit[58] = (reg_addr == BKDR_LOADER_WRITE_DATA_3_OFFSET); - addr_hit[59] = (reg_addr == BKDR_LOADER_WRITE_DATA_4_OFFSET); - addr_hit[60] = (reg_addr == BKDR_LOADER_WRITE_DATA_5_OFFSET); - addr_hit[61] = (reg_addr == BKDR_LOADER_WRITE_DATA_6_OFFSET); - addr_hit[62] = (reg_addr == BKDR_LOADER_WRITE_DATA_7_OFFSET); - addr_hit[63] = (reg_addr == BKDR_LOADER_INDEX_OFFSET); - addr_hit[64] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_0_OFFSET); - addr_hit[65] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_1_OFFSET); - addr_hit[66] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_2_OFFSET); - addr_hit[67] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_3_OFFSET); - addr_hit[68] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_4_OFFSET); - addr_hit[69] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_5_OFFSET); - addr_hit[70] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_6_OFFSET); - addr_hit[71] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_7_OFFSET); - addr_hit[72] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_8_OFFSET); - addr_hit[73] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_9_OFFSET); - addr_hit[74] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_10_OFFSET); - addr_hit[75] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_11_OFFSET); - addr_hit[76] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_12_OFFSET); - addr_hit[77] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_13_OFFSET); + addr_hit[11] = (reg_addr == BKDR_LOADER_WIDTH_INFO_0_OFFSET); + addr_hit[12] = (reg_addr == BKDR_LOADER_WIDTH_INFO_1_OFFSET); + addr_hit[13] = (reg_addr == BKDR_LOADER_WIDTH_INFO_2_OFFSET); + addr_hit[14] = (reg_addr == BKDR_LOADER_WIDTH_INFO_3_OFFSET); + addr_hit[15] = (reg_addr == BKDR_LOADER_WIDTH_INFO_4_OFFSET); + addr_hit[16] = (reg_addr == BKDR_LOADER_WIDTH_INFO_5_OFFSET); + addr_hit[17] = (reg_addr == BKDR_LOADER_DEPTH_INFO_0_OFFSET); + addr_hit[18] = (reg_addr == BKDR_LOADER_DEPTH_INFO_1_OFFSET); + addr_hit[19] = (reg_addr == BKDR_LOADER_DEPTH_INFO_2_OFFSET); + addr_hit[20] = (reg_addr == BKDR_LOADER_DEPTH_INFO_3_OFFSET); + addr_hit[21] = (reg_addr == BKDR_LOADER_DEPTH_INFO_4_OFFSET); + addr_hit[22] = (reg_addr == BKDR_LOADER_DEPTH_INFO_5_OFFSET); + addr_hit[23] = (reg_addr == BKDR_LOADER_READ_DATA_0_OFFSET); + addr_hit[24] = (reg_addr == BKDR_LOADER_READ_DATA_1_OFFSET); + addr_hit[25] = (reg_addr == BKDR_LOADER_READ_DATA_2_OFFSET); + addr_hit[26] = (reg_addr == BKDR_LOADER_READ_DATA_3_OFFSET); + addr_hit[27] = (reg_addr == BKDR_LOADER_READ_DATA_4_OFFSET); + addr_hit[28] = (reg_addr == BKDR_LOADER_READ_DATA_5_OFFSET); + addr_hit[29] = (reg_addr == BKDR_LOADER_READ_DATA_6_OFFSET); + addr_hit[30] = (reg_addr == BKDR_LOADER_READ_DATA_7_OFFSET); + addr_hit[31] = (reg_addr == BKDR_LOADER_WRITE_DATA_0_OFFSET); + addr_hit[32] = (reg_addr == BKDR_LOADER_WRITE_DATA_1_OFFSET); + addr_hit[33] = (reg_addr == BKDR_LOADER_WRITE_DATA_2_OFFSET); + addr_hit[34] = (reg_addr == BKDR_LOADER_WRITE_DATA_3_OFFSET); + addr_hit[35] = (reg_addr == BKDR_LOADER_WRITE_DATA_4_OFFSET); + addr_hit[36] = (reg_addr == BKDR_LOADER_WRITE_DATA_5_OFFSET); + addr_hit[37] = (reg_addr == BKDR_LOADER_WRITE_DATA_6_OFFSET); + addr_hit[38] = (reg_addr == BKDR_LOADER_WRITE_DATA_7_OFFSET); + addr_hit[39] = (reg_addr == BKDR_LOADER_INDEX_OFFSET); + addr_hit[40] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_0_OFFSET); + addr_hit[41] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_1_OFFSET); + addr_hit[42] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_2_OFFSET); + addr_hit[43] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_3_OFFSET); + addr_hit[44] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_4_OFFSET); + addr_hit[45] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_5_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2221,39 +1533,7 @@ module bkdr_loader_regs_reg_top ( (addr_hit[42] & (|(BKDR_LOADER_REGS_PERMIT[42] & ~reg_be))) | (addr_hit[43] & (|(BKDR_LOADER_REGS_PERMIT[43] & ~reg_be))) | (addr_hit[44] & (|(BKDR_LOADER_REGS_PERMIT[44] & ~reg_be))) | - (addr_hit[45] & (|(BKDR_LOADER_REGS_PERMIT[45] & ~reg_be))) | - (addr_hit[46] & (|(BKDR_LOADER_REGS_PERMIT[46] & ~reg_be))) | - (addr_hit[47] & (|(BKDR_LOADER_REGS_PERMIT[47] & ~reg_be))) | - (addr_hit[48] & (|(BKDR_LOADER_REGS_PERMIT[48] & ~reg_be))) | - (addr_hit[49] & (|(BKDR_LOADER_REGS_PERMIT[49] & ~reg_be))) | - (addr_hit[50] & (|(BKDR_LOADER_REGS_PERMIT[50] & ~reg_be))) | - (addr_hit[51] & (|(BKDR_LOADER_REGS_PERMIT[51] & ~reg_be))) | - (addr_hit[52] & (|(BKDR_LOADER_REGS_PERMIT[52] & ~reg_be))) | - (addr_hit[53] & (|(BKDR_LOADER_REGS_PERMIT[53] & ~reg_be))) | - (addr_hit[54] & (|(BKDR_LOADER_REGS_PERMIT[54] & ~reg_be))) | - (addr_hit[55] & (|(BKDR_LOADER_REGS_PERMIT[55] & ~reg_be))) | - (addr_hit[56] & (|(BKDR_LOADER_REGS_PERMIT[56] & ~reg_be))) | - (addr_hit[57] & (|(BKDR_LOADER_REGS_PERMIT[57] & ~reg_be))) | - (addr_hit[58] & (|(BKDR_LOADER_REGS_PERMIT[58] & ~reg_be))) | - (addr_hit[59] & (|(BKDR_LOADER_REGS_PERMIT[59] & ~reg_be))) | - (addr_hit[60] & (|(BKDR_LOADER_REGS_PERMIT[60] & ~reg_be))) | - (addr_hit[61] & (|(BKDR_LOADER_REGS_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(BKDR_LOADER_REGS_PERMIT[62] & ~reg_be))) | - (addr_hit[63] & (|(BKDR_LOADER_REGS_PERMIT[63] & ~reg_be))) | - (addr_hit[64] & (|(BKDR_LOADER_REGS_PERMIT[64] & ~reg_be))) | - (addr_hit[65] & (|(BKDR_LOADER_REGS_PERMIT[65] & ~reg_be))) | - (addr_hit[66] & (|(BKDR_LOADER_REGS_PERMIT[66] & ~reg_be))) | - (addr_hit[67] & (|(BKDR_LOADER_REGS_PERMIT[67] & ~reg_be))) | - (addr_hit[68] & (|(BKDR_LOADER_REGS_PERMIT[68] & ~reg_be))) | - (addr_hit[69] & (|(BKDR_LOADER_REGS_PERMIT[69] & ~reg_be))) | - (addr_hit[70] & (|(BKDR_LOADER_REGS_PERMIT[70] & ~reg_be))) | - (addr_hit[71] & (|(BKDR_LOADER_REGS_PERMIT[71] & ~reg_be))) | - (addr_hit[72] & (|(BKDR_LOADER_REGS_PERMIT[72] & ~reg_be))) | - (addr_hit[73] & (|(BKDR_LOADER_REGS_PERMIT[73] & ~reg_be))) | - (addr_hit[74] & (|(BKDR_LOADER_REGS_PERMIT[74] & ~reg_be))) | - (addr_hit[75] & (|(BKDR_LOADER_REGS_PERMIT[75] & ~reg_be))) | - (addr_hit[76] & (|(BKDR_LOADER_REGS_PERMIT[76] & ~reg_be))) | - (addr_hit[77] & (|(BKDR_LOADER_REGS_PERMIT[77] & ~reg_be))))); + (addr_hit[45] & (|(BKDR_LOADER_REGS_PERMIT[45] & ~reg_be))))); end // Generate write-enables @@ -2280,133 +1560,77 @@ module bkdr_loader_regs_reg_top ( assign target_info_3_re = addr_hit[8] & reg_re & !reg_error; assign target_info_4_re = addr_hit[9] & reg_re & !reg_error; assign target_info_5_re = addr_hit[10] & reg_re & !reg_error; - assign target_info_6_re = addr_hit[11] & reg_re & !reg_error; - assign target_info_7_re = addr_hit[12] & reg_re & !reg_error; - assign target_info_8_re = addr_hit[13] & reg_re & !reg_error; - assign target_info_9_re = addr_hit[14] & reg_re & !reg_error; - assign target_info_10_re = addr_hit[15] & reg_re & !reg_error; - assign target_info_11_re = addr_hit[16] & reg_re & !reg_error; - assign target_info_12_re = addr_hit[17] & reg_re & !reg_error; - assign target_info_13_re = addr_hit[18] & reg_re & !reg_error; - assign width_info_0_re = addr_hit[19] & reg_re & !reg_error; - assign width_info_1_re = addr_hit[20] & reg_re & !reg_error; - assign width_info_2_re = addr_hit[21] & reg_re & !reg_error; - assign width_info_3_re = addr_hit[22] & reg_re & !reg_error; - assign width_info_4_re = addr_hit[23] & reg_re & !reg_error; - assign width_info_5_re = addr_hit[24] & reg_re & !reg_error; - assign width_info_6_re = addr_hit[25] & reg_re & !reg_error; - assign width_info_7_re = addr_hit[26] & reg_re & !reg_error; - assign width_info_8_re = addr_hit[27] & reg_re & !reg_error; - assign width_info_9_re = addr_hit[28] & reg_re & !reg_error; - assign width_info_10_re = addr_hit[29] & reg_re & !reg_error; - assign width_info_11_re = addr_hit[30] & reg_re & !reg_error; - assign width_info_12_re = addr_hit[31] & reg_re & !reg_error; - assign width_info_13_re = addr_hit[32] & reg_re & !reg_error; - assign depth_info_0_re = addr_hit[33] & reg_re & !reg_error; - assign depth_info_1_re = addr_hit[34] & reg_re & !reg_error; - assign depth_info_2_re = addr_hit[35] & reg_re & !reg_error; - assign depth_info_3_re = addr_hit[36] & reg_re & !reg_error; - assign depth_info_4_re = addr_hit[37] & reg_re & !reg_error; - assign depth_info_5_re = addr_hit[38] & reg_re & !reg_error; - assign depth_info_6_re = addr_hit[39] & reg_re & !reg_error; - assign depth_info_7_re = addr_hit[40] & reg_re & !reg_error; - assign depth_info_8_re = addr_hit[41] & reg_re & !reg_error; - assign depth_info_9_re = addr_hit[42] & reg_re & !reg_error; - assign depth_info_10_re = addr_hit[43] & reg_re & !reg_error; - assign depth_info_11_re = addr_hit[44] & reg_re & !reg_error; - assign depth_info_12_re = addr_hit[45] & reg_re & !reg_error; - assign depth_info_13_re = addr_hit[46] & reg_re & !reg_error; - assign read_data_0_re = addr_hit[47] & reg_re & !reg_error; - assign read_data_1_re = addr_hit[48] & reg_re & !reg_error; - assign read_data_2_re = addr_hit[49] & reg_re & !reg_error; - assign read_data_3_re = addr_hit[50] & reg_re & !reg_error; - assign read_data_4_re = addr_hit[51] & reg_re & !reg_error; - assign read_data_5_re = addr_hit[52] & reg_re & !reg_error; - assign read_data_6_re = addr_hit[53] & reg_re & !reg_error; - assign read_data_7_re = addr_hit[54] & reg_re & !reg_error; - assign write_data_0_we = addr_hit[55] & reg_we & !reg_error; + assign width_info_0_re = addr_hit[11] & reg_re & !reg_error; + assign width_info_1_re = addr_hit[12] & reg_re & !reg_error; + assign width_info_2_re = addr_hit[13] & reg_re & !reg_error; + assign width_info_3_re = addr_hit[14] & reg_re & !reg_error; + assign width_info_4_re = addr_hit[15] & reg_re & !reg_error; + assign width_info_5_re = addr_hit[16] & reg_re & !reg_error; + assign depth_info_0_re = addr_hit[17] & reg_re & !reg_error; + assign depth_info_1_re = addr_hit[18] & reg_re & !reg_error; + assign depth_info_2_re = addr_hit[19] & reg_re & !reg_error; + assign depth_info_3_re = addr_hit[20] & reg_re & !reg_error; + assign depth_info_4_re = addr_hit[21] & reg_re & !reg_error; + assign depth_info_5_re = addr_hit[22] & reg_re & !reg_error; + assign read_data_0_re = addr_hit[23] & reg_re & !reg_error; + assign read_data_1_re = addr_hit[24] & reg_re & !reg_error; + assign read_data_2_re = addr_hit[25] & reg_re & !reg_error; + assign read_data_3_re = addr_hit[26] & reg_re & !reg_error; + assign read_data_4_re = addr_hit[27] & reg_re & !reg_error; + assign read_data_5_re = addr_hit[28] & reg_re & !reg_error; + assign read_data_6_re = addr_hit[29] & reg_re & !reg_error; + assign read_data_7_re = addr_hit[30] & reg_re & !reg_error; + assign write_data_0_we = addr_hit[31] & reg_we & !reg_error; assign write_data_0_wd = reg_wdata[31:0]; - assign write_data_1_we = addr_hit[56] & reg_we & !reg_error; + assign write_data_1_we = addr_hit[32] & reg_we & !reg_error; assign write_data_1_wd = reg_wdata[31:0]; - assign write_data_2_we = addr_hit[57] & reg_we & !reg_error; + assign write_data_2_we = addr_hit[33] & reg_we & !reg_error; assign write_data_2_wd = reg_wdata[31:0]; - assign write_data_3_we = addr_hit[58] & reg_we & !reg_error; + assign write_data_3_we = addr_hit[34] & reg_we & !reg_error; assign write_data_3_wd = reg_wdata[31:0]; - assign write_data_4_we = addr_hit[59] & reg_we & !reg_error; + assign write_data_4_we = addr_hit[35] & reg_we & !reg_error; assign write_data_4_wd = reg_wdata[31:0]; - assign write_data_5_we = addr_hit[60] & reg_we & !reg_error; + assign write_data_5_we = addr_hit[36] & reg_we & !reg_error; assign write_data_5_wd = reg_wdata[31:0]; - assign write_data_6_we = addr_hit[61] & reg_we & !reg_error; + assign write_data_6_we = addr_hit[37] & reg_we & !reg_error; assign write_data_6_wd = reg_wdata[31:0]; - assign write_data_7_we = addr_hit[62] & reg_we & !reg_error; + assign write_data_7_we = addr_hit[38] & reg_we & !reg_error; assign write_data_7_wd = reg_wdata[31:0]; - assign index_we = addr_hit[63] & reg_we & !reg_error; + assign index_we = addr_hit[39] & reg_we & !reg_error; assign index_wd = reg_wdata[31:0]; - assign hash_last_loaded_0_re = addr_hit[64] & reg_re & !reg_error; - assign hash_last_loaded_0_we = addr_hit[64] & reg_we & !reg_error; + assign hash_last_loaded_0_re = addr_hit[40] & reg_re & !reg_error; + assign hash_last_loaded_0_we = addr_hit[40] & reg_we & !reg_error; assign hash_last_loaded_0_wd = reg_wdata[31:0]; - assign hash_last_loaded_1_re = addr_hit[65] & reg_re & !reg_error; - assign hash_last_loaded_1_we = addr_hit[65] & reg_we & !reg_error; + assign hash_last_loaded_1_re = addr_hit[41] & reg_re & !reg_error; + assign hash_last_loaded_1_we = addr_hit[41] & reg_we & !reg_error; assign hash_last_loaded_1_wd = reg_wdata[31:0]; - assign hash_last_loaded_2_re = addr_hit[66] & reg_re & !reg_error; - assign hash_last_loaded_2_we = addr_hit[66] & reg_we & !reg_error; + assign hash_last_loaded_2_re = addr_hit[42] & reg_re & !reg_error; + assign hash_last_loaded_2_we = addr_hit[42] & reg_we & !reg_error; assign hash_last_loaded_2_wd = reg_wdata[31:0]; - assign hash_last_loaded_3_re = addr_hit[67] & reg_re & !reg_error; - assign hash_last_loaded_3_we = addr_hit[67] & reg_we & !reg_error; + assign hash_last_loaded_3_re = addr_hit[43] & reg_re & !reg_error; + assign hash_last_loaded_3_we = addr_hit[43] & reg_we & !reg_error; assign hash_last_loaded_3_wd = reg_wdata[31:0]; - assign hash_last_loaded_4_re = addr_hit[68] & reg_re & !reg_error; - assign hash_last_loaded_4_we = addr_hit[68] & reg_we & !reg_error; + assign hash_last_loaded_4_re = addr_hit[44] & reg_re & !reg_error; + assign hash_last_loaded_4_we = addr_hit[44] & reg_we & !reg_error; assign hash_last_loaded_4_wd = reg_wdata[31:0]; - assign hash_last_loaded_5_re = addr_hit[69] & reg_re & !reg_error; - assign hash_last_loaded_5_we = addr_hit[69] & reg_we & !reg_error; + assign hash_last_loaded_5_re = addr_hit[45] & reg_re & !reg_error; + assign hash_last_loaded_5_we = addr_hit[45] & reg_we & !reg_error; assign hash_last_loaded_5_wd = reg_wdata[31:0]; - assign hash_last_loaded_6_re = addr_hit[70] & reg_re & !reg_error; - assign hash_last_loaded_6_we = addr_hit[70] & reg_we & !reg_error; - - assign hash_last_loaded_6_wd = reg_wdata[31:0]; - assign hash_last_loaded_7_re = addr_hit[71] & reg_re & !reg_error; - assign hash_last_loaded_7_we = addr_hit[71] & reg_we & !reg_error; - - assign hash_last_loaded_7_wd = reg_wdata[31:0]; - assign hash_last_loaded_8_re = addr_hit[72] & reg_re & !reg_error; - assign hash_last_loaded_8_we = addr_hit[72] & reg_we & !reg_error; - - assign hash_last_loaded_8_wd = reg_wdata[31:0]; - assign hash_last_loaded_9_re = addr_hit[73] & reg_re & !reg_error; - assign hash_last_loaded_9_we = addr_hit[73] & reg_we & !reg_error; - - assign hash_last_loaded_9_wd = reg_wdata[31:0]; - assign hash_last_loaded_10_re = addr_hit[74] & reg_re & !reg_error; - assign hash_last_loaded_10_we = addr_hit[74] & reg_we & !reg_error; - - assign hash_last_loaded_10_wd = reg_wdata[31:0]; - assign hash_last_loaded_11_re = addr_hit[75] & reg_re & !reg_error; - assign hash_last_loaded_11_we = addr_hit[75] & reg_we & !reg_error; - - assign hash_last_loaded_11_wd = reg_wdata[31:0]; - assign hash_last_loaded_12_re = addr_hit[76] & reg_re & !reg_error; - assign hash_last_loaded_12_we = addr_hit[76] & reg_we & !reg_error; - - assign hash_last_loaded_12_wd = reg_wdata[31:0]; - assign hash_last_loaded_13_re = addr_hit[77] & reg_re & !reg_error; - assign hash_last_loaded_13_we = addr_hit[77] & reg_we & !reg_error; - - assign hash_last_loaded_13_wd = reg_wdata[31:0]; // Assign write-enables to checker logic vector. always_comb begin @@ -2441,53 +1665,21 @@ module bkdr_loader_regs_reg_top ( reg_we_check[28] = 1'b0; reg_we_check[29] = 1'b0; reg_we_check[30] = 1'b0; - reg_we_check[31] = 1'b0; - reg_we_check[32] = 1'b0; - reg_we_check[33] = 1'b0; - reg_we_check[34] = 1'b0; - reg_we_check[35] = 1'b0; - reg_we_check[36] = 1'b0; - reg_we_check[37] = 1'b0; - reg_we_check[38] = 1'b0; - reg_we_check[39] = 1'b0; - reg_we_check[40] = 1'b0; - reg_we_check[41] = 1'b0; - reg_we_check[42] = 1'b0; - reg_we_check[43] = 1'b0; - reg_we_check[44] = 1'b0; - reg_we_check[45] = 1'b0; - reg_we_check[46] = 1'b0; - reg_we_check[47] = 1'b0; - reg_we_check[48] = 1'b0; - reg_we_check[49] = 1'b0; - reg_we_check[50] = 1'b0; - reg_we_check[51] = 1'b0; - reg_we_check[52] = 1'b0; - reg_we_check[53] = 1'b0; - reg_we_check[54] = 1'b0; - reg_we_check[55] = write_data_0_we; - reg_we_check[56] = write_data_1_we; - reg_we_check[57] = write_data_2_we; - reg_we_check[58] = write_data_3_we; - reg_we_check[59] = write_data_4_we; - reg_we_check[60] = write_data_5_we; - reg_we_check[61] = write_data_6_we; - reg_we_check[62] = write_data_7_we; - reg_we_check[63] = index_we; - reg_we_check[64] = hash_last_loaded_0_we; - reg_we_check[65] = hash_last_loaded_1_we; - reg_we_check[66] = hash_last_loaded_2_we; - reg_we_check[67] = hash_last_loaded_3_we; - reg_we_check[68] = hash_last_loaded_4_we; - reg_we_check[69] = hash_last_loaded_5_we; - reg_we_check[70] = hash_last_loaded_6_we; - reg_we_check[71] = hash_last_loaded_7_we; - reg_we_check[72] = hash_last_loaded_8_we; - reg_we_check[73] = hash_last_loaded_9_we; - reg_we_check[74] = hash_last_loaded_10_we; - reg_we_check[75] = hash_last_loaded_11_we; - reg_we_check[76] = hash_last_loaded_12_we; - reg_we_check[77] = hash_last_loaded_13_we; + reg_we_check[31] = write_data_0_we; + reg_we_check[32] = write_data_1_we; + reg_we_check[33] = write_data_2_we; + reg_we_check[34] = write_data_3_we; + reg_we_check[35] = write_data_4_we; + reg_we_check[36] = write_data_5_we; + reg_we_check[37] = write_data_6_we; + reg_we_check[38] = write_data_7_we; + reg_we_check[39] = index_we; + reg_we_check[40] = hash_last_loaded_0_we; + reg_we_check[41] = hash_last_loaded_1_we; + reg_we_check[42] = hash_last_loaded_2_we; + reg_we_check[43] = hash_last_loaded_3_we; + reg_we_check[44] = hash_last_loaded_4_we; + reg_we_check[45] = hash_last_loaded_5_we; end // Read data return @@ -2544,273 +1736,145 @@ module bkdr_loader_regs_reg_top ( end addr_hit[11]: begin - reg_rdata_next[31:0] = target_info_6_qs; - end - - addr_hit[12]: begin - reg_rdata_next[31:0] = target_info_7_qs; - end - - addr_hit[13]: begin - reg_rdata_next[31:0] = target_info_8_qs; - end - - addr_hit[14]: begin - reg_rdata_next[31:0] = target_info_9_qs; - end - - addr_hit[15]: begin - reg_rdata_next[31:0] = target_info_10_qs; - end - - addr_hit[16]: begin - reg_rdata_next[31:0] = target_info_11_qs; - end - - addr_hit[17]: begin - reg_rdata_next[31:0] = target_info_12_qs; - end - - addr_hit[18]: begin - reg_rdata_next[31:0] = target_info_13_qs; - end - - addr_hit[19]: begin reg_rdata_next[31:0] = width_info_0_qs; end - addr_hit[20]: begin + addr_hit[12]: begin reg_rdata_next[31:0] = width_info_1_qs; end - addr_hit[21]: begin + addr_hit[13]: begin reg_rdata_next[31:0] = width_info_2_qs; end - addr_hit[22]: begin + addr_hit[14]: begin reg_rdata_next[31:0] = width_info_3_qs; end - addr_hit[23]: begin + addr_hit[15]: begin reg_rdata_next[31:0] = width_info_4_qs; end - addr_hit[24]: begin + addr_hit[16]: begin reg_rdata_next[31:0] = width_info_5_qs; end - addr_hit[25]: begin - reg_rdata_next[31:0] = width_info_6_qs; - end - - addr_hit[26]: begin - reg_rdata_next[31:0] = width_info_7_qs; - end - - addr_hit[27]: begin - reg_rdata_next[31:0] = width_info_8_qs; - end - - addr_hit[28]: begin - reg_rdata_next[31:0] = width_info_9_qs; - end - - addr_hit[29]: begin - reg_rdata_next[31:0] = width_info_10_qs; - end - - addr_hit[30]: begin - reg_rdata_next[31:0] = width_info_11_qs; - end - - addr_hit[31]: begin - reg_rdata_next[31:0] = width_info_12_qs; - end - - addr_hit[32]: begin - reg_rdata_next[31:0] = width_info_13_qs; - end - - addr_hit[33]: begin + addr_hit[17]: begin reg_rdata_next[31:0] = depth_info_0_qs; end - addr_hit[34]: begin + addr_hit[18]: begin reg_rdata_next[31:0] = depth_info_1_qs; end - addr_hit[35]: begin + addr_hit[19]: begin reg_rdata_next[31:0] = depth_info_2_qs; end - addr_hit[36]: begin + addr_hit[20]: begin reg_rdata_next[31:0] = depth_info_3_qs; end - addr_hit[37]: begin + addr_hit[21]: begin reg_rdata_next[31:0] = depth_info_4_qs; end - addr_hit[38]: begin + addr_hit[22]: begin reg_rdata_next[31:0] = depth_info_5_qs; end - addr_hit[39]: begin - reg_rdata_next[31:0] = depth_info_6_qs; - end - - addr_hit[40]: begin - reg_rdata_next[31:0] = depth_info_7_qs; - end - - addr_hit[41]: begin - reg_rdata_next[31:0] = depth_info_8_qs; - end - - addr_hit[42]: begin - reg_rdata_next[31:0] = depth_info_9_qs; - end - - addr_hit[43]: begin - reg_rdata_next[31:0] = depth_info_10_qs; - end - - addr_hit[44]: begin - reg_rdata_next[31:0] = depth_info_11_qs; - end - - addr_hit[45]: begin - reg_rdata_next[31:0] = depth_info_12_qs; - end - - addr_hit[46]: begin - reg_rdata_next[31:0] = depth_info_13_qs; - end - - addr_hit[47]: begin + addr_hit[23]: begin reg_rdata_next[31:0] = read_data_0_qs; end - addr_hit[48]: begin + addr_hit[24]: begin reg_rdata_next[31:0] = read_data_1_qs; end - addr_hit[49]: begin + addr_hit[25]: begin reg_rdata_next[31:0] = read_data_2_qs; end - addr_hit[50]: begin + addr_hit[26]: begin reg_rdata_next[31:0] = read_data_3_qs; end - addr_hit[51]: begin + addr_hit[27]: begin reg_rdata_next[31:0] = read_data_4_qs; end - addr_hit[52]: begin + addr_hit[28]: begin reg_rdata_next[31:0] = read_data_5_qs; end - addr_hit[53]: begin + addr_hit[29]: begin reg_rdata_next[31:0] = read_data_6_qs; end - addr_hit[54]: begin + addr_hit[30]: begin reg_rdata_next[31:0] = read_data_7_qs; end - addr_hit[55]: begin + addr_hit[31]: begin reg_rdata_next[31:0] = write_data_0_qs; end - addr_hit[56]: begin + addr_hit[32]: begin reg_rdata_next[31:0] = write_data_1_qs; end - addr_hit[57]: begin + addr_hit[33]: begin reg_rdata_next[31:0] = write_data_2_qs; end - addr_hit[58]: begin + addr_hit[34]: begin reg_rdata_next[31:0] = write_data_3_qs; end - addr_hit[59]: begin + addr_hit[35]: begin reg_rdata_next[31:0] = write_data_4_qs; end - addr_hit[60]: begin + addr_hit[36]: begin reg_rdata_next[31:0] = write_data_5_qs; end - addr_hit[61]: begin + addr_hit[37]: begin reg_rdata_next[31:0] = write_data_6_qs; end - addr_hit[62]: begin + addr_hit[38]: begin reg_rdata_next[31:0] = write_data_7_qs; end - addr_hit[63]: begin + addr_hit[39]: begin reg_rdata_next[31:0] = index_qs; end - addr_hit[64]: begin + addr_hit[40]: begin reg_rdata_next[31:0] = hash_last_loaded_0_qs; end - addr_hit[65]: begin + addr_hit[41]: begin reg_rdata_next[31:0] = hash_last_loaded_1_qs; end - addr_hit[66]: begin + addr_hit[42]: begin reg_rdata_next[31:0] = hash_last_loaded_2_qs; end - addr_hit[67]: begin + addr_hit[43]: begin reg_rdata_next[31:0] = hash_last_loaded_3_qs; end - addr_hit[68]: begin + addr_hit[44]: begin reg_rdata_next[31:0] = hash_last_loaded_4_qs; end - addr_hit[69]: begin + addr_hit[45]: begin reg_rdata_next[31:0] = hash_last_loaded_5_qs; end - addr_hit[70]: begin - reg_rdata_next[31:0] = hash_last_loaded_6_qs; - end - - addr_hit[71]: begin - reg_rdata_next[31:0] = hash_last_loaded_7_qs; - end - - addr_hit[72]: begin - reg_rdata_next[31:0] = hash_last_loaded_8_qs; - end - - addr_hit[73]: begin - reg_rdata_next[31:0] = hash_last_loaded_9_qs; - end - - addr_hit[74]: begin - reg_rdata_next[31:0] = hash_last_loaded_10_qs; - end - - addr_hit[75]: begin - reg_rdata_next[31:0] = hash_last_loaded_11_qs; - end - - addr_hit[76]: begin - reg_rdata_next[31:0] = hash_last_loaded_12_qs; - end - - addr_hit[77]: begin - reg_rdata_next[31:0] = hash_last_loaded_13_qs; - end - default: begin reg_rdata_next = '1; end From a9aeeee175a66d3ff885ae2932e5917238820db0 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 20:59:02 +0200 Subject: [PATCH 12/24] [sw,rram_ctrl] add first version of rram_exc_handler This commit adds a first version of the rram_exc_handler. The content of the rram_exc_handler will need to be further developement (#31010). This commit also renames the flash_ecc_exc_handler_en to nvm_ecc_exc_handler_en and puts the rram/flash_exc_handler at the location of nvm_exception_handler. Signed-off-by: Michael Gautschi --- .../silicon_creator/lib/flash_exc_handler.S | 12 +- .../silicon_creator/lib/rram_exc_handler.S | 246 ++++++++++++++++++ sw/device/silicon_creator/rom/BUILD | 16 +- sw/device/silicon_creator/rom/rom.c | 6 +- sw/device/silicon_creator/rom/rom_epmp_test.c | 6 +- sw/device/silicon_creator/rom/rom_start.S | 2 +- sw/device/silicon_creator/rom_ext/BUILD | 19 +- sw/device/silicon_creator/rom_ext/rom_ext.c | 6 +- .../silicon_creator/rom_ext/rom_ext_start.S | 2 +- 9 files changed, 289 insertions(+), 26 deletions(-) create mode 100644 sw/device/silicon_creator/lib/rram_exc_handler.S diff --git a/sw/device/silicon_creator/lib/flash_exc_handler.S b/sw/device/silicon_creator/lib/flash_exc_handler.S index a72469e52bb9c..5e3cebf25e698 100644 --- a/sw/device/silicon_creator/lib/flash_exc_handler.S +++ b/sw/device/silicon_creator/lib/flash_exc_handler.S @@ -33,10 +33,10 @@ * Exception handler. */ .balign 4 - .global flash_exception_handler - .type flash_exception_handler, @function - .extern flash_ecc_exc_handler_en -flash_exception_handler: + .global nvm_exception_handler + .type nvm_exception_handler, @function + .extern nvm_ecc_exc_handler_en +nvm_exception_handler: // Save all registers to the exception frame. The ROM locates its initial // stack_end at `ram_end - 128` and the stack grows downwards from there. // Save `sp` into `mscratch` and use the 128 bytes reserved at the top of @@ -46,7 +46,7 @@ flash_exception_handler: // Before saving the stack frame, check if handling of flash exceptions is // enabled. Determine this with just the stack pointer so that if not enabled, // we don't have to do any other register save/restore. - la sp, flash_ecc_exc_handler_en + la sp, nvm_ecc_exc_handler_en lw sp, 0(sp) xori sp, sp, HARDENED_BOOL_TRUE bnez sp, .L_no_flash_exceptions @@ -233,4 +233,4 @@ flash_exception_handler: // to the next stage if the next stage has trashed its SP register. j INTERRUPT_HANDLER unimp - .size flash_exception_handler, .-flash_exception_handler + .size nvm_exception_handler, .-nvm_exception_handler diff --git a/sw/device/silicon_creator/lib/rram_exc_handler.S b/sw/device/silicon_creator/lib/rram_exc_handler.S new file mode 100644 index 0000000000000..d121efed9e888 --- /dev/null +++ b/sw/device/silicon_creator/lib/rram_exc_handler.S @@ -0,0 +1,246 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * This is the exception handler used by the ROM and ROM_EXT to deal with ECC + * errors reported by the RRAM controller (the flash_ctrl equivalent for tops + * that use RRAM instead of flash for their embedded non-volatile memory). + * Exported as `nvm_exception_handler`/`nvm_ecc_exc_handler_en` since callers + * (rom.c, rom_ext.c, rom_start.S, rom_ext_start.S) use the same names + * regardless of which top/NVM technology is selected. + * + * This file is built separately for the ROM and ROM_EXT by the `rom{,_ext}_isrs` + * rule in each of their respective subdirs. Each of those rules builds this + * file with the INTERRUPT_HANDLER preprocessor symbol defined to be the + * name of the general interrupt handler for the respective target. + */ +#include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/hardened_asm.h" +#include "hw/top/rram_ctrl_regs.h" + +.equ LOAD_ACCESS_FAULT, 5 + +// If we get an ECC error reading from RRAM, this bit will be set in the RRAM +// controller's FAULT_STATUS register. +// +// Unlike flash_ctrl's FAULT_STATUS (which has two clearable PHY error bits, +// PHY_STORAGE_ERR and PHY_RELBL_ERR), RRAM_CTRL's analogous integrity error +// bit (PHY_RD_INTG_ERR) is read-only/non-clearable (swaccess: ro), so it is +// intentionally not included here -- only PHY_RELBL_ERR is rw0c and can be +// cleared by firmware. +// TODO(https://github.com/lowRISC/opentitan/issues/31010) +.equ PHY_RELBL_ERROR, (1 << RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT) + +// NOTE: The "ax" flag below is necessary to ensure that this section +// is allocated executable space in ROM by the linker. +.section .isrs, "ax" + +// ----------------------------------------------------------------------------- + + /** + * Exception handler. + */ + .balign 4 + .global nvm_exception_handler + .type nvm_exception_handler, @function + .extern nvm_ecc_exc_handler_en +nvm_exception_handler: + // Save all registers to the exception frame. The ROM locates its initial + // stack_end at `ram_end - 128` and the stack grows downwards from there. + // Save `sp` into `mscratch` and use the 128 bytes reserved at the top of + // RAM as the exception frame. + csrw mscratch, sp + + // Before saving the stack frame, check if handling of RRAM exceptions is + // enabled. Determine this with just the stack pointer so that if not enabled, + // we don't have to do any other register save/restore. + la sp, nvm_ecc_exc_handler_en + lw sp, 0(sp) + xori sp, sp, HARDENED_BOOL_TRUE + bnez sp, .L_no_rram_exceptions + + // Note: we save the exception frame in RISCV register number order so that + // we can extract the destination register from the faulting instruction and + // use it as an index into the exception frame. + la sp, _exception_frame_start + sw x1, 1 * OT_WORD_SIZE(sp) + sw x2, 2 * OT_WORD_SIZE(sp) + sw x3, 3 * OT_WORD_SIZE(sp) + sw x4, 4 * OT_WORD_SIZE(sp) + sw x5, 5 * OT_WORD_SIZE(sp) + sw x6, 6 * OT_WORD_SIZE(sp) + sw x7, 7 * OT_WORD_SIZE(sp) + sw x8, 8 * OT_WORD_SIZE(sp) + sw x9, 9 * OT_WORD_SIZE(sp) + sw x10, 10 * OT_WORD_SIZE(sp) + sw x11, 11 * OT_WORD_SIZE(sp) + sw x12, 12 * OT_WORD_SIZE(sp) + sw x13, 13 * OT_WORD_SIZE(sp) + sw x14, 14 * OT_WORD_SIZE(sp) + sw x15, 15 * OT_WORD_SIZE(sp) + sw x16, 16 * OT_WORD_SIZE(sp) + sw x17, 17 * OT_WORD_SIZE(sp) + sw x18, 18 * OT_WORD_SIZE(sp) + sw x19, 19 * OT_WORD_SIZE(sp) + sw x20, 20 * OT_WORD_SIZE(sp) + sw x21, 21 * OT_WORD_SIZE(sp) + sw x22, 22 * OT_WORD_SIZE(sp) + sw x23, 23 * OT_WORD_SIZE(sp) + sw x24, 24 * OT_WORD_SIZE(sp) + sw x25, 25 * OT_WORD_SIZE(sp) + sw x26, 26 * OT_WORD_SIZE(sp) + sw x27, 27 * OT_WORD_SIZE(sp) + sw x28, 28 * OT_WORD_SIZE(sp) + sw x29, 29 * OT_WORD_SIZE(sp) + sw x30, 30 * OT_WORD_SIZE(sp) + sw x31, 31 * OT_WORD_SIZE(sp) + + // Get the mcause, mask the reason and check that it is LoadAccessFault. + csrr a1, mcause + andi a1, a1, 31 + li a2, LOAD_ACCESS_FAULT + bne a1, a2, .L_not_a_rram_error + + // Check if there is an RRAM error. + li a3, TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + lw a1, RRAM_CTRL_FAULT_STATUS_REG_OFFSET(a3) + andi a1, a1, PHY_RELBL_ERROR + beqz a1, .L_not_a_rram_error + + // Clear the RRAM error. + sw x0, RRAM_CTRL_FAULT_STATUS_REG_OFFSET(a3) + // Hardening: check that the error is cleared. + lw a1, RRAM_CTRL_FAULT_STATUS_REG_OFFSET(a3) + beqz a1, .L_rram_fault_handled + j .L_not_a_rram_error + unimp + unimp + +.L_rram_fault_handled: + // Compute the MEPC of the instruction after the fault. + // + // Since we support the RISC-V compressed instructions extension, we need to + // check if the two least significant bits of the instruction are + // b11 (0x3), which means that the trapped instruction is not compressed, + // i.e., the trapped instruction is 32bits = 4bytes. Otherwise, the trapped + // instruction is 16bits = 2bytes. + // + // Instruction formats for loads: + // + // LB, LH, LW, LBU, LHU: + // 31 20 19 15 14 12 11 7 6 0 + // +----------------------+----------+------+----------+--------------+ + // | imm[11:0] | rs1 |funct3| rd | 0000011 | + // +----------------------+----------+------+----------+--------------+ + // + // C.LW + // 15 13 12 10 9 7 6 5 4 2 1 0 + // +------+------+------+----+------+----+ + // |funct3| imm | rs1' | imm| rd' | 00 | + // +------+------+------+----+------+----+ + // Where rd' and rs1' are (register_num - 8, ie: rd' of 0 means reg x8). + // + + csrr a0, mepc + lh a2, 0(a0) + addi a0, a0, OT_HALF_WORD_SIZE + // Check if its a 16-bit compressed instruction. + li a1, 3 + and a3, a2, a1 + bne a3, a1, .L_compressed_trap_instr + // Check if its an uncompressed load instruction by checking that the next + // five bits are zero. + srli a3, a2, 2 + andi a3, a3, 0x1f + bnez a3, .L_not_a_rram_error + // Get the register number into a3 by masking off the rd field. + srli a3, a2, 7 + andi a3, a3, 0x1f + // We already added one half word, so for a 32-bit instruction, add another. + addi a0, a0, OT_HALF_WORD_SIZE + j .L_hardened_mepc_check + +.L_compressed_trap_instr: + // Check if its a compressed load instruction. + bnez a3, .L_not_a_rram_error + // Get the register number into a3 by masking off the rd' field and adding 8. + srli a3, a2, 2 + andi a3, a3, 7 + addi a3, a3, 8 + +.L_hardened_mepc_check: + // Hardening: double-check that the retval calculation is 4 bytes or fewer + // from the original value of MEPC. + addi a1, a1, 1 + csrr a2, mepc + sub a2, a0, a2 + bgtu a2, a1, .L_not_a_rram_error + + // Now, using `rd` from the faulting instruction (in a3), load all ones into + // that register. + // RISCV register x0, aka zero. This register is always const 0, so there + // is nothing to do. + beqz a3, .L_rram_fault_done + + // All other registers load the value 0xFFFFFFFF as the faulting value. + li a2, -1 + slli a3, a3, 2 + add a3, a3, sp + sw a2, 0(a3) + +.L_rram_fault_done: + // Exception handler exit and return to C: + // Load the correct MEPC for the next instruction in the current task. + csrw mepc, a0 + + // Restore all registers from the stack and restore SP to its former value. + lw x1, 1 * OT_WORD_SIZE(sp) + lw x2, 2 * OT_WORD_SIZE(sp) + lw x3, 3 * OT_WORD_SIZE(sp) + lw x4, 4 * OT_WORD_SIZE(sp) + lw x5, 5 * OT_WORD_SIZE(sp) + lw x6, 6 * OT_WORD_SIZE(sp) + lw x7, 7 * OT_WORD_SIZE(sp) + lw x8, 8 * OT_WORD_SIZE(sp) + lw x9, 9 * OT_WORD_SIZE(sp) + lw x10, 10 * OT_WORD_SIZE(sp) + lw x11, 11 * OT_WORD_SIZE(sp) + lw x12, 12 * OT_WORD_SIZE(sp) + lw x13, 13 * OT_WORD_SIZE(sp) + lw x14, 14 * OT_WORD_SIZE(sp) + lw x15, 15 * OT_WORD_SIZE(sp) + lw x16, 16 * OT_WORD_SIZE(sp) + lw x17, 17 * OT_WORD_SIZE(sp) + lw x18, 18 * OT_WORD_SIZE(sp) + lw x19, 19 * OT_WORD_SIZE(sp) + lw x20, 20 * OT_WORD_SIZE(sp) + lw x21, 21 * OT_WORD_SIZE(sp) + lw x22, 22 * OT_WORD_SIZE(sp) + lw x23, 23 * OT_WORD_SIZE(sp) + lw x24, 24 * OT_WORD_SIZE(sp) + lw x25, 25 * OT_WORD_SIZE(sp) + lw x26, 26 * OT_WORD_SIZE(sp) + lw x27, 27 * OT_WORD_SIZE(sp) + lw x28, 28 * OT_WORD_SIZE(sp) + lw x29, 29 * OT_WORD_SIZE(sp) + lw x30, 30 * OT_WORD_SIZE(sp) + lw x31, 31 * OT_WORD_SIZE(sp) + csrr sp, mscratch + mret + +.L_no_rram_exceptions: + csrr sp, mscratch +.L_not_a_rram_error: + // Since we aren't dealing with an RRAM error, we'll jump to the normal + // handler for all other exceptiosn and interrupts. That handler emits + // the fault info to the UART and initiates shutdown. No register state + // preservation is necessary because we're not coming back. + // + // Note: we _also_ do not restore SP - we'll restart the stack at + // `ram_end - 128`. This allows us to report exceptions after jumping + // to the next stage if the next stage has trashed its SP register. + j INTERRUPT_HANDLER + unimp + .size nvm_exception_handler, .-nvm_exception_handler diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD index 03428b1159d3a..ed07b94358e50 100644 --- a/sw/device/silicon_creator/rom/BUILD +++ b/sw/device/silicon_creator/rom/BUILD @@ -94,21 +94,29 @@ cc_library( name = "rom_isrs", srcs = [ "rom_isrs.c", - "//sw/device/silicon_creator/lib:flash_exc_handler", - ], + ] + opentitan_select_top( + { + "earlgrey": ["//sw/device/silicon_creator/lib:rram_exc_handler"], + }, + ["//sw/device/silicon_creator/lib:flash_exc_handler"], + ), hdrs = ["rom_isrs.h"], defines = [ "INTERRUPT_HANDLER=rom_interrupt_handler", ], target_compatible_with = [OPENTITAN_CPU], deps = [ - "//hw/top:flash_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib:shutdown", - ], + ] + opentitan_select_top( + { + "earlgrey": ["//hw/top:rram_ctrl_c_regs"], + }, + ["//hw/top:flash_ctrl_c_regs"], + ), ) cc_library( diff --git a/sw/device/silicon_creator/rom/rom.c b/sw/device/silicon_creator/rom/rom.c index cb3fd56008ee2..42d0d78435cb6 100644 --- a/sw/device/silicon_creator/rom/rom.c +++ b/sw/device/silicon_creator/rom/rom.c @@ -100,8 +100,8 @@ boot_data_t boot_data = {0}; static hardened_bool_t waking_from_low_power = 0; // First stage (ROM-->ROM_EXT) secure boot keys loaded from OTP. static sigverify_otp_key_ctx_t sigverify_ctx; -// A ram copy of the OTP word controlling how to handle flash ECC errors. -uint32_t flash_ecc_exc_handler_en; +// A ram copy of the OTP word controlling how to handle NVM ECC errors. +uint32_t nvm_ecc_exc_handler_en; // A check value for the reset reason. uint32_t reset_reason_check; @@ -246,7 +246,7 @@ static rom_error_t rom_init(void) { nvm_ctrl_init(); SEC_MMIO_WRITE_INCREMENT(kNvmCtrlSecMmioInit); - flash_ecc_exc_handler_en = otp_read32( + nvm_ecc_exc_handler_en = otp_read32( OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN_OFFSET); // Initialize in-memory copy of the ePMP register configuration. diff --git a/sw/device/silicon_creator/rom/rom_epmp_test.c b/sw/device/silicon_creator/rom/rom_epmp_test.c index 08f052398d24e..4e32a864713a9 100644 --- a/sw/device/silicon_creator/rom/rom_epmp_test.c +++ b/sw/device/silicon_creator/rom/rom_epmp_test.c @@ -125,11 +125,11 @@ void rom_exception_handler(void) { wait_for_interrupt(); } -// The ROM jumps to the flash_exception_handler first to deal with ECC errors. -// We don't use the flash exception handler in this test, so we alias the +// The ROM jumps to the nvm_exception_handler first to deal with ECC errors. +// We don't use the NVM exception handler in this test, so we alias the // symbol to rom_exception_handler to allow the test program to link. OT_ALIAS("rom_exception_handler") -void flash_exception_handler(void); +void nvm_exception_handler(void); /** * Attempt to execute the code at `pc` by calling it like a function. diff --git a/sw/device/silicon_creator/rom/rom_start.S b/sw/device/silicon_creator/rom/rom_start.S index 26457628231ef..3bf2c91d87c78 100644 --- a/sw/device/silicon_creator/rom/rom_start.S +++ b/sw/device/silicon_creator/rom/rom_start.S @@ -93,7 +93,7 @@ _rom_interrupt_vector_asm: .type _rom_interrupt_vector_c, @function _rom_interrupt_vector_c: // Entry 0: exception handler. - j flash_exception_handler + j nvm_exception_handler // Entries 1-30: interrupt handlers. .rept 30 diff --git a/sw/device/silicon_creator/rom_ext/BUILD b/sw/device/silicon_creator/rom_ext/BUILD index 17b27addf6153..a5812beb80eb9 100644 --- a/sw/device/silicon_creator/rom_ext/BUILD +++ b/sw/device/silicon_creator/rom_ext/BUILD @@ -161,18 +161,27 @@ cc_test( ) cc_library( - name = "rom_ext_flash_exc_handler", - srcs = ["//sw/device/silicon_creator/lib:flash_exc_handler"], + name = "rom_ext_nvm_exc_handler", + srcs = opentitan_select_top( + { + "earlgrey": ["//sw/device/silicon_creator/lib:rram_exc_handler"], + }, + ["//sw/device/silicon_creator/lib:flash_exc_handler"], + ), defines = [ "INTERRUPT_HANDLER=rom_ext_interrupt_handler", ], target_compatible_with = [OPENTITAN_CPU], deps = [ - "//hw/top:flash_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:hardened", "//sw/device/lib/base:macros", - ], + ] + opentitan_select_top( + { + "earlgrey": ["//hw/top:rram_ctrl_c_regs"], + }, + ["//hw/top:flash_ctrl_c_regs"], + ), ) cc_library( @@ -181,7 +190,7 @@ cc_library( hdrs = ["rom_ext_isrs.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ - ":rom_ext_flash_exc_handler", + ":rom_ext_nvm_exc_handler", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:dbg_print", diff --git a/sw/device/silicon_creator/rom_ext/rom_ext.c b/sw/device/silicon_creator/rom_ext/rom_ext.c index ad98a5a60f8f1..0f0daadc914aa 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext.c +++ b/sw/device/silicon_creator/rom_ext/rom_ext.c @@ -90,8 +90,8 @@ extern char _rom_ext_immutable_size[]; // Life cycle state of the chip. lifecycle_state_t lc_state; -// A ram copy of the OTP word controlling how to handle flash ECC errors. -uint32_t flash_ecc_exc_handler_en; +// A ram copy of the OTP word controlling how to handle NVM ECC errors. +uint32_t nvm_ecc_exc_handler_en; // Owner configuration details parsed from the onwer info pages. owner_config_t owner_config; @@ -154,7 +154,7 @@ OT_WARN_UNUSED_RESULT static rom_error_t rom_ext_init(boot_data_t *boot_data) { sec_mmio_next_stage_init(); lc_state = lifecycle_state_get(); - flash_ecc_exc_handler_en = otp_read32( + nvm_ecc_exc_handler_en = otp_read32( OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN_OFFSET); pinmux_init(); // Configure UART0 as stdout. diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_start.S b/sw/device/silicon_creator/rom_ext/rom_ext_start.S index dbb21608fa687..1244ca82ddb4c 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_start.S +++ b/sw/device/silicon_creator/rom_ext/rom_ext_start.S @@ -44,7 +44,7 @@ .type _rom_ext_interrupt_vector, @function _rom_ext_interrupt_vector: // Entry 0: exception handler. - j flash_exception_handler + j nvm_exception_handler // Entries 1-30: interrupt handlers. .rept 30 From 4a6e985c504279f14e53406576cfef6c4c2ec973 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 21:05:14 +0200 Subject: [PATCH 13/24] [sw,penetrationtests] disable flash-specific parts Signed-off-by: Michael Gautschi --- .../tests/penetrationtests/firmware/fi/BUILD | 37 ++++++++++++++++--- .../penetrationtests/firmware/fi/alert_fi.c | 29 +++++++++++++++ .../penetrationtests/firmware/fi/ibex_fi.c | 29 +++++++++++++++ 3 files changed, 90 insertions(+), 5 deletions(-) diff --git a/sw/device/tests/penetrationtests/firmware/fi/BUILD b/sw/device/tests/penetrationtests/firmware/fi/BUILD index 8391c5e3ecb17..468ee0e345548 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/BUILD +++ b/sw/device/tests/penetrationtests/firmware/fi/BUILD @@ -2,6 +2,8 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +load("//hw/top:defs.bzl", "opentitan_if_ip", "opentitan_select_top") + package(default_visibility = ["//visibility:public"]) cc_library( @@ -149,6 +151,15 @@ cc_library( "ibex_fi.c", ], hdrs = ["ibex_fi.h"], + # Selects whether the flash_ctrl-based char_flash_read/_read_static/_write + # handlers are live or stubbed out -- RRAM_CTRL has no equivalent DIF-level + # page erase/write API yet. + defines = opentitan_select_top( + { + "earlgrey": ["USE_RRAM"], + }, + ["USE_FLASH"], + ), deps = [ "//hw/top:aes_c_regs", "//hw/top:alert_handler_c_regs", @@ -163,12 +174,10 @@ cc_library( "//sw/device/lib/base:hardened", "//sw/device/lib/base:memory", "//sw/device/lib/base:status", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/dif:sram_ctrl", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:sram_ctrl_testutils", "//sw/device/lib/testing/test_framework:ujson_ottf", @@ -177,7 +186,14 @@ cc_library( "//sw/device/silicon_creator/manuf/lib:otp_fields", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", "//sw/device/tests/penetrationtests/json:ibex_fi_commands", - ], + ] + opentitan_if_ip( + "flash_ctrl", + [ + "//sw/device/lib/dif:flash_ctrl", + "//sw/device/lib/testing:flash_ctrl_testutils", + ], + [], + ), ) cc_library( @@ -331,6 +347,14 @@ cc_library( name = "alert_fi", srcs = ["alert_fi.c"], hdrs = ["alert_fi.h"], + # Selects whether the flash_ctrl-alert-forcing cases (13-17) are live or + # stubbed out -- RRAM_CTRL has no alert_force DIF support yet. + defines = opentitan_select_top( + { + "earlgrey": ["USE_RRAM"], + }, + ["USE_FLASH"], + ), deps = [ "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", @@ -342,7 +366,6 @@ cc_library( "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:i2c", @@ -365,5 +388,9 @@ cc_library( "//sw/device/lib/ujson", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", "//sw/device/tests/penetrationtests/json:alert_fi_commands", - ], + ] + opentitan_if_ip( + "flash_ctrl", + ["//sw/device/lib/dif:flash_ctrl"], + [], + ), ) diff --git a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c index b70c222616b3c..33651416867ee 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c @@ -15,7 +15,9 @@ #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" +#if defined(USE_FLASH) #include "sw/device/lib/dif/dif_flash_ctrl.h" +#endif // USE_FLASH #include "sw/device/lib/dif/dif_gpio.h" #include "sw/device/lib/dif/dif_hmac.h" #include "sw/device/lib/dif/dif_i2c.h" @@ -59,7 +61,9 @@ static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_entropy_src_t entropy_src; +#if defined(USE_FLASH) static dif_flash_ctrl_t flash_ctrl; +#endif // USE_FLASH static dif_gpio_t gpio; static dif_hmac_t hmac; static dif_i2c_t i2c0; @@ -121,8 +125,10 @@ static status_t init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR); TRY(dif_entropy_src_init(base_addr, &entropy_src)); +#if defined(USE_FLASH) base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); TRY(dif_flash_ctrl_init(base_addr, &flash_ctrl)); +#endif // USE_FLASH base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); TRY(dif_gpio_init(base_addr, &gpio)); @@ -277,23 +283,46 @@ status_t handle_alert_fi_trigger(ujson_t *uj) { TRY(dif_entropy_src_alert_force(&entropy_src, kDifEntropySrcAlertFatalAlert)); break; + // Cases 13-17 force flash_ctrl-specific alerts. RRAM_CTRL has no + // alert_force DIF support yet. Case numbers are kept stable since + // the host-side Python test harness references them by number. case 13: +#if defined(USE_FLASH) TRY(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr)); +#else + return UNIMPLEMENTED(); +#endif // USE_FLASH break; case 14: +#if defined(USE_FLASH) TRY(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertFatalStdErr)); +#else + return UNIMPLEMENTED(); +#endif // USE_FLASH break; case 15: +#if defined(USE_FLASH) TRY(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertFatalErr)); +#else + return UNIMPLEMENTED(); +#endif // USE_FLASH break; case 16: +#if defined(USE_FLASH) TRY(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertFatalPrimFlashAlert)); +#else + return UNIMPLEMENTED(); +#endif // USE_FLASH break; case 17: +#if defined(USE_FLASH) TRY(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovPrimFlashAlert)); +#else + return UNIMPLEMENTED(); +#endif // USE_FLASH break; case 18: TRY(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault)); diff --git a/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c b/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c index 4a831cba6de43..0b9446963b0ec 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c @@ -10,12 +10,16 @@ #include "sw/device/lib/base/csr_registers.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/status.h" +#if defined(USE_FLASH) #include "sw/device/lib/dif/dif_flash_ctrl.h" +#endif // USE_FLASH #include "sw/device/lib/dif/dif_otp_ctrl.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/dif/dif_sram_ctrl.h" #include "sw/device/lib/runtime/log.h" +#if defined(USE_FLASH) #include "sw/device/lib/testing/flash_ctrl_testutils.h" +#endif // USE_FLASH #include "sw/device/lib/testing/otp_ctrl_testutils.h" #include "sw/device/lib/testing/sram_ctrl_testutils.h" #include "sw/device/lib/testing/test_framework/ottf_test_config.h" @@ -101,8 +105,10 @@ uint32_t sizeof(uint32_t)]; // CharFlash config parameters. +#if defined(USE_FLASH) static uint32_t flash_region_index; static uint32_t flash_test_page_addr; +#endif // USE_FLASH // Cond. branch macros. #define CONDBRANCHBEQ "beq x5, x6, endfitestfaultybeq\n" @@ -383,8 +389,10 @@ OT_ALWAYS_INLINE void restore_all_regs(uint32_t buffer[]) { #define DUMP_TMP_REGISTER_FILE save_tmp_regs(); // Flash information. +#if defined(USE_FLASH) static dif_flash_ctrl_state_t flash; static dif_flash_ctrl_device_info_t flash_info; +#endif // USE_FLASH #define FLASH_PAGES_PER_BANK flash_info.data_pages #define FLASH_WORD_SZ flash_info.bytes_per_word #define FLASH_PAGE_SZ flash_info.bytes_per_page @@ -2481,6 +2489,10 @@ status_t handle_ibex_fi_char_csr_combi(ujson_t *uj) { return OK_STATUS(); } +// handle_ibex_fi_char_flash_read/_read_static/_write are stubbed out on tops +// without flash_ctrl -- RRAM_CTRL has no equivalent DIF-level page erase/write +// API yet. +#if defined(USE_FLASH) status_t handle_ibex_fi_char_flash_read(ujson_t *uj) __attribute__((optnone)) { // Set the flash region we want to test. ibex_fi_flash_region_t uj_data; @@ -2619,7 +2631,11 @@ status_t handle_ibex_fi_char_flash_read(ujson_t *uj) __attribute__((optnone)) { return OK_STATUS(); } +#else +status_t handle_ibex_fi_char_flash_read(ujson_t *uj) { return UNIMPLEMENTED(); } +#endif // USE_FLASH +#if defined(USE_FLASH) status_t handle_ibex_fi_char_flash_read_static(ujson_t *uj) __attribute__((optnone)) { // Set the flash region we want to test. @@ -2733,7 +2749,13 @@ status_t handle_ibex_fi_char_flash_read_static(ujson_t *uj) RESP_OK(ujson_serialize_ibex_fi_faulty_pure_data_t, uj, &uj_output); return OK_STATUS(); } +#else +status_t handle_ibex_fi_char_flash_read_static(ujson_t *uj) { + return UNIMPLEMENTED(); +} +#endif // USE_FLASH +#if defined(USE_FLASH) status_t handle_ibex_fi_char_flash_write(ujson_t *uj) __attribute__((optnone)) { // Set the flash region we want to test. ibex_fi_flash_region_t uj_data; @@ -2838,6 +2860,11 @@ status_t handle_ibex_fi_char_flash_write(ujson_t *uj) __attribute__((optnone)) { return OK_STATUS(); } +#else +status_t handle_ibex_fi_char_flash_write(ujson_t *uj) { + return UNIMPLEMENTED(); +} +#endif // USE_FLASH status_t handle_ibex_fi_char_hardened_check_eq_complement_branch(ujson_t *uj) __attribute__((optnone)) { @@ -4834,11 +4861,13 @@ status_t handle_ibex_fi_char_unrolled_reg_op_loop_chain(ujson_t *uj) } status_t handle_ibex_fi_init(ujson_t *uj) { +#if defined(USE_FLASH) // Enable the flash. flash_info = dif_flash_ctrl_get_device_info(); TRY(dif_flash_ctrl_init_state( &flash, mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); TRY(flash_ctrl_testutils_wait_for_init(&flash)); +#endif // USE_FLASH // Init OTP. TRY(dif_otp_ctrl_init( From 57588c85f1c8125fea364913a82e7edd397e28d8 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 23:13:18 +0200 Subject: [PATCH 14/24] [util,bkdr_loader] remove flash targets flash_ctrl has been removed, the flash bkdr targets are no longer available. Signed-off-by: Michael Gautschi --- rules/opentitan/fpga.bzl | 2 -- sw/host/penetrationtests/python/util/hyperdebug.py | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/rules/opentitan/fpga.bzl b/rules/opentitan/fpga.bzl index 791512d371565..21c19e58e4d8e 100644 --- a/rules/opentitan/fpga.bzl +++ b/rules/opentitan/fpga.bzl @@ -198,8 +198,6 @@ def _get_test_commands(ctx, param, exec_env): # splicing, but means that for now we need to make sure that at least the boot data # info pages are cleared between each run. backdoor_writes = "--clear AON=ALL --clear SRAM=ALL --clear SRM2=ALL" - backdoor_writes += " --clear FB0=ALL --clear FI00=ALL --clear FI01=ALL --clear FI02=ALL" - backdoor_writes += " --clear FB1=ALL --clear FI10=ALL --clear FI11=ALL --clear FI12=ALL" backdoor_writes += " --clear RRDA=ALL --clear RRIN=ALL" # Load the ROM & OTP over the backdoor loader. ROM is read-only once mission mode is diff --git a/sw/host/penetrationtests/python/util/hyperdebug.py b/sw/host/penetrationtests/python/util/hyperdebug.py index 06e54bfa6fbcc..cbd5468219979 100644 --- a/sw/host/penetrationtests/python/util/hyperdebug.py +++ b/sw/host/penetrationtests/python/util/hyperdebug.py @@ -134,8 +134,7 @@ def program_memories( # List of FPGA target memories to clear for each test to make sure state does not persist. # This encompasses Retention SRAM and Flash (both info & data pages). clear_targets = ( - "AON", "FB0", "FI00", "FI01", "FI02", "FB1", "FI10", "FI11", "FI12", - "RRDA", "RRIN" + "AON", "RRDA", "RRIN" ) backdoor_writes = " ".join(f"--clear {target}=ALL" for target in clear_targets) if rom_vmem: From 07fc49833844da8f8db528d22b32c2165822dcc4 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 13 Aug 2026 23:19:51 +0200 Subject: [PATCH 15/24] [verilator,earlgrey] remove flash references Everything is loaded into RRAM. This also removes the flash_ctrl test from the verilotor testsuite as it can not pass anymore without flash_ctrl. Signed-off-by: Michael Gautschi --- ci/scripts/run-verilator-tests.sh | 1 - hw/top_earlgrey/dv/verilator/chip_sim_tb.cc | 17 ----------------- .../dv/verilator/verilator_sim_cfg.hjson | 12 ++++-------- 3 files changed, 4 insertions(+), 26 deletions(-) diff --git a/ci/scripts/run-verilator-tests.sh b/ci/scripts/run-verilator-tests.sh index ebefcdd6d0fd4..d2d81fbfa9fdd 100755 --- a/ci/scripts/run-verilator-tests.sh +++ b/ci/scripts/run-verilator-tests.sh @@ -23,7 +23,6 @@ set -e //sw/device/tests:otbn_irq_test_sim_verilator \ //sw/device/tests:kmac_mode_cshake_test_sim_verilator \ //sw/device/tests:kmac_mode_kmac_test_sim_verilator \ - //sw/device/tests:flash_ctrl_test_sim_verilator \ //sw/device/tests:usbdev_test_sim_verilator \ //sw/device/silicon_creator/lib/drivers:hmac_functest_sim_verilator \ //sw/device/silicon_creator/lib/drivers:uart_functest_sim_verilator \ diff --git a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc index 97366d3d84ce6..fea63c066bd75 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc +++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc @@ -27,23 +27,8 @@ int main(int argc, char **argv) { 0xc000 / 4, 4); MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, 4); - // Only handle the lower bank of flash for now. - MemArea flash0(top_scope + - ".u_flash_ctrl.u_eflash.u_flash." - "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem", - 0x80000 / 8, 8); - MemArea flash1(top_scope + - ".u_flash_ctrl.u_eflash.u_flash." - "gen_prim_flash_banks[1].u_prim_flash_bank.u_mem", - 0x80000 / 8, 8); MemArea rram(top_scope + ".u_rram_macro.u_data_array", 0x200000 / 16, 16); - // Start with the flash region erased. Future loads can overwrite. - std::vector all_ones(flash0.GetSizeBytes()); - std::fill(all_ones.begin(), all_ones.end(), 0xffu); - flash0.Write(/*word_offset=*/0, all_ones); - flash1.Write(/*word_offset=*/0, all_ones); - std::vector all_zeros(rram.GetSizeBytes()); std::fill(all_zeros.begin(), all_zeros.end(), 0x00u); rram.Write(/*word_offset=*/0, all_zeros); @@ -55,8 +40,6 @@ int main(int argc, char **argv) { memutil.RegisterMemoryArea("rom0", 0x40000, &rom0); memutil.RegisterMemoryArea("ram", 0x10000000u, &ram); - memutil.RegisterMemoryArea("flash0", 0x20000000u, &flash0); - memutil.RegisterMemoryArea("flash1", 0x20080000u, &flash1); memutil.RegisterMemoryArea("rram", 0x30000000u, &rram); memutil.RegisterMemoryArea("otp", 0x40000000u /* (bogus LMA) */, &otp); simctrl.RegisterExtension(&memutil); diff --git a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson index a8bd0944ea607..de934a0b395ef 100644 --- a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson @@ -57,7 +57,7 @@ // needed as a run time switch to Verilator. '''{eval_cmd} \ opts=; \ - types=(rom flash otbn otp); \ + types=(rom rram otbn otp); \ exts=(scr.39.vmem elf elf vmem); \ images=`echo {sw_images}`; \ for image in $images; do \ @@ -80,14 +80,14 @@ // followed by an index separated with a ':', which is used by the testbench // to know what type of image is it: // - 0 for Boot ROM, - // - 1 for SW test (loaded in flash), + // - 1 for SW test (loaded in RRAM), // - 2 for OTBN test, // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // // For example, if the Bazel label for a test is: - // `//sw/device/tests:example_test_from_flash`, then you would specify this as - // `//sw/device/tests:example_test_from_flash:1`. + // `//sw/device/tests:example_test`, then you would specify this as + // `//sw/device/tests:example_test:1`. tests: [ { name: aes_smoketest @@ -164,10 +164,6 @@ name: uart_smoketest sw_images: ["//sw/device/tests:uart_smoketest:1"] } - { - name: flash_ctrl_test - sw_images: ["//sw/device/tests:flash_ctrl_test:1"] - } { name: pmp_smoketest_napot sw_images: ["//sw/device/tests:pmp_smoketest_napot:1"] From 7749b20560af362c6cbef49a05373ad3d516c82b Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 14 Aug 2026 14:35:19 +0200 Subject: [PATCH 16/24] [nvm_ctrl,sw] use nvm_ctrl in rom_epmp_test This test tries to execute from uninitialized memory. Instead of relying on a all-one(flash) or all-zero(RRAM) pattern for uninitialized words, explicitly write the first and last position of the image with an all-one pattern that will lead to an illegal instruction. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/nvm_ctrl.h | 8 +- sw/device/silicon_creator/rom/BUILD | 3 +- sw/device/silicon_creator/rom/rom_epmp_test.c | 95 +++++++++++-------- 3 files changed, 62 insertions(+), 44 deletions(-) diff --git a/sw/device/silicon_creator/lib/nvm_ctrl.h b/sw/device/silicon_creator/lib/nvm_ctrl.h index 01334507a70f0..2dabd9bae0827 100644 --- a/sw/device/silicon_creator/lib/nvm_ctrl.h +++ b/sw/device/silicon_creator/lib/nvm_ctrl.h @@ -59,6 +59,8 @@ extern "C" { #define NVM_NUM_BANKS FLASH_CTRL_PARAM_REG_NUM_BANKS /** Number of data pages per NVM bank. */ #define NVM_PAGES_PER_BANK FLASH_CTRL_PARAM_REG_PAGES_PER_BANK +/** Value that enables code execution from NVM; see `nvm_ctrl_exec_set()`. */ +#define NVM_EXEC_EN FLASH_CTRL_PARAM_EXEC_EN #if defined(OPENTITAN_IS_EARLGREY) /** Base address of the NVM data partition in the system memory map. */ #define NVM_DATA_BASE_ADDR TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR @@ -98,6 +100,8 @@ extern "C" { #define NVM_PAGES_PER_BANK RRAM_CTRL_PARAM_NUM_DATA_PAGES /** Byte size of one NVM bank. */ #define NVM_BYTES_PER_BANK (NVM_PAGES_PER_BANK * NVM_BYTES_PER_PAGE) +/** Value that enables code execution from NVM; see `nvm_ctrl_exec_set()`. */ +#define NVM_EXEC_EN RRAM_CTRL_PARAM_EXEC_EN /** * Base address of the NVM data partition in the system memory map. * @@ -565,8 +569,8 @@ void nvm_ctrl_bank_erase_perms_set(hardened_bool_t enable); * The caller is responsible for calling * `SEC_MMIO_WRITE_INCREMENT(kNvmCtrlSecMmioExecSet)`. * - * @param exec_val `FLASH_CTRL_PARAM_EXEC_EN` enables execution; all other - * values disable it. + * @param exec_val `NVM_EXEC_EN` enables execution; all other values disable + * it. */ void nvm_ctrl_exec_set(uint32_t exec_val); diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD index ed07b94358e50..1f15ac7df04d2 100644 --- a/sw/device/silicon_creator/rom/BUILD +++ b/sw/device/silicon_creator/rom/BUILD @@ -337,7 +337,6 @@ opentitan_test( ], deps = [ ":mask_rom_lib", - "//hw/top:flash_ctrl_c_regs", "//sw/device/lib/arch:device", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:bitfield", @@ -356,10 +355,10 @@ opentitan_test( "//sw/device/silicon_creator/lib:epmp_state", "//sw/device/silicon_creator/lib:epmp_test_unlock", "//sw/device/silicon_creator/lib:irq_asm", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/lib/base:chip", "//sw/device/silicon_creator/lib/base:sec_mmio", "//sw/device/silicon_creator/lib/base:static_critical", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:uart", ], ) diff --git a/sw/device/silicon_creator/rom/rom_epmp_test.c b/sw/device/silicon_creator/rom/rom_epmp_test.c index 4e32a864713a9..bfe0c446ae414 100644 --- a/sw/device/silicon_creator/rom/rom_epmp_test.c +++ b/sw/device/silicon_creator/rom/rom_epmp_test.c @@ -21,12 +21,11 @@ #include "sw/device/lib/testing/pinmux_testutils.h" #include "sw/device/lib/testing/test_framework/status.h" #include "sw/device/silicon_creator/lib/base/sec_mmio.h" -#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #include "sw/device/silicon_creator/lib/drivers/uart.h" #include "sw/device/silicon_creator/lib/epmp_test_unlock.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" #include "sw/device/silicon_creator/rom/rom_epmp.h" -#include "hw/top/flash_ctrl_regs.h" // Generated. #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" /** @@ -181,8 +180,7 @@ static bool execute(const void *pc, ibex_exc_t expect) { } /** - * An instruction that has all bits set. This value is specifically chosen to - * match an erased flash. + * An instruction that has all bits set. * * Attempts to execute this instruction, `unimp`, will result in an illegal * instruction exception. @@ -262,24 +260,23 @@ static void test_noexec_rwdata(void) { } /** - * Test that eFlash is not executable. + * Test that the NVM (RRAM) host window is not executable. */ -static void test_noexec_eflash(void) { - // Ideally we'd check all of eFlash but that takes a very long time in - // simulation. Instead, check the first and last words are not executable and - // check a sample of other addresses. - uint32_t *eflash = (uint32_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; - size_t eflash_len = - TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / sizeof(eflash[0]); - CHECK(execute(&eflash[0], kIbexExcInstrAccessFault)); - CHECK(execute(&eflash[eflash_len - 1], kIbexExcInstrAccessFault)); +static void test_noexec_nvm(void) { + // Ideally we'd check all of the NVM host window but that takes a very long + // time in simulation. Instead, check the first and last words are not + // executable and check a sample of other addresses. + uint32_t *nvm = (uint32_t *)NVM_DATA_BASE_ADDR; + size_t nvm_len = NVM_DATA_SIZE_BYTES / sizeof(nvm[0]); + CHECK(execute(&nvm[0], kIbexExcInstrAccessFault)); + CHECK(execute(&nvm[nvm_len - 1], kIbexExcInstrAccessFault)); // Step size is picked arbitrarily but should provide a reasonable sample of // addresses. - size_t step = eflash_len / 999; - for (size_t i = step; i < eflash_len; i += step) { - if (!execute(&eflash[i], kIbexExcInstrAccessFault)) { - LOG_ERROR("eflash execution not blocked @ %p", &eflash[i]); + size_t step = nvm_len / 999; + for (size_t i = step; i < nvm_len; i += step) { + if (!execute(&nvm[i], kIbexExcInstrAccessFault)) { + LOG_ERROR("NVM execution not blocked @ %p", &nvm[i]); passed = false; break; } @@ -311,22 +308,22 @@ static void test_noexec_mmio(void) { /** * Test the function used to unlock execution of the ROM extension. * - * Unlock a section of eFlash to simulate the unlocking of the ROM_EXT text. - * Accesses within the unlocked region should execute (and generate an illegal - * instruction exception in this case) while accesses outside the unlocked - * region should still fail with an instruction access fault exception. + * Unlock a section of the NVM host window to simulate the unlocking of the + * ROM_EXT text. Accesses within the unlocked region should execute (and + * generate an illegal instruction exception in this case) while accesses + * outside the unlocked region should still fail with an instruction access + * fault exception. * * @param epmp The ePMP state to update. */ -static void test_unlock_exec_eflash(void) { +static void test_unlock_exec_nvm(void) { // Define a region to unlock (this is somewhat arbitrary but must be word- // aligned and beyond the ROM region, since this same image is placed in the - // flash). - uint32_t *eflash = (uint32_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; - size_t eflash_len = - TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / sizeof(eflash[0]); - uint32_t *image = &eflash[eflash_len / 5]; - size_t image_len = eflash_len / 7; + // NVM). + uint32_t *nvm = (uint32_t *)NVM_DATA_BASE_ADDR; + size_t nvm_len = NVM_DATA_SIZE_BYTES / sizeof(nvm[0]); + uint32_t *image = &nvm[nvm_len / 5]; + size_t image_len = nvm_len / 7; epmp_region_t region = {.start = (uintptr_t)&image[0], .end = (uintptr_t)&image[image_len]}; @@ -335,10 +332,28 @@ static void test_unlock_exec_eflash(void) { rom_epmp_unlock_rom_ext_rx(region); CHECK(epmp_state_check() == kErrorOk); - // Verify that execution within the region succeeds. - // The image must consist of `unimp` instructions so that an illegal - // instruction exception is generated. Because the region is not written and - // tests begin with the flash erased, this instruction is expected to be + // Don't rely on the region's words being unwritten; explicitly write the + // expected value to each boundary address instead. + nvm_ctrl_data_default_perms_set((nvm_page_perms_t){ + .read = kMultiBitBool4True, + .write = kMultiBitBool4True, + }); + SEC_MMIO_WRITE_INCREMENT(kNvmCtrlSecMmioDataDefaultPermsSet); + uint32_t unimp = kUnimpInstruction; + CHECK(nvm_ctrl_data_write((uint32_t)&image[0] - NVM_DATA_BASE_ADDR, 1, + &unimp) == kErrorOk); + CHECK(nvm_ctrl_data_write( + (uint32_t)&image[image_len - 1] - NVM_DATA_BASE_ADDR, 1, &unimp) == + kErrorOk); + nvm_ctrl_data_default_perms_set((nvm_page_perms_t){ + .read = kMultiBitBool4True, + .write = kMultiBitBool4False, + }); + SEC_MMIO_WRITE_INCREMENT(kNvmCtrlSecMmioDataDefaultPermsSet); + + // Verify that execution within the region succeeds. The image must consist + // of `unimp` instructions so that an illegal instruction exception is + // generated; since we just wrote it above, this word is expected to be // UINT32_MAX. CHECK(image[0] == kUnimpInstruction); CHECK(execute(&image[0], kIbexExcIllegalInstrFault)); @@ -369,10 +384,10 @@ void rom_main(void) { mmio_region_from_addr(TOP_EARLGREY_PINMUX_BASE_ADDR), &pinmux)); pinmux_testutils_init(&pinmux); - // Enable execution of code in flash. - flash_ctrl_init(); - flash_ctrl_exec_set(FLASH_CTRL_PARAM_EXEC_EN); - SEC_MMIO_WRITE_INCREMENT(kFlashCtrlSecMmioInit + kFlashCtrlSecMmioExecSet); + // Enable execution of code in NVM. + nvm_ctrl_init(); + nvm_ctrl_exec_set(NVM_EXEC_EN); + SEC_MMIO_WRITE_INCREMENT(kNvmCtrlSecMmioInit + kNvmCtrlSecMmioExecSet); // Configure UART0 as stdout. uart_init(kUartNCOValue); @@ -392,12 +407,12 @@ void rom_main(void) { // Test that execution outside the ROM text is blocked by default. test_noexec_rodata(); test_noexec_rwdata(); - test_noexec_eflash(); + test_noexec_nvm(); test_noexec_mmio(); - // Test that execution is unlocked for a sub-region of eFlash correctly. + // Test that execution is unlocked for a sub-region of NVM correctly. // Simulates the unlocking of the ROM extension text. - test_unlock_exec_eflash(); + test_unlock_exec_nvm(); // The test of the ROM's ePMP configuration is now complete. Unlock the // DV address space so that the test result can be reported. Assumes that PMP From 8baa650e0d169a44d03f644f86a4e1509482eb6c Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 14 Aug 2026 16:57:39 +0200 Subject: [PATCH 17/24] [sw,dv,alert] Port all_escalation_reset_test The alerts checks/triggers for the RRAM alerts are currently empty. This is tracked in issue: (#31009) Signed-off-by: Michael Gautschi --- .../chip_sw_all_escalation_resets_vseq.sv | 8 ++ sw/device/tests/sim_dv/BUILD | 8 +- .../tests/sim_dv/all_escalation_resets_test.c | 122 ++++++++---------- 3 files changed, 60 insertions(+), 78 deletions(-) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index 85dcdf1d7e325..be0f662c2d29c 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -32,6 +32,14 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; '{"edn1", "", TopEarlgreyAlertIdEdn1FatalAlert}, '{"entropy_src", "", TopEarlgreyAlertIdEntropySrcFatalAlert}, '{"rram_ctrl", "", TopEarlgreyAlertIdRramCtrlFatalStdErr}, + // TODO(#31009): RramCtrlFatalErr has no real trigger yet. With the default + // countermeasure ("prim_reg_we_check"), this would resolve to the exact same + // proxy as the FatalStdErr entry above (identical ip_inst_glob + countermeasure), + // which raises fatal_std_err (std_fault_status.reg_intg_err), not fatal_err + // (fault_status) -- so the test would wait forever for an alert that never + // fires whenever this index is drawn. Leave out until #31009 adds a real + // fault_status-specific trigger. + // '{"rram_ctrl", "", TopEarlgreyAlertIdRramCtrlFatalErr}, '{"rram_macro", "", TopEarlgreyAlertIdRramCtrlFatalMacroErr}, '{"gpio", "", TopEarlgreyAlertIdGpioFatalFault}, '{"hmac", "", TopEarlgreyAlertIdHmacFatalFault}, diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index c6e160f1df97f..7f4954209dbc9 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -3,7 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 load("//rules/opentitan:defs.bzl", "OPENTITAN_CPU", "opentitan_test") -load("//hw/top:defs.bzl", "opentitan_select_top") opentitan_test( name = "i2c_host_tx_rx_test", @@ -338,12 +337,7 @@ opentitan_test( "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:ottf_main", - ] + opentitan_select_top( - { - "earlgrey": ["//sw/device/lib/dif:flash_ctrl"], - }, - [], - ), + ], ) opentitan_test( diff --git a/sw/device/tests/sim_dv/all_escalation_resets_test.c b/sw/device/tests/sim_dv/all_escalation_resets_test.c index 7ca7eeea637ba..0031355a8cd3a 100644 --- a/sw/device/tests/sim_dv/all_escalation_resets_test.c +++ b/sw/device/tests/sim_dv/all_escalation_resets_test.c @@ -30,14 +30,11 @@ #if defined(OPENTITAN_IS_EARLGREY) #include "hw/top/dt/adc_ctrl.h" // Generated #include "hw/top/dt/entropy_src.h" // Generated -#include "hw/top/dt/flash_ctrl.h" // Generated #include "hw/top/dt/keymgr_dpe.h" // Generated +#include "hw/top/dt/rram_ctrl.h" // Generated #include "hw/top/dt/sensor_ctrl.h" // Generated #include "hw/top/dt/sysrst_ctrl.h" // Generated #include "hw/top/dt/usbdev.h" // Generated -#include "sw/device/lib/dif/dif_flash_ctrl.h" - -#include "hw/top/flash_ctrl_regs.h" // Generated #elif defined(OPENTITAN_IS_DARJEELING) #include "hw/top/dt/keymgr_dpe.h" // Generated #else @@ -189,14 +186,13 @@ static uint32_t kSramRetStart; */ // Top-specific objects #if defined(OPENTITAN_IS_EARLGREY) -static dif_flash_ctrl_state_t flash_ctrl_state; -dt_flash_ctrl_t kFlashCtrlDt = (dt_flash_ctrl_t)0; -static_assert(kDtFlashCtrlCount >= 1, "This test requires a Flash Ctrl"); +dt_rram_ctrl_t kRramCtrlDt = (dt_rram_ctrl_t)0; +static_assert(kDtRramCtrlCount >= 1, "This test requires an RRAM Ctrl"); static dif_rom_ctrl_t rom_ctrl; static dt_rom_ctrl_t kRomCtrlDt = (dt_rom_ctrl_t)0; static_assert(kDtRomCtrlCount >= 1, "This test requires a ROM CTRL"); -static const char *flash_fatal_check = "flash_fatal_check"; +static const char *rram_fatal_check = "rram_fatal_check"; #elif defined(OPENTITAN_IS_DARJEELING) static dif_sram_ctrl_t sram_ctrl_mbox; static dt_sram_ctrl_t kSramCtrlMboxDt = kDtSramCtrlMbox; @@ -277,9 +273,10 @@ static void restore_fault_checker(fault_checker_t *fault_checker) { #if defined(OPENTITAN_IS_EARLGREY) static const char *adc_ctrl_inst_name = "adc_ctrl"; static const char *entropy_src_inst_name = "entropy_src"; -static const char *flash_ctrl_inst_name = "flash_ctrl"; static const char *i2c1_inst_name = "i2c1"; static const char *i2c2_inst_name = "i2c2"; +static const char *rram_ctrl_inst_name = "rram_ctrl"; +static const char *rram_macro_inst_name = "rram_macro"; static const char *rom_ctrl_inst_name = "rom_ctrl"; static const char *sensor_ctrl_inst_name = "sensor_ctrl"; static const char *spi_host1_inst_name = "spi_host1"; @@ -381,37 +378,31 @@ static void keymgr_dpe_fault_checker(bool enable, const char *ip_inst, // Fault checkers for Top-specific IP #if defined(OPENTITAN_IS_EARLGREY) -static void flash_ctrl_fault_checker(bool enable, const char *ip_inst, - const char *type) { - dif_flash_ctrl_faults_t faults; - CHECK_DIF_OK(dif_flash_ctrl_get_faults(&flash_ctrl_state, &faults)); - uint32_t fault_code = (type == we_check) ? faults.register_integrity_error - : faults.host_gnt_error; +static void rram_ctrl_fault_checker(bool enable, const char *ip_inst, + const char *type) { + // TODO(#31009) + LOG_INFO( + "Expected alert %d rram_ctrl std_fault_status check is yet " + "unimplemented", + kDtRramCtrlAlertFatalStdErr); + trivial_fault_checker(enable, ip_inst, type); +} - CHECK(fault_code == enable, "For %s got codes 0x%x, expected 0x%x", ip_inst, - fault_code, enable); +static void rram_ctrl_fatal_err_fault_checker(bool enable, const char *ip_inst, + const char *type) { + // TODO(#31009) + LOG_INFO( + "Expected alert %d rram_ctrl fault_status check is yet unimplemented", + kDtRramCtrlAlertFatalErr); + trivial_fault_checker(enable, ip_inst, type); } -static void flash_ctrl_prim_fault_checker(bool enable, const char *ip_inst, - const char *type) { - dif_flash_ctrl_faults_t faults; - CHECK_DIF_OK(dif_flash_ctrl_get_faults(&flash_ctrl_state, &faults)); - - CHECK(faults.memory_properties_error == 0, - "For flash memory_properties err exp 1 get 0"); - CHECK(faults.read_error == 0, "For flash read err exp 1 get 0"); - CHECK(faults.prog_window_error == 0, "For flash prog_window err exp 1 get 0"); - CHECK(faults.prog_type_error == 0, "For flash prog_type err exp 1 get 0"); - CHECK(faults.host_gnt_error == 0, "For flash host_gnt err exp 1 get 0"); - CHECK(faults.host_gnt_error == 0, "For flash host_gnt err exp 1 get 0"); - CHECK(faults.register_integrity_error == 0, - "For flash register_integrity err exp 1 get 0"); - CHECK(faults.phy_integrity_error == 0, - "For flash phy_integrity err exp 1 get 0"); - CHECK(faults.lifecycle_manager_error == 0, - "For flash lifecycle_manager err exp 1 get 0"); - CHECK(faults.shadow_storage_error == 0, - "For flash shadow_storage err exp 1 get 0"); +static void rram_macro_fault_checker(bool enable, const char *ip_inst, + const char *type) { + // TODO(#31009) + LOG_INFO("Expected alert %d rram_macro fault check is yet unimplemented", + kDtRramCtrlAlertFatalMacroErr); + trivial_fault_checker(enable, ip_inst, type); } static void rom_ctrl_fault_checker(bool enable, const char *ip_inst, @@ -749,8 +740,6 @@ void ottf_external_nmi_handler(uint32_t *exc_info) { */ static void init_peripherals(void) { #if defined(OPENTITAN_IS_EARLGREY) - CHECK_DIF_OK( - dif_flash_ctrl_init_state_from_dt(&flash_ctrl_state, kFlashCtrlDt)); CHECK_DIF_OK(dif_rom_ctrl_init_from_dt(kRomCtrlDt, &rom_ctrl)); #elif defined(OPENTITAN_IS_DARJEELING) CHECK_DIF_OK(dif_rom_ctrl_init_from_dt(kRomCtrl0Dt, &rom_ctrl0)); @@ -885,15 +874,15 @@ static void init_fault_checkers(fault_checker_t *checkers) { (fault_checker_t){trivial_fault_checker, entropy_src_inst_name, we_check}; static_assert(kDtEntropySrcCount >= 1, "This test needs an entropy src"); - checkers[dt_flash_ctrl_alert_to_alert_id( - kFlashCtrlDt, kDtFlashCtrlAlertFatalErr)] = (fault_checker_t){ - flash_ctrl_fault_checker, flash_ctrl_inst_name, flash_fatal_check}; - checkers[dt_flash_ctrl_alert_to_alert_id( - kFlashCtrlDt, kDtFlashCtrlAlertFatalStdErr)] = (fault_checker_t){ - flash_ctrl_fault_checker, flash_ctrl_inst_name, flash_fatal_check}; - checkers[dt_flash_ctrl_alert_to_alert_id( - kFlashCtrlDt, kDtFlashCtrlAlertFatalPrimFlashAlert)] = (fault_checker_t){ - flash_ctrl_prim_fault_checker, flash_ctrl_inst_name, flash_fatal_check}; + checkers[dt_rram_ctrl_alert_to_alert_id( + kRramCtrlDt, kDtRramCtrlAlertFatalStdErr)] = (fault_checker_t){ + rram_ctrl_fault_checker, rram_ctrl_inst_name, rram_fatal_check}; + checkers[dt_rram_ctrl_alert_to_alert_id( + kRramCtrlDt, kDtRramCtrlAlertFatalErr)] = (fault_checker_t){ + rram_ctrl_fatal_err_fault_checker, rram_ctrl_inst_name, rram_fatal_check}; + checkers[dt_rram_ctrl_alert_to_alert_id( + kRramCtrlDt, kDtRramCtrlAlertFatalMacroErr)] = (fault_checker_t){ + rram_macro_fault_checker, rram_macro_inst_name, rram_fatal_check}; checkers[dt_i2c_alert_to_alert_id((dt_i2c_t)1, kDtI2cAlertFatalFault)] = (fault_checker_t){trivial_fault_checker, i2c1_inst_name, we_check}; @@ -1120,20 +1109,7 @@ static void execute_test(const dif_aon_timer_t *aon_timer) { } #if defined(OPENTITAN_IS_EARLGREY) - // FlashCtrlFatalErr test requires host read request. - if (kExpectedAlertNumber == dt_flash_ctrl_alert_to_alert_id( - kFlashCtrlDt, kDtFlashCtrlAlertFatalErr)) { - enum { - kNumTestWords = 16, - kNumTestBytes = kNumTestWords * sizeof(uint32_t), - }; - uint32_t host_data[kNumTestWords]; - // Send host request to trigger host grant from flash_ctrl. - mmio_region_memcpy_from_mmio32( - mmio_region_from_addr( - dt_flash_ctrl_memory_base(kFlashCtrlDt, kDtFlashCtrlMemoryMem)), - FLASH_CTRL_PARAM_BYTES_PER_BANK, &host_data, kNumTestBytes); - } +// TODO(#31009): Trigger RramCtrlFatalErr. #elif defined(OPENTITAN_IS_DARJEELING) // Darjeeling does not have a Flash Controller #else @@ -1260,13 +1236,17 @@ bool test_main(void) { LOG_INFO("NMI count %d", nmi_count); #if defined(OPENTITAN_IS_EARLGREY) - // ISRs should not run if flash_ctrl or sram_ctrl_main get a fault because - // flash or sram accesses are blocked in those cases. For lc_ctrl fatal - // state, otp_fatal alerts tha will trigger LC to escalate, the lc_ctrl - // blocks the CPU. - if (kExpectedAlertNumber == - dt_flash_ctrl_alert_to_alert_id(kFlashCtrlDt, - kDtFlashCtrlAlertFatalStdErr) || + // ISRs should not run if rram_ctrl or sram_ctrl_main get a fault because + // RRAM or sram accesses are blocked in those cases (rram_ctrl.sv's + // `all_fatal_esc`, which drives local escalation, is asserted by + // FatalStdErr, and by FatalErr for any cause other than phy_relbl_err -- + // not by FatalMacroErr, which doesn't block access and is therefore not + // listed here). For lc_ctrl fatal state, otp_fatal alerts that will + // trigger LC to escalate, the lc_ctrl blocks the CPU. + if (kExpectedAlertNumber == dt_rram_ctrl_alert_to_alert_id( + kRramCtrlDt, kDtRramCtrlAlertFatalStdErr) || + kExpectedAlertNumber == dt_rram_ctrl_alert_to_alert_id( + kRramCtrlDt, kDtRramCtrlAlertFatalErr) || kExpectedAlertNumber == dt_sram_ctrl_alert_to_alert_id(kSramCtrlMainDt, kDtSramCtrlAlertFatalError) || @@ -1279,10 +1259,10 @@ bool test_main(void) { dt_otp_ctrl_alert_to_alert_id(kOtpCtrlDt, kDtOtpCtrlAlertFatalCheckError)) { CHECK(interrupt_count == 0, - "Expected regular ISR should not run for flash_ctrl, lc_ctrl fatal " + "Expected regular ISR should not run for rram_ctrl, lc_ctrl fatal " "state, or sram_ctrl_main faults"); CHECK(nmi_count == 0, - "Expected nmi should not run for flash_ctrl, lc_ctrl fatal state, " + "Expected nmi should not run for rram_ctrl, lc_ctrl fatal state, " "or sram_ctrl_main faults"); } else { CHECK(interrupt_count == 1, "Expected exactly one regular interrupt"); From 63abf0ca002b04e2a58d4db2435bf962cc424c13 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Sun, 16 Aug 2026 16:04:43 +0200 Subject: [PATCH 18/24] [top_earlgrey,doc] Update documentation The flash_ctrl references have been removed as RRAM is the only remaining NVM in Earl Grey. The section about system reset handling with RRAM has been updated but will need to be implemented in RTL (#31015) Signed-off-by: Michael Gautschi --- hw/top_earlgrey/doc/design/README.md | 72 ++++++---------------------- 1 file changed, 15 insertions(+), 57 deletions(-) diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index 50227ed1025b7..84e31f6ccf11d 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -81,32 +81,21 @@ The reset clock domain is identical to the table above, and the power domain map | rst_ast_tlul_i | main | | rst_ast_usb_i | main | -### System Reset Handling and Flash +### System Reset Handling and RRAM -Since `top_earlgrey` contains flash, it is important to examine the memory's relationship with resets. +Since `top_earlgrey` contains RRAM, it is important to examine the memory's relationship with resets. -For flash, resets that occur during a stateful operation (program or erase) must be carefully handled to ensure the flash memory is not damaged. -There are three reset scenarios: - -* Reset due to external supply lowering. -* Reset due to internal peripheral request. -* Reset due to lower power entry and exit. +Unlike flash, RRAM has no separate program or erase step; what would be a program or erase operation on flash is just a write operation on RRAM. #### Reset due to External Supply -Device resets due to supply dropping below a specific threshold are commonly known as "brown-out". -When this occurs, the flash memory must go through specialized sequencing to ensure the cells are not damaged. -This process is handled exclusively between ast and the flash. -Please see the [relevant section](../../ip/ast/README.md#main-vcc-power-detection-and-flash-protection) for more details. - -#### Reset due to Internal Request +Device resets due to supply dropping below a specific threshold are commonly known as a "brown-out". +When this occurs, the memory macro must go through appropriate sequencing, handled between ast and the memory, to ensure it is not damaged. -When the device receives an internal request to reset (for example [aon_timer](../../../ip/aon_timer/README.md#aon-watchdog-timer)), device power is kept on and the flash is directly reset. -It is assumed that the flash device, when powered, will be able to correctly handle such a sequence and properly protect itself. +#### Reset while Write in Progress -#### Reset due to Low Power Entry - -When the device receives a low power entry request while flash activity is ongoing, the [pwrmgr](../../ip_autogen/pwrmgr/README.md#abort-handling) is responsible for ensuring the entry request is aborted. +Resets that happen during a write operation need special care, because an incomplete write could leave the RRAM in an undefined state. +To that end, the RRAM controller indicates to the [pwrmgr](../../ip_autogen/pwrmgr/README.md#abort-handling) when a write is in progress, so that a reset or low power entry request can be aborted until the write completes. ### Main processor (`core_ibex`) @@ -143,7 +132,7 @@ The Ibex documentation has more details on the current pipeline operation, inclu ### Memory -The device contains four memory address spaces for instruction and data. +The device contains three memory address spaces for instruction and data. Instruction ROM (32kB) is the target for the Ibex processor after release of external reset. The ROM contains hard-coded instructions whose purpose is to do a minimal subset of platform checking before checking the next stage of code. @@ -153,28 +142,26 @@ The details of this check will come at a later date. For verification execute-time reasons, this RSA check will be overridable in the FPGA and verification platforms (details TBD). This is part of the *Secure Boot Process* that will be detailed in a security section in the future. -Earl Grey currently contains two non-volatile memory (NVM) technologies: 2MiB of embedded RRAM (resistive RAM) and 1024kB of embedded-flash (e-flash). -RRAM is now the NVM technology in active use: it houses the boot loader mentioned above, as well as the operating system and application that layers on top. -The flash controller is expected to be removed from the design soon. +Earl Grey contains 2MiB of embedded RRAM (resistive RAM), its non-volatile memory (NVM) technology: it houses the boot loader mentioned above, as well as the operating system and application that layers on top. At this time there is no operating system provided; applications are simple proof of concept code to show that the chip can do with a bare-metal framework. RRAM is the primary technology for code and data storage on Earl Grey. -Like flash, RRAM is a non-volatile memory technology, so software must interact with the [RRAM controller](#rram-controller) to write to it rather than writing to the standard memory address space directly; unlike flash, RRAM only requires a read/write interface, with no separate erase step. +Being a non-volatile memory technology, software must interact with the [RRAM controller](#rram-controller) to write to it rather than writing to the standard memory address space directly; unlike flash, RRAM only requires a read/write interface, with no separate erase step. The FPGA emulation of the memory approximates the read and write speeds and non-volatile nature that the RRAM macro exhibits in silicon. -Details on how flash and RRAM are used by software will be detailed in future Secure Boot Process and Software sections over time. +Details on how RRAM is used by software will be detailed in future Secure Boot Process and Software sections over time. The intent is for the contents of the NVM code to survive FPGA reset as it would as a NVM in silicon. Loading of the FPGA with initial content, or updating with new content, is described in other software specifications. -The SPI device peripheral is provided as a method to bulk-load either NVM. +The SPI device peripheral is provided as a method to bulk-load the NVM. The processor debug port (via JTAG) is also available for code loading. See those specifications for more details. Also included is a 128kB of SRAM available for data storage (stack, heap, etc.) by the Ibex processor. It is also available for code storage, though that is not its intended purpose. -The base address of the ROM, RRAM, Flash, and SRAM are given in the address map section later in this document. +The base address of the ROM, RRAM, and SRAM are given in the address map section later in this document. ### Secure boot @@ -337,7 +324,7 @@ The specification for the timer can be found [here](../../../ip/rv_timer/README. ##### RRAM Controller -The RRAM controller manages an emulated RRAM (resistive RAM) macro, and is Earl Grey's primary non-volatile storage peripheral for code and data, having replaced the flash controller (below) in that role. +The RRAM controller manages an emulated RRAM (resistive RAM) macro, and is Earl Grey's primary non-volatile storage peripheral for code and data, having replaced the flash controller in that role. It also houses emulated OTP (one-time programmable) functionality, replacing the use of a dedicated OTP macro. The primary read path for this data is in the standard memory address space. Writes on the other hand, need to be initiated by software which must interact with the RRAM controller. @@ -351,37 +338,8 @@ The RRAM controller peripheral in this release approximates the expected timing Security is also a concern, since secret data can be stored in the RRAM. The RRAM controller provides per-page memory protection, on-the-fly XEX scrambling (using the PRINCE cipher) with a key sideloaded from OTP, end-to-end bus integrity, and per-word address infection to protect against a range of physical and software attacks. A secure wipe of the RRAM contents with random data is also performed on entry to the RMA lifecycle state. -RRAM already has the ability to emulate OTP storage; it is planned to be connected to the OTP controller for this purpose in a future revision. For more details see the [RRAM controller module specification](../../../ip/rram_ctrl/README.md). -##### Flash Controller - -The final peripheral discussed in this release of the netlist is an emulated flash controller. -As mentioned in the memory section, flash has been superseded by RRAM as Earl Grey's primary NVM technology, and the flash controller is expected to be removed from the design soon. -The primary read path for this data is in the standard memory address space. -Writes to that address space are ignored, however, since one can not write to flash in a standard way. -Instead, to write to flash, software must interact with the flash controller. - -Flash functionality include three primary commands: read, erase, and program. -Read, as mentioned above, is standard, and uses the chip memory address space. -Erase is done at a page level, where the page size is parameterizable in the flash controller. -Upon receiving an erase request, the flash controller wipes all contents of that page, rendering the data in all `1`s state (`0xFFFFFFFF` per word). -Afterwards, software can program individual words to any value. -It is notable that software can continue to attempt to program words even before another erase, but it is not physically possible to return a flash bit back to a `'1'` state without another erase. -So future content is in effect an AND of the current content and the written value. - -``` -next_value = AND(current_value, write_word) -``` - -Erase and program are slow. -A typical erase time is measured in milliseconds, program times in microseconds. -The flash controller peripheral in this release approximates those expected times. - -Security is also a concern, since secret data can be stored in the flash. -Some memory protection is provided by the flash controller. -For more details see the [flash controller module specification](../../ip_autogen/flash_ctrl/README.md). - ### Interconnection Interconnecting the processor and peripheral and memory units is a bus network built upon the TileLink-Uncached-Light protocol. From 4b23b58414ddcf4ac9a74d58598c7641b1f4560a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 17 Aug 2026 16:02:22 +0200 Subject: [PATCH 19/24] [util,rram] make gen-rram-img slot aware When generating an rram image for the simulation we are adding the scrambling and address infection in the python script and then load the final image with the rram_ctrl_bkdr_util to the RRAM memories. The scrambling and address infection is different for slot A/B because the physical RRAM address is different. Hence, the gen-rram-img script needs to know for which slot it has to generate the simulation stimuli. This does not impact the normal *.128.vmem file which is loaded through the bootstrap protocol because this one does not yet include scrambling or address infection. Signed-off-by: Michael Gautschi --- .../dv/env/seq_lib/chip_sw_base_vseq.sv | 3 + rules/opentitan/cc.bzl | 12 ++++ rules/opentitan/defs.bzl | 8 ++- rules/opentitan/legacy.bzl | 8 +++ rules/opentitan/transform.bzl | 11 +++- sw/device/silicon_creator/rom/e2e/BUILD | 4 ++ sw/device/silicon_creator/rom_ext/BUILD | 4 +- util/design/gen-rram-img.py | 57 +++++++++++++++---- 8 files changed, 94 insertions(+), 13 deletions(-) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv index 2f30576460fd0..11374c29d86f0 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv @@ -125,6 +125,9 @@ class chip_sw_base_vseq extends chip_base_vseq; // TODO: support bootstrapping entire flash address space, not just slot A. end else begin + // Slot A and slot B images are each pre-scrambled (see gen-rram-img.py's --slot) for their + // true absolute address in the RRAM data partition, so their vmem files' own addresses + // don't overlap and can be loaded directly. if (cfg.sw_images.exists(SwTypeTestSlotA)) begin string image_path = {cfg.sw_images[SwTypeTestSlotA], ".128.scr.vmem"}; cfg.mem_bkdr_util_h[RramData].load_mem_from_file(image_path); diff --git a/rules/opentitan/cc.bzl b/rules/opentitan/cc.bzl index 7b88d8988772a..2ac0fd92d47bb 100644 --- a/rules/opentitan/cc.bzl +++ b/rules/opentitan/cc.bzl @@ -659,6 +659,18 @@ common_binary_attrs = { default = "flash", values = ["flash", "rram", "ram", "rom"], ), + "slot": attr.string( + doc = "Which firmware slot this binary occupies. Only relevant when kind == \"rram\": " + + "RRAM's scrambling tweak (and address infection) depend on the word's true " + + "absolute address in the (unified, slot-agnostic) RRAM data partition, but a " + + "slot's compiled image is always addressed starting at 0 (see " + + "gen-rram-img.py's --slot). Slot A starts at word address 0; slot B starts " + + "halfway through the data partition. \"virtual\" images are loaded via address " + + "translation rather than a fixed physical offset, so scrambling them is a build " + + "error - see scramble_rram().", + default = "a", + values = ["a", "b", "virtual"], + ), # FIXME(cfrantz): This should come from the ExecEnvInfo provider, but # I was unable to make that work. See the comment in `exec_env.bzl`. "extract_sw_logs": attr.label( diff --git a/rules/opentitan/defs.bzl b/rules/opentitan/defs.bzl index 3748e0edc7bd4..d9a0de4c3ecb8 100644 --- a/rules/opentitan/defs.bzl +++ b/rules/opentitan/defs.bzl @@ -267,7 +267,7 @@ def exec_env_to_top_map(exec_env): # binaries which can be compiled for the active top. # # See exec_env_to_top_map() for constraints on the exec_env for this work. -def opentitan_binary(name, exec_env, **kwargs): +def opentitan_binary(name, exec_env, kind = None, **kwargs): # Filter execution environments by top. ev_map = exec_env_to_top_map(exec_env) select_map = {} @@ -285,9 +285,15 @@ def opentitan_binary(name, exec_env, **kwargs): ["@platforms//:incompatible"], ) + # Default `kind` to "rram" on earlgrey, same as opentitan_test(), unless + # the caller passes an explicit `kind`. + if kind == None: + kind = opentitan_select_top({"earlgrey": _default_kind_for_top("earlgrey")}, "flash") + _opentitan_binary( name = name, exec_env = opentitan_select_top(select_map, []), + kind = kind, **kwargs ) diff --git a/rules/opentitan/legacy.bzl b/rules/opentitan/legacy.bzl index c129a4153e9fc..42735f8172c53 100644 --- a/rules/opentitan/legacy.bzl +++ b/rules/opentitan/legacy.bzl @@ -155,6 +155,14 @@ scramble_rram_vmem = rv_rule( attrs = { "src": attr.label(allow_single_file = True), "otp": attr.label(allow_single_file = True), + "slot": attr.string( + doc = "Which firmware slot `src` was linked for. `src` is a slot-relative " + + "(0-based) image, but address-infection and scrambling need the word's " + + "true absolute address in the RRAM data partition - see gen-rram-img.py's " + + "--slot.", + default = "a", + values = ["a", "b"], + ), "out": attr.string( default = "", doc = "Optional name for the output file. If provided the output name will be .scr.vmem otherwise .scr.vmem.", diff --git a/rules/opentitan/transform.bzl b/rules/opentitan/transform.bzl index 69c20552446eb..7f1437f9ce565 100644 --- a/rules/opentitan/transform.bzl +++ b/rules/opentitan/transform.bzl @@ -316,6 +316,9 @@ def scramble_rram(ctx, **kwargs): src: The src File object. otp: The OTP settings. otp_mmap: The OTP memory mapping file. + slot: Which firmware slot `src` was linked for ("a" or "b"). This matters for bkdr loading + the NVM content to the RRAM because RRAM's address-infection and scrambling depend on the + absolute RRAM address. top_secret_cfg: The secret configuration file. otp_data_perm: The OTP data permutation configuration. @@ -330,9 +333,13 @@ def scramble_rram(ctx, **kwargs): suffix = get_override(ctx, "attr.suffix", kwargs) output = "{}.{}".format(name, suffix) - output = ctx.actions.declare_file(output) src = get_override(ctx, "file.src", kwargs) otp = get_override(ctx, "file.otp", kwargs) + slot = get_override(ctx, "attr.slot", kwargs) + if slot == "virtual": + fail("Cannot scramble an RRAM image for the \"virtual\" slot.") + + output = ctx.actions.declare_file(output) inputs = [src] arguments = [ @@ -340,6 +347,8 @@ def scramble_rram(ctx, **kwargs): src.path, "--out-rram-vmem", output.path, + "--slot", + slot, ] # Always get top_secret_cfg since the tool requires it diff --git a/sw/device/silicon_creator/rom/e2e/BUILD b/sw/device/silicon_creator/rom/e2e/BUILD index 1997b3ea403ab..2bd5eb4fd6e82 100644 --- a/sw/device/silicon_creator/rom/e2e/BUILD +++ b/sw/device/silicon_creator/rom/e2e/BUILD @@ -94,6 +94,7 @@ opentitan_test( "//hw/top_darjeeling:sim_dv", ], linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_{}".format(slot), + slot = slot, deps = [ "//hw/top:otp_ctrl_c_regs", "//hw/top/dt", @@ -133,6 +134,7 @@ opentitan_test( "//hw/top_darjeeling:sim_dv", ], linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_{}".format(slot), + slot = slot, deps = [ "//hw/top:otp_ctrl_c_regs", "//hw/top/dt", @@ -161,6 +163,7 @@ opentitan_test( # We need to specify the manifest because the simulation environments do not # specify one by default. manifest = "//sw/device/silicon_creator/rom_ext:manifest", + slot = slot, deps = [ "//hw/top:otp_ctrl_c_regs", "//hw/top/dt", @@ -271,6 +274,7 @@ opentitan_test( src = ":empty_test_slot_{}_{}_corrupted_sim_dv_vmem128_signed".format(slot, key), # Override the name to match what the dv testbench expects. out = "empty_test_slot_{}_corrupted_sim_dv.{}.signed.128".format(slot, key), + slot = slot, ) for slot in SLOTS for key in SIGVERIFY_LC_KEYS diff --git a/sw/device/silicon_creator/rom_ext/BUILD b/sw/device/silicon_creator/rom_ext/BUILD index a5812beb80eb9..f2625209f2736 100644 --- a/sw/device/silicon_creator/rom_ext/BUILD +++ b/sw/device/silicon_creator/rom_ext/BUILD @@ -351,7 +351,8 @@ ROM_EXT_FEATURES = [ testonly = True, # TODO(#22780): Integrate real keys for A1 flows. ecdsa_key = {"//sw/device/silicon_creator/rom/keys/fake/ecdsa:ecdsa_keyset": "prod_key_0"}, - exec_env = [ + # "virtual" slot is only supported for FPGA targets. + exec_env = ["//hw/top_earlgrey:fpga_cw340"] if slot == "virtual" else [ "//hw/top_earlgrey:fpga_cw340", "//hw/top_earlgrey:sim_dv_base", "//hw/top_earlgrey:sim_verilator_base", @@ -359,6 +360,7 @@ ROM_EXT_FEATURES = [ ], linker_script = ":ld_slot_{}".format(slot), manifest = ":manifest", + slot = slot, spx_key = {"//sw/device/silicon_creator/rom/keys/fake/spx:spx_keyset": "prod_key_0"}, transitive_features = ROM_EXT_FEATURES, deps = [ diff --git a/util/design/gen-rram-img.py b/util/design/gen-rram-img.py index f958fcd553fb9..b39ca51423371 100755 --- a/util/design/gen-rram-img.py +++ b/util/design/gen-rram-img.py @@ -46,15 +46,27 @@ RRAM_ADDR_SIZE = 17 # bits RRAM_PRINCE_NUM_HALF_ROUNDS = 5 -# First RRAM word address in the OTP partition, i.e. the exclusive upper bound -# of the data partition. rram_ctrl_pkg::OtpStartPage * WordsPerPage -# = (TotalPages - OtpPages) * WordsPerPage = (4096 - 5) * 32. +# rram_ctrl_pkg::WordsPerPage. +RRAM_WORDS_PER_PAGE = 32 +# rram_ctrl_pkg::TotalDataPages = TotalBytes / (DataWidth / 8) / WordsPerPage = 4096. +RRAM_TOTAL_DATA_PAGES = 4096 +# rram_ctrl_pkg::OtpPages = TotalOtpBytes / (DataWidth / 8) / WordsPerPage = 5. +RRAM_OTP_PAGES = 5 + +# There are always exactly two slots splitting the full data partition evenly in half (see +# NVM_BYTES_PER_SLOT in sw/device/silicon_creator/lib/nvm_ctrl.h). +# slot A starts at word address 0, slot B starts halfway through. +RRAM_SLOT_B_START_WORD_ADDR = (RRAM_TOTAL_DATA_PAGES // 2) * RRAM_WORDS_PER_PAGE + +# First RRAM word address in the OTP partition, i.e. the exclusive upper bound of the (firmware) +# data partition. rram_ctrl_pkg::OtpStartPage * WordsPerPage +# = (TotalDataPages - OtpPages) * WordsPerPage. # This is also where rram_ctrl_otp.sv's per-64b-chunk integrity page starts. -RRAM_OTP_START_WORD_ADDR = 4091 * 32 +RRAM_OTP_START_WORD_ADDR = (RRAM_TOTAL_DATA_PAGES - RRAM_OTP_PAGES) * RRAM_WORDS_PER_PAGE # First RRAM word address of OTP's actual data (one page after # RRAM_OTP_START_WORD_ADDR - that first page is the integrity page). -# rram_ctrl_pkg::(OtpStartPage + 1) * WordsPerPage = 4092 * 32. -RRAM_OTP_DATA_START_WORD_ADDR = 4092 * 32 +# rram_ctrl_pkg::(OtpStartPage + 1) * WordsPerPage. +RRAM_OTP_DATA_START_WORD_ADDR = RRAM_OTP_START_WORD_ADDR + RRAM_WORDS_PER_PAGE # How OTP's 16b-native words pack into RRAM's 128b words and integrity bytes. # See rram_ctrl_otp.sv (OtpIntgDataWidth, OtpIntgWidth) and @@ -256,7 +268,8 @@ def _gen_otp_rram_vmem_lines(otp_vmem_file: str, def _reformat_rram_vmem( rram_vmem_file: str, - scrambling_configs: ScramblingConfigs) -> List[str]: + scrambling_configs: ScramblingConfigs, + addr_offset: int = 0) -> List[str]: # Open (raw) RRAM VMEM file and read into memory, skipping comment lines. try: rram_vmem = Path(rram_vmem_file).read_text() @@ -265,18 +278,27 @@ def _reformat_rram_vmem( rram_vmem_lines = re.findall(r"^@.*$", rram_vmem, flags=re.MULTILINE) # Add addr-infection and potentially scramble, each RRAM word. + # + # `--in-rram-vmem` is produced from a raw (headerless) binary extracted from the firmware + # ELF, so it is always addressed starting at 0 regardless of which slot the firmware was + # actually linked for (slot B's linker script places it at the true absolute address, but + # that address is lost when the ELF is flattened to a raw .bin). `addr_offset` restores the + # true absolute address before address-infecting/scrambling, since both of those are a + # function of the word's real physical address in the (unified, slot-agnostic) RRAM array. reformatted_vmem_lines = [] for line in rram_vmem_lines: line_items = line.split() reformatted_line = "" address = None address_offset = 0 + addr_hex_digits = None data = None for item in line_items: # Process the address first. if re.match(r"^@", item): - reformatted_line += item - address = int(item.lstrip("@"), 16) + addr_hex_digits = len(item) - 1 + address = int(item.lstrip("@"), 16) + addr_offset + reformatted_line += f"@{address:0{addr_hex_digits}x}" address_offset = 0 # Process the data words. else: @@ -345,6 +367,17 @@ def main(argv: List[str]): image a given test actually selects at runtime - it is only meant to supply scrambling-key seeds for the firmware image. """) + parser.add_argument("--slot", + type=str, + choices=["a", "b"], + help=""" + Which firmware slot --in-rram-vmem was linked for. Required together with + --in-rram-vmem/--out-rram-vmem: the input is a slot-relative (0-based) raw + binary dump, but address-infection and scrambling need the word's true + absolute address in the (unified, slot-agnostic) RRAM data partition. + Slot A starts at word address 0; slot B starts halfway through the data + partition. + """) parser.add_argument("--otp-data-perm", type=vmem_permutation_string, metavar="", @@ -389,9 +422,13 @@ def main(argv: List[str]): if args.in_rram_vmem or args.out_rram_vmem: if not (args.in_rram_vmem and args.out_rram_vmem): raise ValueError("--in-rram-vmem and --out-rram-vmem must be given together.") + if not args.slot: + raise ValueError("--slot is required together with --in-rram-vmem/--out-rram-vmem.") + addr_offset = RRAM_SLOT_B_START_WORD_ADDR if args.slot == "b" else 0 reformatted_vmem_lines = _reformat_rram_vmem(args.in_rram_vmem, - scrambling_configs) + scrambling_configs, + addr_offset) # Write re-formatted output file. Use binary mode and a large buffer size # to improve performance. From b269aa2ae5eafa93e1b0cf26609e22ecb63a1b8a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 17 Aug 2026 17:24:42 +0200 Subject: [PATCH 20/24] [dv,EarlGrey] Port chip_sw_ate* to RRAM These tests were still tailored to flash. Renaming flash to NVM (except SPI_FLASH which is the spi protocol) and adopt to the RRAM. (one data bank instead of two flash banks). Also generate and load 128vmem files instead of 64vmem files. Signed-off-by: Michael Gautschi --- .../chip_sw_ate_bootstrap_disjoint_vseq.sv | 74 ++++++------------- .../chip_sw_ate_bootstrap_flash_erase_vseq.sv | 10 +-- .../chip_sw_ate_bootstrap_one_frame_vseq.sv | 22 +++--- ...ip_sw_exit_test_unlocked_bootstrap_vseq.sv | 2 +- 4 files changed, 40 insertions(+), 68 deletions(-) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv index 3224ed3ee01b8..3d0219cd2c549 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_disjoint_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This test performs a the first two steps of a ROM bootstrap operation, i.e., flash erase followed -// by a single page program operation. It then confirms flash has been programmed, by backdoor +// This test performs a the first two steps of a ROM bootstrap operation, i.e., NVM erase followed +// by a single page program operation. It then confirms NVM has been programmed, by backdoor // reading back the first data page. class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; @@ -19,7 +19,7 @@ class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; byte sw_byte_q[$]; // The base class body function calls cpu_init, which calls spi_device_load_bootstrap. This will - // load up the contents of the firmware image into the two banks of flash. That will only happen + // load up the contents of the firmware image into the NVM. That will only happen // if a SW image exists: make sure it does and fail quickly if not. if (!cfg.sw_images.exists(SwTypeTestSlotA)) begin `uvm_fatal(get_name(), "Slot A image doesn't exist.") @@ -29,18 +29,18 @@ class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; // Read the SW frames again into a local queue. This feels a little silly (because we did it in // the base class as well), but it's reasonably quick. - sw_image = {cfg.sw_images[SwTypeTestSlotA], ".64.vmem"}; - read_sw_frames(sw_image, sw_byte_q); + sw_image = {cfg.sw_images[SwTypeTestSlotA], ".128.vmem"}; + read_sw_frames(sw_image, sw_byte_q, .word_size_bits(128)); - // Read back the programmed flash data page to confirm it was programmed correctly. + // Read back the programmed NVM data page to confirm it was programmed correctly. for (int a = 0; a < sw_byte_q.size; a += 4) begin bit [31:0] expected = {sw_byte_q[a + 3], sw_byte_q[a + 2], sw_byte_q[a + 1], sw_byte_q[a + 0]}; - if (!check_flash_word_32(a, expected)) num_errors++; + if (!check_nvm_word_32(a, expected)) num_errors++; end if (num_errors > 0) begin `uvm_error(get_name(), - $sformatf("Found %0d errors when checking programmed flash", num_errors)) + $sformatf("Found %0d errors when checking programmed NVM", num_errors)) end // Set test passed. @@ -51,7 +51,7 @@ class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; // This overrides a task in chip_sw_base_vseq // // We run the normal version *unless* the relevant range of byte_q happens to only contain 'hff. - // If it does, there is no need to write the page: we know that we have just erased flash to that + // If it does, there is no need to write the page: we know that we have just erased NVM to that // value anyway. protected virtual task spi_write_flash_page(const ref byte byte_q[$], int unsigned start_idx, @@ -74,62 +74,34 @@ class chip_sw_ate_bootstrap_disjoint_vseq extends chip_sw_base_vseq; end endtask - // Do a backdoor read of a 32-bit word in flash. On a match, return true. On a mismatch, generate + // Do a backdoor read of a 32-bit word in NVM. On a match, return true. On a mismatch, generate // a uvm_error describing the mismatch and return false. // - function bit check_flash_word_32(int unsigned address, bit [31:0] expected); - int unsigned rel_address; - chip_mem_e mem_idx; + function bit check_nvm_word_32(int unsigned address, bit [31:0] expected); + // RRAM backs the whole NVM data partition with one contiguous region (unlike flash, which + // backed slots A and B with two separate physical banks), so the SW address maps onto it + // directly and should never fall outside of it. + chip_mem_e mem_idx = RramData; logic [31:0] actual; - if (!expand_flash_address(address, rel_address, mem_idx)) begin - `uvm_error(get_name(), $sformatf("Cannot interpret 0x%0h as a flash address.", address)) + if (address >= cfg.mem_bkdr_util_h[mem_idx].get_size_bytes()) begin + `uvm_error(get_name(), + $sformatf("Address 0x%0h is out of range for the RRAM model (mem_idx %0p).", + address, mem_idx)) return 1'b0; end - // At this point, we know the slot and offset for the address. It might be that there isn't - // actually any flash memory backing the address. If the expected word is not '1, something has - // gone wrong (and we definitely won't have written anything). - if (rel_address >= cfg.mem_bkdr_util_h[mem_idx].get_depth()) begin - if (~&expected) begin - `uvm_error(get_name(), - $sformatf({"Address 0x%0h is intepreted as a relative address of 0x%0h ", - "in bank %0d, which is out of range for the flash model. ", - "The expected value is 0x%0h (not '1), ", - "so cannot have been written successfully."}, - address, rel_address, mem_idx, expected)) - end - - // If expected is '1, that's fine: we won't have sent the word over SPI. - return 1'b1; - end - - // If we get here, we have tried to write the word over SPI, or didn't bother because we wanted - // a value of '1 anyway. Look up the associated backdoor and check that the flash memory agrees. - actual = cfg.mem_bkdr_util_h[mem_idx].read32(rel_address); + // Look up the associated backdoor and check that the NVM memory agrees. + actual = cfg.mem_bkdr_util_h[mem_idx].read32(address); if (actual === expected) begin return 1'b1; end else begin `uvm_error(get_name(), - $sformatf({"Flash data mismatch at 0x%0h (mem_idx %0p; rel_address 0x%0h). ", + $sformatf({"NVM data mismatch at 0x%0h (mem_idx %0p). ", "We expected 0x%0h but saw 0x%0h."}, - address, mem_idx, rel_address, expected, actual)) + address, mem_idx, expected, actual)) return 1'b0; end endfunction - - // Extract a SW flash address into a relative address within RRAM's (single, unified) data - // partition. - // - // Unlike flash, which backed slots A and B with two separate physical banks, RRAM backs both - // slots with one contiguous region, so the SW address maps onto it directly with no per-slot - // offset. The out-of-range case is handled by the depth check at the call site below. - local function bit expand_flash_address(int unsigned address, - output int unsigned rel_address, - output chip_mem_e mem_idx); - mem_idx = RramData; - rel_address = address; - return 1'b1; - endfunction endclass diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv index 3c5992b669ba1..95409cc09e1e1 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_flash_erase_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This test performs a the first step of a ROM bootstrap operation, i.e., flash erase. It then -// confirms flash has been erased by reading back a few SPI flash frames to check they are all 1s +// This test performs a the first step of a ROM bootstrap operation, i.e., NVM erase. It then +// confirms NVM has been erased by reading back a few SPI flash frames to check they are all 1s // (which matches the erased state). class chip_sw_ate_bootstrap_flash_erase_vseq extends chip_sw_base_vseq; @@ -13,7 +13,7 @@ class chip_sw_ate_bootstrap_flash_erase_vseq extends chip_sw_base_vseq; super.new(name); endfunction - local function automatic void _check_flash_data_page(input int unsigned address, + local function automatic void _check_nvm_data_page(input int unsigned address, input bit [31:0] expected); logic [TL_DW-1:0] actual; actual = cfg.mem_bkdr_util_h[RramData].read32(address); @@ -45,9 +45,9 @@ class chip_sw_ate_bootstrap_flash_erase_vseq extends chip_sw_base_vseq; `uvm_info(get_name(), "Sending SPI flash erase command", UVM_LOW) erase_flash_over_spi(); - // Read first flash data word to confirm they are erased. + // Read first NVM data word to confirm they are erased. `uvm_info(get_name(), "Checking the first data word was erased", UVM_LOW) - _check_flash_data_page('h0, 32'hFFFF_FFFF); + _check_nvm_data_page('h0, 32'hFFFF_FFFF); // Set test passed. cfg.chip_vif.sw_straps_if.drive(3'h0); diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv index 7b9e4898192c5..e065b27de7654 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_ate_bootstrap_one_frame_vseq.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This test performs the first two steps of a ROM bootstrap operation, i.e., flash erase followed +// This test performs the first two steps of a ROM bootstrap operation, i.e., NVM erase followed // by a single page program operation. It then reads the first data page through a backdoor to check // this has been programmed. @@ -10,7 +10,7 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; `uvm_object_utils(chip_sw_ate_bootstrap_one_frame_vseq) `uvm_object_new - local function automatic void _check_flash_data_page(input integer address, + local function automatic void _check_nvm_data_page(input integer address, input integer expected); logic [TL_DW-1:0] actual; actual = cfg.mem_bkdr_util_h[RramData].read32(address); @@ -23,7 +23,7 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; byte sw_byte_q[$]; int unsigned SPI_FLASH_PAGE_SIZE = 256; - // Do the standard setup, including loading up the flash image with spi_device_load_bootstrap. + // Do the standard setup, including loading up the NVM image with spi_device_load_bootstrap. // // This sequence won't actually load the whole image (see the way we've overridden // spi_write_flash_stream) @@ -31,19 +31,19 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; // Read the SW frames again into a local queue. This feels a little silly (because we did it in // the base class as well), but it's reasonably quick. - sw_image = {cfg.sw_images[SwTypeTestSlotA], ".64.vmem"}; - read_sw_frames(sw_image, sw_byte_q); + sw_image = {cfg.sw_images[SwTypeTestSlotA], ".128.vmem"}; + read_sw_frames(sw_image, sw_byte_q, .word_size_bits(128)); - // Do a backdoor read to check that the first page of flash (which should have been loaded in + // Do a backdoor read to check that the first page of NVM (which should have been loaded in // super.body) has indeed been loaded. `uvm_info(`gfn, $sformatf("Checking page program succeeded\n"), UVM_LOW); for (int a = 0; a < SPI_FLASH_PAGE_SIZE; a += 4) begin bit [31:0] expected = {sw_byte_q[a+3], sw_byte_q[a+2], sw_byte_q[a+1], sw_byte_q[a+0]}; - if (!check_flash_word_32(a, expected)) num_errors++; + if (!check_nvm_word_32(a, expected)) num_errors++; end if (num_errors > 0) begin `uvm_error(get_name(), - $sformatf("Found %0d errors in first page of programmed flash", num_errors)) + $sformatf("Found %0d errors in first page of programmed NVM", num_errors)) end // Set test passed. @@ -65,17 +65,17 @@ class chip_sw_ate_bootstrap_one_frame_vseq extends chip_sw_base_vseq; super.spi_write_flash_stream(page_bytes, page_size); endtask - // Do a backdoor read of a 32-bit word from the first bank of flash. On a match, return true. On a + // Do a backdoor read of a 32-bit word from the first bank of NVM. On a match, return true. On a // mismatch, generate a uvm_error describing the mismatch and return false. // - local function bit check_flash_word_32(int unsigned address, bit [31:0] expected); + local function bit check_nvm_word_32(int unsigned address, bit [31:0] expected); logic [31:0] actual = cfg.mem_bkdr_util_h[RramData].read32(address); if (actual === expected) begin return 1'b1; end else begin `uvm_error(get_name(), - $sformatf({"Flash data mismatch at 0x%0h (in RramData). ", + $sformatf({"NVM data mismatch at 0x%0h (in RramData). ", "We expected 0x%0h but saw 0x%0h."}, address, expected, actual)) return 1'b0; diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv index c6d0d571eea88..32f3cf8bc54b4 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv @@ -86,7 +86,7 @@ class chip_sw_exit_test_unlocked_bootstrap_vseq extends chip_sw_base_vseq; `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInBootRom) // bootstrap the same image - spi_device_load_bootstrap({cfg.sw_images[SwTypeTestSlotA], ".64.vmem"}); + spi_device_load_bootstrap({cfg.sw_images[SwTypeTestSlotA], ".128.vmem"}); // Disable bootstrap for subsequent boots. cfg.use_spi_load_bootstrap = 1'b0; From 18b1916e933405a930782a0386aa99b207b23a71 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 17 Aug 2026 17:56:47 +0200 Subject: [PATCH 21/24] [earlgrey,formal] remove stale flash references for formal With the removal of flash_ctrl many connections dissapear. Updating the testplans and connectivity csvs. These still need to be updated for the RRAM, which will be done in a later stage. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/chip_conn_testplan.hjson | 84 ++----------------- .../data/ip/chip_alert_handler_testplan.hjson | 2 +- .../data/ip/chip_lc_ctrl_testplan.hjson | 11 +-- hw/top_earlgrey/formal/chip_conn_cfg.hjson | 2 - .../formal/conn_csvs/analog_sigs.csv | 3 - .../formal/conn_csvs/ast_flash.csv | 14 ---- .../formal/conn_csvs/ast_scanmode.csv | 1 - .../formal/conn_csvs/clkmgr_infra.csv | 3 - .../formal/conn_csvs/flash_ctrl.csv | 11 --- hw/top_earlgrey/formal/conn_csvs/jtag.csv | 8 -- .../formal/conn_csvs/lc_ctrl_broadcast.csv | 13 +-- .../formal/conn_csvs/rstmgr_resets_o.csv | 3 - 12 files changed, 13 insertions(+), 142 deletions(-) delete mode 100644 hw/top_earlgrey/formal/conn_csvs/ast_flash.csv delete mode 100644 hw/top_earlgrey/formal/conn_csvs/flash_ctrl.csv diff --git a/hw/top_earlgrey/data/chip_conn_testplan.hjson b/hw/top_earlgrey/data/chip_conn_testplan.hjson index 48606abb01f23..6504b643903c0 100644 --- a/hw/top_earlgrey/data/chip_conn_testplan.hjson +++ b/hw/top_earlgrey/data/chip_conn_testplan.hjson @@ -210,7 +210,6 @@ name: scanmode_connections desc: '''Verify the connectivity of scanmode to the following IPs: - clkmgr - - flash_ctrl - lc_ctrl - otp_ctrl - padring @@ -223,7 +222,7 @@ - xbar_peri ''' stage: V2 - tests: ["ast_scanmode_padring", "ast_scanmode_clkmgr", "ast_scanmode_flash_ctrl", + tests: ["ast_scanmode_padring", "ast_scanmode_clkmgr", "ast_scanmode_lc_ctrl", "ast_scanmode_otp_ctrl", "ast_scanmode_pinmux", "ast_scanmode_rstmgr", "ast_scanmode_rv_core_ibex", "ast_scanmode_rv_dm", "ast_scanmode_spi_device", "ast_scanmode_xbar_main", "ast_scanmode_xbar_peri"] @@ -386,7 +385,6 @@ name: clkmgr_clk_io_div4_infra desc: '''Verify clkmgr's `clk_io_div4_infra` is connected to the following block's clock input: - - flash_ctrl clk_otp_i - sram_ctrl main clk_otp_i - sram_ctrl retention clk_i - sram_ctrl retention clk_otp_i @@ -395,8 +393,7 @@ - xbar_peri clk_peri_i ''' stage: V2 - tests: ["clkmgr_infra_clk_flash_ctrl_otp_clk", - "clkmgr_infra_clk_sram_ctrl_main_otp_clk", + tests: ["clkmgr_infra_clk_sram_ctrl_main_otp_clk", "clkmgr_infra_clk_sram_ctrl_ret_clk", "clkmgr_infra_clk_sram_ctrl_ret_otp_clk", "clkmgr_infra_clk_sysrst_ctrl_clk", @@ -408,7 +405,6 @@ { name: clkmgr_clk_main_infra desc: '''Verify clkmgr's `clk_main_infra` is connected to the following blocks' clock input: - - flash_ctrl clk_i - rv_dm clk_i - rom_ctrl clk_i - rv_core_ibex clk_i @@ -417,8 +413,7 @@ - xbar_main clk_main_i ''' stage: V2 - tests: ["clkmgr_infra_clk_flash_ctrl_clk", - "clkmgr_infra_clk_rv_dm_clk", + tests: ["clkmgr_infra_clk_rv_dm_clk", "clkmgr_infra_clk_rom_clk", "clkmgr_infra_clk_rv_core_ibex_clk", "clkmgr_infra_clk_rv_core_ibex_edn_clk", @@ -739,20 +734,6 @@ tags: ["conn"] } - ///////////////////////// - // ast_flash.csv // - ///////////////////////// - { - name: ast_flash_ctrl - desc: '''Verify ast's flash signals are connected to the flash controller.''' - stage: V2 - tests: ["ast_flash_obs_ctrl", - "ast_flash_pwr_dwn_out", - "ast_flash_pwr_rdy_out", - "ast_flash_bist_en_out"] - si_stage: NA - tags: ["conn"] - } ///////////////////////////// // ast_entropy_src_cfg.csv // ///////////////////////////// @@ -773,15 +754,6 @@ ///////////////////////// // jtag.csv // ///////////////////////// - { - name: flash_jtag - desc: "Verify jtag interface is connected to flash_phy_req interface." - stage: V2 - tests: ["pinmux_flash_ctrl_tck", "pinmux_flash_ctrl_tms", "pinmux_flash_ctrl_tdi", - "pinmux_flash_ctrl_tdo", "pinmux_flash_ctrl_tdo_en"] - si_stage: NA - tags: ["conn"] - } { name: lc_jtag_trst desc: "Verify jtag rst pin is connected to lc_ctrl interface." @@ -802,7 +774,6 @@ - aon_timer - sram_ctrl main - sram_ctrl retention - - flash_ctrl - aes - kmac - otbn @@ -812,7 +783,6 @@ "lc_escalate_en_aon_timer", "lc_escalate_en_sram_main", "lc_escalate_en_sram_ret", - "lc_escalate_en_flash", "lc_escalate_en_aes", "lc_escalate_en_kmac", "lc_escalate_en_otbn"] @@ -828,14 +798,6 @@ si_stage: NA tags: ["conn"] } - { - name: lc_nvm_debug_en - desc: "Verify lc_ctrl's lc_nvm_debug_en is connected correctly to flash_ctrl." - stage: V2 - tests: ["lc_nvm_debug_en_flash_ctrl"] - si_stage: NA - tags: ["conn"] - } { name: lc_cpu_en desc: "Verify that the lc_ctrl's lc_cpu_en_o signal is correctly connected to rv_core_ibex." @@ -869,12 +831,10 @@ tags: ["conn"] } { - name: lc_flash_otbn_rma + name: lc_otbn_rma desc: "Verify lc_ctrl's RMA request connections." stage: V2 - tests: ["lc_rma_seed_flash_ctrl", - "lc_rma_req_flash_ctrl", - "flash_ctrl_rma_ack_otbn", + tests: ["lc_rma_req_otbn", "otbn_rma_ack_lc"] si_stage: NA tags: ["conn"] @@ -898,16 +858,11 @@ } { name: lc_access_control - desc: "Verify lc_ctrl's access control modulation signals are correctly connected to flash and OTP." + desc: "Verify lc_ctrl's access control modulation signals are correctly connected to OTP." stage: V2 tests: ["lc_creator_seed_sw_rw_en_otp", "lc_seed_hw_rd_en_otp", - "lc_rma_state_otp", - "lc_creator_seed_sw_rw_en_flash", - "lc_seed_hw_rd_en_flash", - "lc_owner_seed_sw_rw_en_flash", - "lc_iso_part_sw_rd_en_flash", - "lc_iso_part_sw_wr_en_flash"] + "lc_rma_state_otp"] si_stage: NA tags: ["conn"] } @@ -1218,7 +1173,6 @@ { name: rst_sys_io_div4_d0 desc: '''Verify rstmgr's rst_sys_io_div4_n[1] is connected to the following: - - flash_ctrl's rst_otp_ni - gpio's rst_ni - rv_timer's rst_ni - uart0's rst_ni @@ -1229,8 +1183,7 @@ - xbar_peri's rst_peri_ni ''' stage: V2 - tests: ["rstmgr_sys_io_div4_d0_flash_ctrl_rst_otp_ni", - "rstmgr_sys_io_div4_d0_gpio_rst_ni", + tests: ["rstmgr_sys_io_div4_d0_gpio_rst_ni", "rstmgr_sys_io_div4_d0_rv_timer_rst_ni", "rstmgr_sys_io_div4_d0_uart0_rst_ni", "rstmgr_sys_io_div4_d0_uart1_rst_ni", @@ -1251,7 +1204,6 @@ - edn0's rst_ni - edn1's rst_ni - entropy_src's rst_ni - - flash_ctrl's rst_ni - hmac's rst_ni - keymgr's rst_edn_ni - keymgr's rst_ni @@ -1275,7 +1227,6 @@ "rstmgr_sys_d0_edn0_rst_ni", "rstmgr_sys_d0_edn1_rst_ni", "rstmgr_sys_d0_entropy_src_rst_ni", - "rstmgr_sys_d0_flash_ctrl_rst_ni", "rstmgr_sys_d0_hmac_rst_ni", "rstmgr_sys_d0_keymgr_rst_edn_ni", "rstmgr_sys_d0_keymgr_rst_ni", @@ -1297,13 +1248,11 @@ name: rst_sys_shadowed_d0 desc: '''Verify rstmgr's rst_sys_shadowed_n[1] is connected to the following: - aes's rst_shadowed_ni - - flash_ctrl's rst_shadowed_ni - keymgr's rst_shadowed_ni - kmac's rst_shadowed_ni ''' stage: V2 tests: ["rstmgr_sys_shadowed_d0_aes_rst_shadowed_ni", - "rstmgr_sys_shadowed_d0_flash_ctrl_rst_shadowed_ni", "rstmgr_sys_shadowed_d0_keymgr_rst_shadowed_ni", "rstmgr_sys_shadowed_d0_kmac_rst_shadowed_ni"] si_stage: NA @@ -1492,23 +1441,6 @@ ///////////////////////// // analog_sigs.csv // ///////////////////////// - { - name: flash_ctrl_test_voltage - desc: "Verify the connectivity between the test voltage pad and flash_ctrl." - stage: V2 - tests: ["flash_test_volt"] - si_stage: NA - tags: ["conn"] - } - { - name: flash_ctrl_test_mode - desc: "Verify the connectivity between the test mode pads and flash_ctrl." - stage: V2 - tests: ["flash_test_mode0", - "flash_test_mode1"] - si_stage: NA - tags: ["conn"] - } { name: ast_adc desc: "Verify the connectivity between the CC pads and the ast ADC input." diff --git a/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson index f971785b36322..7f482857c6826 100644 --- a/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson @@ -203,7 +203,7 @@ - After wake up from normal sleep mode, clear all alert cause registers and check that all alerts are still firing after waking up. - Repeat the previous steps for random number of iterations. - - Fatal alerts from flash_ctrl, otp_ctrl, sram_ctrl, and lc_ctrl are omitted because + - Fatal alerts from rram_ctrl, otp_ctrl, sram_ctrl, and lc_ctrl are omitted because they disable the CPU and require a reset for the system to continue to function. ''' features: ["ALERT_HANDLER.PING_TIMER"] diff --git a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson index ad1087c9363fc..ed3d8e90625c4 100644 --- a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson @@ -160,14 +160,10 @@ - lc_hw_debug_en_o: impacts pinmux, pwrmgr, sram_ctrl (main and ret) & the rv_dm - lc_keymgr_en_o: impacts keymgr dpe - lc_clk_byp_req_o: impacts clkmgr (handshake with lc_clk_byp_ack_i) - - lc_nvm_rma_req_o: impacts flash_ctrl (handshake with lc_nvm_rma_ack_i) - - lc_nvm_rma_seed_o: impacts flash_ctrl + - lc_nvm_rma_req_o: impacts otbn (handshake with lc_nvm_rma_ack_i) - lc_check_byp_en_o: impacts otp_ctrl - - lc_creator_seed_sw_rw_en_o: impacts flash_ctrl & otp_ctrl - - lc_owner_seed_sw_rw_en_o: impacts flash_ctrl - - lc_iso_part_sw_rd_en_o: impacts flash_ctrl - - lc_iso_part_sw_wr_en_o: impacts flash_ctrl - - lc_seed_hw_rd_en_o: impacts flash_ctrl & otp_ctrl + - lc_creator_seed_sw_rw_en_o: impacts otp_ctrl + - lc_seed_hw_rd_en_o: impacts otp_ctrl - These outputs are enabled per the [life cycle architecture spec](doc/security/specs/device_life_cycle/README.md#architecture). @@ -176,7 +172,6 @@ Note that the following signals are already verified with connectivity tests and SVAs: - lc_dft_en_o (AST connection) - lc_cpu_en_o (rv_core_ibex) - - lc_nvm_debug_en_o (flash_ctrl) - lc_escalate_en_o (multiple) ''' stage: V2 diff --git a/hw/top_earlgrey/formal/chip_conn_cfg.hjson b/hw/top_earlgrey/formal/chip_conn_cfg.hjson index 59dab9112dd5e..b1dd5de68047b 100644 --- a/hw/top_earlgrey/formal/chip_conn_cfg.hjson +++ b/hw/top_earlgrey/formal/chip_conn_cfg.hjson @@ -22,7 +22,6 @@ "{conn_csvs_dir}/ast_rstmgr.csv", "{conn_csvs_dir}/ast_otp.csv", "{conn_csvs_dir}/ast_pwrmgr.csv", - "{conn_csvs_dir}/ast_flash.csv", "{conn_csvs_dir}/clkmgr_cg_en.csv", "{conn_csvs_dir}/clkmgr_idle.csv", "{conn_csvs_dir}/clkmgr_infra.csv", @@ -31,7 +30,6 @@ "{conn_csvs_dir}/clkmgr_secure.csv", "{conn_csvs_dir}/clkmgr_timers.csv", "{conn_csvs_dir}/clkmgr_trans.csv", - "{conn_csvs_dir}/flash_ctrl.csv", "{conn_csvs_dir}/jtag.csv", "{conn_csvs_dir}/lc_ctrl_broadcast.csv", "{conn_csvs_dir}/otp_lc_vendor_test.csv", diff --git a/hw/top_earlgrey/formal/conn_csvs/analog_sigs.csv b/hw/top_earlgrey/formal/conn_csvs/analog_sigs.csv index 2ff65cfc55117..fc2de3e1692b6 100644 --- a/hw/top_earlgrey/formal/conn_csvs/analog_sigs.csv +++ b/hw/top_earlgrey/formal/conn_csvs/analog_sigs.csv @@ -8,8 +8,5 @@ ,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,, CONNECTION, OTP_EXT_VOLT, , OTP_EXT_VOLT, top_earlgrey.earlgrey_pd_main.u_otp_macro , ext_voltage_h_io, -CONNECTION, FLASH_TEST_MODE0, , FLASH_TEST_MODE0, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, flash_test_mode_a_io[0], -CONNECTION, FLASH_TEST_MODE1, , FLASH_TEST_MODE1, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, flash_test_mode_a_io[1], -CONNECTION, FLASH_TEST_VOLT, , FLASH_TEST_VOLT, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, flash_test_voltage_h_io, CONNECTION, AST_CC1, , CC1, u_ast, adc_a0_ai, CONNECTION, AST_CC2, , CC2, u_ast, adc_a1_ai, diff --git a/hw/top_earlgrey/formal/conn_csvs/ast_flash.csv b/hw/top_earlgrey/formal/conn_csvs/ast_flash.csv deleted file mode 100644 index 2ca272832cf9b..0000000000000 --- a/hw/top_earlgrey/formal/conn_csvs/ast_flash.csv +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Run these checks with: -# dvsim hw/top_earlgrey/formal/chip_conn_cfg.hjson - -,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,, - -CONNECTION, FLASH_AST_OBS_CTRL_I, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, fla_obs_o, u_ast, fla_obs_i -CONNECTION, AST_FLASH_OBS_CTRL_O, u_ast, obs_ctrl_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, obs_ctrl_i -CONNECTION, AST_FLASH_PWR_DWN_O, u_ast, flash_power_down_h_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, flash_power_down_h_i -CONNECTION, AST_FLASH_PWR_RDY_O, u_ast, flash_power_ready_h_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, flash_power_ready_h_i -CONNECTION, AST_FLASH_BIST_EN_O, u_ast, flash_bist_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, bist_enable_i diff --git a/hw/top_earlgrey/formal/conn_csvs/ast_scanmode.csv b/hw/top_earlgrey/formal/conn_csvs/ast_scanmode.csv index 0ceeb2c8a1e90..e99b54c3c97e2 100644 --- a/hw/top_earlgrey/formal/conn_csvs/ast_scanmode.csv +++ b/hw/top_earlgrey/formal/conn_csvs/ast_scanmode.csv @@ -10,7 +10,6 @@ # Verify the scanmode connectivities. CONNECTION, AST_SCANMODE_PADRING, u_ast, dft_scan_md_o, u_padring, scanmode_i CONNECTION, AST_SCANMODE_CLKMGR, u_ast, dft_scan_md_o, top_earlgrey.earlgrey_pd_aon.u_clkmgr, scanmode_i -CONNECTION, AST_SCANMODE_FLASH_CTRL, u_ast, dft_scan_md_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, scanmode_i CONNECTION, AST_SCANMODE_LC_CTRL, u_ast, dft_scan_md_o, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, scanmode_i CONNECTION, AST_SCANMODE_OTP_CTRL, u_ast, dft_scan_md_o, top_earlgrey.earlgrey_pd_main.u_otp_macro, scanmode_i CONNECTION, AST_SCANMODE_PINMUX, u_ast, dft_scan_md_o, top_earlgrey.earlgrey_pd_main.u_pinmux, scanmode_i diff --git a/hw/top_earlgrey/formal/conn_csvs/clkmgr_infra.csv b/hw/top_earlgrey/formal/conn_csvs/clkmgr_infra.csv index 9ce0cb94ae42c..b05aa19aab913 100644 --- a/hw/top_earlgrey/formal/conn_csvs/clkmgr_infra.csv +++ b/hw/top_earlgrey/formal/conn_csvs/clkmgr_infra.csv @@ -8,9 +8,6 @@ ,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,, # clkmgr infra clock connectivity -# flash_ctrl -CONNECTION, CLKMGR_INFRA_CLK_FLASH_CTRL_CLK_OTP, top_earlgrey.earlgrey_pd_aon.u_clkmgr, clocks_o.clk_io_div4_infra, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, clk_otp_i -CONNECTION, CLKMGR_INFRA_CLK_FLASH_CTRL_CLK, top_earlgrey.earlgrey_pd_aon.u_clkmgr, clocks_o.clk_main_infra, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, clk_i #rv_dm CONNECTION, CLKMGR_INFRA_CLK_RV_DM_CLK, top_earlgrey.earlgrey_pd_aon.u_clkmgr, clocks_o.clk_main_infra, top_earlgrey.earlgrey_pd_main.u_rv_dm, clk_i diff --git a/hw/top_earlgrey/formal/conn_csvs/flash_ctrl.csv b/hw/top_earlgrey/formal/conn_csvs/flash_ctrl.csv deleted file mode 100644 index 9fb510ba2b471..0000000000000 --- a/hw/top_earlgrey/formal/conn_csvs/flash_ctrl.csv +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Run these checks with: -# dvsim hw/top_earlgrey/formal/chip_conn_cfg.hjson - -,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,, - -# flash_ctrl prim flash recov_alert connectivity -CONNECTION, RECOV_PRIM_FLASH_ALERT, top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash, recov_alert_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, alert_srcs[4] diff --git a/hw/top_earlgrey/formal/conn_csvs/jtag.csv b/hw/top_earlgrey/formal/conn_csvs/jtag.csv index 78584b7843f5e..ae2d22ad1699b 100644 --- a/hw/top_earlgrey/formal/conn_csvs/jtag.csv +++ b/hw/top_earlgrey/formal/conn_csvs/jtag.csv @@ -10,11 +10,3 @@ # Pinmux and lc_ctrl jtag connection. CONNECTION, PINMUX_LC_CTRL_JTAG_REQ, top_earlgrey.earlgrey_pd_main.u_pinmux, lc_jtag_o, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, jtag_i CONNECTION, PINMUX_LC_CTRL_JTAG_RSP, top_earlgrey.earlgrey_pd_main.u_pinmux, lc_jtag_i, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, jtag_o - -# Pinmux and flash_ctrl jtag connection. -CONNECTION, PINMUX_FLASH_CTRL_TCK, top_earlgrey.earlgrey_pd_main.u_pinmux, mio_to_periph_o[47], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, cio_tck_i -CONNECTION, PINMUX_FLASH_CTRL_TMS, top_earlgrey.earlgrey_pd_main.u_pinmux, mio_to_periph_o[48], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, cio_tms_i -CONNECTION, PINMUX_FLASH_CTRL_TDI, top_earlgrey.earlgrey_pd_main.u_pinmux, mio_to_periph_o[49], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, cio_tdi_i - -CONNECTION, PINMUX_FLASH_CTRL_TDO, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, cio_tdo_o, top_earlgrey.earlgrey_pd_main.u_pinmux, periph_to_mio_i[52] -CONNECTION, PINMUX_FLASH_CTRL_TDO_EN, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, cio_tdo_en_o, top_earlgrey.earlgrey_pd_main.u_pinmux, periph_to_mio_oe_i[52] diff --git a/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv b/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv index 91f75a24db40d..f4933e936d4f4 100644 --- a/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv +++ b/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv @@ -12,7 +12,6 @@ CONNECTION, LC_ESCALATE_EN_OTP, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, l CONNECTION, LC_ESCALATE_EN_AON_TIMER, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_aon.u_aon_timer, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_SRAM_MAIN, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_SRAM_RET, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret, lc_escalate_en_i -CONNECTION, LC_ESCALATE_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_AES, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_main.u_aes, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_KMAC, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_main.u_kmac, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_OTBN, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.earlgrey_pd_main.u_otbn, lc_escalate_en_i @@ -21,8 +20,6 @@ CONNECTION, LC_ESCALATE_EN_OTBN, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, l CONNECTION, LC_KEYMGR_EN_KEYMGR, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_keymgr_en_o, top_earlgrey.earlgrey_pd_main.u_keymgr_dpe, lc_keymgr_en_i CONNECTION, LC_KEYMGR_DIV_KEYMGR, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_keymgr_div_o, top_earlgrey.earlgrey_pd_main.u_keymgr_dpe, lc_keymgr_div_i -# Verify that lc_ctrl's lc_nvm_debug_en_o signal is correctly connected to flash_ctrl. -CONNECTION, LC_NVM_DEBUG_EN_FLASH_CTRL, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_debug_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_nvm_debug_en_i # Verify that the lc_ctrl's lc_cpu_en_o signal is correctly connected to rv_core_ibex. CONNECTION, LC_CPU_EN_RV_CORE_IBEX, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_cpu_en_o, top_earlgrey.earlgrey_pd_main.u_rv_core_ibex, lc_cpu_en_i @@ -42,9 +39,6 @@ CONNECTION, LC_DFT_EN_PINMUX, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_dft_en CONNECTION, LC_DFT_EN_AST, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_dft_en_o, u_ast, lc_dft_en_i # Verify lc_ctrl's RMA request connections. -CONNECTION, LC_RMA_SEED_FLASH_CTRL, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_rma_seed_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rma_seed_i -CONNECTION, LC_RMA_REQ_FLASH_CTRL, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_rma_req_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rma_req_i -CONNECTION, FLASH_CTRL_RMA_ACK_LC, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rma_ack_o, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_rma_ack_i[0] CONNECTION, LC_RMA_REQ_OTBN, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_rma_req_o, top_earlgrey.earlgrey_pd_main.u_otbn, lc_rma_req_i CONNECTION, OTBN_RMA_ACK_LC, top_earlgrey.earlgrey_pd_main.u_otbn, lc_rma_ack_o, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_nvm_rma_ack_i[1] @@ -55,12 +49,7 @@ CONNECTION, CLKMGR_CLK_BYP_ACK_LC, top_earlgrey.earlgrey_pd_aon.u_clkmgr, lc_c # Verify lc_ctrl's check bypass signal is correctly connected to OTP (used when programming a life cycle transition). CONNECTION, LC_CHECK_BYP_EN_OTP, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_check_byp_en_o, top_earlgrey.earlgrey_pd_main.u_otp_ctrl, lc_check_byp_en_i -# Verify lc_ctrl's access control modulation signals are correctly connected to flash and OTP. +# Verify lc_ctrl's access control modulation signals are correctly connected to OTP. CONNECTION, LC_CREATOR_SEED_SW_RW_EN_OTP, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_creator_seed_sw_rw_en_o, top_earlgrey.earlgrey_pd_main.u_otp_ctrl, lc_creator_seed_sw_rw_en_i CONNECTION, LC_SEED_HW_RD_EN_OTP, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_seed_hw_rd_en_o, top_earlgrey.earlgrey_pd_main.u_otp_ctrl, lc_seed_hw_rd_en_i CONNECTION, LC_RMA_STATE_OTP, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_rma_state_o, top_earlgrey.earlgrey_pd_main.u_otp_ctrl, lc_rma_state_i -CONNECTION, LC_CREATOR_SEED_SW_RW_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_creator_seed_sw_rw_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_creator_seed_sw_rw_en_i -CONNECTION, LC_SEED_HW_RD_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_seed_hw_rd_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_seed_hw_rd_en_i -CONNECTION, LC_OWNER_SEED_SW_RW_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_owner_seed_sw_rw_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_owner_seed_sw_rw_en_i -CONNECTION, LC_ISO_PART_SW_RD_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_iso_part_sw_rd_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_iso_part_sw_rd_en_i -CONNECTION, LC_ISO_PART_SW_WR_EN_FLASH, top_earlgrey.earlgrey_pd_main.u_lc_ctrl, lc_iso_part_sw_wr_en_o, top_earlgrey.earlgrey_pd_main.u_flash_ctrl, lc_iso_part_sw_wr_en_i diff --git a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv index 3bd62b9df206c..2243162294a2a 100644 --- a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv +++ b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv @@ -62,9 +62,6 @@ CONNECTION, RSTMGR_LC_IO_DIV4_AON_SENSOR_CTRL_RST_NI, top_earlgrey.earlgrey_pd_a CONNECTION, RSTMGR_LC_AON_AON_SENSOR_CTRL_RST_AON_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_aon_n[0], top_earlgrey.earlgrey_pd_aon.u_sensor_ctrl, rst_aon_ni CONNECTION, RSTMGR_LC_IO_DIV4_AON_SRAM_CTRL_RET_RST_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_io_div4_n[0], top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret, rst_ni CONNECTION, RSTMGR_LC_IO_DIV4_AON_SRAM_CTRL_RET_RST_OTP_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_io_div4_n[0], top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret, rst_otp_ni -CONNECTION, RSTMGR_LC_D0_FLASH_CTRL_RST_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_n[1], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rst_ni -CONNECTION, RSTMGR_LC_SHADOWED_D0_FLASH_CTRL_RST_SHADOWED_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_shadowed_n[1], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rst_shadowed_ni -CONNECTION, RSTMGR_LC_IO_DIV4_D0_FLASH_CTRL_RST_OTP_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_io_div4_n[1], top_earlgrey.earlgrey_pd_main.u_flash_ctrl, rst_otp_ni CONNECTION, RSTMGR_SYS_D0_RV_DM_RST_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_sys_n[1], top_earlgrey.earlgrey_pd_main.u_rv_dm, rst_ni CONNECTION, RSTMGR_LC_D0_RV_PLIC_RST_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_n[1], top_earlgrey.earlgrey_pd_main.u_rv_plic, rst_ni CONNECTION, RSTMGR_LC_D0_AES_RST_NI, top_earlgrey.earlgrey_pd_aon.u_rstmgr, resets_o.rst_lc_n[1], top_earlgrey.earlgrey_pd_main.u_aes, rst_ni From 4a6c5bf59a85b4bd692945ff2d75217d70c1f62e Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 17 Aug 2026 20:44:37 +0200 Subject: [PATCH 22/24] [sw,dv,csrng_test] use nvm_ctrl in port csrng_lc_hw_debug_en_test Signed-off-by: Michael Gautschi --- sw/device/tests/sim_dv/BUILD | 3 +- .../tests/sim_dv/csrng_lc_hw_debug_en_test.c | 33 +++++-------------- 2 files changed, 9 insertions(+), 27 deletions(-) diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index 7f4954209dbc9..912e1e28ffb83 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -746,7 +746,6 @@ opentitan_test( "//sw/device/lib/base:mmio", "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:kmac", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", @@ -755,7 +754,7 @@ opentitan_test( "//sw/device/lib/testing:csrng_testutils", "//sw/device/lib/testing:entropy_src_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otp_ctrl_testutils", "//sw/device/lib/testing:rand_testutils", "//sw/device/lib/testing:rstmgr_testutils", diff --git a/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c b/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c index 7877537d4b5b2..29b7eab893fee 100644 --- a/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c +++ b/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c @@ -6,7 +6,6 @@ #include "sw/device/lib/base/mmio.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_kmac.h" #include "sw/device/lib/dif/dif_lc_ctrl.h" #include "sw/device/lib/dif/dif_otp_ctrl.h" @@ -15,7 +14,7 @@ #include "sw/device/lib/testing/csrng_testutils.h" #include "sw/device/lib/testing/entropy_src_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/flash_ctrl_testutils.h" +#include "sw/device/lib/testing/nvm_testutils.h" #include "sw/device/lib/testing/otp_ctrl_testutils.h" #include "sw/device/lib/testing/rand_testutils.h" #include "sw/device/lib/testing/rstmgr_testutils.h" @@ -44,7 +43,7 @@ enum { kExitTokenSizeInWords = kExitTokenSizeInBytes / sizeof(uint32_t), }; -// Store CSRNG output in flash to compare results across life cycle stages. +// Store CSRNG output in NVM to compare results across life cycle stages. OT_SET_BSS_SECTION(".non_volatile_scratch", uint32_t nv_csrng_output[kEntropyFifoBufferSize];) @@ -52,7 +51,6 @@ static dif_lc_ctrl_t lc_ctrl; static dif_otp_ctrl_t otp_ctrl; static dif_csrng_t csrng; static dif_entropy_src_t entropy_src; -static dif_flash_ctrl_state_t flash_ctrl_state; static dif_kmac_t kmac; static dif_rstmgr_t rstmgr; @@ -114,10 +112,6 @@ static void peripherals_init(void) { CHECK_DIF_OK(dif_rstmgr_init( mmio_region_from_addr(TOP_EARLGREY_RSTMGR_BASE_ADDR), &rstmgr)); - CHECK_DIF_OK(dif_flash_ctrl_init_state( - &flash_ctrl_state, - mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); - kmac_init(); } @@ -290,14 +284,8 @@ static void csrng_static_generate_run(uint32_t *output, size_t output_len) { bool test_main(void) { peripherals_init(); - CHECK_STATUS_OK( - flash_ctrl_testutils_default_region_access(&flash_ctrl_state, - /*rd_en=*/true, - /*prog_en=*/true, - /*erase_en=*/true, - /*scramble_en=*/false, - /*ecc_en=*/false, - /*he_en=*/false)); + CHECK_STATUS_OK(nvm_testutils_default_region_setup(kNvmPagePermsReadWrite, + kNvmPageCfgRaw)); dif_rstmgr_reset_info_bitfield_t rst_info = rstmgr_testutils_reason_get(); rstmgr_testutils_reason_clear(); @@ -308,17 +296,12 @@ bool test_main(void) { if (rst_info == kDifRstmgrResetInfoPor && lc_state == kDifLcCtrlStateTestUnlocked0) { - enum { - kPartitionId = 0, - }; - uint32_t address = - (uint32_t)(nv_csrng_output)-TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + uint32_t address = (uint32_t)(nv_csrng_output)-NVM_DATA_BASE_ADDR; uint32_t expected[kEntropyFifoBufferSize]; csrng_static_generate_run(expected, ARRAYSIZE(expected)); - CHECK_STATUS_OK(flash_ctrl_testutils_write(&flash_ctrl_state, address, - /*partition_id=*/0, expected, - kDifFlashCtrlPartitionTypeData, - ARRAYSIZE(expected))); + CHECK_STATUS_OK(nvm_testutils_data_write(address, expected, + ARRAYSIZE(expected), + /*erase_before_write=*/true)); CHECK_ARRAYS_EQ(nv_csrng_output, expected, ARRAYSIZE(expected)); lock_otp_secret0_partition(); From 26d89a5860a4692f7d154c0aeed9412f006b1750 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 18 Aug 2026 12:47:15 +0200 Subject: [PATCH 23/24] [rram_ctrl,dv,sw] Port flash_ctrl_lc_rw_en test to rram - Rename to rram_ctrl_lc_rw_en - use nvm_* calls in rram_ctrl_lc_rw_en.c with few RRAM specific things - add this test back to the testplan. Signed-off-by: Michael Gautschi --- .../data/ip/chip_lc_ctrl_testplan.hjson | 8 ++- hw/top_earlgrey/dv/chip_sim_cfg.hjson | 7 ++ hw/top_earlgrey/dv/env/chip_env.core | 3 +- ....sv => chip_sw_rram_ctrl_lc_rw_en_vseq.sv} | 4 +- .../dv/env/seq_lib/chip_vseq_list.sv | 1 + sw/device/tests/sim_dv/BUILD | 7 +- ...rw_en_test.c => rram_ctrl_lc_rw_en_test.c} | 71 +++++++++++-------- 7 files changed, 63 insertions(+), 38 deletions(-) rename hw/top_earlgrey/dv/env/seq_lib/{chip_sw_flash_ctrl_lc_rw_en_vseq.sv => chip_sw_rram_ctrl_lc_rw_en_vseq.sv} (95%) rename sw/device/tests/sim_dv/{flash_ctrl_lc_rw_en_test.c => rram_ctrl_lc_rw_en_test.c} (80%) diff --git a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson index ed3d8e90625c4..080ac1e91231a 100644 --- a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson @@ -162,8 +162,11 @@ - lc_clk_byp_req_o: impacts clkmgr (handshake with lc_clk_byp_ack_i) - lc_nvm_rma_req_o: impacts otbn (handshake with lc_nvm_rma_ack_i) - lc_check_byp_en_o: impacts otp_ctrl - - lc_creator_seed_sw_rw_en_o: impacts otp_ctrl - - lc_seed_hw_rd_en_o: impacts otp_ctrl + - lc_creator_seed_sw_rw_en_o: impacts otp_ctrl & rram_ctrl + - lc_seed_hw_rd_en_o: impacts otp_ctrl & rram_ctrl + - lc_owner_seed_sw_rw_en_o: impacts rram_ctrl + - lc_iso_part_sw_rd_en_o: impacts rram_ctrl + - lc_iso_part_sw_wr_en_o: impacts rram_ctrl - These outputs are enabled per the [life cycle architecture spec](doc/security/specs/device_life_cycle/README.md#architecture). @@ -196,6 +199,7 @@ "chip_sw_otp_ctrl_lc_signals_dev", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_otp_ctrl_lc_signals_prod", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_otp_ctrl_lc_signals_rma", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl + "chip_sw_rram_ctrl_lc_rw_en", // lc_creator*, lc_seed*, lc_owner*, lc_iso*: rram_ctrl ] } { diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 9cd98f2902dd4..3ddfbc049e44c 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -915,6 +915,13 @@ run_opts: ["+bypass_alert_ready_to_end_check=1"] reseed: 3 } + { + name: chip_sw_rram_ctrl_lc_rw_en + uvm_test_seq: chip_sw_rram_ctrl_lc_rw_en_vseq + sw_images: ["//sw/device/tests/sim_dv:rram_ctrl_lc_rw_en_test:1:new_rules"] + run_opts: ["+bypass_alert_ready_to_end_check=1"] + en_run_modes: ["sw_test_mode_test_rom"] + } { name: chip_sw_lc_walkthrough_dev uvm_test_seq: chip_sw_lc_walkthrough_vseq diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index 9c587da6cd02f..c4f2081895282 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -86,8 +86,7 @@ filesets: - seq_lib/chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_gpio_smoke_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_gpio_vseq.sv: {is_include_file: true} - - seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv: {is_include_file: true} - - seq_lib/chip_sw_flash_rma_unlocked_vseq.sv: {is_include_file: true} + - seq_lib/chip_sw_rram_ctrl_lc_rw_en_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_transition_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_ctrl_lc_rw_en_vseq.sv similarity index 95% rename from hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv rename to hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_ctrl_lc_rw_en_vseq.sv index 9ac11e218c644..b96999cf621c4 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_ctrl_lc_rw_en_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_ctrl_lc_rw_en_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class chip_sw_flash_ctrl_lc_rw_en_vseq extends chip_sw_base_vseq; - `uvm_object_utils(chip_sw_flash_ctrl_lc_rw_en_vseq) +class chip_sw_rram_ctrl_lc_rw_en_vseq extends chip_sw_base_vseq; + `uvm_object_utils(chip_sw_rram_ctrl_lc_rw_en_vseq) `uvm_object_new diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv index 3c322543aafa6..4af0f502cd831 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv @@ -41,6 +41,7 @@ `include "chip_sw_lc_volatile_raw_unlock_vseq.sv" `include "chip_sw_lc_walkthrough_vseq.sv" `include "chip_sw_lc_walkthrough_testunlocks_vseq.sv" +`include "chip_sw_rram_ctrl_lc_rw_en_vseq.sv" `include "chip_sw_otp_ctrl_escalation_vseq.sv" `include "chip_sw_spi_host_tx_rx_vseq.sv" `include "chip_sw_spi_passthrough_vseq.sv" diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index 912e1e28ffb83..2923f76712f00 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -49,21 +49,20 @@ opentitan_test( ) opentitan_test( - name = "flash_ctrl_lc_rw_en_test", - srcs = ["flash_ctrl_lc_rw_en_test.c"], + name = "rram_ctrl_lc_rw_en_test", + srcs = ["rram_ctrl_lc_rw_en_test.c"], exec_env = {"//hw/top_earlgrey:sim_dv": None}, deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:macros", "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:keymgr_dpe", "//sw/device/lib/dif:kmac", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:flash_ctrl_testutils", "//sw/device/lib/testing:keymgr_dpe_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing/test_framework:ottf_main", ], ) diff --git a/sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c b/sw/device/tests/sim_dv/rram_ctrl_lc_rw_en_test.c similarity index 80% rename from sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c rename to sw/device/tests/sim_dv/rram_ctrl_lc_rw_en_test.c index 6ae2ba1ec17fa..1af6cea5eed1a 100644 --- a/sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c +++ b/sw/device/tests/sim_dv/rram_ctrl_lc_rw_en_test.c @@ -2,22 +2,22 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "hw/top/dt/rram_ctrl.h" #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_keymgr_dpe.h" #include "sw/device/lib/dif/dif_kmac.h" #include "sw/device/lib/dif/dif_lc_ctrl.h" #include "sw/device/lib/dif/dif_otp_ctrl.h" #include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/flash_ctrl_testutils.h" #include "sw/device/lib/testing/keymgr_dpe_testutils.h" +#include "sw/device/lib/testing/nvm_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/lib/testing/test_framework/ottf_alerts.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" -static dif_flash_ctrl_state_t flash; static dif_keymgr_dpe_t keymgr_dpe; static dif_kmac_t kmac; static dif_lc_ctrl_t lc; @@ -26,15 +26,10 @@ static dif_otp_ctrl_t otp; OTTF_DEFINE_TEST_CONFIG(); enum { - kFlashInfoPageIdCreatorSecret = 1, - kFlashInfoPageIdOwnerSecret = 2, - kFlashInfoPageIdIsoPart = 3, kPartSize = 16, - kBankId = 0, - kPartitionId = 0, }; -// Random data to read/write to flash partitions. +// Random data to read/write to NVM info partitions. const uint32_t kCreatorSecretTest[kPartSize] = { 0xb295d21b, 0xecdfbdcd, 0x67e7ab2d, 0x6f660b08, 0x273bf65c, 0xe80f1695, @@ -71,7 +66,7 @@ typedef struct partition_check_cfg { check_id_t check_id; // Page ID of the partition to check. - uint32_t page_id; + nvm_info_page_t page_id; // Data to write to the partition. const uint32_t *data; @@ -96,7 +91,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdUnprovisionedCreatorSeed] = { .check_id = kCheckIdUnprovisionedCreatorSeed, - .page_id = kFlashInfoPageIdCreatorSecret, + .page_id = kNvmInfoPageCreatorSecret, .data = kCreatorSecretTest, .size = kPartSize, .do_write = true, @@ -107,7 +102,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdUnprovisonedOwnerSeed] = { .check_id = kCheckIdUnprovisonedOwnerSeed, - .page_id = kFlashInfoPageIdOwnerSecret, + .page_id = kNvmInfoPageOwnerSecret, .data = kOwnerSecretTest, .size = kPartSize, .do_write = true, @@ -118,7 +113,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdLcDevIsoPartAccess] = { .check_id = kCheckIdLcDevIsoPartAccess, - .page_id = kFlashInfoPageIdIsoPart, + .page_id = kNvmInfoPageWaferAuthSecret, .data = kIsoPartData, .size = kPartSize, .do_write = true, @@ -129,7 +124,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdProvisionedCreatorSeed] = { .check_id = kCheckIdProvisionedCreatorSeed, - .page_id = kFlashInfoPageIdCreatorSecret, + .page_id = kNvmInfoPageCreatorSecret, .data = kCreatorSecretTest, .size = kPartSize, .do_write = true, @@ -140,7 +135,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdProvisionedOwnerSeed] = { .check_id = kCheckIdProvisionedOwnerSeed, - .page_id = kFlashInfoPageIdOwnerSecret, + .page_id = kNvmInfoPageOwnerSecret, .data = kOwnerSecretTest, .size = kPartSize, .do_write = true, @@ -151,7 +146,7 @@ static const partition_check_cfg_t kTest[] = { [kCheckIdLcProdIsoPartAccess] = { .check_id = kCheckIdLcProdIsoPartAccess, - .page_id = kFlashInfoPageIdIsoPart, + .page_id = kNvmInfoPageWaferAuthSecret, .data = kIsoPartData, .size = kPartSize, .do_write = false, @@ -173,19 +168,29 @@ static void init_peripheral_handles(void) { dif_kmac_init(mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR), &kmac)); CHECK_DIF_OK(dif_lc_ctrl_init( mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR), &lc)); - CHECK_DIF_OK(dif_flash_ctrl_init_state( - &flash, mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); } static void partition_check(const partition_check_cfg_t cfg) { - uint32_t address = 0; - CHECK_STATUS_OK(flash_ctrl_testutils_info_region_setup( - &flash, cfg.page_id, kBankId, kPartitionId, &address)); + CHECK_STATUS_OK(nvm_testutils_info_page_setup( + cfg.page_id, kNvmPagePermsReadWrite, kNvmPageCfgPlain)); if (cfg.do_write) { - status_t result = flash_ctrl_testutils_erase_and_write_page( - &flash, address, kPartitionId, cfg.data, kDifFlashCtrlPartitionTypeInfo, - cfg.size); + // A permission-denied access completes with rram_ctrl's `mp_err`/`wr_err` + // set, which raises the `recov_err` alert as a side effect. Denied writes + // must be alert-expected or the OTTF alert catcher fails the test. + if (!cfg.expect_write_ok) { + CHECK_STATUS_OK( + ottf_alerts_expect_alert_start(dt_rram_ctrl_alert_to_alert_id( + kDtRramCtrlFirst, kDtRramCtrlAlertRecovErr))); + } + status_t result = nvm_testutils_write_info_page( + cfg.page_id, /*byte_offset=*/0, cfg.data, cfg.size, + /*erase_before_write=*/true, /*readback=*/false); + if (!cfg.expect_write_ok) { + CHECK_STATUS_OK( + ottf_alerts_expect_alert_finish(dt_rram_ctrl_alert_to_alert_id( + kDtRramCtrlFirst, kDtRramCtrlAlertRecovErr))); + } if (cfg.expect_write_ok) { CHECK_STATUS_OK(result); @@ -196,9 +201,19 @@ static void partition_check(const partition_check_cfg_t cfg) { if (cfg.do_read) { uint32_t readback_data[cfg.size]; - status_t result = - flash_ctrl_testutils_read(&flash, address, kPartitionId, readback_data, - kDifFlashCtrlPartitionTypeInfo, cfg.size, 0); + // Same as above: a denied read also raises `recov_err`. + if (!cfg.expect_read_ok) { + CHECK_STATUS_OK( + ottf_alerts_expect_alert_start(dt_rram_ctrl_alert_to_alert_id( + kDtRramCtrlFirst, kDtRramCtrlAlertRecovErr))); + } + status_t result = nvm_testutils_read_info_page( + cfg.page_id, /*byte_offset=*/0, readback_data, cfg.size); + if (!cfg.expect_read_ok) { + CHECK_STATUS_OK( + ottf_alerts_expect_alert_finish(dt_rram_ctrl_alert_to_alert_id( + kDtRramCtrlFirst, kDtRramCtrlAlertRecovErr))); + } if (cfg.expect_read_ok) { CHECK_STATUS_OK(result); @@ -235,7 +250,7 @@ bool test_main(void) { .entropy_mode = kDifKmacEntropyModeSoftware, })); - // chip_sw_flash_ctrl_lc_rw_en_vseq steps through DEV and PROD LC states. + // chip_sw_rram_ctrl_lc_rw_en_vseq steps through DEV and PROD LC states. // DEV LC state: // - Initial state: Unprovisioned. // - Final state: Provisioned. From 021f26d50923e69d8f564dbe1be0dd42fcc49796 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 18 Aug 2026 12:49:09 +0200 Subject: [PATCH 24/24] [rram_ctrl,dv,sw] Port flash_rma_unlocked to RRAM - rename to rram_rma_unlocked - use nvm_ functions in rram_rma_unlocked_test.c - add this test back to the testplan Signed-off-by: Michael Gautschi --- .../data/ip/chip_lc_ctrl_testplan.hjson | 4 +- hw/top_earlgrey/dv/chip_sim_cfg.hjson | 8 + hw/top_earlgrey/dv/env/chip_env.core | 1 + ...q.sv => chip_sw_rram_rma_unlocked_vseq.sv} | 4 +- .../dv/env/seq_lib/chip_vseq_list.sv | 1 + sw/device/tests/sim_dv/BUILD | 9 +- ...locked_test.c => rram_rma_unlocked_test.c} | 223 ++++++++---------- 7 files changed, 123 insertions(+), 127 deletions(-) rename hw/top_earlgrey/dv/env/seq_lib/{chip_sw_flash_rma_unlocked_vseq.sv => chip_sw_rram_rma_unlocked_vseq.sv} (98%) rename sw/device/tests/sim_dv/{flash_rma_unlocked_test.c => rram_rma_unlocked_test.c} (57%) diff --git a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson index 080ac1e91231a..e199039fcacae 100644 --- a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson @@ -160,7 +160,8 @@ - lc_hw_debug_en_o: impacts pinmux, pwrmgr, sram_ctrl (main and ret) & the rv_dm - lc_keymgr_en_o: impacts keymgr dpe - lc_clk_byp_req_o: impacts clkmgr (handshake with lc_clk_byp_ack_i) - - lc_nvm_rma_req_o: impacts otbn (handshake with lc_nvm_rma_ack_i) + - lc_nvm_rma_req_o: impacts otbn/rram_ctrl (handshake with lc_nvm_rma_ack_i) + - lc_nvm_rma_seed_o: impacts rram_ctrl - lc_check_byp_en_o: impacts otp_ctrl - lc_creator_seed_sw_rw_en_o: impacts otp_ctrl & rram_ctrl - lc_seed_hw_rd_en_o: impacts otp_ctrl & rram_ctrl @@ -200,6 +201,7 @@ "chip_sw_otp_ctrl_lc_signals_prod", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_otp_ctrl_lc_signals_rma", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl "chip_sw_rram_ctrl_lc_rw_en", // lc_creator*, lc_seed*, lc_owner*, lc_iso*: rram_ctrl + "chip_sw_rram_rma_unlocked", // lc_nvm_rma_req_o, lc_nvm_rma_seed_o: rram_ctrl ] } { diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 3ddfbc049e44c..75d32815a2ab9 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -778,6 +778,14 @@ sw_images: ["//sw/device/tests/sim_dv:gpio_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } + { + name: chip_sw_rram_rma_unlocked + uvm_test_seq: chip_sw_rram_rma_unlocked_vseq + sw_images: ["//sw/device/tests/sim_dv:rram_rma_unlocked_test:0:test_in_rom:new_rules"] + en_run_modes: ["sw_test_mode_common"] + run_opts: ["+sw_test_timeout_ns=150_000_000"] + run_timeout_mins: 200 + } { name: chip_sw_kmac_entropy uvm_test_seq: chip_sw_base_vseq diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index c4f2081895282..72fc061e61d55 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -87,6 +87,7 @@ filesets: - seq_lib/chip_sw_gpio_smoke_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_gpio_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_rram_ctrl_lc_rw_en_vseq.sv: {is_include_file: true} + - seq_lib/chip_sw_rram_rma_unlocked_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_exit_test_unlocked_bootstrap_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_transition_vseq.sv: {is_include_file: true} - seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv: {is_include_file: true} diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_rma_unlocked_vseq.sv similarity index 98% rename from hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv rename to hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_rma_unlocked_vseq.sv index 90503769a5720..25073f0d26643 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rram_rma_unlocked_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class chip_sw_flash_rma_unlocked_vseq extends chip_sw_base_vseq; - `uvm_object_utils(chip_sw_flash_rma_unlocked_vseq) +class chip_sw_rram_rma_unlocked_vseq extends chip_sw_base_vseq; + `uvm_object_utils(chip_sw_rram_rma_unlocked_vseq) `uvm_object_new diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv index 4af0f502cd831..03dba27198090 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv @@ -42,6 +42,7 @@ `include "chip_sw_lc_walkthrough_vseq.sv" `include "chip_sw_lc_walkthrough_testunlocks_vseq.sv" `include "chip_sw_rram_ctrl_lc_rw_en_vseq.sv" +`include "chip_sw_rram_rma_unlocked_vseq.sv" `include "chip_sw_otp_ctrl_escalation_vseq.sv" `include "chip_sw_spi_host_tx_rx_vseq.sv" `include "chip_sw_spi_passthrough_vseq.sv" diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index 2923f76712f00..506bd5e4af911 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -68,8 +68,8 @@ opentitan_test( ) opentitan_test( - name = "flash_rma_unlocked_test", - srcs = ["flash_rma_unlocked_test.c"], + name = "rram_rma_unlocked_test", + srcs = ["rram_rma_unlocked_test.c"], # This test doesn't use the OTTF. exec_env = {"//hw/top_earlgrey:sim_dv": None}, # This test is designed to run and complete entirely in the ROM boot stage. @@ -78,17 +78,18 @@ opentitan_test( kind = "rom", linker_script = "//sw/device/lib/testing/test_rom:linker_script", deps = [ + "//hw/top:otp_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/arch:device", + "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:lc_ctrl", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:hart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print_uart", - "//sw/device/lib/testing:flash_ctrl_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:status", diff --git a/sw/device/tests/sim_dv/flash_rma_unlocked_test.c b/sw/device/tests/sim_dv/rram_rma_unlocked_test.c similarity index 57% rename from sw/device/tests/sim_dv/flash_rma_unlocked_test.c rename to sw/device/tests/sim_dv/rram_rma_unlocked_test.c index 17c286284590c..5ba0371a7b738 100644 --- a/sw/device/tests/sim_dv/flash_rma_unlocked_test.c +++ b/sw/device/tests/sim_dv/rram_rma_unlocked_test.c @@ -6,51 +6,37 @@ // the test runs 1.6h (110ms in simtime). #include "sw/device/lib/arch/device.h" +#include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_lc_ctrl.h" #include "sw/device/lib/dif/dif_otp_ctrl.h" #include "sw/device/lib/dif/dif_uart.h" #include "sw/device/lib/runtime/hart.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/runtime/print_uart.h" -#include "sw/device/lib/testing/flash_ctrl_testutils.h" +#include "sw/device/lib/testing/nvm_testutils.h" #include "sw/device/lib/testing/pinmux_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/status.h" +#include "hw/top/otp_ctrl_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. -#define LC_TOKEN_SIZE 16 - static dif_pinmux_t pinmux; static dif_uart_t uart0; -static dif_flash_ctrl_state_t flash_state; static dif_lc_ctrl_t lc; // This is updated by the sv component of the test static volatile const uint8_t kTestPhase = 0; static volatile const uint8_t kSrcLcState = 0; -// Closed source short rma support +// Closed source short rma support: under `+en_small_rma=1` the vseq's +// `enable_small_rma()` forces the RMA data-partition wipe's `end_page` down +// to 2. static volatile const uint8_t kShortRma = 0; + enum { - kFlashInfoPageIdCreatorSecret = 1, - kFlashInfoPageIdOwnerSecret = 2, - kFlashInfoPageIdIsoPart = 3, - kFlashInfoBank = 0, - kRegionBaseBank0Page0Index = 0, - kRegionBaseBank0Page255Index = 255, - kRegionBaseBank1Page0Index = 256, - kRegionBaseBank1Page255Index = 511, - kFlashBank0Page0DataRegion = 0, - kFlashBank0Page255DataRegion = 1, - kFlashBank1Page0DataRegion = 2, - kFlashBank1Page255DataRegion = 3, - kPartitionId = 0, - kRegionSize = 1, kDataSize = 16, - kPageSize = 2048, }; enum { @@ -59,7 +45,43 @@ enum { kTestPhaseCheckWipe = 2, }; -static const uint32_t kRandomData[7][kDataSize] = { +// Page indices covering the start, middle, and end of the flat NVM data +// partition. This stands in for flash's old "check both banks" coverage -- +// RRAM's data partition has no bank concept, just one address range -- by +// spreading the same handful of checks across the full range instead. +// +// The literal last page of the whole partition falls inside RRAM's reserved +// per-slot tail (part of it is even read/write protected in hardware -- see +// `kRramCtrlOtpPageCount` in rram_ctrl.h) -- writing there hangs rather than +// erroring. Use the last page of slot B that's still inside its *usable* +// range instead (`NVM_SLOT_B_END_BYTES` is nvm_ctrl.h's own exclusive upper +// bound of that range). For flash (no reserved tail), this is the same as +// the literal last page, so no separate branch is needed. +enum { + kDataPageCount = NVM_DATA_SIZE_BYTES / NVM_BYTES_PER_PAGE, + kDataPageStart = 0, + kDataPageMiddle = kDataPageCount / 2, + kDataPageEnd = (NVM_SLOT_B_END_BYTES / NVM_BYTES_PER_PAGE) - 1, +}; + +// Data region indices used to configure the three data-partition pages +// above; arbitrary but must be distinct. +enum { + kDataRegionStart = 0, + kDataRegionMiddle = 1, + kDataRegionEnd = 2, +}; + +// Under short RMA, only global pages 0-2 of the data partition are guaranteed +// wiped. Move the middle/end checks next to the base so they stay within that +// range instead of deep in slot B. +static uint32_t data_page_middle(void) { + return kShortRma ? 1 : kDataPageMiddle; +} + +static uint32_t data_page_end(void) { return kShortRma ? 2 : kDataPageEnd; } + +static const uint32_t kRandomData[6][kDataSize] = { {0x27af716e, 0xdd493905, 0x4d674f07, 0x1e876023, 0x555477e5, 0x8c079501, 0xfa0aed05, 0x1091a5e4, 0xe94119be, 0xe0bed120, 0xb4611217, 0x1fa02d2a, 0x5252583f, 0xc2a5083b, 0xc43409c3, 0xdb348c5c}, @@ -78,41 +100,35 @@ static const uint32_t kRandomData[7][kDataSize] = { {0xf8ff57b9, 0x444ff4a9, 0xf3574d3c, 0xf6682a84, 0x67455a38, 0x9c138df2, 0x4054e3e5, 0xde4b1a26, 0x047cc121, 0x42cbd0ae, 0x3eec418f, 0x454323c4, 0xf21bee28, 0x28dd24b7, 0x29dd06a6, 0xf83e419f}, - {0x0eb23677, 0x58c97854, 0x284e1a8f, 0x9b460e99, 0x339b0fe6, 0x80778f39, - 0x9dbc2981, 0xb4bdc15f, 0x3abbdeb2, 0xab39dd53, 0x96bb2c4a, 0x9b2d1795, - 0x733bf534, 0xc4914b4b, 0x64487458, 0x9d0fa332}}; +}; -static void write_info_page_scrambled(uint32_t page_index, +static void write_info_page_scrambled(nvm_info_page_t page, const uint32_t *data) { - uint32_t address = 0; - CHECK_STATUS_OK(flash_ctrl_testutils_info_region_scrambled_setup( - &flash_state, page_index, kFlashInfoBank, kPartitionId, &address)); - CHECK_STATUS_OK(flash_ctrl_testutils_erase_and_write_page( - &flash_state, address, kPartitionId, data, kDifFlashCtrlPartitionTypeInfo, - kDataSize)); + CHECK_STATUS_OK( + nvm_testutils_info_page_setup(page, kPageReadWrite, kPageScrambleCfg)); + CHECK_STATUS_OK(nvm_testutils_write_info_page(page, /*byte_offset=*/0, data, + kDataSize, + /*erase_before_write=*/true, + /*readback=*/false)); } -static void write_data_page_scrambled(uint32_t page_index, uint32_t region, +static void write_data_page_scrambled(uint32_t region, uint32_t page_index, const uint32_t *data) { - uint32_t address; - CHECK_STATUS_OK(flash_ctrl_testutils_data_region_scrambled_setup( - &flash_state, page_index, region, kRegionSize, &address)); - CHECK_STATUS_OK(flash_ctrl_testutils_erase_and_write_page( - &flash_state, address, kPartitionId, data, kDifFlashCtrlPartitionTypeData, - kDataSize)); + CHECK_STATUS_OK(nvm_testutils_data_region_setup( + region, page_index, /*size=*/1, kPageReadWrite, kPageScrambleCfg)); + CHECK_STATUS_OK(nvm_testutils_data_write(page_index * NVM_BYTES_PER_PAGE, + data, kDataSize, + /*erase_before_write=*/true)); } static void read_and_check_info_page_scrambled(bool is_equal, - uint32_t page_index, + nvm_info_page_t page, const uint32_t *data) { uint32_t readback_data[kDataSize]; - uint32_t address = 0; - CHECK_STATUS_OK(flash_ctrl_testutils_info_region_scrambled_setup( - &flash_state, page_index, kFlashInfoBank, kPartitionId, &address)); - - CHECK_STATUS_OK(flash_ctrl_testutils_read( - &flash_state, address, kPartitionId, readback_data, - kDifFlashCtrlPartitionTypeInfo, kDataSize, 0)); + CHECK_STATUS_OK( + nvm_testutils_info_page_setup(page, kPageReadWrite, kPageScrambleCfg)); + CHECK_STATUS_OK(nvm_testutils_read_info_page(page, /*byte_offset=*/0, + readback_data, kDataSize)); if (is_equal) { CHECK_ARRAYS_EQ(readback_data, data, kDataSize); } else { @@ -120,18 +136,18 @@ static void read_and_check_info_page_scrambled(bool is_equal, } } -static void read_and_check_data_page_scrambled(bool is_equal, +static void read_and_check_data_page_scrambled(bool is_equal, uint32_t region, uint32_t page_index, - uint32_t region, const uint32_t *data) { uint32_t readback_data[kDataSize]; - uint32_t address; - CHECK_STATUS_OK(flash_ctrl_testutils_data_region_scrambled_setup( - &flash_state, page_index, region, kRegionSize, &address)); - - CHECK_STATUS_OK(flash_ctrl_testutils_read( - &flash_state, address, kPartitionId, readback_data, - kDifFlashCtrlPartitionTypeData, kDataSize, 0)); + CHECK_STATUS_OK(nvm_testutils_data_region_setup( + region, page_index, /*size=*/1, kPageReadWrite, kPageScrambleCfg)); + mmio_region_t data_region = mmio_region_from_addr(NVM_DATA_BASE_ADDR); + for (size_t i = 0; i < kDataSize; ++i) { + readback_data[i] = mmio_region_read32( + data_region, + (ptrdiff_t)(page_index * NVM_BYTES_PER_PAGE + i * sizeof(uint32_t))); + } if (is_equal) { CHECK_ARRAYS_EQ(readback_data, data, kDataSize); } else { @@ -139,7 +155,7 @@ static void read_and_check_data_page_scrambled(bool is_equal, } } -// Function for the first boot, the flash is written to with known data. +// Function for the first boot, the NVM is written to with known data. // All partitions can be written to when the LC_STATE is Dev and // the OTP secret 2 partition has not been provisioned. static void write_data_test_phase(void) { @@ -147,26 +163,13 @@ static void write_data_test_phase(void) { CHECK_DIF_OK(dif_lc_ctrl_get_state(&lc, &curr_state)); CHECK(curr_state == kSrcLcState); - uint32_t write_idx = 0; - write_info_page_scrambled(kFlashInfoPageIdCreatorSecret, kRandomData[0]); - write_info_page_scrambled(kFlashInfoPageIdOwnerSecret, kRandomData[1]); - write_info_page_scrambled(kFlashInfoPageIdIsoPart, kRandomData[2]); - write_data_page_scrambled(kRegionBaseBank0Page0Index, - kFlashBank0Page0DataRegion, kRandomData[3]); - if (kShortRma) - write_idx = (kRegionBaseBank0Page0Index + 1); - else - write_idx = kRegionBaseBank0Page255Index; - write_data_page_scrambled(write_idx, kFlashBank0Page255DataRegion, + write_info_page_scrambled(kNvmInfoPageCreatorSecret, kRandomData[0]); + write_info_page_scrambled(kNvmInfoPageOwnerSecret, kRandomData[1]); + write_info_page_scrambled(kNvmInfoPageWaferAuthSecret, kRandomData[2]); + write_data_page_scrambled(kDataRegionStart, kDataPageStart, kRandomData[3]); + write_data_page_scrambled(kDataRegionMiddle, data_page_middle(), kRandomData[4]); - write_data_page_scrambled(kRegionBaseBank1Page0Index, - kFlashBank1Page0DataRegion, kRandomData[5]); - if (kShortRma) - write_idx = (kRegionBaseBank1Page0Index + 1); - else - write_idx = kRegionBaseBank1Page255Index; - write_data_page_scrambled(write_idx, kFlashBank1Page255DataRegion, - kRandomData[6]); + write_data_page_scrambled(kDataRegionEnd, data_page_end(), kRandomData[5]); LOG_INFO("Write data test complete - waiting for TB"); // Going into WFI which will be detected by the testbench @@ -177,7 +180,7 @@ static void write_data_test_phase(void) { // Function for the second boot, the LC_STATE is still Dev but the OTP secret 2 // partition has now been provisioned by the testbench. Reading back -// from the flash pages that are still accessible as a smoke check. +// from the NVM pages that are still accessible as a smoke check. // Creator Secret is not accessible because of OTP secret 2 provisioning. // Isolation Partition cannot be read in LC_STATE of Dev. // All others are accessible. @@ -187,28 +190,15 @@ static void enter_rma_test_phase(void) { dif_lc_ctrl_state_t curr_state; CHECK_DIF_OK(dif_lc_ctrl_get_state(&lc, &curr_state)); CHECK(curr_state == kSrcLcState); - uint32_t read_idx = 0; - read_and_check_info_page_scrambled(true, kFlashInfoPageIdOwnerSecret, + read_and_check_info_page_scrambled(true, kNvmInfoPageOwnerSecret, kRandomData[1]); - read_and_check_data_page_scrambled(true, kRegionBaseBank0Page0Index, - kFlashBank0Page0DataRegion, + read_and_check_data_page_scrambled(true, kDataRegionStart, kDataPageStart, kRandomData[3]); - if (kShortRma) - read_idx = (kRegionBaseBank0Page0Index + 1); - else - read_idx = kRegionBaseBank0Page255Index; - read_and_check_data_page_scrambled( - true, read_idx, kFlashBank0Page255DataRegion, kRandomData[4]); - read_and_check_data_page_scrambled(true, kRegionBaseBank1Page0Index, - kFlashBank1Page0DataRegion, + read_and_check_data_page_scrambled(true, kDataRegionMiddle, + data_page_middle(), kRandomData[4]); + read_and_check_data_page_scrambled(true, kDataRegionEnd, data_page_end(), kRandomData[5]); - if (kShortRma) - read_idx = (kRegionBaseBank1Page0Index + 1); - else - read_idx = kRegionBaseBank1Page255Index; - read_and_check_data_page_scrambled( - true, read_idx, kFlashBank1Page255DataRegion, kRandomData[6]); LOG_INFO("Enter RMA test complete - waiting for TB"); // Enter WFI for detection in the testbench. @@ -216,39 +206,26 @@ static void enter_rma_test_phase(void) { wait_for_interrupt(); } -// Function for the third boot, all flash partitions are readable as the +// Function for the third boot, all NVM partitions are readable as the // LC_STATE is now RMA. Check that the data read from these partitions does // *not* match the original data and therefore has been successfully wiped. static void check_wipe_test_phase(void) { dif_lc_ctrl_state_t curr_state; CHECK_DIF_OK(dif_lc_ctrl_get_state(&lc, &curr_state)); CHECK(curr_state == kDifLcCtrlStateRma); - uint32_t read_idx = 0; - read_and_check_info_page_scrambled(false, kFlashInfoPageIdCreatorSecret, + read_and_check_info_page_scrambled(false, kNvmInfoPageCreatorSecret, kRandomData[0]); - read_and_check_info_page_scrambled(false, kFlashInfoPageIdOwnerSecret, + read_and_check_info_page_scrambled(false, kNvmInfoPageOwnerSecret, kRandomData[1]); - read_and_check_info_page_scrambled(false, kFlashInfoPageIdIsoPart, + read_and_check_info_page_scrambled(false, kNvmInfoPageWaferAuthSecret, kRandomData[2]); - read_and_check_data_page_scrambled(false, kRegionBaseBank0Page0Index, - kFlashBank0Page0DataRegion, + read_and_check_data_page_scrambled(false, kDataRegionStart, kDataPageStart, kRandomData[3]); - if (kShortRma) - read_idx = (kRegionBaseBank0Page0Index + 1); - else - read_idx = kRegionBaseBank0Page255Index; - read_and_check_data_page_scrambled( - false, read_idx, kFlashBank0Page255DataRegion, kRandomData[4]); - read_and_check_data_page_scrambled(false, kRegionBaseBank1Page0Index, - kFlashBank1Page0DataRegion, + read_and_check_data_page_scrambled(false, kDataRegionMiddle, + data_page_middle(), kRandomData[4]); + read_and_check_data_page_scrambled(false, kDataRegionEnd, data_page_end(), kRandomData[5]); - if (kShortRma) - read_idx = (kRegionBaseBank1Page0Index + 1); - else - read_idx = kRegionBaseBank1Page255Index; - read_and_check_data_page_scrambled( - false, read_idx, kFlashBank1Page255DataRegion, kRandomData[6]); LOG_INFO("Wipe test complete - done"); } @@ -256,6 +233,15 @@ bool rom_test_main(void) { // We need to set the test status as "in test" to indicate to the test code // has been reached, even though this test is also in the "boot ROM". test_status_set(kTestStatusInTest); + + // This test runs as its own boot ROM (`kind = "rom"`) rather than after the + // normal test_rom boot flow. The RRAM controller must be initialized before + // any read/write. + uint32_t otp_nvm_default_cfg = abs_mmio_read32( + TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + + OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET); + CHECK_STATUS_OK(nvm_testutils_rom_init(otp_nvm_default_cfg)); + CHECK_DIF_OK(dif_pinmux_init( mmio_region_from_addr(TOP_EARLGREY_PINMUX_BASE_ADDR), &pinmux)); pinmux_testutils_init(&pinmux); @@ -281,9 +267,6 @@ bool rom_test_main(void) { } // Start of the test specific code. - CHECK_DIF_OK(dif_flash_ctrl_init_state( - &flash_state, - mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); CHECK_DIF_OK(dif_lc_ctrl_init( mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR), &lc)); @@ -298,7 +281,7 @@ bool rom_test_main(void) { }; CHECK_DIF_OK(dif_otp_ctrl_configure(&otp, otp_config)); - LOG_INFO("Test phase %d", kTestPhase); + LOG_INFO("Test phase %d (kShortRma: %d)", kTestPhase, kShortRma); switch (kTestPhase) { case kTestPhaseWriteData: write_data_test_phase();