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[dv, chip_sim, verilator] Add build option to skip ROM verification #30389

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@vogelpi

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Already with today's ROM size of 32 KiB, the initial ROM verification (hashing using KMAC) happening inside ROM_CTRL at every chip boot takes around 3.5ms of simulation time. We are soon going to extend the ROM to 192 KiB which will increase this initial time before actually starting to execute the ROM to roughly 20ms. This will slow down the regressions as well as CI.

We should thus consider skipping this initial ROM verification for the majority of tests. One way that could work would be to add an RTL parameter that is enabled with a build option and then a DPI call to extract the ROM digest from the image and implant it back into the ROM_CTRL register (where the digest obtained from KMAC would land). Only for one or a few couple of tests in CI (DV and Verilator), we would not use this optimization to keep verifying that the full path. FPGA will obviously keep verifying the full path.

What do poeple think about this? Are there maybe better ideas? @andreaskurth , @rswarbrick , @thommythomaso , @martin-velay, @bonnie-banks123 ?

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