From aa9fc882eda96b3228c3693e1b10cf26276bf696 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 13 Aug 2026 09:56:14 +0200 Subject: [PATCH 1/2] Update C5 LP_I2C --- esp32c5/svd/patches/_i2c.yml | 21 +++++++++++++++++++++ esp32c5/svd/patches/esp32c5.yaml | 8 -------- esp32c6/svd/patches/_i2c.yml | 19 ++++++++++++++++++- esp32c6/svd/patches/esp32c6.yaml | 21 --------------------- 4 files changed, 39 insertions(+), 30 deletions(-) diff --git a/esp32c5/svd/patches/_i2c.yml b/esp32c5/svd/patches/_i2c.yml index 3e9efad750..340cc74e84 100644 --- a/esp32c5/svd/patches/_i2c.yml +++ b/esp32c5/svd/patches/_i2c.yml @@ -45,3 +45,24 @@ I2C0: _modify: SCL_MAIN_ST_TO_I2C: name: SCL_MAIN_ST_TO + +LP_I2C0: + _strip: "I2C_" + "*": + _strip: "I2C_" + _modify: + INT_STATUS: + name: INT_ST + DATA: + _modify: + FIFO_RDATA: + access: read-write + COMD?: + _modify: + COMMAND?: + name: COMMAND + COMMAND?_DONE: + name: COMMAND_DONE + _array: + COMD?: {} + _include: ../../../common_patches/int_strip.yaml diff --git a/esp32c5/svd/patches/esp32c5.yaml b/esp32c5/svd/patches/esp32c5.yaml index 133a52ae9f..7ac648b421 100644 --- a/esp32c5/svd/patches/esp32c5.yaml +++ b/esp32c5/svd/patches/esp32c5.yaml @@ -607,14 +607,6 @@ LP_APM0: LP_TIMER: _include: ../../../common_patches/lptim_int_strip.yaml -LP_I2C0: - _modify: - I2C_FIFO_CONF: - name: FIFO_CONF - - FIFO_CONF: - _strip: "I2C_" - PARL_IO: _include: ../../../common_patches/int_strip.yaml diff --git a/esp32c6/svd/patches/_i2c.yml b/esp32c6/svd/patches/_i2c.yml index 9c24e7b0d6..0326534fd0 100644 --- a/esp32c6/svd/patches/_i2c.yml +++ b/esp32c6/svd/patches/_i2c.yml @@ -6,5 +6,22 @@ I2C0: access: read-write LP_I2C0: - FIFO_CONF: + _strip: "I2C_" + "*": _strip: "I2C_" + _modify: + INT_STATUS: + name: INT_ST + DATA: + _modify: + FIFO_RDATA: + access: read-write + COMD?: + _modify: + COMMAND?: + name: COMMAND + COMMAND?_DONE: + name: COMMAND_DONE + _array: + COMD?: {} + _include: ../../../common_patches/int_strip.yaml diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml index e1007dd591..4d3da55146 100644 --- a/esp32c6/svd/patches/esp32c6.yaml +++ b/esp32c6/svd/patches/esp32c6.yaml @@ -83,27 +83,6 @@ LP_AON: STORE[1-9]: _from: STORE0 -LP_I2C0: - _strip: "I2C_" - "*": - _strip: "I2C_" - _modify: - INT_STATUS: - name: INT_ST - DATA: - _modify: - FIFO_RDATA: - access: read-write - COMD?: - _modify: - COMMAND?: - name: COMMAND - COMMAND?_DONE: - name: COMMAND_DONE - _array: - COMD?: {} - _include: ../../../common_patches/int_strip.yaml - LP_IO: _array: GPIO?: {} From bc053715434188a4d5aec7e13891dda37c4f2149 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 13 Aug 2026 09:58:45 +0200 Subject: [PATCH 2/2] Regenerate PAC --- esp32c5/src/lp_i2c0.rs | 391 ++++++++---------- esp32c5/src/lp_i2c0/clk_conf.rs | 105 +++++ esp32c5/src/lp_i2c0/comd.rs | 58 +++ esp32c5/src/lp_i2c0/ctr.rs | 171 ++++++++ esp32c5/src/lp_i2c0/data.rs | 43 ++ esp32c5/src/lp_i2c0/fifo_st.rs | 52 +++ esp32c5/src/lp_i2c0/filter_cfg.rs | 90 ++++ esp32c5/src/lp_i2c0/i2c_clk_conf.rs | 105 ----- esp32c5/src/lp_i2c0/i2c_comd0.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd1.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd2.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd3.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd4.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd5.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd6.rs | 58 --- esp32c5/src/lp_i2c0/i2c_comd7.rs | 58 --- esp32c5/src/lp_i2c0/i2c_ctr.rs | 171 -------- esp32c5/src/lp_i2c0/i2c_data.rs | 28 -- esp32c5/src/lp_i2c0/i2c_fifo_st.rs | 52 --- esp32c5/src/lp_i2c0/i2c_filter_cfg.rs | 90 ---- esp32c5/src/lp_i2c0/i2c_int_clr.rs | 143 ------- esp32c5/src/lp_i2c0/i2c_int_ena.rs | 293 ------------- esp32c5/src/lp_i2c0/i2c_int_raw.rs | 165 -------- esp32c5/src/lp_i2c0/i2c_int_status.rs | 163 -------- esp32c5/src/lp_i2c0/i2c_rxfifo_start_addr.rs | 28 -- esp32c5/src/lp_i2c0/i2c_scl_high_period.rs | 60 --- esp32c5/src/lp_i2c0/i2c_scl_low_period.rs | 43 -- .../src/lp_i2c0/i2c_scl_main_st_time_out.rs | 47 --- esp32c5/src/lp_i2c0/i2c_scl_sp_conf.rs | 88 ---- esp32c5/src/lp_i2c0/i2c_scl_st_time_out.rs | 45 -- esp32c5/src/lp_i2c0/i2c_sr.rs | 76 ---- esp32c5/src/lp_i2c0/i2c_to.rs | 60 --- esp32c5/src/lp_i2c0/i2c_txfifo_start_addr.rs | 28 -- esp32c5/src/lp_i2c0/int_clr.rs | 134 ++++++ esp32c5/src/lp_i2c0/int_ena.rs | 268 ++++++++++++ esp32c5/src/lp_i2c0/int_raw.rs | 150 +++++++ esp32c5/src/lp_i2c0/int_st.rs | 148 +++++++ esp32c5/src/lp_i2c0/rxfifo_start_addr.rs | 28 ++ esp32c5/src/lp_i2c0/scl_high_period.rs | 58 +++ esp32c5/src/lp_i2c0/scl_low_period.rs | 43 ++ esp32c5/src/lp_i2c0/scl_main_st_time_out.rs | 45 ++ ...cl_rstart_setup.rs => scl_rstart_setup.rs} | 30 +- esp32c5/src/lp_i2c0/scl_sp_conf.rs | 88 ++++ esp32c5/src/lp_i2c0/scl_st_time_out.rs | 45 ++ ...2c_scl_start_hold.rs => scl_start_hold.rs} | 30 +- ...{i2c_scl_stop_hold.rs => scl_stop_hold.rs} | 30 +- ...2c_scl_stop_setup.rs => scl_stop_setup.rs} | 30 +- .../lp_i2c0/{i2c_sda_hold.rs => sda_hold.rs} | 30 +- .../{i2c_sda_sample.rs => sda_sample.rs} | 30 +- esp32c5/src/lp_i2c0/sr.rs | 76 ++++ esp32c5/src/lp_i2c0/to.rs | 60 +++ esp32c5/src/lp_i2c0/txfifo_start_addr.rs | 28 ++ 52 files changed, 1943 insertions(+), 2467 deletions(-) create mode 100644 esp32c5/src/lp_i2c0/clk_conf.rs create mode 100644 esp32c5/src/lp_i2c0/comd.rs create mode 100644 esp32c5/src/lp_i2c0/ctr.rs create mode 100644 esp32c5/src/lp_i2c0/data.rs create mode 100644 esp32c5/src/lp_i2c0/fifo_st.rs create mode 100644 esp32c5/src/lp_i2c0/filter_cfg.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_clk_conf.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd0.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd1.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd2.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd3.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd4.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd5.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd6.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_comd7.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_ctr.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_data.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_fifo_st.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_filter_cfg.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_int_clr.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_int_ena.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_int_raw.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_int_status.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_rxfifo_start_addr.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_scl_high_period.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_scl_low_period.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_scl_main_st_time_out.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_scl_sp_conf.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_scl_st_time_out.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_sr.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_to.rs delete mode 100644 esp32c5/src/lp_i2c0/i2c_txfifo_start_addr.rs create mode 100644 esp32c5/src/lp_i2c0/int_clr.rs create mode 100644 esp32c5/src/lp_i2c0/int_ena.rs create mode 100644 esp32c5/src/lp_i2c0/int_raw.rs create mode 100644 esp32c5/src/lp_i2c0/int_st.rs create mode 100644 esp32c5/src/lp_i2c0/rxfifo_start_addr.rs create mode 100644 esp32c5/src/lp_i2c0/scl_high_period.rs create mode 100644 esp32c5/src/lp_i2c0/scl_low_period.rs create mode 100644 esp32c5/src/lp_i2c0/scl_main_st_time_out.rs rename esp32c5/src/lp_i2c0/{i2c_scl_rstart_setup.rs => scl_rstart_setup.rs} (56%) create mode 100644 esp32c5/src/lp_i2c0/scl_sp_conf.rs create mode 100644 esp32c5/src/lp_i2c0/scl_st_time_out.rs rename esp32c5/src/lp_i2c0/{i2c_scl_start_hold.rs => scl_start_hold.rs} (56%) rename esp32c5/src/lp_i2c0/{i2c_scl_stop_hold.rs => scl_stop_hold.rs} (53%) rename esp32c5/src/lp_i2c0/{i2c_scl_stop_setup.rs => scl_stop_setup.rs} (55%) rename esp32c5/src/lp_i2c0/{i2c_sda_hold.rs => sda_hold.rs} (53%) rename esp32c5/src/lp_i2c0/{i2c_sda_sample.rs => sda_sample.rs} (50%) create mode 100644 esp32c5/src/lp_i2c0/sr.rs create mode 100644 esp32c5/src/lp_i2c0/to.rs create mode 100644 esp32c5/src/lp_i2c0/txfifo_start_addr.rs diff --git a/esp32c5/src/lp_i2c0.rs b/esp32c5/src/lp_i2c0.rs index e269541fb6..b773feaa6a 100644 --- a/esp32c5/src/lp_i2c0.rs +++ b/esp32c5/src/lp_i2c0.rs @@ -2,71 +2,64 @@ #[cfg_attr(feature = "impl-register-debug", derive(Debug))] #[doc = "Register block"] pub struct RegisterBlock { - i2c_scl_low_period: I2C_SCL_LOW_PERIOD, - i2c_ctr: I2C_CTR, - i2c_sr: I2C_SR, - i2c_to: I2C_TO, + scl_low_period: SCL_LOW_PERIOD, + ctr: CTR, + sr: SR, + to: TO, _reserved4: [u8; 0x04], - i2c_fifo_st: I2C_FIFO_ST, + fifo_st: FIFO_ST, fifo_conf: FIFO_CONF, - i2c_data: I2C_DATA, - i2c_int_raw: I2C_INT_RAW, - i2c_int_clr: I2C_INT_CLR, - i2c_int_ena: I2C_INT_ENA, - i2c_int_status: I2C_INT_STATUS, - i2c_sda_hold: I2C_SDA_HOLD, - i2c_sda_sample: I2C_SDA_SAMPLE, - i2c_scl_high_period: I2C_SCL_HIGH_PERIOD, + data: DATA, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_ena: INT_ENA, + int_st: INT_ST, + sda_hold: SDA_HOLD, + sda_sample: SDA_SAMPLE, + scl_high_period: SCL_HIGH_PERIOD, _reserved14: [u8; 0x04], - i2c_scl_start_hold: I2C_SCL_START_HOLD, - i2c_scl_rstart_setup: I2C_SCL_RSTART_SETUP, - i2c_scl_stop_hold: I2C_SCL_STOP_HOLD, - i2c_scl_stop_setup: I2C_SCL_STOP_SETUP, - i2c_filter_cfg: I2C_FILTER_CFG, - i2c_clk_conf: I2C_CLK_CONF, - i2c_comd0: I2C_COMD0, - i2c_comd1: I2C_COMD1, - i2c_comd2: I2C_COMD2, - i2c_comd3: I2C_COMD3, - i2c_comd4: I2C_COMD4, - i2c_comd5: I2C_COMD5, - i2c_comd6: I2C_COMD6, - i2c_comd7: I2C_COMD7, - i2c_scl_st_time_out: I2C_SCL_ST_TIME_OUT, - i2c_scl_main_st_time_out: I2C_SCL_MAIN_ST_TIME_OUT, - i2c_scl_sp_conf: I2C_SCL_SP_CONF, - _reserved31: [u8; 0x74], - i2c_date: I2C_DATE, - _reserved32: [u8; 0x04], - i2c_txfifo_start_addr: I2C_TXFIFO_START_ADDR, - _reserved33: [u8; 0x7c], - i2c_rxfifo_start_addr: I2C_RXFIFO_START_ADDR, + scl_start_hold: SCL_START_HOLD, + scl_rstart_setup: SCL_RSTART_SETUP, + scl_stop_hold: SCL_STOP_HOLD, + scl_stop_setup: SCL_STOP_SETUP, + filter_cfg: FILTER_CFG, + clk_conf: CLK_CONF, + comd: [COMD; 8], + scl_st_time_out: SCL_ST_TIME_OUT, + scl_main_st_time_out: SCL_MAIN_ST_TIME_OUT, + scl_sp_conf: SCL_SP_CONF, + _reserved24: [u8; 0x74], + date: DATE, + _reserved25: [u8; 0x04], + txfifo_start_addr: TXFIFO_START_ADDR, + _reserved26: [u8; 0x7c], + rxfifo_start_addr: RXFIFO_START_ADDR, } impl RegisterBlock { #[doc = "0x00 - Configures the low level width of the SCL Clock"] #[inline(always)] - pub const fn i2c_scl_low_period(&self) -> &I2C_SCL_LOW_PERIOD { - &self.i2c_scl_low_period + pub const fn scl_low_period(&self) -> &SCL_LOW_PERIOD { + &self.scl_low_period } #[doc = "0x04 - Transmission setting"] #[inline(always)] - pub const fn i2c_ctr(&self) -> &I2C_CTR { - &self.i2c_ctr + pub const fn ctr(&self) -> &CTR { + &self.ctr } #[doc = "0x08 - Describe I2C work status."] #[inline(always)] - pub const fn i2c_sr(&self) -> &I2C_SR { - &self.i2c_sr + pub const fn sr(&self) -> &SR { + &self.sr } #[doc = "0x0c - Setting time out control for receiving data."] #[inline(always)] - pub const fn i2c_to(&self) -> &I2C_TO { - &self.i2c_to + pub const fn to(&self) -> &TO { + &self.to } #[doc = "0x14 - FIFO status register."] #[inline(always)] - pub const fn i2c_fifo_st(&self) -> &I2C_FIFO_ST { - &self.i2c_fifo_st + pub const fn fifo_st(&self) -> &FIFO_ST { + &self.fifo_st } #[doc = "0x18 - FIFO configuration register."] #[inline(always)] @@ -75,276 +68,218 @@ impl RegisterBlock { } #[doc = "0x1c - Rx FIFO read data."] #[inline(always)] - pub const fn i2c_data(&self) -> &I2C_DATA { - &self.i2c_data + pub const fn data(&self) -> &DATA { + &self.data } #[doc = "0x20 - Raw interrupt status"] #[inline(always)] - pub const fn i2c_int_raw(&self) -> &I2C_INT_RAW { - &self.i2c_int_raw + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw } #[doc = "0x24 - Interrupt clear bits"] #[inline(always)] - pub const fn i2c_int_clr(&self) -> &I2C_INT_CLR { - &self.i2c_int_clr + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr } #[doc = "0x28 - Interrupt enable bits"] #[inline(always)] - pub const fn i2c_int_ena(&self) -> &I2C_INT_ENA { - &self.i2c_int_ena + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena } #[doc = "0x2c - Status of captured I2C communication events"] #[inline(always)] - pub const fn i2c_int_status(&self) -> &I2C_INT_STATUS { - &self.i2c_int_status + pub const fn int_st(&self) -> &INT_ST { + &self.int_st } #[doc = "0x30 - Configures the hold time after a negative SCL edge."] #[inline(always)] - pub const fn i2c_sda_hold(&self) -> &I2C_SDA_HOLD { - &self.i2c_sda_hold + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold } #[doc = "0x34 - Configures the sample time after a positive SCL edge."] #[inline(always)] - pub const fn i2c_sda_sample(&self) -> &I2C_SDA_SAMPLE { - &self.i2c_sda_sample + pub const fn sda_sample(&self) -> &SDA_SAMPLE { + &self.sda_sample } #[doc = "0x38 - Configures the high level width of SCL"] #[inline(always)] - pub const fn i2c_scl_high_period(&self) -> &I2C_SCL_HIGH_PERIOD { - &self.i2c_scl_high_period + pub const fn scl_high_period(&self) -> &SCL_HIGH_PERIOD { + &self.scl_high_period } #[doc = "0x40 - Configures the delay between the SDA and SCL negative edge for a start condition"] #[inline(always)] - pub const fn i2c_scl_start_hold(&self) -> &I2C_SCL_START_HOLD { - &self.i2c_scl_start_hold + pub const fn scl_start_hold(&self) -> &SCL_START_HOLD { + &self.scl_start_hold } #[doc = "0x44 - Configures the delay between the positive edge of SCL and the negative edge of SDA"] #[inline(always)] - pub const fn i2c_scl_rstart_setup(&self) -> &I2C_SCL_RSTART_SETUP { - &self.i2c_scl_rstart_setup + pub const fn scl_rstart_setup(&self) -> &SCL_RSTART_SETUP { + &self.scl_rstart_setup } #[doc = "0x48 - Configures the delay after the SCL clock edge for a stop condition"] #[inline(always)] - pub const fn i2c_scl_stop_hold(&self) -> &I2C_SCL_STOP_HOLD { - &self.i2c_scl_stop_hold + pub const fn scl_stop_hold(&self) -> &SCL_STOP_HOLD { + &self.scl_stop_hold } #[doc = "0x4c - Configures the delay between the SDA and SCL positive edge for a stop condition"] #[inline(always)] - pub const fn i2c_scl_stop_setup(&self) -> &I2C_SCL_STOP_SETUP { - &self.i2c_scl_stop_setup + pub const fn scl_stop_setup(&self) -> &SCL_STOP_SETUP { + &self.scl_stop_setup } #[doc = "0x50 - SCL and SDA filter configuration register"] #[inline(always)] - pub const fn i2c_filter_cfg(&self) -> &I2C_FILTER_CFG { - &self.i2c_filter_cfg + pub const fn filter_cfg(&self) -> &FILTER_CFG { + &self.filter_cfg } #[doc = "0x54 - I2C CLK configuration register"] #[inline(always)] - pub const fn i2c_clk_conf(&self) -> &I2C_CLK_CONF { - &self.i2c_clk_conf + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf } - #[doc = "0x58 - I2C command register 0"] + #[doc = "0x58..0x78 - I2C command register %s"] #[inline(always)] - pub const fn i2c_comd0(&self) -> &I2C_COMD0 { - &self.i2c_comd0 + pub const fn comd(&self, n: usize) -> &COMD { + &self.comd[n] } - #[doc = "0x5c - I2C command register 1"] + #[doc = "Iterator for array of:"] + #[doc = "0x58..0x78 - I2C command register %s"] #[inline(always)] - pub const fn i2c_comd1(&self) -> &I2C_COMD1 { - &self.i2c_comd1 - } - #[doc = "0x60 - I2C command register 2"] - #[inline(always)] - pub const fn i2c_comd2(&self) -> &I2C_COMD2 { - &self.i2c_comd2 - } - #[doc = "0x64 - I2C command register 3"] - #[inline(always)] - pub const fn i2c_comd3(&self) -> &I2C_COMD3 { - &self.i2c_comd3 - } - #[doc = "0x68 - I2C command register 4"] - #[inline(always)] - pub const fn i2c_comd4(&self) -> &I2C_COMD4 { - &self.i2c_comd4 - } - #[doc = "0x6c - I2C command register 5"] - #[inline(always)] - pub const fn i2c_comd5(&self) -> &I2C_COMD5 { - &self.i2c_comd5 - } - #[doc = "0x70 - I2C command register 6"] - #[inline(always)] - pub const fn i2c_comd6(&self) -> &I2C_COMD6 { - &self.i2c_comd6 - } - #[doc = "0x74 - I2C command register 7"] - #[inline(always)] - pub const fn i2c_comd7(&self) -> &I2C_COMD7 { - &self.i2c_comd7 + pub fn comd_iter(&self) -> impl Iterator { + self.comd.iter() } #[doc = "0x78 - SCL status time out register"] #[inline(always)] - pub const fn i2c_scl_st_time_out(&self) -> &I2C_SCL_ST_TIME_OUT { - &self.i2c_scl_st_time_out + pub const fn scl_st_time_out(&self) -> &SCL_ST_TIME_OUT { + &self.scl_st_time_out } #[doc = "0x7c - SCL main status time out register"] #[inline(always)] - pub const fn i2c_scl_main_st_time_out(&self) -> &I2C_SCL_MAIN_ST_TIME_OUT { - &self.i2c_scl_main_st_time_out + pub const fn scl_main_st_time_out(&self) -> &SCL_MAIN_ST_TIME_OUT { + &self.scl_main_st_time_out } #[doc = "0x80 - Power configuration register"] #[inline(always)] - pub const fn i2c_scl_sp_conf(&self) -> &I2C_SCL_SP_CONF { - &self.i2c_scl_sp_conf + pub const fn scl_sp_conf(&self) -> &SCL_SP_CONF { + &self.scl_sp_conf } #[doc = "0xf8 - Version register"] #[inline(always)] - pub const fn i2c_date(&self) -> &I2C_DATE { - &self.i2c_date + pub const fn date(&self) -> &DATE { + &self.date } #[doc = "0x100 - I2C TXFIFO base address register"] #[inline(always)] - pub const fn i2c_txfifo_start_addr(&self) -> &I2C_TXFIFO_START_ADDR { - &self.i2c_txfifo_start_addr + pub const fn txfifo_start_addr(&self) -> &TXFIFO_START_ADDR { + &self.txfifo_start_addr } #[doc = "0x180 - I2C RXFIFO base address register"] #[inline(always)] - pub const fn i2c_rxfifo_start_addr(&self) -> &I2C_RXFIFO_START_ADDR { - &self.i2c_rxfifo_start_addr + pub const fn rxfifo_start_addr(&self) -> &RXFIFO_START_ADDR { + &self.rxfifo_start_addr } } -#[doc = "I2C_SCL_LOW_PERIOD (rw) register accessor: Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_low_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_low_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_low_period`] module"] -pub type I2C_SCL_LOW_PERIOD = crate::Reg; +#[doc = "SCL_LOW_PERIOD (rw) register accessor: Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_low_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_low_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_low_period`] module"] +pub type SCL_LOW_PERIOD = crate::Reg; #[doc = "Configures the low level width of the SCL Clock"] -pub mod i2c_scl_low_period; -#[doc = "I2C_CTR (rw) register accessor: Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_ctr`] module"] -pub type I2C_CTR = crate::Reg; +pub mod scl_low_period; +#[doc = "CTR (rw) register accessor: Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] +pub type CTR = crate::Reg; #[doc = "Transmission setting"] -pub mod i2c_ctr; -#[doc = "I2C_SR (r) register accessor: Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_sr`] module"] -pub type I2C_SR = crate::Reg; +pub mod ctr; +#[doc = "SR (r) register accessor: Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +pub type SR = crate::Reg; #[doc = "Describe I2C work status."] -pub mod i2c_sr; -#[doc = "I2C_TO (rw) register accessor: Setting time out control for receiving data.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_to::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_to::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_to`] module"] -pub type I2C_TO = crate::Reg; +pub mod sr; +#[doc = "TO (rw) register accessor: Setting time out control for receiving data.\n\nYou can [`read`](crate::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`] module"] +pub type TO = crate::Reg; #[doc = "Setting time out control for receiving data."] -pub mod i2c_to; -#[doc = "I2C_FIFO_ST (r) register accessor: FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifo_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_fifo_st`] module"] -pub type I2C_FIFO_ST = crate::Reg; +pub mod to; +#[doc = "FIFO_ST (r) register accessor: FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_st`] module"] +pub type FIFO_ST = crate::Reg; #[doc = "FIFO status register."] -pub mod i2c_fifo_st; +pub mod fifo_st; #[doc = "FIFO_CONF (rw) register accessor: FIFO configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_conf`] module"] pub type FIFO_CONF = crate::Reg; #[doc = "FIFO configuration register."] pub mod fifo_conf; -#[doc = "I2C_DATA (r) register accessor: Rx FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_data`] module"] -pub type I2C_DATA = crate::Reg; +#[doc = "DATA (rw) register accessor: Rx FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +pub type DATA = crate::Reg; #[doc = "Rx FIFO read data."] -pub mod i2c_data; -#[doc = "I2C_INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_int_raw`] module"] -pub type I2C_INT_RAW = crate::Reg; +pub mod data; +#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; #[doc = "Raw interrupt status"] -pub mod i2c_int_raw; -#[doc = "I2C_INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_int_clr`] module"] -pub type I2C_INT_CLR = crate::Reg; +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; #[doc = "Interrupt clear bits"] -pub mod i2c_int_clr; -#[doc = "I2C_INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_int_ena`] module"] -pub type I2C_INT_ENA = crate::Reg; +pub mod int_clr; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; #[doc = "Interrupt enable bits"] -pub mod i2c_int_ena; -#[doc = "I2C_INT_STATUS (r) register accessor: Status of captured I2C communication events\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_int_status`] module"] -pub type I2C_INT_STATUS = crate::Reg; +pub mod int_ena; +#[doc = "INT_ST (r) register accessor: Status of captured I2C communication events\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; #[doc = "Status of captured I2C communication events"] -pub mod i2c_int_status; -#[doc = "I2C_SDA_HOLD (rw) register accessor: Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_sda_hold`] module"] -pub type I2C_SDA_HOLD = crate::Reg; +pub mod int_st; +#[doc = "SDA_HOLD (rw) register accessor: Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] +pub type SDA_HOLD = crate::Reg; #[doc = "Configures the hold time after a negative SCL edge."] -pub mod i2c_sda_hold; -#[doc = "I2C_SDA_SAMPLE (rw) register accessor: Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sda_sample::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sda_sample::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_sda_sample`] module"] -pub type I2C_SDA_SAMPLE = crate::Reg; +pub mod sda_hold; +#[doc = "SDA_SAMPLE (rw) register accessor: Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_sample::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_sample::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_sample`] module"] +pub type SDA_SAMPLE = crate::Reg; #[doc = "Configures the sample time after a positive SCL edge."] -pub mod i2c_sda_sample; -#[doc = "I2C_SCL_HIGH_PERIOD (rw) register accessor: Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_high_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_high_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_high_period`] module"] -pub type I2C_SCL_HIGH_PERIOD = crate::Reg; +pub mod sda_sample; +#[doc = "SCL_HIGH_PERIOD (rw) register accessor: Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_high_period`] module"] +pub type SCL_HIGH_PERIOD = crate::Reg; #[doc = "Configures the high level width of SCL"] -pub mod i2c_scl_high_period; -#[doc = "I2C_SCL_START_HOLD (rw) register accessor: Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_start_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_start_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_start_hold`] module"] -pub type I2C_SCL_START_HOLD = crate::Reg; +pub mod scl_high_period; +#[doc = "SCL_START_HOLD (rw) register accessor: Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_start_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_start_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_start_hold`] module"] +pub type SCL_START_HOLD = crate::Reg; #[doc = "Configures the delay between the SDA and SCL negative edge for a start condition"] -pub mod i2c_scl_start_hold; -#[doc = "I2C_SCL_RSTART_SETUP (rw) register accessor: Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_rstart_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_rstart_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_rstart_setup`] module"] -pub type I2C_SCL_RSTART_SETUP = crate::Reg; +pub mod scl_start_hold; +#[doc = "SCL_RSTART_SETUP (rw) register accessor: Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_rstart_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_rstart_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_rstart_setup`] module"] +pub type SCL_RSTART_SETUP = crate::Reg; #[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA"] -pub mod i2c_scl_rstart_setup; -#[doc = "I2C_SCL_STOP_HOLD (rw) register accessor: Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_stop_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_stop_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_stop_hold`] module"] -pub type I2C_SCL_STOP_HOLD = crate::Reg; +pub mod scl_rstart_setup; +#[doc = "SCL_STOP_HOLD (rw) register accessor: Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_hold`] module"] +pub type SCL_STOP_HOLD = crate::Reg; #[doc = "Configures the delay after the SCL clock edge for a stop condition"] -pub mod i2c_scl_stop_hold; -#[doc = "I2C_SCL_STOP_SETUP (rw) register accessor: Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_stop_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_stop_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_stop_setup`] module"] -pub type I2C_SCL_STOP_SETUP = crate::Reg; +pub mod scl_stop_hold; +#[doc = "SCL_STOP_SETUP (rw) register accessor: Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_setup`] module"] +pub type SCL_STOP_SETUP = crate::Reg; #[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition"] -pub mod i2c_scl_stop_setup; -#[doc = "I2C_FILTER_CFG (rw) register accessor: SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_filter_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_filter_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_filter_cfg`] module"] -pub type I2C_FILTER_CFG = crate::Reg; +pub mod scl_stop_setup; +#[doc = "FILTER_CFG (rw) register accessor: SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_cfg`] module"] +pub type FILTER_CFG = crate::Reg; #[doc = "SCL and SDA filter configuration register"] -pub mod i2c_filter_cfg; -#[doc = "I2C_CLK_CONF (rw) register accessor: I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_clk_conf`] module"] -pub type I2C_CLK_CONF = crate::Reg; +pub mod filter_cfg; +#[doc = "CLK_CONF (rw) register accessor: I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; #[doc = "I2C CLK configuration register"] -pub mod i2c_clk_conf; -#[doc = "I2C_COMD0 (rw) register accessor: I2C command register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd0`] module"] -pub type I2C_COMD0 = crate::Reg; -#[doc = "I2C command register 0"] -pub mod i2c_comd0; -#[doc = "I2C_COMD1 (rw) register accessor: I2C command register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd1`] module"] -pub type I2C_COMD1 = crate::Reg; -#[doc = "I2C command register 1"] -pub mod i2c_comd1; -#[doc = "I2C_COMD2 (rw) register accessor: I2C command register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd2`] module"] -pub type I2C_COMD2 = crate::Reg; -#[doc = "I2C command register 2"] -pub mod i2c_comd2; -#[doc = "I2C_COMD3 (rw) register accessor: I2C command register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd3`] module"] -pub type I2C_COMD3 = crate::Reg; -#[doc = "I2C command register 3"] -pub mod i2c_comd3; -#[doc = "I2C_COMD4 (rw) register accessor: I2C command register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd4`] module"] -pub type I2C_COMD4 = crate::Reg; -#[doc = "I2C command register 4"] -pub mod i2c_comd4; -#[doc = "I2C_COMD5 (rw) register accessor: I2C command register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd5`] module"] -pub type I2C_COMD5 = crate::Reg; -#[doc = "I2C command register 5"] -pub mod i2c_comd5; -#[doc = "I2C_COMD6 (rw) register accessor: I2C command register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd6`] module"] -pub type I2C_COMD6 = crate::Reg; -#[doc = "I2C command register 6"] -pub mod i2c_comd6; -#[doc = "I2C_COMD7 (rw) register accessor: I2C command register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_comd7`] module"] -pub type I2C_COMD7 = crate::Reg; -#[doc = "I2C command register 7"] -pub mod i2c_comd7; -#[doc = "I2C_SCL_ST_TIME_OUT (rw) register accessor: SCL status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_st_time_out`] module"] -pub type I2C_SCL_ST_TIME_OUT = crate::Reg; +pub mod clk_conf; +#[doc = "COMD (rw) register accessor: I2C command register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`comd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd`] module"] +pub type COMD = crate::Reg; +#[doc = "I2C command register %s"] +pub mod comd; +#[doc = "SCL_ST_TIME_OUT (rw) register accessor: SCL status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_st_time_out`] module"] +pub type SCL_ST_TIME_OUT = crate::Reg; #[doc = "SCL status time out register"] -pub mod i2c_scl_st_time_out; -#[doc = "I2C_SCL_MAIN_ST_TIME_OUT (rw) register accessor: SCL main status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_main_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_main_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_main_st_time_out`] module"] -pub type I2C_SCL_MAIN_ST_TIME_OUT = - crate::Reg; +pub mod scl_st_time_out; +#[doc = "SCL_MAIN_ST_TIME_OUT (rw) register accessor: SCL main status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_main_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_main_st_time_out`] module"] +pub type SCL_MAIN_ST_TIME_OUT = crate::Reg; #[doc = "SCL main status time out register"] -pub mod i2c_scl_main_st_time_out; -#[doc = "I2C_SCL_SP_CONF (rw) register accessor: Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_sp_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_sp_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_sp_conf`] module"] -pub type I2C_SCL_SP_CONF = crate::Reg; +pub mod scl_main_st_time_out; +#[doc = "SCL_SP_CONF (rw) register accessor: Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_sp_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_sp_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_sp_conf`] module"] +pub type SCL_SP_CONF = crate::Reg; #[doc = "Power configuration register"] -pub mod i2c_scl_sp_conf; -pub use crate::aes::{date as i2c_date, DATE as I2C_DATE}; -#[doc = "I2C_TXFIFO_START_ADDR (r) register accessor: I2C TXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txfifo_start_addr`] module"] -pub type I2C_TXFIFO_START_ADDR = crate::Reg; +pub mod scl_sp_conf; +pub use crate::aes::{date, DATE}; +#[doc = "TXFIFO_START_ADDR (r) register accessor: I2C TXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifo_start_addr`] module"] +pub type TXFIFO_START_ADDR = crate::Reg; #[doc = "I2C TXFIFO base address register"] -pub mod i2c_txfifo_start_addr; -#[doc = "I2C_RXFIFO_START_ADDR (r) register accessor: I2C RXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxfifo_start_addr`] module"] -pub type I2C_RXFIFO_START_ADDR = crate::Reg; +pub mod txfifo_start_addr; +#[doc = "RXFIFO_START_ADDR (r) register accessor: I2C RXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifo_start_addr`] module"] +pub type RXFIFO_START_ADDR = crate::Reg; #[doc = "I2C RXFIFO base address register"] -pub mod i2c_rxfifo_start_addr; +pub mod rxfifo_start_addr; diff --git a/esp32c5/src/lp_i2c0/clk_conf.rs b/esp32c5/src/lp_i2c0/clk_conf.rs new file mode 100644 index 0000000000..0cb7744388 --- /dev/null +++ b/esp32c5/src/lp_i2c0/clk_conf.rs @@ -0,0 +1,105 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_R = crate::BitReader; +#[doc = "Field `SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCLK_ACTIVE` reader - The clock switch for i2c module"] +pub type SCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SCLK_ACTIVE` writer - The clock switch for i2c module"] +pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + pub fn sclk_active(&self) -> SCLK_ACTIVE_R { + SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("sclk_div_num", &self.sclk_div_num()) + .field("sclk_div_a", &self.sclk_div_a()) + .field("sclk_div_b", &self.sclk_div_b()) + .field("sclk_sel", &self.sclk_sel()) + .field("sclk_active", &self.sclk_active()) + .finish() + } +} +impl W { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<'_, CLK_CONF_SPEC> { + SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<'_, CLK_CONF_SPEC> { + SCLK_DIV_A_W::new(self, 8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<'_, CLK_CONF_SPEC> { + SCLK_DIV_B_W::new(self, 14) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W<'_, CLK_CONF_SPEC> { + SCLK_SEL_W::new(self, 20) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<'_, CLK_CONF_SPEC> { + SCLK_ACTIVE_W::new(self, 21) + } +} +#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0020_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: u32 = 0x0020_0000; +} diff --git a/esp32c5/src/lp_i2c0/comd.rs b/esp32c5/src/lp_i2c0/comd.rs new file mode 100644 index 0000000000..1d29cfb36d --- /dev/null +++ b/esp32c5/src/lp_i2c0/comd.rs @@ -0,0 +1,58 @@ +#[doc = "Register `COMD%s` reader"] +pub type R = crate::R; +#[doc = "Register `COMD%s` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND` reader - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] +pub type COMMAND_R = crate::FieldReader; +#[doc = "Field `COMMAND` writer - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] +pub type COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND_DONE` reader - When command 0 is done in I2C Master mode, this bit changes to highlevel."] +pub type COMMAND_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE` writer - When command 0 is done in I2C Master mode, this bit changes to highlevel."] +pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] + #[inline(always)] + pub fn command(&self) -> COMMAND_R { + COMMAND_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."] + #[inline(always)] + pub fn command_done(&self) -> COMMAND_DONE_R { + COMMAND_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD") + .field("command", &self.command()) + .field("command_done", &self.command_done()) + .finish() + } +} +impl W { + #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] + #[inline(always)] + pub fn command(&mut self) -> COMMAND_W<'_, COMD_SPEC> { + COMMAND_W::new(self, 0) + } + #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."] + #[inline(always)] + pub fn command_done(&mut self) -> COMMAND_DONE_W<'_, COMD_SPEC> { + COMMAND_DONE_W::new(self, 31) + } +} +#[doc = "I2C command register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`comd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD_SPEC; +impl crate::RegisterSpec for COMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd::R`](R) reader structure"] +impl crate::Readable for COMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd::W`](W) writer structure"] +impl crate::Writable for COMD_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets COMD%s to value 0"] +impl crate::Resettable for COMD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/ctr.rs b/esp32c5/src/lp_i2c0/ctr.rs new file mode 100644 index 0000000000..5ae78e3379 --- /dev/null +++ b/esp32c5/src/lp_i2c0/ctr.rs @@ -0,0 +1,171 @@ +#[doc = "Register `CTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTR` writer"] +pub type W = crate::W; +#[doc = "Field `SDA_FORCE_OUT` reader - 1: direct output, 0: open drain output."] +pub type SDA_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SDA_FORCE_OUT` writer - 1: direct output, 0: open drain output."] +pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_FORCE_OUT` reader - 1: direct output, 0: open drain output."] +pub type SCL_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SCL_FORCE_OUT` writer - 1: direct output, 0: open drain output."] +pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAMPLE_SCL_LEVEL` reader - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_R = crate::BitReader; +#[doc = "Field `SAMPLE_SCL_LEVEL` writer - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FULL_ACK_LEVEL` reader - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_R = crate::BitReader; +#[doc = "Field `RX_FULL_ACK_LEVEL` writer - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START` writer - Set this bit to start sending the data in txfifo."] +pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] +pub type TX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] +pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Reserved"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Reserved"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_EN` reader - This is the enable bit for arbitration_lost."] +pub type ARBITRATION_EN_R = crate::BitReader; +#[doc = "Field `ARBITRATION_EN` writer - This is the enable bit for arbitration_lost."] +pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FSM_RST` writer - This register is used to reset the scl FMS."] +pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONF_UPGATE` writer - synchronization bit"] +pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: direct output, 0: open drain output."] + #[inline(always)] + pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R { + SDA_FORCE_OUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: direct output, 0: open drain output."] + #[inline(always)] + pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R { + SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] + #[inline(always)] + pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R { + SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R { + RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] + #[inline(always)] + pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R { + TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] + #[inline(always)] + pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R { + RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the enable bit for arbitration_lost."] + #[inline(always)] + pub fn arbitration_en(&self) -> ARBITRATION_EN_R { + ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTR") + .field("sda_force_out", &self.sda_force_out()) + .field("scl_force_out", &self.scl_force_out()) + .field("sample_scl_level", &self.sample_scl_level()) + .field("rx_full_ack_level", &self.rx_full_ack_level()) + .field("tx_lsb_first", &self.tx_lsb_first()) + .field("rx_lsb_first", &self.rx_lsb_first()) + .field("clk_en", &self.clk_en()) + .field("arbitration_en", &self.arbitration_en()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - 1: direct output, 0: open drain output."] + #[inline(always)] + pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<'_, CTR_SPEC> { + SDA_FORCE_OUT_W::new(self, 0) + } + #[doc = "Bit 1 - 1: direct output, 0: open drain output."] + #[inline(always)] + pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<'_, CTR_SPEC> { + SCL_FORCE_OUT_W::new(self, 1) + } + #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] + #[inline(always)] + pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<'_, CTR_SPEC> { + SAMPLE_SCL_LEVEL_W::new(self, 2) + } + #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<'_, CTR_SPEC> { + RX_FULL_ACK_LEVEL_W::new(self, 3) + } + #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."] + #[inline(always)] + pub fn trans_start(&mut self) -> TRANS_START_W<'_, CTR_SPEC> { + TRANS_START_W::new(self, 5) + } + #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] + #[inline(always)] + pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<'_, CTR_SPEC> { + TX_LSB_FIRST_W::new(self, 6) + } + #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] + #[inline(always)] + pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<'_, CTR_SPEC> { + RX_LSB_FIRST_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn clk_en(&mut self) -> CLK_EN_W<'_, CTR_SPEC> { + CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - This is the enable bit for arbitration_lost."] + #[inline(always)] + pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<'_, CTR_SPEC> { + ARBITRATION_EN_W::new(self, 9) + } + #[doc = "Bit 10 - This register is used to reset the scl FMS."] + #[inline(always)] + pub fn fsm_rst(&mut self) -> FSM_RST_W<'_, CTR_SPEC> { + FSM_RST_W::new(self, 10) + } + #[doc = "Bit 11 - synchronization bit"] + #[inline(always)] + pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<'_, CTR_SPEC> { + CONF_UPGATE_W::new(self, 11) + } +} +#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_SPEC; +impl crate::RegisterSpec for CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] +impl crate::Writable for CTR_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTR to value 0x0208"] +impl crate::Resettable for CTR_SPEC { + const RESET_VALUE: u32 = 0x0208; +} diff --git a/esp32c5/src/lp_i2c0/data.rs b/esp32c5/src/lp_i2c0/data.rs new file mode 100644 index 0000000000..86f9853298 --- /dev/null +++ b/esp32c5/src/lp_i2c0/data.rs @@ -0,0 +1,43 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_RDATA` reader - The value of rx FIFO read data."] +pub type FIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `FIFO_RDATA` writer - The value of rx FIFO read data."] +pub type FIFO_RDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The value of rx FIFO read data."] + #[inline(always)] + pub fn fifo_rdata(&self) -> FIFO_RDATA_R { + FIFO_RDATA_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA") + .field("fifo_rdata", &self.fifo_rdata()) + .finish() + } +} +impl W { + #[doc = "Bits 0:7 - The value of rx FIFO read data."] + #[inline(always)] + pub fn fifo_rdata(&mut self) -> FIFO_RDATA_W<'_, DATA_SPEC> { + FIFO_RDATA_W::new(self, 0) + } +} +#[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC {} diff --git a/esp32c5/src/lp_i2c0/fifo_st.rs b/esp32c5/src/lp_i2c0/fifo_st.rs new file mode 100644 index 0000000000..2f3cd98ff8 --- /dev/null +++ b/esp32c5/src/lp_i2c0/fifo_st.rs @@ -0,0 +1,52 @@ +#[doc = "Register `FIFO_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_RADDR` reader - This is the offset address of the APB reading from rxfifo"] +pub type RXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `RXFIFO_WADDR` reader - This is the offset address of i2c module receiving data and writing to rxfifo."] +pub type RXFIFO_WADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_RADDR` reader - This is the offset address of i2c module reading from txfifo."] +pub type TXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_WADDR` reader - This is the offset address of APB bus writing to txfifo."] +pub type TXFIFO_WADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - This is the offset address of the APB reading from rxfifo"] + #[inline(always)] + pub fn rxfifo_raddr(&self) -> RXFIFO_RADDR_R { + RXFIFO_RADDR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 5:8 - This is the offset address of i2c module receiving data and writing to rxfifo."] + #[inline(always)] + pub fn rxfifo_waddr(&self) -> RXFIFO_WADDR_R { + RXFIFO_WADDR_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bits 10:13 - This is the offset address of i2c module reading from txfifo."] + #[inline(always)] + pub fn txfifo_raddr(&self) -> TXFIFO_RADDR_R { + TXFIFO_RADDR_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 15:18 - This is the offset address of APB bus writing to txfifo."] + #[inline(always)] + pub fn txfifo_waddr(&self) -> TXFIFO_WADDR_R { + TXFIFO_WADDR_R::new(((self.bits >> 15) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_ST") + .field("rxfifo_raddr", &self.rxfifo_raddr()) + .field("rxfifo_waddr", &self.rxfifo_waddr()) + .field("txfifo_raddr", &self.txfifo_raddr()) + .field("txfifo_waddr", &self.txfifo_waddr()) + .finish() + } +} +#[doc = "FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_ST_SPEC; +impl crate::RegisterSpec for FIFO_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"] +impl crate::Readable for FIFO_ST_SPEC {} +#[doc = "`reset()` method sets FIFO_ST to value 0"] +impl crate::Resettable for FIFO_ST_SPEC {} diff --git a/esp32c5/src/lp_i2c0/filter_cfg.rs b/esp32c5/src/lp_i2c0/filter_cfg.rs new file mode 100644 index 0000000000..cb1ba92986 --- /dev/null +++ b/esp32c5/src/lp_i2c0/filter_cfg.rs @@ -0,0 +1,90 @@ +#[doc = "Register `FILTER_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_FILTER_THRES` reader - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] +pub type SCL_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SCL_FILTER_THRES` writer - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] +pub type SCL_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SDA_FILTER_THRES` reader - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] +pub type SDA_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SDA_FILTER_THRES` writer - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] +pub type SDA_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SCL_FILTER_EN` reader - This is the filter enable bit for SCL."] +pub type SCL_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SCL_FILTER_EN` writer - This is the filter enable bit for SCL."] +pub type SCL_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_FILTER_EN` reader - This is the filter enable bit for SDA."] +pub type SDA_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SDA_FILTER_EN` writer - This is the filter enable bit for SDA."] +pub type SDA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] + #[inline(always)] + pub fn scl_filter_thres(&self) -> SCL_FILTER_THRES_R { + SCL_FILTER_THRES_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] + #[inline(always)] + pub fn sda_filter_thres(&self) -> SDA_FILTER_THRES_R { + SDA_FILTER_THRES_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - This is the filter enable bit for SCL."] + #[inline(always)] + pub fn scl_filter_en(&self) -> SCL_FILTER_EN_R { + SCL_FILTER_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the filter enable bit for SDA."] + #[inline(always)] + pub fn sda_filter_en(&self) -> SDA_FILTER_EN_R { + SDA_FILTER_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CFG") + .field("scl_filter_thres", &self.scl_filter_thres()) + .field("sda_filter_thres", &self.sda_filter_thres()) + .field("scl_filter_en", &self.scl_filter_en()) + .field("sda_filter_en", &self.sda_filter_en()) + .finish() + } +} +impl W { + #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] + #[inline(always)] + pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<'_, FILTER_CFG_SPEC> { + SCL_FILTER_THRES_W::new(self, 0) + } + #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] + #[inline(always)] + pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<'_, FILTER_CFG_SPEC> { + SDA_FILTER_THRES_W::new(self, 4) + } + #[doc = "Bit 8 - This is the filter enable bit for SCL."] + #[inline(always)] + pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<'_, FILTER_CFG_SPEC> { + SCL_FILTER_EN_W::new(self, 8) + } + #[doc = "Bit 9 - This is the filter enable bit for SDA."] + #[inline(always)] + pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<'_, FILTER_CFG_SPEC> { + SDA_FILTER_EN_W::new(self, 9) + } +} +#[doc = "SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CFG_SPEC; +impl crate::RegisterSpec for FILTER_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_cfg::R`](R) reader structure"] +impl crate::Readable for FILTER_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_cfg::W`](W) writer structure"] +impl crate::Writable for FILTER_CFG_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FILTER_CFG to value 0x0300"] +impl crate::Resettable for FILTER_CFG_SPEC { + const RESET_VALUE: u32 = 0x0300; +} diff --git a/esp32c5/src/lp_i2c0/i2c_clk_conf.rs b/esp32c5/src/lp_i2c0/i2c_clk_conf.rs deleted file mode 100644 index 58d8fda2c4..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_clk_conf.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `I2C_CLK_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_CLK_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `I2C_SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `I2C_SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_A_R = crate::FieldReader; -#[doc = "Field `I2C_SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `I2C_SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_B_R = crate::FieldReader; -#[doc = "Field `I2C_SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"] -pub type I2C_SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `I2C_SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] -pub type I2C_SCLK_SEL_R = crate::BitReader; -#[doc = "Field `I2C_SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] -pub type I2C_SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCLK_ACTIVE` reader - The clock switch for i2c module"] -pub type I2C_SCLK_ACTIVE_R = crate::BitReader; -#[doc = "Field `I2C_SCLK_ACTIVE` writer - The clock switch for i2c module"] -pub type I2C_SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_num(&self) -> I2C_SCLK_DIV_NUM_R { - I2C_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_a(&self) -> I2C_SCLK_DIV_A_R { - I2C_SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_b(&self) -> I2C_SCLK_DIV_B_R { - I2C_SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8) - } - #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] - #[inline(always)] - pub fn i2c_sclk_sel(&self) -> I2C_SCLK_SEL_R { - I2C_SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - The clock switch for i2c module"] - #[inline(always)] - pub fn i2c_sclk_active(&self) -> I2C_SCLK_ACTIVE_R { - I2C_SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_CLK_CONF") - .field("i2c_sclk_div_num", &self.i2c_sclk_div_num()) - .field("i2c_sclk_div_a", &self.i2c_sclk_div_a()) - .field("i2c_sclk_div_b", &self.i2c_sclk_div_b()) - .field("i2c_sclk_sel", &self.i2c_sclk_sel()) - .field("i2c_sclk_active", &self.i2c_sclk_active()) - .finish() - } -} -impl W { - #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_num(&mut self) -> I2C_SCLK_DIV_NUM_W<'_, I2C_CLK_CONF_SPEC> { - I2C_SCLK_DIV_NUM_W::new(self, 0) - } - #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_a(&mut self) -> I2C_SCLK_DIV_A_W<'_, I2C_CLK_CONF_SPEC> { - I2C_SCLK_DIV_A_W::new(self, 8) - } - #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] - #[inline(always)] - pub fn i2c_sclk_div_b(&mut self) -> I2C_SCLK_DIV_B_W<'_, I2C_CLK_CONF_SPEC> { - I2C_SCLK_DIV_B_W::new(self, 14) - } - #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] - #[inline(always)] - pub fn i2c_sclk_sel(&mut self) -> I2C_SCLK_SEL_W<'_, I2C_CLK_CONF_SPEC> { - I2C_SCLK_SEL_W::new(self, 20) - } - #[doc = "Bit 21 - The clock switch for i2c module"] - #[inline(always)] - pub fn i2c_sclk_active(&mut self) -> I2C_SCLK_ACTIVE_W<'_, I2C_CLK_CONF_SPEC> { - I2C_SCLK_ACTIVE_W::new(self, 21) - } -} -#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_CLK_CONF_SPEC; -impl crate::RegisterSpec for I2C_CLK_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_clk_conf::R`](R) reader structure"] -impl crate::Readable for I2C_CLK_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_clk_conf::W`](W) writer structure"] -impl crate::Writable for I2C_CLK_CONF_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_CLK_CONF to value 0x0020_0000"] -impl crate::Resettable for I2C_CLK_CONF_SPEC { - const RESET_VALUE: u32 = 0x0020_0000; -} diff --git a/esp32c5/src/lp_i2c0/i2c_comd0.rs b/esp32c5/src/lp_i2c0/i2c_comd0.rs deleted file mode 100644 index ed209295ad..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd0.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD0` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD0` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND0` reader - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND0_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND0` writer - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND0_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND0_DONE` reader - When command 0 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND0_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND0_DONE` writer - When command 0 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND0_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command0(&self) -> I2C_COMMAND0_R { - I2C_COMMAND0_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command0_done(&self) -> I2C_COMMAND0_DONE_R { - I2C_COMMAND0_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD0") - .field("i2c_command0", &self.i2c_command0()) - .field("i2c_command0_done", &self.i2c_command0_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command0(&mut self) -> I2C_COMMAND0_W<'_, I2C_COMD0_SPEC> { - I2C_COMMAND0_W::new(self, 0) - } - #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command0_done(&mut self) -> I2C_COMMAND0_DONE_W<'_, I2C_COMD0_SPEC> { - I2C_COMMAND0_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD0_SPEC; -impl crate::RegisterSpec for I2C_COMD0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd0::R`](R) reader structure"] -impl crate::Readable for I2C_COMD0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd0::W`](W) writer structure"] -impl crate::Writable for I2C_COMD0_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD0 to value 0"] -impl crate::Resettable for I2C_COMD0_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd1.rs b/esp32c5/src/lp_i2c0/i2c_comd1.rs deleted file mode 100644 index 75f4762685..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd1.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD1` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD1` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND1` reader - This is the content of command 1. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND1_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND1` writer - This is the content of command 1. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND1_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND1_DONE` reader - When command 1 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND1_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND1_DONE` writer - When command 1 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 1. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command1(&self) -> I2C_COMMAND1_R { - I2C_COMMAND1_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 1 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command1_done(&self) -> I2C_COMMAND1_DONE_R { - I2C_COMMAND1_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD1") - .field("i2c_command1", &self.i2c_command1()) - .field("i2c_command1_done", &self.i2c_command1_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 1. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command1(&mut self) -> I2C_COMMAND1_W<'_, I2C_COMD1_SPEC> { - I2C_COMMAND1_W::new(self, 0) - } - #[doc = "Bit 31 - When command 1 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command1_done(&mut self) -> I2C_COMMAND1_DONE_W<'_, I2C_COMD1_SPEC> { - I2C_COMMAND1_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD1_SPEC; -impl crate::RegisterSpec for I2C_COMD1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd1::R`](R) reader structure"] -impl crate::Readable for I2C_COMD1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd1::W`](W) writer structure"] -impl crate::Writable for I2C_COMD1_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD1 to value 0"] -impl crate::Resettable for I2C_COMD1_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd2.rs b/esp32c5/src/lp_i2c0/i2c_comd2.rs deleted file mode 100644 index e6f6669166..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd2.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD2` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD2` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND2` reader - This is the content of command 2. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND2_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND2` writer - This is the content of command 2. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND2_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND2_DONE` reader - When command 2 is done in I2C Master mode, this bit changes to highLevel."] -pub type I2C_COMMAND2_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND2_DONE` writer - When command 2 is done in I2C Master mode, this bit changes to highLevel."] -pub type I2C_COMMAND2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 2. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command2(&self) -> I2C_COMMAND2_R { - I2C_COMMAND2_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 2 is done in I2C Master mode, this bit changes to highLevel."] - #[inline(always)] - pub fn i2c_command2_done(&self) -> I2C_COMMAND2_DONE_R { - I2C_COMMAND2_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD2") - .field("i2c_command2", &self.i2c_command2()) - .field("i2c_command2_done", &self.i2c_command2_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 2. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command2(&mut self) -> I2C_COMMAND2_W<'_, I2C_COMD2_SPEC> { - I2C_COMMAND2_W::new(self, 0) - } - #[doc = "Bit 31 - When command 2 is done in I2C Master mode, this bit changes to highLevel."] - #[inline(always)] - pub fn i2c_command2_done(&mut self) -> I2C_COMMAND2_DONE_W<'_, I2C_COMD2_SPEC> { - I2C_COMMAND2_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD2_SPEC; -impl crate::RegisterSpec for I2C_COMD2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd2::R`](R) reader structure"] -impl crate::Readable for I2C_COMD2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd2::W`](W) writer structure"] -impl crate::Writable for I2C_COMD2_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD2 to value 0"] -impl crate::Resettable for I2C_COMD2_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd3.rs b/esp32c5/src/lp_i2c0/i2c_comd3.rs deleted file mode 100644 index 0ea03f9ddc..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd3.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD3` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD3` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND3` reader - This is the content of command 3. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND3_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND3` writer - This is the content of command 3. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND3_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND3_DONE` reader - When command 3 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND3_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND3_DONE` writer - When command 3 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND3_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 3. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command3(&self) -> I2C_COMMAND3_R { - I2C_COMMAND3_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 3 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command3_done(&self) -> I2C_COMMAND3_DONE_R { - I2C_COMMAND3_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD3") - .field("i2c_command3", &self.i2c_command3()) - .field("i2c_command3_done", &self.i2c_command3_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 3. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command3(&mut self) -> I2C_COMMAND3_W<'_, I2C_COMD3_SPEC> { - I2C_COMMAND3_W::new(self, 0) - } - #[doc = "Bit 31 - When command 3 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command3_done(&mut self) -> I2C_COMMAND3_DONE_W<'_, I2C_COMD3_SPEC> { - I2C_COMMAND3_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD3_SPEC; -impl crate::RegisterSpec for I2C_COMD3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd3::R`](R) reader structure"] -impl crate::Readable for I2C_COMD3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd3::W`](W) writer structure"] -impl crate::Writable for I2C_COMD3_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD3 to value 0"] -impl crate::Resettable for I2C_COMD3_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd4.rs b/esp32c5/src/lp_i2c0/i2c_comd4.rs deleted file mode 100644 index ce286d1fc3..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd4.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD4` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD4` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND4` reader - This is the content of command 4. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND4_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND4` writer - This is the content of command 4. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND4_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND4_DONE` reader - When command 4 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND4_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND4_DONE` writer - When command 4 is done in I2C Master mode, this bit changes to highlevel."] -pub type I2C_COMMAND4_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 4. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command4(&self) -> I2C_COMMAND4_R { - I2C_COMMAND4_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 4 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command4_done(&self) -> I2C_COMMAND4_DONE_R { - I2C_COMMAND4_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD4") - .field("i2c_command4", &self.i2c_command4()) - .field("i2c_command4_done", &self.i2c_command4_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 4. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command4(&mut self) -> I2C_COMMAND4_W<'_, I2C_COMD4_SPEC> { - I2C_COMMAND4_W::new(self, 0) - } - #[doc = "Bit 31 - When command 4 is done in I2C Master mode, this bit changes to highlevel."] - #[inline(always)] - pub fn i2c_command4_done(&mut self) -> I2C_COMMAND4_DONE_W<'_, I2C_COMD4_SPEC> { - I2C_COMMAND4_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD4_SPEC; -impl crate::RegisterSpec for I2C_COMD4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd4::R`](R) reader structure"] -impl crate::Readable for I2C_COMD4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd4::W`](W) writer structure"] -impl crate::Writable for I2C_COMD4_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD4 to value 0"] -impl crate::Resettable for I2C_COMD4_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd5.rs b/esp32c5/src/lp_i2c0/i2c_comd5.rs deleted file mode 100644 index a5eb1c2a97..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd5.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD5` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD5` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND5` reader - This is the content of command 5. It consists of three parts:op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND5_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND5` writer - This is the content of command 5. It consists of three parts:op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND5_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND5_DONE` reader - When command 5 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND5_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND5_DONE` writer - When command 5 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND5_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 5. It consists of three parts:op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command5(&self) -> I2C_COMMAND5_R { - I2C_COMMAND5_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 5 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command5_done(&self) -> I2C_COMMAND5_DONE_R { - I2C_COMMAND5_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD5") - .field("i2c_command5", &self.i2c_command5()) - .field("i2c_command5_done", &self.i2c_command5_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 5. It consists of three parts:op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command5(&mut self) -> I2C_COMMAND5_W<'_, I2C_COMD5_SPEC> { - I2C_COMMAND5_W::new(self, 0) - } - #[doc = "Bit 31 - When command 5 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command5_done(&mut self) -> I2C_COMMAND5_DONE_W<'_, I2C_COMD5_SPEC> { - I2C_COMMAND5_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD5_SPEC; -impl crate::RegisterSpec for I2C_COMD5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd5::R`](R) reader structure"] -impl crate::Readable for I2C_COMD5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd5::W`](W) writer structure"] -impl crate::Writable for I2C_COMD5_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD5 to value 0"] -impl crate::Resettable for I2C_COMD5_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd6.rs b/esp32c5/src/lp_i2c0/i2c_comd6.rs deleted file mode 100644 index 0222793ceb..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd6.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD6` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD6` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND6` reader - This is the content of command 6. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND6_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND6` writer - This is the content of command 6. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND6_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND6_DONE` reader - When command 6 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND6_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND6_DONE` writer - When command 6 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND6_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 6. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command6(&self) -> I2C_COMMAND6_R { - I2C_COMMAND6_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 6 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command6_done(&self) -> I2C_COMMAND6_DONE_R { - I2C_COMMAND6_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD6") - .field("i2c_command6", &self.i2c_command6()) - .field("i2c_command6_done", &self.i2c_command6_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 6. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command6(&mut self) -> I2C_COMMAND6_W<'_, I2C_COMD6_SPEC> { - I2C_COMMAND6_W::new(self, 0) - } - #[doc = "Bit 31 - When command 6 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command6_done(&mut self) -> I2C_COMMAND6_DONE_W<'_, I2C_COMD6_SPEC> { - I2C_COMMAND6_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD6_SPEC; -impl crate::RegisterSpec for I2C_COMD6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd6::R`](R) reader structure"] -impl crate::Readable for I2C_COMD6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd6::W`](W) writer structure"] -impl crate::Writable for I2C_COMD6_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD6 to value 0"] -impl crate::Resettable for I2C_COMD6_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_comd7.rs b/esp32c5/src/lp_i2c0/i2c_comd7.rs deleted file mode 100644 index 555d0a1590..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_comd7.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `I2C_COMD7` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_COMD7` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_COMMAND7` reader - This is the content of command 7. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND7_R = crate::FieldReader; -#[doc = "Field `I2C_COMMAND7` writer - This is the content of command 7. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] -pub type I2C_COMMAND7_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `I2C_COMMAND7_DONE` reader - When command 7 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND7_DONE_R = crate::BitReader; -#[doc = "Field `I2C_COMMAND7_DONE` writer - When command 7 is done in I2C Master mode, this bit changes to high level."] -pub type I2C_COMMAND7_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:13 - This is the content of command 7. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command7(&self) -> I2C_COMMAND7_R { - I2C_COMMAND7_R::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bit 31 - When command 7 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command7_done(&self) -> I2C_COMMAND7_DONE_R { - I2C_COMMAND7_DONE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_COMD7") - .field("i2c_command7", &self.i2c_command7()) - .field("i2c_command7_done", &self.i2c_command7_done()) - .finish() - } -} -impl W { - #[doc = "Bits 0:13 - This is the content of command 7. It consists of three parts: op_code is the command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for moreInformation."] - #[inline(always)] - pub fn i2c_command7(&mut self) -> I2C_COMMAND7_W<'_, I2C_COMD7_SPEC> { - I2C_COMMAND7_W::new(self, 0) - } - #[doc = "Bit 31 - When command 7 is done in I2C Master mode, this bit changes to high level."] - #[inline(always)] - pub fn i2c_command7_done(&mut self) -> I2C_COMMAND7_DONE_W<'_, I2C_COMD7_SPEC> { - I2C_COMMAND7_DONE_W::new(self, 31) - } -} -#[doc = "I2C command register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_comd7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_comd7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_COMD7_SPEC; -impl crate::RegisterSpec for I2C_COMD7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_comd7::R`](R) reader structure"] -impl crate::Readable for I2C_COMD7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_comd7::W`](W) writer structure"] -impl crate::Writable for I2C_COMD7_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_COMD7 to value 0"] -impl crate::Resettable for I2C_COMD7_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_ctr.rs b/esp32c5/src/lp_i2c0/i2c_ctr.rs deleted file mode 100644 index 5fac68b67f..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_ctr.rs +++ /dev/null @@ -1,171 +0,0 @@ -#[doc = "Register `I2C_CTR` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_CTR` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SDA_FORCE_OUT` reader - 1: direct output, 0: open drain output."] -pub type I2C_SDA_FORCE_OUT_R = crate::BitReader; -#[doc = "Field `I2C_SDA_FORCE_OUT` writer - 1: direct output, 0: open drain output."] -pub type I2C_SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_FORCE_OUT` reader - 1: direct output, 0: open drain output."] -pub type I2C_SCL_FORCE_OUT_R = crate::BitReader; -#[doc = "Field `I2C_SCL_FORCE_OUT` writer - 1: direct output, 0: open drain output."] -pub type I2C_SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SAMPLE_SCL_LEVEL` reader - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] -pub type I2C_SAMPLE_SCL_LEVEL_R = crate::BitReader; -#[doc = "Field `I2C_SAMPLE_SCL_LEVEL` writer - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] -pub type I2C_SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RX_FULL_ACK_LEVEL` reader - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] -pub type I2C_RX_FULL_ACK_LEVEL_R = crate::BitReader; -#[doc = "Field `I2C_RX_FULL_ACK_LEVEL` writer - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] -pub type I2C_RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TRANS_START` writer - Set this bit to start sending the data in txfifo."] -pub type I2C_TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TX_LSB_FIRST` reader - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] -pub type I2C_TX_LSB_FIRST_R = crate::BitReader; -#[doc = "Field `I2C_TX_LSB_FIRST` writer - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] -pub type I2C_TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] -pub type I2C_RX_LSB_FIRST_R = crate::BitReader; -#[doc = "Field `I2C_RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] -pub type I2C_RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_CLK_EN` reader - Reserved"] -pub type I2C_CLK_EN_R = crate::BitReader; -#[doc = "Field `I2C_CLK_EN` writer - Reserved"] -pub type I2C_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_ARBITRATION_EN` reader - This is the enable bit for arbitration_lost."] -pub type I2C_ARBITRATION_EN_R = crate::BitReader; -#[doc = "Field `I2C_ARBITRATION_EN` writer - This is the enable bit for arbitration_lost."] -pub type I2C_ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_FSM_RST` writer - This register is used to reset the scl FMS."] -pub type I2C_FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_CONF_UPGATE` writer - synchronization bit"] -pub type I2C_CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: direct output, 0: open drain output."] - #[inline(always)] - pub fn i2c_sda_force_out(&self) -> I2C_SDA_FORCE_OUT_R { - I2C_SDA_FORCE_OUT_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - 1: direct output, 0: open drain output."] - #[inline(always)] - pub fn i2c_scl_force_out(&self) -> I2C_SCL_FORCE_OUT_R { - I2C_SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] - #[inline(always)] - pub fn i2c_sample_scl_level(&self) -> I2C_SAMPLE_SCL_LEVEL_R { - I2C_SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] - #[inline(always)] - pub fn i2c_rx_full_ack_level(&self) -> I2C_RX_FULL_ACK_LEVEL_R { - I2C_RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] - #[inline(always)] - pub fn i2c_tx_lsb_first(&self) -> I2C_TX_LSB_FIRST_R { - I2C_TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] - #[inline(always)] - pub fn i2c_rx_lsb_first(&self) -> I2C_RX_LSB_FIRST_R { - I2C_RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Reserved"] - #[inline(always)] - pub fn i2c_clk_en(&self) -> I2C_CLK_EN_R { - I2C_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - This is the enable bit for arbitration_lost."] - #[inline(always)] - pub fn i2c_arbitration_en(&self) -> I2C_ARBITRATION_EN_R { - I2C_ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_CTR") - .field("i2c_sda_force_out", &self.i2c_sda_force_out()) - .field("i2c_scl_force_out", &self.i2c_scl_force_out()) - .field("i2c_sample_scl_level", &self.i2c_sample_scl_level()) - .field("i2c_rx_full_ack_level", &self.i2c_rx_full_ack_level()) - .field("i2c_tx_lsb_first", &self.i2c_tx_lsb_first()) - .field("i2c_rx_lsb_first", &self.i2c_rx_lsb_first()) - .field("i2c_clk_en", &self.i2c_clk_en()) - .field("i2c_arbitration_en", &self.i2c_arbitration_en()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - 1: direct output, 0: open drain output."] - #[inline(always)] - pub fn i2c_sda_force_out(&mut self) -> I2C_SDA_FORCE_OUT_W<'_, I2C_CTR_SPEC> { - I2C_SDA_FORCE_OUT_W::new(self, 0) - } - #[doc = "Bit 1 - 1: direct output, 0: open drain output."] - #[inline(always)] - pub fn i2c_scl_force_out(&mut self) -> I2C_SCL_FORCE_OUT_W<'_, I2C_CTR_SPEC> { - I2C_SCL_FORCE_OUT_W::new(self, 1) - } - #[doc = "Bit 2 - This register is used to select the sample mode.1: sample SDA data on the SCL low level.0: sample SDA data on the SCL high level."] - #[inline(always)] - pub fn i2c_sample_scl_level(&mut self) -> I2C_SAMPLE_SCL_LEVEL_W<'_, I2C_CTR_SPEC> { - I2C_SAMPLE_SCL_LEVEL_W::new(self, 2) - } - #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."] - #[inline(always)] - pub fn i2c_rx_full_ack_level(&mut self) -> I2C_RX_FULL_ACK_LEVEL_W<'_, I2C_CTR_SPEC> { - I2C_RX_FULL_ACK_LEVEL_W::new(self, 3) - } - #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."] - #[inline(always)] - pub fn i2c_trans_start(&mut self) -> I2C_TRANS_START_W<'_, I2C_CTR_SPEC> { - I2C_TRANS_START_W::new(self, 5) - } - #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit,0: send data from the most significant bit."] - #[inline(always)] - pub fn i2c_tx_lsb_first(&mut self) -> I2C_TX_LSB_FIRST_W<'_, I2C_CTR_SPEC> { - I2C_TX_LSB_FIRST_W::new(self, 6) - } - #[doc = "Bit 7 - This bit is used to control the storage mode for received data.1: receive data from the least significant bit,0: receive data from the most significant bit."] - #[inline(always)] - pub fn i2c_rx_lsb_first(&mut self) -> I2C_RX_LSB_FIRST_W<'_, I2C_CTR_SPEC> { - I2C_RX_LSB_FIRST_W::new(self, 7) - } - #[doc = "Bit 8 - Reserved"] - #[inline(always)] - pub fn i2c_clk_en(&mut self) -> I2C_CLK_EN_W<'_, I2C_CTR_SPEC> { - I2C_CLK_EN_W::new(self, 8) - } - #[doc = "Bit 9 - This is the enable bit for arbitration_lost."] - #[inline(always)] - pub fn i2c_arbitration_en(&mut self) -> I2C_ARBITRATION_EN_W<'_, I2C_CTR_SPEC> { - I2C_ARBITRATION_EN_W::new(self, 9) - } - #[doc = "Bit 10 - This register is used to reset the scl FMS."] - #[inline(always)] - pub fn i2c_fsm_rst(&mut self) -> I2C_FSM_RST_W<'_, I2C_CTR_SPEC> { - I2C_FSM_RST_W::new(self, 10) - } - #[doc = "Bit 11 - synchronization bit"] - #[inline(always)] - pub fn i2c_conf_upgate(&mut self) -> I2C_CONF_UPGATE_W<'_, I2C_CTR_SPEC> { - I2C_CONF_UPGATE_W::new(self, 11) - } -} -#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_CTR_SPEC; -impl crate::RegisterSpec for I2C_CTR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_ctr::R`](R) reader structure"] -impl crate::Readable for I2C_CTR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_ctr::W`](W) writer structure"] -impl crate::Writable for I2C_CTR_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_CTR to value 0x0208"] -impl crate::Resettable for I2C_CTR_SPEC { - const RESET_VALUE: u32 = 0x0208; -} diff --git a/esp32c5/src/lp_i2c0/i2c_data.rs b/esp32c5/src/lp_i2c0/i2c_data.rs deleted file mode 100644 index fbc5238f26..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_data.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `I2C_DATA` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_FIFO_RDATA` reader - The value of rx FIFO read data."] -pub type I2C_FIFO_RDATA_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - The value of rx FIFO read data."] - #[inline(always)] - pub fn i2c_fifo_rdata(&self) -> I2C_FIFO_RDATA_R { - I2C_FIFO_RDATA_R::new((self.bits & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_DATA") - .field("i2c_fifo_rdata", &self.i2c_fifo_rdata()) - .finish() - } -} -#[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_DATA_SPEC; -impl crate::RegisterSpec for I2C_DATA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_data::R`](R) reader structure"] -impl crate::Readable for I2C_DATA_SPEC {} -#[doc = "`reset()` method sets I2C_DATA to value 0"] -impl crate::Resettable for I2C_DATA_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_fifo_st.rs b/esp32c5/src/lp_i2c0/i2c_fifo_st.rs deleted file mode 100644 index 7d67c238ea..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_fifo_st.rs +++ /dev/null @@ -1,52 +0,0 @@ -#[doc = "Register `I2C_FIFO_ST` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_RXFIFO_RADDR` reader - This is the offset address of the APB reading from rxfifo"] -pub type I2C_RXFIFO_RADDR_R = crate::FieldReader; -#[doc = "Field `I2C_RXFIFO_WADDR` reader - This is the offset address of i2c module receiving data and writing to rxfifo."] -pub type I2C_RXFIFO_WADDR_R = crate::FieldReader; -#[doc = "Field `I2C_TXFIFO_RADDR` reader - This is the offset address of i2c module reading from txfifo."] -pub type I2C_TXFIFO_RADDR_R = crate::FieldReader; -#[doc = "Field `I2C_TXFIFO_WADDR` reader - This is the offset address of APB bus writing to txfifo."] -pub type I2C_TXFIFO_WADDR_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - This is the offset address of the APB reading from rxfifo"] - #[inline(always)] - pub fn i2c_rxfifo_raddr(&self) -> I2C_RXFIFO_RADDR_R { - I2C_RXFIFO_RADDR_R::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 5:8 - This is the offset address of i2c module receiving data and writing to rxfifo."] - #[inline(always)] - pub fn i2c_rxfifo_waddr(&self) -> I2C_RXFIFO_WADDR_R { - I2C_RXFIFO_WADDR_R::new(((self.bits >> 5) & 0x0f) as u8) - } - #[doc = "Bits 10:13 - This is the offset address of i2c module reading from txfifo."] - #[inline(always)] - pub fn i2c_txfifo_raddr(&self) -> I2C_TXFIFO_RADDR_R { - I2C_TXFIFO_RADDR_R::new(((self.bits >> 10) & 0x0f) as u8) - } - #[doc = "Bits 15:18 - This is the offset address of APB bus writing to txfifo."] - #[inline(always)] - pub fn i2c_txfifo_waddr(&self) -> I2C_TXFIFO_WADDR_R { - I2C_TXFIFO_WADDR_R::new(((self.bits >> 15) & 0x0f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_FIFO_ST") - .field("i2c_rxfifo_raddr", &self.i2c_rxfifo_raddr()) - .field("i2c_rxfifo_waddr", &self.i2c_rxfifo_waddr()) - .field("i2c_txfifo_raddr", &self.i2c_txfifo_raddr()) - .field("i2c_txfifo_waddr", &self.i2c_txfifo_waddr()) - .finish() - } -} -#[doc = "FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifo_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_FIFO_ST_SPEC; -impl crate::RegisterSpec for I2C_FIFO_ST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_fifo_st::R`](R) reader structure"] -impl crate::Readable for I2C_FIFO_ST_SPEC {} -#[doc = "`reset()` method sets I2C_FIFO_ST to value 0"] -impl crate::Resettable for I2C_FIFO_ST_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_filter_cfg.rs b/esp32c5/src/lp_i2c0/i2c_filter_cfg.rs deleted file mode 100644 index 82e924b885..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_filter_cfg.rs +++ /dev/null @@ -1,90 +0,0 @@ -#[doc = "Register `I2C_FILTER_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_FILTER_CFG` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_FILTER_THRES` reader - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] -pub type I2C_SCL_FILTER_THRES_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_FILTER_THRES` writer - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] -pub type I2C_SCL_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `I2C_SDA_FILTER_THRES` reader - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] -pub type I2C_SDA_FILTER_THRES_R = crate::FieldReader; -#[doc = "Field `I2C_SDA_FILTER_THRES` writer - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] -pub type I2C_SDA_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `I2C_SCL_FILTER_EN` reader - This is the filter enable bit for SCL."] -pub type I2C_SCL_FILTER_EN_R = crate::BitReader; -#[doc = "Field `I2C_SCL_FILTER_EN` writer - This is the filter enable bit for SCL."] -pub type I2C_SCL_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SDA_FILTER_EN` reader - This is the filter enable bit for SDA."] -pub type I2C_SDA_FILTER_EN_R = crate::BitReader; -#[doc = "Field `I2C_SDA_FILTER_EN` writer - This is the filter enable bit for SDA."] -pub type I2C_SDA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] - #[inline(always)] - pub fn i2c_scl_filter_thres(&self) -> I2C_SCL_FILTER_THRES_R { - I2C_SCL_FILTER_THRES_R::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] - #[inline(always)] - pub fn i2c_sda_filter_thres(&self) -> I2C_SDA_FILTER_THRES_R { - I2C_SDA_FILTER_THRES_R::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bit 8 - This is the filter enable bit for SCL."] - #[inline(always)] - pub fn i2c_scl_filter_en(&self) -> I2C_SCL_FILTER_EN_R { - I2C_SCL_FILTER_EN_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - This is the filter enable bit for SDA."] - #[inline(always)] - pub fn i2c_sda_filter_en(&self) -> I2C_SDA_FILTER_EN_R { - I2C_SDA_FILTER_EN_R::new(((self.bits >> 9) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_FILTER_CFG") - .field("i2c_scl_filter_thres", &self.i2c_scl_filter_thres()) - .field("i2c_sda_filter_thres", &self.i2c_sda_filter_thres()) - .field("i2c_scl_filter_en", &self.i2c_scl_filter_en()) - .field("i2c_sda_filter_en", &self.i2c_sda_filter_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] - #[inline(always)] - pub fn i2c_scl_filter_thres(&mut self) -> I2C_SCL_FILTER_THRES_W<'_, I2C_FILTER_CFG_SPEC> { - I2C_SCL_FILTER_THRES_W::new(self, 0) - } - #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register valuein I2C module clock cycles, the I2C controller will ignore that pulse."] - #[inline(always)] - pub fn i2c_sda_filter_thres(&mut self) -> I2C_SDA_FILTER_THRES_W<'_, I2C_FILTER_CFG_SPEC> { - I2C_SDA_FILTER_THRES_W::new(self, 4) - } - #[doc = "Bit 8 - This is the filter enable bit for SCL."] - #[inline(always)] - pub fn i2c_scl_filter_en(&mut self) -> I2C_SCL_FILTER_EN_W<'_, I2C_FILTER_CFG_SPEC> { - I2C_SCL_FILTER_EN_W::new(self, 8) - } - #[doc = "Bit 9 - This is the filter enable bit for SDA."] - #[inline(always)] - pub fn i2c_sda_filter_en(&mut self) -> I2C_SDA_FILTER_EN_W<'_, I2C_FILTER_CFG_SPEC> { - I2C_SDA_FILTER_EN_W::new(self, 9) - } -} -#[doc = "SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_filter_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_filter_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_FILTER_CFG_SPEC; -impl crate::RegisterSpec for I2C_FILTER_CFG_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_filter_cfg::R`](R) reader structure"] -impl crate::Readable for I2C_FILTER_CFG_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_filter_cfg::W`](W) writer structure"] -impl crate::Writable for I2C_FILTER_CFG_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_FILTER_CFG to value 0x0300"] -impl crate::Resettable for I2C_FILTER_CFG_SPEC { - const RESET_VALUE: u32 = 0x0300; -} diff --git a/esp32c5/src/lp_i2c0/i2c_int_clr.rs b/esp32c5/src/lp_i2c0/i2c_int_clr.rs deleted file mode 100644 index 45bc8d08f4..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_int_clr.rs +++ /dev/null @@ -1,143 +0,0 @@ -#[doc = "Register `I2C_INT_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_RXFIFO_WM_INT_CLR` writer - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."] -pub type I2C_RXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TXFIFO_WM_INT_CLR` writer - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."] -pub type I2C_TXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RXFIFO_OVF_INT_CLR` writer - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."] -pub type I2C_RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_END_DETECT_INT_CLR` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."] -pub type I2C_END_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_BYTE_TRANS_DONE_INT_CLR` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."] -pub type I2C_BYTE_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_ARBITRATION_LOST_INT_CLR` writer - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."] -pub type I2C_ARBITRATION_LOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_MST_TXFIFO_UDF_INT_CLR` writer - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_MST_TXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TRANS_COMPLETE_INT_CLR` writer - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_TRANS_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TIME_OUT_INT_CLR` writer - Set this bit to clear the I2C_TIME_OUT_INT interrupt."] -pub type I2C_TIME_OUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TRANS_START_INT_CLR` writer - Set this bit to clear the I2C_TRANS_START_INT interrupt."] -pub type I2C_TRANS_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_NACK_INT_CLR` writer - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."] -pub type I2C_NACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TXFIFO_OVF_INT_CLR` writer - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."] -pub type I2C_TXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RXFIFO_UDF_INT_CLR` writer - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."] -pub type I2C_RXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_ST_TO_INT_CLR` writer - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."] -pub type I2C_SCL_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_INT_CLR` writer - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type I2C_SCL_MAIN_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_DET_START_INT_CLR` writer - Set this bit to clear I2C_DET_START_INT interrupt."] -pub type I2C_DET_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_wm_int_clr(&mut self) -> I2C_RXFIFO_WM_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_RXFIFO_WM_INT_CLR_W::new(self, 0) - } - #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_wm_int_clr(&mut self) -> I2C_TXFIFO_WM_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_TXFIFO_WM_INT_CLR_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_ovf_int_clr(&mut self) -> I2C_RXFIFO_OVF_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_RXFIFO_OVF_INT_CLR_W::new(self, 2) - } - #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_end_detect_int_clr(&mut self) -> I2C_END_DETECT_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_END_DETECT_INT_CLR_W::new(self, 3) - } - #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_byte_trans_done_int_clr( - &mut self, - ) -> I2C_BYTE_TRANS_DONE_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_BYTE_TRANS_DONE_INT_CLR_W::new(self, 4) - } - #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."] - #[inline(always)] - pub fn i2c_arbitration_lost_int_clr( - &mut self, - ) -> I2C_ARBITRATION_LOST_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_ARBITRATION_LOST_INT_CLR_W::new(self, 5) - } - #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_mst_txfifo_udf_int_clr( - &mut self, - ) -> I2C_MST_TXFIFO_UDF_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_MST_TXFIFO_UDF_INT_CLR_W::new(self, 6) - } - #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_complete_int_clr( - &mut self, - ) -> I2C_TRANS_COMPLETE_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_TRANS_COMPLETE_INT_CLR_W::new(self, 7) - } - #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."] - #[inline(always)] - pub fn i2c_time_out_int_clr(&mut self) -> I2C_TIME_OUT_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_TIME_OUT_INT_CLR_W::new(self, 8) - } - #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_start_int_clr(&mut self) -> I2C_TRANS_START_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_TRANS_START_INT_CLR_W::new(self, 9) - } - #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."] - #[inline(always)] - pub fn i2c_nack_int_clr(&mut self) -> I2C_NACK_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_NACK_INT_CLR_W::new(self, 10) - } - #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_ovf_int_clr(&mut self) -> I2C_TXFIFO_OVF_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_TXFIFO_OVF_INT_CLR_W::new(self, 11) - } - #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_udf_int_clr(&mut self) -> I2C_RXFIFO_UDF_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_RXFIFO_UDF_INT_CLR_W::new(self, 12) - } - #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_st_to_int_clr(&mut self) -> I2C_SCL_ST_TO_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_SCL_ST_TO_INT_CLR_W::new(self, 13) - } - #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_main_st_to_int_clr( - &mut self, - ) -> I2C_SCL_MAIN_ST_TO_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_SCL_MAIN_ST_TO_INT_CLR_W::new(self, 14) - } - #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."] - #[inline(always)] - pub fn i2c_det_start_int_clr(&mut self) -> I2C_DET_START_INT_CLR_W<'_, I2C_INT_CLR_SPEC> { - I2C_DET_START_INT_CLR_W::new(self, 15) - } -} -#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_INT_CLR_SPEC; -impl crate::RegisterSpec for I2C_INT_CLR_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`i2c_int_clr::W`](W) writer structure"] -impl crate::Writable for I2C_INT_CLR_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_INT_CLR to value 0"] -impl crate::Resettable for I2C_INT_CLR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_int_ena.rs b/esp32c5/src/lp_i2c0/i2c_int_ena.rs deleted file mode 100644 index 3e7b156a5c..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_int_ena.rs +++ /dev/null @@ -1,293 +0,0 @@ -#[doc = "Register `I2C_INT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_INT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_RXFIFO_WM_INT_ENA` reader - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] -pub type I2C_RXFIFO_WM_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_WM_INT_ENA` writer - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] -pub type I2C_RXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TXFIFO_WM_INT_ENA` reader - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] -pub type I2C_TXFIFO_WM_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_WM_INT_ENA` writer - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] -pub type I2C_TXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RXFIFO_OVF_INT_ENA` reader - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] -pub type I2C_RXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_OVF_INT_ENA` writer - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] -pub type I2C_RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_END_DETECT_INT_ENA` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_END_DETECT_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_END_DETECT_INT_ENA` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_END_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_BYTE_TRANS_DONE_INT_ENA` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_BYTE_TRANS_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_BYTE_TRANS_DONE_INT_ENA` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_BYTE_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_ARBITRATION_LOST_INT_ENA` reader - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] -pub type I2C_ARBITRATION_LOST_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_ARBITRATION_LOST_INT_ENA` writer - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] -pub type I2C_ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_MST_TXFIFO_UDF_INT_ENA` reader - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_MST_TXFIFO_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_MST_TXFIFO_UDF_INT_ENA` writer - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_MST_TXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TRANS_COMPLETE_INT_ENA` reader - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_TRANS_COMPLETE_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_COMPLETE_INT_ENA` writer - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_TRANS_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TIME_OUT_INT_ENA` reader - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] -pub type I2C_TIME_OUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_TIME_OUT_INT_ENA` writer - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] -pub type I2C_TIME_OUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TRANS_START_INT_ENA` reader - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] -pub type I2C_TRANS_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_START_INT_ENA` writer - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] -pub type I2C_TRANS_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_NACK_INT_ENA` reader - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] -pub type I2C_NACK_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_NACK_INT_ENA` writer - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] -pub type I2C_NACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_TXFIFO_OVF_INT_ENA` reader - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] -pub type I2C_TXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_OVF_INT_ENA` writer - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] -pub type I2C_TXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_RXFIFO_UDF_INT_ENA` reader - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] -pub type I2C_RXFIFO_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_UDF_INT_ENA` writer - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] -pub type I2C_RXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_ST_TO_INT_ENA` reader - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] -pub type I2C_SCL_ST_TO_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_SCL_ST_TO_INT_ENA` writer - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] -pub type I2C_SCL_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_INT_ENA` reader - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type I2C_SCL_MAIN_ST_TO_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_INT_ENA` writer - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type I2C_SCL_MAIN_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_DET_START_INT_ENA` reader - The interrupt enable bit for I2C_DET_START_INT interrupt."] -pub type I2C_DET_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2C_DET_START_INT_ENA` writer - The interrupt enable bit for I2C_DET_START_INT interrupt."] -pub type I2C_DET_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_wm_int_ena(&self) -> I2C_RXFIFO_WM_INT_ENA_R { - I2C_RXFIFO_WM_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_wm_int_ena(&self) -> I2C_TXFIFO_WM_INT_ENA_R { - I2C_TXFIFO_WM_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_ovf_int_ena(&self) -> I2C_RXFIFO_OVF_INT_ENA_R { - I2C_RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_end_detect_int_ena(&self) -> I2C_END_DETECT_INT_ENA_R { - I2C_END_DETECT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_byte_trans_done_int_ena(&self) -> I2C_BYTE_TRANS_DONE_INT_ENA_R { - I2C_BYTE_TRANS_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] - #[inline(always)] - pub fn i2c_arbitration_lost_int_ena(&self) -> I2C_ARBITRATION_LOST_INT_ENA_R { - I2C_ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_mst_txfifo_udf_int_ena(&self) -> I2C_MST_TXFIFO_UDF_INT_ENA_R { - I2C_MST_TXFIFO_UDF_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_complete_int_ena(&self) -> I2C_TRANS_COMPLETE_INT_ENA_R { - I2C_TRANS_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] - #[inline(always)] - pub fn i2c_time_out_int_ena(&self) -> I2C_TIME_OUT_INT_ENA_R { - I2C_TIME_OUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_start_int_ena(&self) -> I2C_TRANS_START_INT_ENA_R { - I2C_TRANS_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] - #[inline(always)] - pub fn i2c_nack_int_ena(&self) -> I2C_NACK_INT_ENA_R { - I2C_NACK_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_ovf_int_ena(&self) -> I2C_TXFIFO_OVF_INT_ENA_R { - I2C_TXFIFO_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_udf_int_ena(&self) -> I2C_RXFIFO_UDF_INT_ENA_R { - I2C_RXFIFO_UDF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_st_to_int_ena(&self) -> I2C_SCL_ST_TO_INT_ENA_R { - I2C_SCL_ST_TO_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_main_st_to_int_ena(&self) -> I2C_SCL_MAIN_ST_TO_INT_ENA_R { - I2C_SCL_MAIN_ST_TO_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."] - #[inline(always)] - pub fn i2c_det_start_int_ena(&self) -> I2C_DET_START_INT_ENA_R { - I2C_DET_START_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_INT_ENA") - .field("i2c_rxfifo_wm_int_ena", &self.i2c_rxfifo_wm_int_ena()) - .field("i2c_txfifo_wm_int_ena", &self.i2c_txfifo_wm_int_ena()) - .field("i2c_rxfifo_ovf_int_ena", &self.i2c_rxfifo_ovf_int_ena()) - .field("i2c_end_detect_int_ena", &self.i2c_end_detect_int_ena()) - .field( - "i2c_byte_trans_done_int_ena", - &self.i2c_byte_trans_done_int_ena(), - ) - .field( - "i2c_arbitration_lost_int_ena", - &self.i2c_arbitration_lost_int_ena(), - ) - .field( - "i2c_mst_txfifo_udf_int_ena", - &self.i2c_mst_txfifo_udf_int_ena(), - ) - .field( - "i2c_trans_complete_int_ena", - &self.i2c_trans_complete_int_ena(), - ) - .field("i2c_time_out_int_ena", &self.i2c_time_out_int_ena()) - .field("i2c_trans_start_int_ena", &self.i2c_trans_start_int_ena()) - .field("i2c_nack_int_ena", &self.i2c_nack_int_ena()) - .field("i2c_txfifo_ovf_int_ena", &self.i2c_txfifo_ovf_int_ena()) - .field("i2c_rxfifo_udf_int_ena", &self.i2c_rxfifo_udf_int_ena()) - .field("i2c_scl_st_to_int_ena", &self.i2c_scl_st_to_int_ena()) - .field( - "i2c_scl_main_st_to_int_ena", - &self.i2c_scl_main_st_to_int_ena(), - ) - .field("i2c_det_start_int_ena", &self.i2c_det_start_int_ena()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_wm_int_ena(&mut self) -> I2C_RXFIFO_WM_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_RXFIFO_WM_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_wm_int_ena(&mut self) -> I2C_TXFIFO_WM_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_TXFIFO_WM_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_ovf_int_ena(&mut self) -> I2C_RXFIFO_OVF_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_RXFIFO_OVF_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_end_detect_int_ena(&mut self) -> I2C_END_DETECT_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_END_DETECT_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_byte_trans_done_int_ena( - &mut self, - ) -> I2C_BYTE_TRANS_DONE_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_BYTE_TRANS_DONE_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] - #[inline(always)] - pub fn i2c_arbitration_lost_int_ena( - &mut self, - ) -> I2C_ARBITRATION_LOST_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_ARBITRATION_LOST_INT_ENA_W::new(self, 5) - } - #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_mst_txfifo_udf_int_ena( - &mut self, - ) -> I2C_MST_TXFIFO_UDF_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_MST_TXFIFO_UDF_INT_ENA_W::new(self, 6) - } - #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_complete_int_ena( - &mut self, - ) -> I2C_TRANS_COMPLETE_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_TRANS_COMPLETE_INT_ENA_W::new(self, 7) - } - #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] - #[inline(always)] - pub fn i2c_time_out_int_ena(&mut self) -> I2C_TIME_OUT_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_TIME_OUT_INT_ENA_W::new(self, 8) - } - #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_start_int_ena(&mut self) -> I2C_TRANS_START_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_TRANS_START_INT_ENA_W::new(self, 9) - } - #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] - #[inline(always)] - pub fn i2c_nack_int_ena(&mut self) -> I2C_NACK_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_NACK_INT_ENA_W::new(self, 10) - } - #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_ovf_int_ena(&mut self) -> I2C_TXFIFO_OVF_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_TXFIFO_OVF_INT_ENA_W::new(self, 11) - } - #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_udf_int_ena(&mut self) -> I2C_RXFIFO_UDF_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_RXFIFO_UDF_INT_ENA_W::new(self, 12) - } - #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_st_to_int_ena(&mut self) -> I2C_SCL_ST_TO_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_SCL_ST_TO_INT_ENA_W::new(self, 13) - } - #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_main_st_to_int_ena( - &mut self, - ) -> I2C_SCL_MAIN_ST_TO_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_SCL_MAIN_ST_TO_INT_ENA_W::new(self, 14) - } - #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."] - #[inline(always)] - pub fn i2c_det_start_int_ena(&mut self) -> I2C_DET_START_INT_ENA_W<'_, I2C_INT_ENA_SPEC> { - I2C_DET_START_INT_ENA_W::new(self, 15) - } -} -#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_INT_ENA_SPEC; -impl crate::RegisterSpec for I2C_INT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_int_ena::R`](R) reader structure"] -impl crate::Readable for I2C_INT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_int_ena::W`](W) writer structure"] -impl crate::Writable for I2C_INT_ENA_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_INT_ENA to value 0"] -impl crate::Resettable for I2C_INT_ENA_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_int_raw.rs b/esp32c5/src/lp_i2c0/i2c_int_raw.rs deleted file mode 100644 index a01786fd1f..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_int_raw.rs +++ /dev/null @@ -1,165 +0,0 @@ -#[doc = "Register `I2C_INT_RAW` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_RXFIFO_WM_INT_RAW` reader - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."] -pub type I2C_RXFIFO_WM_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_WM_INT_RAW` reader - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."] -pub type I2C_TXFIFO_WM_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_OVF_INT_RAW` reader - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."] -pub type I2C_RXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_END_DETECT_INT_RAW` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_END_DETECT_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_BYTE_TRANS_DONE_INT_RAW` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_BYTE_TRANS_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_ARBITRATION_LOST_INT_RAW` reader - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."] -pub type I2C_ARBITRATION_LOST_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_MST_TXFIFO_UDF_INT_RAW` reader - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_MST_TXFIFO_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_COMPLETE_INT_RAW` reader - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_TRANS_COMPLETE_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_TIME_OUT_INT_RAW` reader - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."] -pub type I2C_TIME_OUT_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_START_INT_RAW` reader - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."] -pub type I2C_TRANS_START_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_NACK_INT_RAW` reader - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."] -pub type I2C_NACK_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_OVF_INT_RAW` reader - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."] -pub type I2C_TXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_UDF_INT_RAW` reader - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."] -pub type I2C_RXFIFO_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_SCL_ST_TO_INT_RAW` reader - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."] -pub type I2C_SCL_ST_TO_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_INT_RAW` reader - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type I2C_SCL_MAIN_ST_TO_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2C_DET_START_INT_RAW` reader - The raw interrupt bit for I2C_DET_START_INT interrupt."] -pub type I2C_DET_START_INT_RAW_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_wm_int_raw(&self) -> I2C_RXFIFO_WM_INT_RAW_R { - I2C_RXFIFO_WM_INT_RAW_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_wm_int_raw(&self) -> I2C_TXFIFO_WM_INT_RAW_R { - I2C_TXFIFO_WM_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_ovf_int_raw(&self) -> I2C_RXFIFO_OVF_INT_RAW_R { - I2C_RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_end_detect_int_raw(&self) -> I2C_END_DETECT_INT_RAW_R { - I2C_END_DETECT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_byte_trans_done_int_raw(&self) -> I2C_BYTE_TRANS_DONE_INT_RAW_R { - I2C_BYTE_TRANS_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."] - #[inline(always)] - pub fn i2c_arbitration_lost_int_raw(&self) -> I2C_ARBITRATION_LOST_INT_RAW_R { - I2C_ARBITRATION_LOST_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_mst_txfifo_udf_int_raw(&self) -> I2C_MST_TXFIFO_UDF_INT_RAW_R { - I2C_MST_TXFIFO_UDF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_complete_int_raw(&self) -> I2C_TRANS_COMPLETE_INT_RAW_R { - I2C_TRANS_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."] - #[inline(always)] - pub fn i2c_time_out_int_raw(&self) -> I2C_TIME_OUT_INT_RAW_R { - I2C_TIME_OUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_start_int_raw(&self) -> I2C_TRANS_START_INT_RAW_R { - I2C_TRANS_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."] - #[inline(always)] - pub fn i2c_nack_int_raw(&self) -> I2C_NACK_INT_RAW_R { - I2C_NACK_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_ovf_int_raw(&self) -> I2C_TXFIFO_OVF_INT_RAW_R { - I2C_TXFIFO_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_udf_int_raw(&self) -> I2C_RXFIFO_UDF_INT_RAW_R { - I2C_RXFIFO_UDF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_st_to_int_raw(&self) -> I2C_SCL_ST_TO_INT_RAW_R { - I2C_SCL_ST_TO_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_main_st_to_int_raw(&self) -> I2C_SCL_MAIN_ST_TO_INT_RAW_R { - I2C_SCL_MAIN_ST_TO_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - The raw interrupt bit for I2C_DET_START_INT interrupt."] - #[inline(always)] - pub fn i2c_det_start_int_raw(&self) -> I2C_DET_START_INT_RAW_R { - I2C_DET_START_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_INT_RAW") - .field("i2c_rxfifo_wm_int_raw", &self.i2c_rxfifo_wm_int_raw()) - .field("i2c_txfifo_wm_int_raw", &self.i2c_txfifo_wm_int_raw()) - .field("i2c_rxfifo_ovf_int_raw", &self.i2c_rxfifo_ovf_int_raw()) - .field("i2c_end_detect_int_raw", &self.i2c_end_detect_int_raw()) - .field( - "i2c_byte_trans_done_int_raw", - &self.i2c_byte_trans_done_int_raw(), - ) - .field( - "i2c_arbitration_lost_int_raw", - &self.i2c_arbitration_lost_int_raw(), - ) - .field( - "i2c_mst_txfifo_udf_int_raw", - &self.i2c_mst_txfifo_udf_int_raw(), - ) - .field( - "i2c_trans_complete_int_raw", - &self.i2c_trans_complete_int_raw(), - ) - .field("i2c_time_out_int_raw", &self.i2c_time_out_int_raw()) - .field("i2c_trans_start_int_raw", &self.i2c_trans_start_int_raw()) - .field("i2c_nack_int_raw", &self.i2c_nack_int_raw()) - .field("i2c_txfifo_ovf_int_raw", &self.i2c_txfifo_ovf_int_raw()) - .field("i2c_rxfifo_udf_int_raw", &self.i2c_rxfifo_udf_int_raw()) - .field("i2c_scl_st_to_int_raw", &self.i2c_scl_st_to_int_raw()) - .field( - "i2c_scl_main_st_to_int_raw", - &self.i2c_scl_main_st_to_int_raw(), - ) - .field("i2c_det_start_int_raw", &self.i2c_det_start_int_raw()) - .finish() - } -} -#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_INT_RAW_SPEC; -impl crate::RegisterSpec for I2C_INT_RAW_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_int_raw::R`](R) reader structure"] -impl crate::Readable for I2C_INT_RAW_SPEC {} -#[doc = "`reset()` method sets I2C_INT_RAW to value 0x02"] -impl crate::Resettable for I2C_INT_RAW_SPEC { - const RESET_VALUE: u32 = 0x02; -} diff --git a/esp32c5/src/lp_i2c0/i2c_int_status.rs b/esp32c5/src/lp_i2c0/i2c_int_status.rs deleted file mode 100644 index 21e1cbefbf..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_int_status.rs +++ /dev/null @@ -1,163 +0,0 @@ -#[doc = "Register `I2C_INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_RXFIFO_WM_INT_ST` reader - The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt."] -pub type I2C_RXFIFO_WM_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_WM_INT_ST` reader - The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt."] -pub type I2C_TXFIFO_WM_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_OVF_INT_ST` reader - The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt."] -pub type I2C_RXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_END_DETECT_INT_ST` reader - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_END_DETECT_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_BYTE_TRANS_DONE_INT_ST` reader - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] -pub type I2C_BYTE_TRANS_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_ARBITRATION_LOST_INT_ST` reader - The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt."] -pub type I2C_ARBITRATION_LOST_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_MST_TXFIFO_UDF_INT_ST` reader - The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_MST_TXFIFO_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_COMPLETE_INT_ST` reader - The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt."] -pub type I2C_TRANS_COMPLETE_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_TIME_OUT_INT_ST` reader - The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt."] -pub type I2C_TIME_OUT_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_TRANS_START_INT_ST` reader - The masked interrupt status bit for the I2C_TRANS_START_INT interrupt."] -pub type I2C_TRANS_START_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_NACK_INT_ST` reader - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt."] -pub type I2C_NACK_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_TXFIFO_OVF_INT_ST` reader - The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt."] -pub type I2C_TXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_UDF_INT_ST` reader - The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt."] -pub type I2C_RXFIFO_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_SCL_ST_TO_INT_ST` reader - The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt."] -pub type I2C_SCL_ST_TO_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_INT_ST` reader - The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type I2C_SCL_MAIN_ST_TO_INT_ST_R = crate::BitReader; -#[doc = "Field `I2C_DET_START_INT_ST` reader - The masked interrupt status bit for I2C_DET_START_INT interrupt."] -pub type I2C_DET_START_INT_ST_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_wm_int_st(&self) -> I2C_RXFIFO_WM_INT_ST_R { - I2C_RXFIFO_WM_INT_ST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_wm_int_st(&self) -> I2C_TXFIFO_WM_INT_ST_R { - I2C_TXFIFO_WM_INT_ST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_ovf_int_st(&self) -> I2C_RXFIFO_OVF_INT_ST_R { - I2C_RXFIFO_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_end_detect_int_st(&self) -> I2C_END_DETECT_INT_ST_R { - I2C_END_DETECT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] - #[inline(always)] - pub fn i2c_byte_trans_done_int_st(&self) -> I2C_BYTE_TRANS_DONE_INT_ST_R { - I2C_BYTE_TRANS_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt."] - #[inline(always)] - pub fn i2c_arbitration_lost_int_st(&self) -> I2C_ARBITRATION_LOST_INT_ST_R { - I2C_ARBITRATION_LOST_INT_ST_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_mst_txfifo_udf_int_st(&self) -> I2C_MST_TXFIFO_UDF_INT_ST_R { - I2C_MST_TXFIFO_UDF_INT_ST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_complete_int_st(&self) -> I2C_TRANS_COMPLETE_INT_ST_R { - I2C_TRANS_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt."] - #[inline(always)] - pub fn i2c_time_out_int_st(&self) -> I2C_TIME_OUT_INT_ST_R { - I2C_TIME_OUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - The masked interrupt status bit for the I2C_TRANS_START_INT interrupt."] - #[inline(always)] - pub fn i2c_trans_start_int_st(&self) -> I2C_TRANS_START_INT_ST_R { - I2C_TRANS_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt."] - #[inline(always)] - pub fn i2c_nack_int_st(&self) -> I2C_NACK_INT_ST_R { - I2C_NACK_INT_ST_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt."] - #[inline(always)] - pub fn i2c_txfifo_ovf_int_st(&self) -> I2C_TXFIFO_OVF_INT_ST_R { - I2C_TXFIFO_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt."] - #[inline(always)] - pub fn i2c_rxfifo_udf_int_st(&self) -> I2C_RXFIFO_UDF_INT_ST_R { - I2C_RXFIFO_UDF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_st_to_int_st(&self) -> I2C_SCL_ST_TO_INT_ST_R { - I2C_SCL_ST_TO_INT_ST_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] - #[inline(always)] - pub fn i2c_scl_main_st_to_int_st(&self) -> I2C_SCL_MAIN_ST_TO_INT_ST_R { - I2C_SCL_MAIN_ST_TO_INT_ST_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - The masked interrupt status bit for I2C_DET_START_INT interrupt."] - #[inline(always)] - pub fn i2c_det_start_int_st(&self) -> I2C_DET_START_INT_ST_R { - I2C_DET_START_INT_ST_R::new(((self.bits >> 15) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_INT_STATUS") - .field("i2c_rxfifo_wm_int_st", &self.i2c_rxfifo_wm_int_st()) - .field("i2c_txfifo_wm_int_st", &self.i2c_txfifo_wm_int_st()) - .field("i2c_rxfifo_ovf_int_st", &self.i2c_rxfifo_ovf_int_st()) - .field("i2c_end_detect_int_st", &self.i2c_end_detect_int_st()) - .field( - "i2c_byte_trans_done_int_st", - &self.i2c_byte_trans_done_int_st(), - ) - .field( - "i2c_arbitration_lost_int_st", - &self.i2c_arbitration_lost_int_st(), - ) - .field( - "i2c_mst_txfifo_udf_int_st", - &self.i2c_mst_txfifo_udf_int_st(), - ) - .field( - "i2c_trans_complete_int_st", - &self.i2c_trans_complete_int_st(), - ) - .field("i2c_time_out_int_st", &self.i2c_time_out_int_st()) - .field("i2c_trans_start_int_st", &self.i2c_trans_start_int_st()) - .field("i2c_nack_int_st", &self.i2c_nack_int_st()) - .field("i2c_txfifo_ovf_int_st", &self.i2c_txfifo_ovf_int_st()) - .field("i2c_rxfifo_udf_int_st", &self.i2c_rxfifo_udf_int_st()) - .field("i2c_scl_st_to_int_st", &self.i2c_scl_st_to_int_st()) - .field( - "i2c_scl_main_st_to_int_st", - &self.i2c_scl_main_st_to_int_st(), - ) - .field("i2c_det_start_int_st", &self.i2c_det_start_int_st()) - .finish() - } -} -#[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_INT_STATUS_SPEC; -impl crate::RegisterSpec for I2C_INT_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_int_status::R`](R) reader structure"] -impl crate::Readable for I2C_INT_STATUS_SPEC {} -#[doc = "`reset()` method sets I2C_INT_STATUS to value 0"] -impl crate::Resettable for I2C_INT_STATUS_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_rxfifo_start_addr.rs b/esp32c5/src/lp_i2c0/i2c_rxfifo_start_addr.rs deleted file mode 100644 index b9a13b2503..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_rxfifo_start_addr.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `I2C_RXFIFO_START_ADDR` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_RXFIFO_START_ADDR` reader - This is the I2C rxfifo first address."] -pub type I2C_RXFIFO_START_ADDR_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - This is the I2C rxfifo first address."] - #[inline(always)] - pub fn i2c_rxfifo_start_addr(&self) -> I2C_RXFIFO_START_ADDR_R { - I2C_RXFIFO_START_ADDR_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_RXFIFO_START_ADDR") - .field("i2c_rxfifo_start_addr", &self.i2c_rxfifo_start_addr()) - .finish() - } -} -#[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_RXFIFO_START_ADDR_SPEC; -impl crate::RegisterSpec for I2C_RXFIFO_START_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_rxfifo_start_addr::R`](R) reader structure"] -impl crate::Readable for I2C_RXFIFO_START_ADDR_SPEC {} -#[doc = "`reset()` method sets I2C_RXFIFO_START_ADDR to value 0"] -impl crate::Resettable for I2C_RXFIFO_START_ADDR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_high_period.rs b/esp32c5/src/lp_i2c0/i2c_scl_high_period.rs deleted file mode 100644 index df4b75778d..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_scl_high_period.rs +++ /dev/null @@ -1,60 +0,0 @@ -#[doc = "Register `I2C_SCL_HIGH_PERIOD` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_HIGH_PERIOD` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_HIGH_PERIOD` reader - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] -pub type I2C_SCL_HIGH_PERIOD_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_HIGH_PERIOD` writer - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] -pub type I2C_SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `I2C_SCL_WAIT_HIGH_PERIOD` reader - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] -pub type I2C_SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_WAIT_HIGH_PERIOD` writer - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] -pub type I2C_SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_high_period(&self) -> I2C_SCL_HIGH_PERIOD_R { - I2C_SCL_HIGH_PERIOD_R::new((self.bits & 0x01ff) as u16) - } - #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_wait_high_period(&self) -> I2C_SCL_WAIT_HIGH_PERIOD_R { - I2C_SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 9) & 0x7f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_HIGH_PERIOD") - .field("i2c_scl_high_period", &self.i2c_scl_high_period()) - .field("i2c_scl_wait_high_period", &self.i2c_scl_wait_high_period()) - .finish() - } -} -impl W { - #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_high_period(&mut self) -> I2C_SCL_HIGH_PERIOD_W<'_, I2C_SCL_HIGH_PERIOD_SPEC> { - I2C_SCL_HIGH_PERIOD_W::new(self, 0) - } - #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_wait_high_period( - &mut self, - ) -> I2C_SCL_WAIT_HIGH_PERIOD_W<'_, I2C_SCL_HIGH_PERIOD_SPEC> { - I2C_SCL_WAIT_HIGH_PERIOD_W::new(self, 9) - } -} -#[doc = "Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_high_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_high_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_HIGH_PERIOD_SPEC; -impl crate::RegisterSpec for I2C_SCL_HIGH_PERIOD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_scl_high_period::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_HIGH_PERIOD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_high_period::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_HIGH_PERIOD_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_SCL_HIGH_PERIOD to value 0"] -impl crate::Resettable for I2C_SCL_HIGH_PERIOD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_low_period.rs b/esp32c5/src/lp_i2c0/i2c_scl_low_period.rs deleted file mode 100644 index 09786ea191..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_scl_low_period.rs +++ /dev/null @@ -1,43 +0,0 @@ -#[doc = "Register `I2C_SCL_LOW_PERIOD` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_LOW_PERIOD` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_LOW_PERIOD` reader - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] -pub type I2C_SCL_LOW_PERIOD_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_LOW_PERIOD` writer - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] -pub type I2C_SCL_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -impl R { - #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_low_period(&self) -> I2C_SCL_LOW_PERIOD_R { - I2C_SCL_LOW_PERIOD_R::new((self.bits & 0x01ff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_LOW_PERIOD") - .field("i2c_scl_low_period", &self.i2c_scl_low_period()) - .finish() - } -} -impl W { - #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] - #[inline(always)] - pub fn i2c_scl_low_period(&mut self) -> I2C_SCL_LOW_PERIOD_W<'_, I2C_SCL_LOW_PERIOD_SPEC> { - I2C_SCL_LOW_PERIOD_W::new(self, 0) - } -} -#[doc = "Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_low_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_low_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_LOW_PERIOD_SPEC; -impl crate::RegisterSpec for I2C_SCL_LOW_PERIOD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_scl_low_period::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_LOW_PERIOD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_low_period::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_LOW_PERIOD_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_SCL_LOW_PERIOD to value 0"] -impl crate::Resettable for I2C_SCL_LOW_PERIOD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_main_st_time_out.rs b/esp32c5/src/lp_i2c0/i2c_scl_main_st_time_out.rs deleted file mode 100644 index a887d27fba..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_scl_main_st_time_out.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `I2C_SCL_MAIN_ST_TIME_OUT` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_MAIN_ST_TIME_OUT` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_I2C` reader - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] -pub type I2C_SCL_MAIN_ST_TO_I2C_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_MAIN_ST_TO_I2C` writer - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] -pub type I2C_SCL_MAIN_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] - #[inline(always)] - pub fn i2c_scl_main_st_to_i2c(&self) -> I2C_SCL_MAIN_ST_TO_I2C_R { - I2C_SCL_MAIN_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_MAIN_ST_TIME_OUT") - .field("i2c_scl_main_st_to_i2c", &self.i2c_scl_main_st_to_i2c()) - .finish() - } -} -impl W { - #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] - #[inline(always)] - pub fn i2c_scl_main_st_to_i2c( - &mut self, - ) -> I2C_SCL_MAIN_ST_TO_I2C_W<'_, I2C_SCL_MAIN_ST_TIME_OUT_SPEC> { - I2C_SCL_MAIN_ST_TO_I2C_W::new(self, 0) - } -} -#[doc = "SCL main status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_main_st_time_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_main_st_time_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_MAIN_ST_TIME_OUT_SPEC; -impl crate::RegisterSpec for I2C_SCL_MAIN_ST_TIME_OUT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_scl_main_st_time_out::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_MAIN_ST_TIME_OUT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_main_st_time_out::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_MAIN_ST_TIME_OUT_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_SCL_MAIN_ST_TIME_OUT to value 0x10"] -impl crate::Resettable for I2C_SCL_MAIN_ST_TIME_OUT_SPEC { - const RESET_VALUE: u32 = 0x10; -} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_sp_conf.rs b/esp32c5/src/lp_i2c0/i2c_scl_sp_conf.rs deleted file mode 100644 index d5438f0201..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_scl_sp_conf.rs +++ /dev/null @@ -1,88 +0,0 @@ -#[doc = "Register `I2C_SCL_SP_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_SP_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_RST_SLV_EN` reader - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] -pub type I2C_SCL_RST_SLV_EN_R = crate::BitReader; -#[doc = "Field `I2C_SCL_RST_SLV_EN` writer - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] -pub type I2C_SCL_RST_SLV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SCL_RST_SLV_NUM` reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] -pub type I2C_SCL_RST_SLV_NUM_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_RST_SLV_NUM` writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] -pub type I2C_SCL_RST_SLV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `I2C_SCL_PD_EN` reader - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] -pub type I2C_SCL_PD_EN_R = crate::BitReader; -#[doc = "Field `I2C_SCL_PD_EN` writer - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] -pub type I2C_SCL_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2C_SDA_PD_EN` reader - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] -pub type I2C_SDA_PD_EN_R = crate::BitReader; -#[doc = "Field `I2C_SDA_PD_EN` writer - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] -pub type I2C_SDA_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] - #[inline(always)] - pub fn i2c_scl_rst_slv_en(&self) -> I2C_SCL_RST_SLV_EN_R { - I2C_SCL_RST_SLV_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] - #[inline(always)] - pub fn i2c_scl_rst_slv_num(&self) -> I2C_SCL_RST_SLV_NUM_R { - I2C_SCL_RST_SLV_NUM_R::new(((self.bits >> 1) & 0x1f) as u8) - } - #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] - #[inline(always)] - pub fn i2c_scl_pd_en(&self) -> I2C_SCL_PD_EN_R { - I2C_SCL_PD_EN_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] - #[inline(always)] - pub fn i2c_sda_pd_en(&self) -> I2C_SDA_PD_EN_R { - I2C_SDA_PD_EN_R::new(((self.bits >> 7) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_SP_CONF") - .field("i2c_scl_rst_slv_en", &self.i2c_scl_rst_slv_en()) - .field("i2c_scl_rst_slv_num", &self.i2c_scl_rst_slv_num()) - .field("i2c_scl_pd_en", &self.i2c_scl_pd_en()) - .field("i2c_sda_pd_en", &self.i2c_sda_pd_en()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] - #[inline(always)] - pub fn i2c_scl_rst_slv_en(&mut self) -> I2C_SCL_RST_SLV_EN_W<'_, I2C_SCL_SP_CONF_SPEC> { - I2C_SCL_RST_SLV_EN_W::new(self, 0) - } - #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] - #[inline(always)] - pub fn i2c_scl_rst_slv_num(&mut self) -> I2C_SCL_RST_SLV_NUM_W<'_, I2C_SCL_SP_CONF_SPEC> { - I2C_SCL_RST_SLV_NUM_W::new(self, 1) - } - #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] - #[inline(always)] - pub fn i2c_scl_pd_en(&mut self) -> I2C_SCL_PD_EN_W<'_, I2C_SCL_SP_CONF_SPEC> { - I2C_SCL_PD_EN_W::new(self, 6) - } - #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] - #[inline(always)] - pub fn i2c_sda_pd_en(&mut self) -> I2C_SDA_PD_EN_W<'_, I2C_SCL_SP_CONF_SPEC> { - I2C_SDA_PD_EN_W::new(self, 7) - } -} -#[doc = "Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_sp_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_sp_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_SP_CONF_SPEC; -impl crate::RegisterSpec for I2C_SCL_SP_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_scl_sp_conf::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_SP_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_sp_conf::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_SP_CONF_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_SCL_SP_CONF to value 0"] -impl crate::Resettable for I2C_SCL_SP_CONF_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_st_time_out.rs b/esp32c5/src/lp_i2c0/i2c_scl_st_time_out.rs deleted file mode 100644 index 94a62aa84a..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_scl_st_time_out.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `I2C_SCL_ST_TIME_OUT` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_ST_TIME_OUT` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_SCL_ST_TO_I2C` reader - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] -pub type I2C_SCL_ST_TO_I2C_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_ST_TO_I2C` writer - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] -pub type I2C_SCL_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] - #[inline(always)] - pub fn i2c_scl_st_to_i2c(&self) -> I2C_SCL_ST_TO_I2C_R { - I2C_SCL_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_ST_TIME_OUT") - .field("i2c_scl_st_to_i2c", &self.i2c_scl_st_to_i2c()) - .finish() - } -} -impl W { - #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] - #[inline(always)] - pub fn i2c_scl_st_to_i2c(&mut self) -> I2C_SCL_ST_TO_I2C_W<'_, I2C_SCL_ST_TIME_OUT_SPEC> { - I2C_SCL_ST_TO_I2C_W::new(self, 0) - } -} -#[doc = "SCL status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_st_time_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_st_time_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_ST_TIME_OUT_SPEC; -impl crate::RegisterSpec for I2C_SCL_ST_TIME_OUT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_scl_st_time_out::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_ST_TIME_OUT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_st_time_out::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_ST_TIME_OUT_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_SCL_ST_TIME_OUT to value 0x10"] -impl crate::Resettable for I2C_SCL_ST_TIME_OUT_SPEC { - const RESET_VALUE: u32 = 0x10; -} diff --git a/esp32c5/src/lp_i2c0/i2c_sr.rs b/esp32c5/src/lp_i2c0/i2c_sr.rs deleted file mode 100644 index 929ec9a71d..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_sr.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `I2C_SR` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_RESP_REC` reader - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] -pub type I2C_RESP_REC_R = crate::BitReader; -#[doc = "Field `I2C_ARB_LOST` reader - When the I2C controller loses control of SCL line, this register changes to 1."] -pub type I2C_ARB_LOST_R = crate::BitReader; -#[doc = "Field `I2C_BUS_BUSY` reader - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."] -pub type I2C_BUS_BUSY_R = crate::BitReader; -#[doc = "Field `I2C_RXFIFO_CNT` reader - This field represents the amount of data needed to be sent."] -pub type I2C_RXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `I2C_TXFIFO_CNT` reader - This field stores the amount of received data in RAM."] -pub type I2C_TXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_MAIN_STATE_LAST` reader - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] -pub type I2C_SCL_MAIN_STATE_LAST_R = crate::FieldReader; -#[doc = "Field `I2C_SCL_STATE_LAST` reader - This field indicates the states of the state machine used to produce SCL.0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] -pub type I2C_SCL_STATE_LAST_R = crate::FieldReader; -impl R { - #[doc = "Bit 0 - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] - #[inline(always)] - pub fn i2c_resp_rec(&self) -> I2C_RESP_REC_R { - I2C_RESP_REC_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - When the I2C controller loses control of SCL line, this register changes to 1."] - #[inline(always)] - pub fn i2c_arb_lost(&self) -> I2C_ARB_LOST_R { - I2C_ARB_LOST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."] - #[inline(always)] - pub fn i2c_bus_busy(&self) -> I2C_BUS_BUSY_R { - I2C_BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 8:12 - This field represents the amount of data needed to be sent."] - #[inline(always)] - pub fn i2c_rxfifo_cnt(&self) -> I2C_RXFIFO_CNT_R { - I2C_RXFIFO_CNT_R::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bits 18:22 - This field stores the amount of received data in RAM."] - #[inline(always)] - pub fn i2c_txfifo_cnt(&self) -> I2C_TXFIFO_CNT_R { - I2C_TXFIFO_CNT_R::new(((self.bits >> 18) & 0x1f) as u8) - } - #[doc = "Bits 24:26 - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] - #[inline(always)] - pub fn i2c_scl_main_state_last(&self) -> I2C_SCL_MAIN_STATE_LAST_R { - I2C_SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bits 28:30 - This field indicates the states of the state machine used to produce SCL.0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] - #[inline(always)] - pub fn i2c_scl_state_last(&self) -> I2C_SCL_STATE_LAST_R { - I2C_SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SR") - .field("i2c_resp_rec", &self.i2c_resp_rec()) - .field("i2c_arb_lost", &self.i2c_arb_lost()) - .field("i2c_bus_busy", &self.i2c_bus_busy()) - .field("i2c_rxfifo_cnt", &self.i2c_rxfifo_cnt()) - .field("i2c_txfifo_cnt", &self.i2c_txfifo_cnt()) - .field("i2c_scl_main_state_last", &self.i2c_scl_main_state_last()) - .field("i2c_scl_state_last", &self.i2c_scl_state_last()) - .finish() - } -} -#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SR_SPEC; -impl crate::RegisterSpec for I2C_SR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_sr::R`](R) reader structure"] -impl crate::Readable for I2C_SR_SPEC {} -#[doc = "`reset()` method sets I2C_SR to value 0"] -impl crate::Resettable for I2C_SR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_to.rs b/esp32c5/src/lp_i2c0/i2c_to.rs deleted file mode 100644 index b4b00092f0..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_to.rs +++ /dev/null @@ -1,60 +0,0 @@ -#[doc = "Register `I2C_TO` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_TO` writer"] -pub type W = crate::W; -#[doc = "Field `I2C_TIME_OUT_VALUE` reader - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] -pub type I2C_TIME_OUT_VALUE_R = crate::FieldReader; -#[doc = "Field `I2C_TIME_OUT_VALUE` writer - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] -pub type I2C_TIME_OUT_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `I2C_TIME_OUT_EN` reader - This is the enable bit for time out control."] -pub type I2C_TIME_OUT_EN_R = crate::BitReader; -#[doc = "Field `I2C_TIME_OUT_EN` writer - This is the enable bit for time out control."] -pub type I2C_TIME_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] - #[inline(always)] - pub fn i2c_time_out_value(&self) -> I2C_TIME_OUT_VALUE_R { - I2C_TIME_OUT_VALUE_R::new((self.bits & 0x1f) as u8) - } - #[doc = "Bit 5 - This is the enable bit for time out control."] - #[inline(always)] - pub fn i2c_time_out_en(&self) -> I2C_TIME_OUT_EN_R { - I2C_TIME_OUT_EN_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_TO") - .field("i2c_time_out_value", &self.i2c_time_out_value()) - .field("i2c_time_out_en", &self.i2c_time_out_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] - #[inline(always)] - pub fn i2c_time_out_value(&mut self) -> I2C_TIME_OUT_VALUE_W<'_, I2C_TO_SPEC> { - I2C_TIME_OUT_VALUE_W::new(self, 0) - } - #[doc = "Bit 5 - This is the enable bit for time out control."] - #[inline(always)] - pub fn i2c_time_out_en(&mut self) -> I2C_TIME_OUT_EN_W<'_, I2C_TO_SPEC> { - I2C_TIME_OUT_EN_W::new(self, 5) - } -} -#[doc = "Setting time out control for receiving data.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_to::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_to::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_TO_SPEC; -impl crate::RegisterSpec for I2C_TO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_to::R`](R) reader structure"] -impl crate::Readable for I2C_TO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_to::W`](W) writer structure"] -impl crate::Writable for I2C_TO_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets I2C_TO to value 0x10"] -impl crate::Resettable for I2C_TO_SPEC { - const RESET_VALUE: u32 = 0x10; -} diff --git a/esp32c5/src/lp_i2c0/i2c_txfifo_start_addr.rs b/esp32c5/src/lp_i2c0/i2c_txfifo_start_addr.rs deleted file mode 100644 index 494a138311..0000000000 --- a/esp32c5/src/lp_i2c0/i2c_txfifo_start_addr.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `I2C_TXFIFO_START_ADDR` reader"] -pub type R = crate::R; -#[doc = "Field `I2C_TXFIFO_START_ADDR` reader - This is the I2C txfifo first address."] -pub type I2C_TXFIFO_START_ADDR_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - This is the I2C txfifo first address."] - #[inline(always)] - pub fn i2c_txfifo_start_addr(&self) -> I2C_TXFIFO_START_ADDR_R { - I2C_TXFIFO_START_ADDR_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_TXFIFO_START_ADDR") - .field("i2c_txfifo_start_addr", &self.i2c_txfifo_start_addr()) - .finish() - } -} -#[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_TXFIFO_START_ADDR_SPEC; -impl crate::RegisterSpec for I2C_TXFIFO_START_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2c_txfifo_start_addr::R`](R) reader structure"] -impl crate::Readable for I2C_TXFIFO_START_ADDR_SPEC {} -#[doc = "`reset()` method sets I2C_TXFIFO_START_ADDR to value 0"] -impl crate::Resettable for I2C_TXFIFO_START_ADDR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/int_clr.rs b/esp32c5/src/lp_i2c0/int_clr.rs new file mode 100644 index 0000000000..d25472fb68 --- /dev/null +++ b/esp32c5/src/lp_i2c0/int_clr.rs @@ -0,0 +1,134 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM` writer - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXFIFO_WM` writer - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `END_DETECT` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ARBITRATION_LOST` writer - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF` writer - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` writer - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TIME_OUT` writer - Set this bit to clear the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANS_START` writer - Set this bit to clear the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NACK` writer - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXFIFO_OVF` writer - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_UDF` writer - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCL_ST_TO` writer - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO` writer - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DET_START` writer - Set this bit to clear I2C_DET_START_INT interrupt."] +pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<'_, INT_CLR_SPEC> { + RXFIFO_WM_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<'_, INT_CLR_SPEC> { + TXFIFO_WM_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<'_, INT_CLR_SPEC> { + RXFIFO_OVF_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect(&mut self) -> END_DETECT_W<'_, INT_CLR_SPEC> { + END_DETECT_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<'_, INT_CLR_SPEC> { + BYTE_TRANS_DONE_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<'_, INT_CLR_SPEC> { + ARBITRATION_LOST_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<'_, INT_CLR_SPEC> { + MST_TXFIFO_UDF_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<'_, INT_CLR_SPEC> { + TRANS_COMPLETE_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out(&mut self) -> TIME_OUT_W<'_, INT_CLR_SPEC> { + TIME_OUT_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start(&mut self) -> TRANS_START_W<'_, INT_CLR_SPEC> { + TRANS_START_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack(&mut self) -> NACK_W<'_, INT_CLR_SPEC> { + NACK_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<'_, INT_CLR_SPEC> { + TXFIFO_OVF_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<'_, INT_CLR_SPEC> { + RXFIFO_UDF_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<'_, INT_CLR_SPEC> { + SCL_ST_TO_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<'_, INT_CLR_SPEC> { + SCL_MAIN_ST_TO_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start(&mut self) -> DET_START_W<'_, INT_CLR_SPEC> { + DET_START_W::new(self, 15) + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/int_ena.rs b/esp32c5/src/lp_i2c0/int_ena.rs new file mode 100644 index 0000000000..b8e6e9d992 --- /dev/null +++ b/esp32c5/src/lp_i2c0/int_ena.rs @@ -0,0 +1,268 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM` reader - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM` writer - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM` reader - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` writer - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF` reader - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` writer - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `END_DETECT` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST` reader - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` writer - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF` reader - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` writer - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` reader - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` writer - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT` reader - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TIME_OUT` writer - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START` reader - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `TRANS_START` writer - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK` reader - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `NACK` writer - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF` reader - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` writer - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF` reader - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` writer - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO` reader - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` writer - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO` reader - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` writer - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START` reader - The interrupt enable bit for I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; +#[doc = "Field `DET_START` writer - The interrupt enable bit for I2C_DET_START_INT interrupt."] +pub type DET_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("rxfifo_wm", &self.rxfifo_wm()) + .field("txfifo_wm", &self.txfifo_wm()) + .field("rxfifo_ovf", &self.rxfifo_ovf()) + .field("end_detect", &self.end_detect()) + .field("byte_trans_done", &self.byte_trans_done()) + .field("arbitration_lost", &self.arbitration_lost()) + .field("mst_txfifo_udf", &self.mst_txfifo_udf()) + .field("trans_complete", &self.trans_complete()) + .field("time_out", &self.time_out()) + .field("trans_start", &self.trans_start()) + .field("nack", &self.nack()) + .field("txfifo_ovf", &self.txfifo_ovf()) + .field("rxfifo_udf", &self.rxfifo_udf()) + .field("scl_st_to", &self.scl_st_to()) + .field("scl_main_st_to", &self.scl_main_st_to()) + .field("det_start", &self.det_start()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<'_, INT_ENA_SPEC> { + RXFIFO_WM_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<'_, INT_ENA_SPEC> { + TXFIFO_WM_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<'_, INT_ENA_SPEC> { + RXFIFO_OVF_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect(&mut self) -> END_DETECT_W<'_, INT_ENA_SPEC> { + END_DETECT_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<'_, INT_ENA_SPEC> { + BYTE_TRANS_DONE_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<'_, INT_ENA_SPEC> { + ARBITRATION_LOST_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<'_, INT_ENA_SPEC> { + MST_TXFIFO_UDF_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<'_, INT_ENA_SPEC> { + TRANS_COMPLETE_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out(&mut self) -> TIME_OUT_W<'_, INT_ENA_SPEC> { + TIME_OUT_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start(&mut self) -> TRANS_START_W<'_, INT_ENA_SPEC> { + TRANS_START_W::new(self, 9) + } + #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack(&mut self) -> NACK_W<'_, INT_ENA_SPEC> { + NACK_W::new(self, 10) + } + #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<'_, INT_ENA_SPEC> { + TXFIFO_OVF_W::new(self, 11) + } + #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<'_, INT_ENA_SPEC> { + RXFIFO_UDF_W::new(self, 12) + } + #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<'_, INT_ENA_SPEC> { + SCL_ST_TO_W::new(self, 13) + } + #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<'_, INT_ENA_SPEC> { + SCL_MAIN_ST_TO_W::new(self, 14) + } + #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start(&mut self) -> DET_START_W<'_, INT_ENA_SPEC> { + DET_START_W::new(self, 15) + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC {} diff --git a/esp32c5/src/lp_i2c0/int_raw.rs b/esp32c5/src/lp_i2c0/int_raw.rs new file mode 100644 index 0000000000..e3ecf8152d --- /dev/null +++ b/esp32c5/src/lp_i2c0/int_raw.rs @@ -0,0 +1,150 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM` reader - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` reader - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` reader - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `END_DETECT` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` reader - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` reader - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TIME_OUT` reader - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TRANS_START` reader - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `NACK` reader - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` reader - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` reader - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` reader - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` reader - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `DET_START` reader - The raw interrupt bit for I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt bit for I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field("rxfifo_wm", &self.rxfifo_wm()) + .field("txfifo_wm", &self.txfifo_wm()) + .field("rxfifo_ovf", &self.rxfifo_ovf()) + .field("end_detect", &self.end_detect()) + .field("byte_trans_done", &self.byte_trans_done()) + .field("arbitration_lost", &self.arbitration_lost()) + .field("mst_txfifo_udf", &self.mst_txfifo_udf()) + .field("trans_complete", &self.trans_complete()) + .field("time_out", &self.time_out()) + .field("trans_start", &self.trans_start()) + .field("nack", &self.nack()) + .field("txfifo_ovf", &self.txfifo_ovf()) + .field("rxfifo_udf", &self.rxfifo_udf()) + .field("scl_st_to", &self.scl_st_to()) + .field("scl_main_st_to", &self.scl_main_st_to()) + .field("det_start", &self.det_start()) + .finish() + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0x02"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/esp32c5/src/lp_i2c0/int_st.rs b/esp32c5/src/lp_i2c0/int_st.rs new file mode 100644 index 0000000000..005fc03c6d --- /dev/null +++ b/esp32c5/src/lp_i2c0/int_st.rs @@ -0,0 +1,148 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM` reader - The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` reader - The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` reader - The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `END_DETECT` reader - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` reader - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` reader - The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` reader - The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TIME_OUT` reader - The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TRANS_START` reader - The masked interrupt status bit for the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `NACK` reader - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` reader - The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` reader - The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` reader - The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` reader - The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `DET_START` reader - The masked interrupt status bit for I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status bit for the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status bit for the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status bit for I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("rxfifo_wm", &self.rxfifo_wm()) + .field("txfifo_wm", &self.txfifo_wm()) + .field("rxfifo_ovf", &self.rxfifo_ovf()) + .field("end_detect", &self.end_detect()) + .field("byte_trans_done", &self.byte_trans_done()) + .field("arbitration_lost", &self.arbitration_lost()) + .field("mst_txfifo_udf", &self.mst_txfifo_udf()) + .field("trans_complete", &self.trans_complete()) + .field("time_out", &self.time_out()) + .field("trans_start", &self.trans_start()) + .field("nack", &self.nack()) + .field("txfifo_ovf", &self.txfifo_ovf()) + .field("rxfifo_udf", &self.rxfifo_udf()) + .field("scl_st_to", &self.scl_st_to()) + .field("scl_main_st_to", &self.scl_main_st_to()) + .field("det_start", &self.det_start()) + .finish() + } +} +#[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC {} diff --git a/esp32c5/src/lp_i2c0/rxfifo_start_addr.rs b/esp32c5/src/lp_i2c0/rxfifo_start_addr.rs new file mode 100644 index 0000000000..e81f18ee82 --- /dev/null +++ b/esp32c5/src/lp_i2c0/rxfifo_start_addr.rs @@ -0,0 +1,28 @@ +#[doc = "Register `RXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_START_ADDR` reader - This is the I2C rxfifo first address."] +pub type RXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This is the I2C rxfifo first address."] + #[inline(always)] + pub fn rxfifo_start_addr(&self) -> RXFIFO_START_ADDR_R { + RXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXFIFO_START_ADDR") + .field("rxfifo_start_addr", &self.rxfifo_start_addr()) + .finish() + } +} +#[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for RXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets RXFIFO_START_ADDR to value 0"] +impl crate::Resettable for RXFIFO_START_ADDR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/scl_high_period.rs b/esp32c5/src/lp_i2c0/scl_high_period.rs new file mode 100644 index 0000000000..99a341c312 --- /dev/null +++ b/esp32c5/src/lp_i2c0/scl_high_period.rs @@ -0,0 +1,58 @@ +#[doc = "Register `SCL_HIGH_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_HIGH_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_HIGH_PERIOD` reader - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] +pub type SCL_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_HIGH_PERIOD` writer - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] +pub type SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` reader - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] +pub type SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` writer - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] +pub type SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_high_period(&self) -> SCL_HIGH_PERIOD_R { + SCL_HIGH_PERIOD_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_wait_high_period(&self) -> SCL_WAIT_HIGH_PERIOD_R { + SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_HIGH_PERIOD") + .field("scl_high_period", &self.scl_high_period()) + .field("scl_wait_high_period", &self.scl_wait_high_period()) + .finish() + } +} +impl W { + #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<'_, SCL_HIGH_PERIOD_SPEC> { + SCL_HIGH_PERIOD_W::new(self, 0) + } + #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W<'_, SCL_HIGH_PERIOD_SPEC> { + SCL_WAIT_HIGH_PERIOD_W::new(self, 9) + } +} +#[doc = "Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_HIGH_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_HIGH_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_high_period::R`](R) reader structure"] +impl crate::Readable for SCL_HIGH_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_high_period::W`](W) writer structure"] +impl crate::Writable for SCL_HIGH_PERIOD_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCL_HIGH_PERIOD to value 0"] +impl crate::Resettable for SCL_HIGH_PERIOD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/scl_low_period.rs b/esp32c5/src/lp_i2c0/scl_low_period.rs new file mode 100644 index 0000000000..c4159b9346 --- /dev/null +++ b/esp32c5/src/lp_i2c0/scl_low_period.rs @@ -0,0 +1,43 @@ +#[doc = "Register `SCL_LOW_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_LOW_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_LOW_PERIOD` reader - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] +pub type SCL_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_LOW_PERIOD` writer - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] +pub type SCL_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_low_period(&self) -> SCL_LOW_PERIOD_R { + SCL_LOW_PERIOD_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_LOW_PERIOD") + .field("scl_low_period", &self.scl_low_period()) + .finish() + } +} +impl W { + #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."] + #[inline(always)] + pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<'_, SCL_LOW_PERIOD_SPEC> { + SCL_LOW_PERIOD_W::new(self, 0) + } +} +#[doc = "Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_low_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_low_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_LOW_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_LOW_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_low_period::R`](R) reader structure"] +impl crate::Readable for SCL_LOW_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_low_period::W`](W) writer structure"] +impl crate::Writable for SCL_LOW_PERIOD_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCL_LOW_PERIOD to value 0"] +impl crate::Resettable for SCL_LOW_PERIOD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/scl_main_st_time_out.rs b/esp32c5/src/lp_i2c0/scl_main_st_time_out.rs new file mode 100644 index 0000000000..6a9419f732 --- /dev/null +++ b/esp32c5/src/lp_i2c0/scl_main_st_time_out.rs @@ -0,0 +1,45 @@ +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` reader - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] +pub type SCL_MAIN_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` writer - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] +pub type SCL_MAIN_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] + #[inline(always)] + pub fn scl_main_st_to_i2c(&self) -> SCL_MAIN_ST_TO_I2C_R { + SCL_MAIN_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_MAIN_ST_TIME_OUT") + .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"] + #[inline(always)] + pub fn scl_main_st_to_i2c(&mut self) -> SCL_MAIN_ST_TO_I2C_W<'_, SCL_MAIN_ST_TIME_OUT_SPEC> { + SCL_MAIN_ST_TO_I2C_W::new(self, 0) + } +} +#[doc = "SCL main status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_main_st_time_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_MAIN_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_MAIN_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_main_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_MAIN_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_main_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_MAIN_ST_TIME_OUT_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCL_MAIN_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_MAIN_ST_TIME_OUT_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_rstart_setup.rs b/esp32c5/src/lp_i2c0/scl_rstart_setup.rs similarity index 56% rename from esp32c5/src/lp_i2c0/i2c_scl_rstart_setup.rs rename to esp32c5/src/lp_i2c0/scl_rstart_setup.rs index faa6a57fc2..10b0484176 100644 --- a/esp32c5/src/lp_i2c0/i2c_scl_rstart_setup.rs +++ b/esp32c5/src/lp_i2c0/scl_rstart_setup.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SCL_RSTART_SETUP` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_RSTART_SETUP` writer"] -pub type W = crate::W; +#[doc = "Register `SCL_RSTART_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_RSTART_SETUP` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure the time between the positiveedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure the time between the positiveedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_RSTART_SETUP") + f.debug_struct("SCL_RSTART_SETUP") .field("time", &self.time()) .finish() } @@ -24,22 +24,22 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure the time between the positiveedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SCL_RSTART_SETUP_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SCL_RSTART_SETUP_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_rstart_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_rstart_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_RSTART_SETUP_SPEC; -impl crate::RegisterSpec for I2C_SCL_RSTART_SETUP_SPEC { +#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_rstart_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_rstart_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_RSTART_SETUP_SPEC; +impl crate::RegisterSpec for SCL_RSTART_SETUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_scl_rstart_setup::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_RSTART_SETUP_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_rstart_setup::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_RSTART_SETUP_SPEC { +#[doc = "`read()` method returns [`scl_rstart_setup::R`](R) reader structure"] +impl crate::Readable for SCL_RSTART_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_rstart_setup::W`](W) writer structure"] +impl crate::Writable for SCL_RSTART_SETUP_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SCL_RSTART_SETUP to value 0x08"] -impl crate::Resettable for I2C_SCL_RSTART_SETUP_SPEC { +#[doc = "`reset()` method sets SCL_RSTART_SETUP to value 0x08"] +impl crate::Resettable for SCL_RSTART_SETUP_SPEC { const RESET_VALUE: u32 = 0x08; } diff --git a/esp32c5/src/lp_i2c0/scl_sp_conf.rs b/esp32c5/src/lp_i2c0/scl_sp_conf.rs new file mode 100644 index 0000000000..eeeae0461b --- /dev/null +++ b/esp32c5/src/lp_i2c0/scl_sp_conf.rs @@ -0,0 +1,88 @@ +#[doc = "Register `SCL_SP_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_SP_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_RST_SLV_EN` reader - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_R = crate::BitReader; +#[doc = "Field `SCL_RST_SLV_EN` writer - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_RST_SLV_NUM` reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] +pub type SCL_RST_SLV_NUM_R = crate::FieldReader; +#[doc = "Field `SCL_RST_SLV_NUM` writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] +pub type SCL_RST_SLV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SCL_PD_EN` reader - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] +pub type SCL_PD_EN_R = crate::BitReader; +#[doc = "Field `SCL_PD_EN` writer - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] +pub type SCL_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_PD_EN` reader - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] +pub type SDA_PD_EN_R = crate::BitReader; +#[doc = "Field `SDA_PD_EN` writer - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] +pub type SDA_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + pub fn scl_rst_slv_en(&self) -> SCL_RST_SLV_EN_R { + SCL_RST_SLV_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] + #[inline(always)] + pub fn scl_rst_slv_num(&self) -> SCL_RST_SLV_NUM_R { + SCL_RST_SLV_NUM_R::new(((self.bits >> 1) & 0x1f) as u8) + } + #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] + #[inline(always)] + pub fn scl_pd_en(&self) -> SCL_PD_EN_R { + SCL_PD_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] + #[inline(always)] + pub fn sda_pd_en(&self) -> SDA_PD_EN_R { + SDA_PD_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_SP_CONF") + .field("scl_rst_slv_en", &self.scl_rst_slv_en()) + .field("scl_rst_slv_num", &self.scl_rst_slv_num()) + .field("scl_pd_en", &self.scl_pd_en()) + .field("sda_pd_en", &self.sda_pd_en()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W<'_, SCL_SP_CONF_SPEC> { + SCL_RST_SLV_EN_W::new(self, 0) + } + #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."] + #[inline(always)] + pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W<'_, SCL_SP_CONF_SPEC> { + SCL_RST_SLV_NUM_W::new(self, 1) + } + #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."] + #[inline(always)] + pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W<'_, SCL_SP_CONF_SPEC> { + SCL_PD_EN_W::new(self, 6) + } + #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."] + #[inline(always)] + pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W<'_, SCL_SP_CONF_SPEC> { + SDA_PD_EN_W::new(self, 7) + } +} +#[doc = "Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_sp_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_sp_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_SP_CONF_SPEC; +impl crate::RegisterSpec for SCL_SP_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_sp_conf::R`](R) reader structure"] +impl crate::Readable for SCL_SP_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_sp_conf::W`](W) writer structure"] +impl crate::Writable for SCL_SP_CONF_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCL_SP_CONF to value 0"] +impl crate::Resettable for SCL_SP_CONF_SPEC {} diff --git a/esp32c5/src/lp_i2c0/scl_st_time_out.rs b/esp32c5/src/lp_i2c0/scl_st_time_out.rs new file mode 100644 index 0000000000..f850a0a087 --- /dev/null +++ b/esp32c5/src/lp_i2c0/scl_st_time_out.rs @@ -0,0 +1,45 @@ +#[doc = "Register `SCL_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_ST_TO_I2C` reader - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] +pub type SCL_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_ST_TO_I2C` writer - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] +pub type SCL_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] + #[inline(always)] + pub fn scl_st_to_i2c(&self) -> SCL_ST_TO_I2C_R { + SCL_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_ST_TIME_OUT") + .field("scl_st_to_i2c", &self.scl_st_to_i2c()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"] + #[inline(always)] + pub fn scl_st_to_i2c(&mut self) -> SCL_ST_TO_I2C_W<'_, SCL_ST_TIME_OUT_SPEC> { + SCL_ST_TO_I2C_W::new(self, 0) + } +} +#[doc = "SCL status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_st_time_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_st_time_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_ST_TIME_OUT_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCL_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_ST_TIME_OUT_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/esp32c5/src/lp_i2c0/i2c_scl_start_hold.rs b/esp32c5/src/lp_i2c0/scl_start_hold.rs similarity index 56% rename from esp32c5/src/lp_i2c0/i2c_scl_start_hold.rs rename to esp32c5/src/lp_i2c0/scl_start_hold.rs index 9fc6fbdf76..22d9e82bcf 100644 --- a/esp32c5/src/lp_i2c0/i2c_scl_start_hold.rs +++ b/esp32c5/src/lp_i2c0/scl_start_hold.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SCL_START_HOLD` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_START_HOLD` writer"] -pub type W = crate::W; +#[doc = "Register `SCL_START_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_START_HOLD` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure the time between the negative edgeof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure the time between the negative edgeof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_START_HOLD") + f.debug_struct("SCL_START_HOLD") .field("time", &self.time()) .finish() } @@ -24,22 +24,22 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure the time between the negative edgeof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SCL_START_HOLD_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SCL_START_HOLD_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_start_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_start_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_START_HOLD_SPEC; -impl crate::RegisterSpec for I2C_SCL_START_HOLD_SPEC { +#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_start_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_start_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_START_HOLD_SPEC; +impl crate::RegisterSpec for SCL_START_HOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_scl_start_hold::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_START_HOLD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_start_hold::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_START_HOLD_SPEC { +#[doc = "`read()` method returns [`scl_start_hold::R`](R) reader structure"] +impl crate::Readable for SCL_START_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_start_hold::W`](W) writer structure"] +impl crate::Writable for SCL_START_HOLD_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SCL_START_HOLD to value 0x08"] -impl crate::Resettable for I2C_SCL_START_HOLD_SPEC { +#[doc = "`reset()` method sets SCL_START_HOLD to value 0x08"] +impl crate::Resettable for SCL_START_HOLD_SPEC { const RESET_VALUE: u32 = 0x08; } diff --git a/esp32c5/src/lp_i2c0/i2c_scl_stop_hold.rs b/esp32c5/src/lp_i2c0/scl_stop_hold.rs similarity index 53% rename from esp32c5/src/lp_i2c0/i2c_scl_stop_hold.rs rename to esp32c5/src/lp_i2c0/scl_stop_hold.rs index 13938f3b5c..a9a5a70639 100644 --- a/esp32c5/src/lp_i2c0/i2c_scl_stop_hold.rs +++ b/esp32c5/src/lp_i2c0/scl_stop_hold.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SCL_STOP_HOLD` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_STOP_HOLD` writer"] -pub type W = crate::W; +#[doc = "Register `SCL_STOP_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_HOLD` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure the delay after the STOP condition,in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure the delay after the STOP condition,in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_STOP_HOLD") + f.debug_struct("SCL_STOP_HOLD") .field("time", &self.time()) .finish() } @@ -24,22 +24,22 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition,in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SCL_STOP_HOLD_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SCL_STOP_HOLD_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_stop_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_stop_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_STOP_HOLD_SPEC; -impl crate::RegisterSpec for I2C_SCL_STOP_HOLD_SPEC { +#[doc = "Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_HOLD_SPEC; +impl crate::RegisterSpec for SCL_STOP_HOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_scl_stop_hold::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_STOP_HOLD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_stop_hold::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_STOP_HOLD_SPEC { +#[doc = "`read()` method returns [`scl_stop_hold::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_hold::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_HOLD_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SCL_STOP_HOLD to value 0x08"] -impl crate::Resettable for I2C_SCL_STOP_HOLD_SPEC { +#[doc = "`reset()` method sets SCL_STOP_HOLD to value 0x08"] +impl crate::Resettable for SCL_STOP_HOLD_SPEC { const RESET_VALUE: u32 = 0x08; } diff --git a/esp32c5/src/lp_i2c0/i2c_scl_stop_setup.rs b/esp32c5/src/lp_i2c0/scl_stop_setup.rs similarity index 55% rename from esp32c5/src/lp_i2c0/i2c_scl_stop_setup.rs rename to esp32c5/src/lp_i2c0/scl_stop_setup.rs index fedfea7291..0cdff8e0e7 100644 --- a/esp32c5/src/lp_i2c0/i2c_scl_stop_setup.rs +++ b/esp32c5/src/lp_i2c0/scl_stop_setup.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SCL_STOP_SETUP` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SCL_STOP_SETUP` writer"] -pub type W = crate::W; +#[doc = "Register `SCL_STOP_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_SETUP` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure the time between the positive edgeof SCL and the positive edge of SDA, in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure the time between the positive edgeof SCL and the positive edge of SDA, in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SCL_STOP_SETUP") + f.debug_struct("SCL_STOP_SETUP") .field("time", &self.time()) .finish() } @@ -24,22 +24,22 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure the time between the positive edgeof SCL and the positive edge of SDA, in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SCL_STOP_SETUP_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SCL_STOP_SETUP_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_stop_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_stop_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SCL_STOP_SETUP_SPEC; -impl crate::RegisterSpec for I2C_SCL_STOP_SETUP_SPEC { +#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_SETUP_SPEC; +impl crate::RegisterSpec for SCL_STOP_SETUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_scl_stop_setup::R`](R) reader structure"] -impl crate::Readable for I2C_SCL_STOP_SETUP_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_scl_stop_setup::W`](W) writer structure"] -impl crate::Writable for I2C_SCL_STOP_SETUP_SPEC { +#[doc = "`read()` method returns [`scl_stop_setup::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_setup::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_SETUP_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SCL_STOP_SETUP to value 0x08"] -impl crate::Resettable for I2C_SCL_STOP_SETUP_SPEC { +#[doc = "`reset()` method sets SCL_STOP_SETUP to value 0x08"] +impl crate::Resettable for SCL_STOP_SETUP_SPEC { const RESET_VALUE: u32 = 0x08; } diff --git a/esp32c5/src/lp_i2c0/i2c_sda_hold.rs b/esp32c5/src/lp_i2c0/sda_hold.rs similarity index 53% rename from esp32c5/src/lp_i2c0/i2c_sda_hold.rs rename to esp32c5/src/lp_i2c0/sda_hold.rs index a2e9dec0a0..c008af6b8b 100644 --- a/esp32c5/src/lp_i2c0/i2c_sda_hold.rs +++ b/esp32c5/src/lp_i2c0/sda_hold.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SDA_HOLD` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SDA_HOLD` writer"] -pub type W = crate::W; +#[doc = "Register `SDA_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_HOLD` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure the time to hold the data after the negativeedge of SCL, in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure the time to hold the data after the negativeedge of SCL, in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SDA_HOLD") + f.debug_struct("SDA_HOLD") .field("time", &self.time()) .finish() } @@ -24,20 +24,20 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negativeedge of SCL, in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SDA_HOLD_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SDA_HOLD_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SDA_HOLD_SPEC; -impl crate::RegisterSpec for I2C_SDA_HOLD_SPEC { +#[doc = "Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_HOLD_SPEC; +impl crate::RegisterSpec for SDA_HOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_sda_hold::R`](R) reader structure"] -impl crate::Readable for I2C_SDA_HOLD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_sda_hold::W`](W) writer structure"] -impl crate::Writable for I2C_SDA_HOLD_SPEC { +#[doc = "`read()` method returns [`sda_hold::R`](R) reader structure"] +impl crate::Readable for SDA_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_hold::W`](W) writer structure"] +impl crate::Writable for SDA_HOLD_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SDA_HOLD to value 0"] -impl crate::Resettable for I2C_SDA_HOLD_SPEC {} +#[doc = "`reset()` method sets SDA_HOLD to value 0"] +impl crate::Resettable for SDA_HOLD_SPEC {} diff --git a/esp32c5/src/lp_i2c0/i2c_sda_sample.rs b/esp32c5/src/lp_i2c0/sda_sample.rs similarity index 50% rename from esp32c5/src/lp_i2c0/i2c_sda_sample.rs rename to esp32c5/src/lp_i2c0/sda_sample.rs index e26afb0264..0f2277203a 100644 --- a/esp32c5/src/lp_i2c0/i2c_sda_sample.rs +++ b/esp32c5/src/lp_i2c0/sda_sample.rs @@ -1,7 +1,7 @@ -#[doc = "Register `I2C_SDA_SAMPLE` reader"] -pub type R = crate::R; -#[doc = "Register `I2C_SDA_SAMPLE` writer"] -pub type W = crate::W; +#[doc = "Register `SDA_SAMPLE` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_SAMPLE` writer"] +pub type W = crate::W; #[doc = "Field `TIME` reader - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."] pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."] @@ -16,7 +16,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C_SDA_SAMPLE") + f.debug_struct("SDA_SAMPLE") .field("time", &self.time()) .finish() } @@ -24,20 +24,20 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."] #[inline(always)] - pub fn time(&mut self) -> TIME_W<'_, I2C_SDA_SAMPLE_SPEC> { + pub fn time(&mut self) -> TIME_W<'_, SDA_SAMPLE_SPEC> { TIME_W::new(self, 0) } } -#[doc = "Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sda_sample::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sda_sample::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2C_SDA_SAMPLE_SPEC; -impl crate::RegisterSpec for I2C_SDA_SAMPLE_SPEC { +#[doc = "Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_sample::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_sample::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_SAMPLE_SPEC; +impl crate::RegisterSpec for SDA_SAMPLE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`i2c_sda_sample::R`](R) reader structure"] -impl crate::Readable for I2C_SDA_SAMPLE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2c_sda_sample::W`](W) writer structure"] -impl crate::Writable for I2C_SDA_SAMPLE_SPEC { +#[doc = "`read()` method returns [`sda_sample::R`](R) reader structure"] +impl crate::Readable for SDA_SAMPLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_sample::W`](W) writer structure"] +impl crate::Writable for SDA_SAMPLE_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets I2C_SDA_SAMPLE to value 0"] -impl crate::Resettable for I2C_SDA_SAMPLE_SPEC {} +#[doc = "`reset()` method sets SDA_SAMPLE to value 0"] +impl crate::Resettable for SDA_SAMPLE_SPEC {} diff --git a/esp32c5/src/lp_i2c0/sr.rs b/esp32c5/src/lp_i2c0/sr.rs new file mode 100644 index 0000000000..8d71ec6ad1 --- /dev/null +++ b/esp32c5/src/lp_i2c0/sr.rs @@ -0,0 +1,76 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Field `RESP_REC` reader - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] +pub type RESP_REC_R = crate::BitReader; +#[doc = "Field `ARB_LOST` reader - When the I2C controller loses control of SCL line, this register changes to 1."] +pub type ARB_LOST_R = crate::BitReader; +#[doc = "Field `BUS_BUSY` reader - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."] +pub type BUS_BUSY_R = crate::BitReader; +#[doc = "Field `RXFIFO_CNT` reader - This field represents the amount of data needed to be sent."] +pub type RXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `TXFIFO_CNT` reader - This field stores the amount of received data in RAM."] +pub type TXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_STATE_LAST` reader - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] +pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader; +#[doc = "Field `SCL_STATE_LAST` reader - This field indicates the states of the state machine used to produce SCL.0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] +pub type SCL_STATE_LAST_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] + #[inline(always)] + pub fn resp_rec(&self) -> RESP_REC_R { + RESP_REC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - When the I2C controller loses control of SCL line, this register changes to 1."] + #[inline(always)] + pub fn arb_lost(&self) -> ARB_LOST_R { + ARB_LOST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."] + #[inline(always)] + pub fn bus_busy(&self) -> BUS_BUSY_R { + BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:12 - This field represents the amount of data needed to be sent."] + #[inline(always)] + pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { + RXFIFO_CNT_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - This field stores the amount of received data in RAM."] + #[inline(always)] + pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { + TXFIFO_CNT_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 24:26 - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] + #[inline(always)] + pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R { + SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 28:30 - This field indicates the states of the state machine used to produce SCL.0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] + #[inline(always)] + pub fn scl_state_last(&self) -> SCL_STATE_LAST_R { + SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR") + .field("resp_rec", &self.resp_rec()) + .field("arb_lost", &self.arb_lost()) + .field("bus_busy", &self.bus_busy()) + .field("rxfifo_cnt", &self.rxfifo_cnt()) + .field("txfifo_cnt", &self.txfifo_cnt()) + .field("scl_main_state_last", &self.scl_main_state_last()) + .field("scl_state_last", &self.scl_state_last()) + .finish() + } +} +#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_SPEC; +impl crate::RegisterSpec for SR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} +#[doc = "`reset()` method sets SR to value 0"] +impl crate::Resettable for SR_SPEC {} diff --git a/esp32c5/src/lp_i2c0/to.rs b/esp32c5/src/lp_i2c0/to.rs new file mode 100644 index 0000000000..c4f7206bad --- /dev/null +++ b/esp32c5/src/lp_i2c0/to.rs @@ -0,0 +1,60 @@ +#[doc = "Register `TO` reader"] +pub type R = crate::R; +#[doc = "Register `TO` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_OUT_VALUE` reader - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] +pub type TIME_OUT_VALUE_R = crate::FieldReader; +#[doc = "Field `TIME_OUT_VALUE` writer - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] +pub type TIME_OUT_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TIME_OUT_EN` reader - This is the enable bit for time out control."] +pub type TIME_OUT_EN_R = crate::BitReader; +#[doc = "Field `TIME_OUT_EN` writer - This is the enable bit for time out control."] +pub type TIME_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] + #[inline(always)] + pub fn time_out_value(&self) -> TIME_OUT_VALUE_R { + TIME_OUT_VALUE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - This is the enable bit for time out control."] + #[inline(always)] + pub fn time_out_en(&self) -> TIME_OUT_EN_R { + TIME_OUT_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TO") + .field("time_out_value", &self.time_out_value()) + .field("time_out_en", &self.time_out_en()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APBclock cycles."] + #[inline(always)] + pub fn time_out_value(&mut self) -> TIME_OUT_VALUE_W<'_, TO_SPEC> { + TIME_OUT_VALUE_W::new(self, 0) + } + #[doc = "Bit 5 - This is the enable bit for time out control."] + #[inline(always)] + pub fn time_out_en(&mut self) -> TIME_OUT_EN_W<'_, TO_SPEC> { + TIME_OUT_EN_W::new(self, 5) + } +} +#[doc = "Setting time out control for receiving data.\n\nYou can [`read`](crate::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TO_SPEC; +impl crate::RegisterSpec for TO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`to::R`](R) reader structure"] +impl crate::Readable for TO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"] +impl crate::Writable for TO_SPEC { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TO to value 0x10"] +impl crate::Resettable for TO_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/esp32c5/src/lp_i2c0/txfifo_start_addr.rs b/esp32c5/src/lp_i2c0/txfifo_start_addr.rs new file mode 100644 index 0000000000..8a1297655c --- /dev/null +++ b/esp32c5/src/lp_i2c0/txfifo_start_addr.rs @@ -0,0 +1,28 @@ +#[doc = "Register `TXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `TXFIFO_START_ADDR` reader - This is the I2C txfifo first address."] +pub type TXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This is the I2C txfifo first address."] + #[inline(always)] + pub fn txfifo_start_addr(&self) -> TXFIFO_START_ADDR_R { + TXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXFIFO_START_ADDR") + .field("txfifo_start_addr", &self.txfifo_start_addr()) + .finish() + } +} +#[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for TXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets TXFIFO_START_ADDR to value 0"] +impl crate::Resettable for TXFIFO_START_ADDR_SPEC {}