diff --git a/common_patches/mcpwm.yaml b/common_patches/mcpwm.yaml
new file mode 100644
index 0000000000..7a6fa52480
--- /dev/null
+++ b/common_patches/mcpwm.yaml
@@ -0,0 +1,26 @@
+CAP_STATUS:
+  _array:
+    CAP?_EDGE:
+      description: Describes the last captured edge on channel%s.
+  CAP?_EDGE:
+    Rising: [0, "Rising edge"]
+    Falling: [1, "Falling edge"]
+
+CAP_CH?_CFG:
+  _modify:
+    CAP?_MODE:
+      description: Describes which edges to trigger a capture event
+  CAP?_MODE:
+    None: [0, "Capture nothing"]
+    FallingEdge: [1, "Capture falling edges"]
+    RisingEdge: [2, "Capture rising edges"]
+    AnyEdge: [3, "Capture any edges"]
+
+TIMER_SYNCI_CFG:
+  _array:
+    TIMER?_SYNCISEL: {}
+    EXTERNAL_SYNCI?_INVERT: {}
+
+OPERATOR_TIMERSEL:
+  _array:
+    OPERATOR?_TIMERSEL: {}
\ No newline at end of file
diff --git a/common_patches/mcpwm_collect.yaml b/common_patches/mcpwm_collect.yaml
index 06631cc38f..94aa2ea0f9 100644
--- a/common_patches/mcpwm_collect.yaml
+++ b/common_patches/mcpwm_collect.yaml
@@ -91,4 +91,4 @@ _array:
     description: Value of last capture on channel %s
     _strip: CAP?_
 
-_include: int_strip.yaml
+_include: int_strip.yaml
\ No newline at end of file
diff --git a/esp32/src/mcpwm0/cap_ch_cfg.rs b/esp32/src/mcpwm0/cap_ch_cfg.rs
index cfcda326b2..83b6603e41 100644
--- a/esp32/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - "]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - "]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - "]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP0_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP0_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP0_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP0_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP0_MODE {}
+#[doc = "Field `MODE` reader - Describes which edges to trigger a capture event"]
+pub type MODE_R = crate::FieldReader<CAP0_MODE>;
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_MODE {
+        match self.bits {
+            0 => CAP0_MODE::None,
+            1 => CAP0_MODE::FallingEdge,
+            2 => CAP0_MODE::RisingEdge,
+            3 => CAP0_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP0_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP0_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP0_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP0_MODE::AnyEdge
+    }
+}
+#[doc = "Field `MODE` writer - Describes which edges to trigger a capture event"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP0_MODE, crate::Safe>;
+impl<'a, REG> MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - "]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - "]
@@ -26,7 +109,7 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
diff --git a/esp32/src/mcpwm0/cap_status.rs b/esp32/src/mcpwm0/cap_status.rs
index b9bf8c1543..5ce5bfa149 100644
--- a/esp32/src/mcpwm0/cap_status.rs
+++ b/esp32/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - "]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - "]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - "]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32/src/mcpwm0/cap_timer_phase.rs b/esp32/src/mcpwm0/cap_timer_phase.rs
index 24fe6d9482..baee9f1486 100644
--- a/esp32/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32/src/mcpwm0/cap_timer_phase.rs
@@ -2,30 +2,30 @@
 pub type R = crate::R<CAP_TIMER_PHASE_SPEC>;
 #[doc = "Register `CAP_TIMER_PHASE` writer"]
 pub type W = crate::W<CAP_TIMER_PHASE_SPEC>;
-#[doc = "Field `CAP_TIMER_PHASE` reader - "]
-pub type CAP_TIMER_PHASE_R = crate::FieldReader<u32>;
-#[doc = "Field `CAP_TIMER_PHASE` writer - "]
-pub type CAP_TIMER_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+#[doc = "Field `CAP_PHASE` reader - "]
+pub type CAP_PHASE_R = crate::FieldReader<u32>;
+#[doc = "Field `CAP_PHASE` writer - "]
+pub type CAP_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl R {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    pub fn cap_timer_phase(&self) -> CAP_TIMER_PHASE_R {
-        CAP_TIMER_PHASE_R::new(self.bits)
+    pub fn cap_phase(&self) -> CAP_PHASE_R {
+        CAP_PHASE_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_timer_phase", &self.cap_timer_phase())
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    pub fn cap_timer_phase(&mut self) -> CAP_TIMER_PHASE_W<'_, CAP_TIMER_PHASE_SPEC> {
-        CAP_TIMER_PHASE_W::new(self, 0)
+    pub fn cap_phase(&mut self) -> CAP_PHASE_W<'_, CAP_TIMER_PHASE_SPEC> {
+        CAP_PHASE_W::new(self, 0)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_phase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_phase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/mcpwm0/int_clr.rs b/esp32/src/mcpwm0/int_clr.rs
index d03facb94e..06897aa8d8 100644
--- a/esp32/src/mcpwm0/int_clr.rs
+++ b/esp32/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - "]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - "]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - "]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - "]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - "]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - "]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - "]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - "]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - "]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - "]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - "]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - "]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - "]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - "]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - "]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP0_TEA` writer - "]
-pub type OP0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP1_TEA` writer - "]
-pub type OP1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP2_TEA` writer - "]
-pub type OP2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP0_TEB` writer - "]
-pub type OP0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP1_TEB` writer - "]
-pub type OP1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `OP2_TEB` writer - "]
-pub type OP2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH0_CBC` writer - "]
-pub type FH0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH1_CBC` writer - "]
-pub type FH1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH2_CBC` writer - "]
-pub type FH2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH0_OST` writer - "]
-pub type FH0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH1_OST` writer - "]
-pub type FH1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FH2_OST` writer - "]
-pub type FH2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - "]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - "]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - "]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4"]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5"]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6"]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8"]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10"]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12"]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14"]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn op0_tea(&mut self) -> OP0_TEA_W<'_, INT_CLR_SPEC> {
-        OP0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn op1_tea(&mut self) -> OP1_TEA_W<'_, INT_CLR_SPEC> {
-        OP1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn op2_tea(&mut self) -> OP2_TEA_W<'_, INT_CLR_SPEC> {
-        OP2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn op0_teb(&mut self) -> OP0_TEB_W<'_, INT_CLR_SPEC> {
-        OP0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn op1_teb(&mut self) -> OP1_TEB_W<'_, INT_CLR_SPEC> {
-        OP1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn op2_teb(&mut self) -> OP2_TEB_W<'_, INT_CLR_SPEC> {
-        OP2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fh0_cbc(&mut self) -> FH0_CBC_W<'_, INT_CLR_SPEC> {
-        FH0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22"]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fh1_cbc(&mut self) -> FH1_CBC_W<'_, INT_CLR_SPEC> {
-        FH1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fh2_cbc(&mut self) -> FH2_CBC_W<'_, INT_CLR_SPEC> {
-        FH2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fh0_ost(&mut self) -> FH0_OST_W<'_, INT_CLR_SPEC> {
-        FH0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25"]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn fh1_ost(&mut self) -> FH1_OST_W<'_, INT_CLR_SPEC> {
-        FH1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26"]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn fh2_ost(&mut self) -> FH2_OST_W<'_, INT_CLR_SPEC> {
-        FH2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28"]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/mcpwm0/int_ena.rs b/esp32/src/mcpwm0/int_ena.rs
index 50b2d8f403..f167f5d2b6 100644
--- a/esp32/src/mcpwm0/int_ena.rs
+++ b/esp32/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - "]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - "]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - "]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - "]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - "]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - "]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - "]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - "]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - "]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - "]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - "]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - "]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - "]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - "]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - "]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - "]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - "]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - "]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - "]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - "]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - "]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - "]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - "]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - "]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - "]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - "]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - "]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - "]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - "]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - "]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP0_TEA` reader - "]
-pub type OP0_TEA_R = crate::BitReader;
-#[doc = "Field `OP0_TEA` writer - "]
-pub type OP0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP1_TEA` reader - "]
-pub type OP1_TEA_R = crate::BitReader;
-#[doc = "Field `OP1_TEA` writer - "]
-pub type OP1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP2_TEA` reader - "]
-pub type OP2_TEA_R = crate::BitReader;
-#[doc = "Field `OP2_TEA` writer - "]
-pub type OP2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP0_TEB` reader - "]
-pub type OP0_TEB_R = crate::BitReader;
-#[doc = "Field `OP0_TEB` writer - "]
-pub type OP0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP1_TEB` reader - "]
-pub type OP1_TEB_R = crate::BitReader;
-#[doc = "Field `OP1_TEB` writer - "]
-pub type OP1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP2_TEB` reader - "]
-pub type OP2_TEB_R = crate::BitReader;
-#[doc = "Field `OP2_TEB` writer - "]
-pub type OP2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH0_CBC` reader - "]
-pub type FH0_CBC_R = crate::BitReader;
-#[doc = "Field `FH0_CBC` writer - "]
-pub type FH0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH1_CBC` reader - "]
-pub type FH1_CBC_R = crate::BitReader;
-#[doc = "Field `FH1_CBC` writer - "]
-pub type FH1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH2_CBC` reader - "]
-pub type FH2_CBC_R = crate::BitReader;
-#[doc = "Field `FH2_CBC` writer - "]
-pub type FH2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH0_OST` reader - "]
-pub type FH0_OST_R = crate::BitReader;
-#[doc = "Field `FH0_OST` writer - "]
-pub type FH0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH1_OST` reader - "]
-pub type FH1_OST_R = crate::BitReader;
-#[doc = "Field `FH1_OST` writer - "]
-pub type FH1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH2_OST` reader - "]
-pub type FH2_OST_R = crate::BitReader;
-#[doc = "Field `FH2_OST` writer - "]
-pub type FH2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - "]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - "]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - "]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - "]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - "]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - "]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4"]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8"]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12"]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14"]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn op0_tea(&self) -> OP0_TEA_R {
-        OP0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn op1_tea(&self) -> OP1_TEA_R {
-        OP1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn op2_tea(&self) -> OP2_TEA_R {
-        OP2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18"]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn op0_teb(&self) -> OP0_TEB_R {
-        OP0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn op1_teb(&self) -> OP1_TEB_R {
-        OP1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn op2_teb(&self) -> OP2_TEB_R {
-        OP2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn fh0_cbc(&self) -> FH0_CBC_R {
-        FH0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22"]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn fh1_cbc(&self) -> FH1_CBC_R {
-        FH1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn fh2_cbc(&self) -> FH2_CBC_R {
-        FH2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24"]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fh0_ost(&self) -> FH0_OST_R {
-        FH0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fh1_ost(&self) -> FH1_OST_R {
-        FH1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn fh2_ost(&self) -> FH2_OST_R {
-        FH2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28"]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -293,18 +363,18 @@ impl core::fmt::Debug for R {
             .field("fault0_clr", &self.fault0_clr())
             .field("fault1_clr", &self.fault1_clr())
             .field("fault2_clr", &self.fault2_clr())
-            .field("op0_tea", &self.op0_tea())
-            .field("op1_tea", &self.op1_tea())
-            .field("op2_tea", &self.op2_tea())
-            .field("op0_teb", &self.op0_teb())
-            .field("op1_teb", &self.op1_teb())
-            .field("op2_teb", &self.op2_teb())
-            .field("fh0_cbc", &self.fh0_cbc())
-            .field("fh1_cbc", &self.fh1_cbc())
-            .field("fh2_cbc", &self.fh2_cbc())
-            .field("fh0_ost", &self.fh0_ost())
-            .field("fh1_ost", &self.fh1_ost())
-            .field("fh2_ost", &self.fh2_ost())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
             .field("cap0", &self.cap0())
             .field("cap1", &self.cap1())
             .field("cap2", &self.cap2())
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4"]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5"]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8"]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12"]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15"]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn op0_tea(&mut self) -> OP0_TEA_W<'_, INT_ENA_SPEC> {
-        OP0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16"]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn op1_tea(&mut self) -> OP1_TEA_W<'_, INT_ENA_SPEC> {
-        OP1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn op2_tea(&mut self) -> OP2_TEA_W<'_, INT_ENA_SPEC> {
-        OP2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn op0_teb(&mut self) -> OP0_TEB_W<'_, INT_ENA_SPEC> {
-        OP0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn op1_teb(&mut self) -> OP1_TEB_W<'_, INT_ENA_SPEC> {
-        OP1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20"]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn op2_teb(&mut self) -> OP2_TEB_W<'_, INT_ENA_SPEC> {
-        OP2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn fh0_cbc(&mut self) -> FH0_CBC_W<'_, INT_ENA_SPEC> {
-        FH0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn fh1_cbc(&mut self) -> FH1_CBC_W<'_, INT_ENA_SPEC> {
-        FH1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn fh2_cbc(&mut self) -> FH2_CBC_W<'_, INT_ENA_SPEC> {
-        FH2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24"]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn fh0_ost(&mut self) -> FH0_OST_W<'_, INT_ENA_SPEC> {
-        FH0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25"]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn fh1_ost(&mut self) -> FH1_OST_W<'_, INT_ENA_SPEC> {
-        FH1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn fh2_ost(&mut self) -> FH2_OST_W<'_, INT_ENA_SPEC> {
-        FH2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28"]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/mcpwm0/int_raw.rs b/esp32/src/mcpwm0/int_raw.rs
index 5693931421..bb026ba5e7 100644
--- a/esp32/src/mcpwm0/int_raw.rs
+++ b/esp32/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - "]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - "]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - "]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - "]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - "]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - "]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - "]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - "]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - "]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - "]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - "]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - "]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - "]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - "]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - "]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - "]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - "]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - "]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - "]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - "]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - "]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - "]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - "]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - "]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - "]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - "]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - "]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - "]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - "]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - "]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP0_TEA` reader - "]
-pub type OP0_TEA_R = crate::BitReader;
-#[doc = "Field `OP0_TEA` writer - "]
-pub type OP0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP1_TEA` reader - "]
-pub type OP1_TEA_R = crate::BitReader;
-#[doc = "Field `OP1_TEA` writer - "]
-pub type OP1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP2_TEA` reader - "]
-pub type OP2_TEA_R = crate::BitReader;
-#[doc = "Field `OP2_TEA` writer - "]
-pub type OP2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP0_TEB` reader - "]
-pub type OP0_TEB_R = crate::BitReader;
-#[doc = "Field `OP0_TEB` writer - "]
-pub type OP0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP1_TEB` reader - "]
-pub type OP1_TEB_R = crate::BitReader;
-#[doc = "Field `OP1_TEB` writer - "]
-pub type OP1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `OP2_TEB` reader - "]
-pub type OP2_TEB_R = crate::BitReader;
-#[doc = "Field `OP2_TEB` writer - "]
-pub type OP2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH0_CBC` reader - "]
-pub type FH0_CBC_R = crate::BitReader;
-#[doc = "Field `FH0_CBC` writer - "]
-pub type FH0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH1_CBC` reader - "]
-pub type FH1_CBC_R = crate::BitReader;
-#[doc = "Field `FH1_CBC` writer - "]
-pub type FH1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH2_CBC` reader - "]
-pub type FH2_CBC_R = crate::BitReader;
-#[doc = "Field `FH2_CBC` writer - "]
-pub type FH2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH0_OST` reader - "]
-pub type FH0_OST_R = crate::BitReader;
-#[doc = "Field `FH0_OST` writer - "]
-pub type FH0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH1_OST` reader - "]
-pub type FH1_OST_R = crate::BitReader;
-#[doc = "Field `FH1_OST` writer - "]
-pub type FH1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FH2_OST` reader - "]
-pub type FH2_OST_R = crate::BitReader;
-#[doc = "Field `FH2_OST` writer - "]
-pub type FH2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - "]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - "]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - "]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - "]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - "]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - "]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4"]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8"]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12"]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14"]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn op0_tea(&self) -> OP0_TEA_R {
-        OP0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn op1_tea(&self) -> OP1_TEA_R {
-        OP1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn op2_tea(&self) -> OP2_TEA_R {
-        OP2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn op0_teb(&self) -> OP0_TEB_R {
-        OP0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn op1_teb(&self) -> OP1_TEB_R {
-        OP1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn op2_teb(&self) -> OP2_TEB_R {
-        OP2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn fh0_cbc(&self) -> FH0_CBC_R {
-        FH0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22"]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn fh1_cbc(&self) -> FH1_CBC_R {
-        FH1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn fh2_cbc(&self) -> FH2_CBC_R {
-        FH2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24"]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fh0_ost(&self) -> FH0_OST_R {
-        FH0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fh1_ost(&self) -> FH1_OST_R {
-        FH1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn fh2_ost(&self) -> FH2_OST_R {
-        FH2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28"]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -293,18 +363,18 @@ impl core::fmt::Debug for R {
             .field("fault0_clr", &self.fault0_clr())
             .field("fault1_clr", &self.fault1_clr())
             .field("fault2_clr", &self.fault2_clr())
-            .field("op0_tea", &self.op0_tea())
-            .field("op1_tea", &self.op1_tea())
-            .field("op2_tea", &self.op2_tea())
-            .field("op0_teb", &self.op0_teb())
-            .field("op1_teb", &self.op1_teb())
-            .field("op2_teb", &self.op2_teb())
-            .field("fh0_cbc", &self.fh0_cbc())
-            .field("fh1_cbc", &self.fh1_cbc())
-            .field("fh2_cbc", &self.fh2_cbc())
-            .field("fh0_ost", &self.fh0_ost())
-            .field("fh1_ost", &self.fh1_ost())
-            .field("fh2_ost", &self.fh2_ost())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
             .field("cap0", &self.cap0())
             .field("cap1", &self.cap1())
             .field("cap2", &self.cap2())
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8"]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12"]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn op0_tea(&mut self) -> OP0_TEA_W<'_, INT_RAW_SPEC> {
-        OP0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn op1_tea(&mut self) -> OP1_TEA_W<'_, INT_RAW_SPEC> {
-        OP1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn op2_tea(&mut self) -> OP2_TEA_W<'_, INT_RAW_SPEC> {
-        OP2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn op0_teb(&mut self) -> OP0_TEB_W<'_, INT_RAW_SPEC> {
-        OP0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn op1_teb(&mut self) -> OP1_TEB_W<'_, INT_RAW_SPEC> {
-        OP1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn op2_teb(&mut self) -> OP2_TEB_W<'_, INT_RAW_SPEC> {
-        OP2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn fh0_cbc(&mut self) -> FH0_CBC_W<'_, INT_RAW_SPEC> {
-        FH0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn fh1_cbc(&mut self) -> FH1_CBC_W<'_, INT_RAW_SPEC> {
-        FH1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn fh2_cbc(&mut self) -> FH2_CBC_W<'_, INT_RAW_SPEC> {
-        FH2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24"]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn fh0_ost(&mut self) -> FH0_OST_W<'_, INT_RAW_SPEC> {
-        FH0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25"]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn fh1_ost(&mut self) -> FH1_OST_W<'_, INT_RAW_SPEC> {
-        FH1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn fh2_ost(&mut self) -> FH2_OST_W<'_, INT_RAW_SPEC> {
-        FH2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28"]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/mcpwm0/int_st.rs b/esp32/src/mcpwm0/int_st.rs
index 2184102161..6743d972d8 100644
--- a/esp32/src/mcpwm0/int_st.rs
+++ b/esp32/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - "]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - "]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - "]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - "]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - "]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - "]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - "]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - "]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - "]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - "]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - "]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - "]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - "]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - "]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - "]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `OP0_TEA` reader - "]
-pub type OP0_TEA_R = crate::BitReader;
-#[doc = "Field `OP1_TEA` reader - "]
-pub type OP1_TEA_R = crate::BitReader;
-#[doc = "Field `OP2_TEA` reader - "]
-pub type OP2_TEA_R = crate::BitReader;
-#[doc = "Field `OP0_TEB` reader - "]
-pub type OP0_TEB_R = crate::BitReader;
-#[doc = "Field `OP1_TEB` reader - "]
-pub type OP1_TEB_R = crate::BitReader;
-#[doc = "Field `OP2_TEB` reader - "]
-pub type OP2_TEB_R = crate::BitReader;
-#[doc = "Field `FH0_CBC` reader - "]
-pub type FH0_CBC_R = crate::BitReader;
-#[doc = "Field `FH1_CBC` reader - "]
-pub type FH1_CBC_R = crate::BitReader;
-#[doc = "Field `FH2_CBC` reader - "]
-pub type FH2_CBC_R = crate::BitReader;
-#[doc = "Field `FH0_OST` reader - "]
-pub type FH0_OST_R = crate::BitReader;
-#[doc = "Field `FH1_OST` reader - "]
-pub type FH1_OST_R = crate::BitReader;
-#[doc = "Field `FH2_OST` reader - "]
-pub type FH2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - "]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - "]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - "]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2"]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3"]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4"]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7"]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8"]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12"]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13"]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14"]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn op0_tea(&self) -> OP0_TEA_R {
-        OP0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn op1_tea(&self) -> OP1_TEA_R {
-        OP1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn op2_tea(&self) -> OP2_TEA_R {
-        OP2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn op0_teb(&self) -> OP0_TEB_R {
-        OP0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn op1_teb(&self) -> OP1_TEB_R {
-        OP1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn op2_teb(&self) -> OP2_TEB_R {
-        OP2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn fh0_cbc(&self) -> FH0_CBC_R {
-        FH0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22"]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn fh1_cbc(&self) -> FH1_CBC_R {
-        FH1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23"]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn fh2_cbc(&self) -> FH2_CBC_R {
-        FH2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24"]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fh0_ost(&self) -> FH0_OST_R {
-        FH0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fh1_ost(&self) -> FH1_OST_R {
-        FH1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn fh2_ost(&self) -> FH2_OST_R {
-        FH2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27"]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28"]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29"]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -231,18 +341,18 @@ impl core::fmt::Debug for R {
             .field("fault0_clr", &self.fault0_clr())
             .field("fault1_clr", &self.fault1_clr())
             .field("fault2_clr", &self.fault2_clr())
-            .field("op0_tea", &self.op0_tea())
-            .field("op1_tea", &self.op1_tea())
-            .field("op2_tea", &self.op2_tea())
-            .field("op0_teb", &self.op0_teb())
-            .field("op1_teb", &self.op1_teb())
-            .field("op2_teb", &self.op2_teb())
-            .field("fh0_cbc", &self.fh0_cbc())
-            .field("fh1_cbc", &self.fh1_cbc())
-            .field("fh2_cbc", &self.fh2_cbc())
-            .field("fh0_ost", &self.fh0_ost())
-            .field("fh1_ost", &self.fh1_ost())
-            .field("fh2_ost", &self.fh2_ost())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
             .field("cap0", &self.cap0())
             .field("cap1", &self.cap1())
             .field("cap2", &self.cap2())
diff --git a/esp32/src/mcpwm0/operator_timersel.rs b/esp32/src/mcpwm0/operator_timersel.rs
index d2b8878601..f0e0faeef1 100644
--- a/esp32/src/mcpwm0/operator_timersel.rs
+++ b/esp32/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - "]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - "]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - "]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - "]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - "]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - "]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - "]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - "]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
-    #[doc = "Bits 0:1"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
     }
-    #[doc = "Bits 2:3"]
+    #[doc = "Iterator for array of:"]
+    #[doc = ""]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
     }
-    #[doc = "Bits 4:5"]
+    #[doc = "Bits 0:1 - OPERATOR0_TIMERSEL"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - OPERATOR1_TIMERSEL"]
+    #[inline(always)]
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - OPERATOR2_TIMERSEL"]
+    #[inline(always)]
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:1"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
+    #[doc = "Bits 0:1 - OPERATOR0_TIMERSEL"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
-    #[doc = "Bits 2:3"]
+    #[doc = "Bits 2:3 - OPERATOR1_TIMERSEL"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
-    #[doc = "Bits 4:5"]
+    #[doc = "Bits 4:5 - OPERATOR2_TIMERSEL"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/mcpwm0/timer_synci_cfg.rs b/esp32/src/mcpwm0/timer_synci_cfg.rs
index 9278da36e3..b8f576161c 100644
--- a/esp32/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - "]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - "]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - "]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - "]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - "]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - "]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - "]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - "]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - "]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - "]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - "]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - "]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - "]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - "]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - "]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - "]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:2"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
     }
-    #[doc = "Bits 3:5"]
+    #[doc = "Iterator for array of:"]
+    #[doc = ""]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
     }
-    #[doc = "Bits 6:8"]
+    #[doc = "Bits 0:2 - TIMER0_SYNCISEL"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bits 3:5 - TIMER1_SYNCISEL"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
-    #[doc = "Bit 10"]
+    #[doc = "Bits 6:8 - TIMER2_SYNCISEL"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
     }
-    #[doc = "Bit 11"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = ""]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
+    }
+    #[doc = "Bit 9 - EXTERNAL_SYNCI0_INVERT"]
+    #[inline(always)]
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - EXTERNAL_SYNCI1_INVERT"]
+    #[inline(always)]
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - EXTERNAL_SYNCI2_INVERT"]
+    #[inline(always)]
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:2"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
+    #[doc = "Bits 0:2 - TIMER0_SYNCISEL"]
+    #[inline(always)]
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
+    }
+    #[doc = "Bits 3:5 - TIMER1_SYNCISEL"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
-    #[doc = "Bits 3:5"]
+    #[doc = "Bits 6:8 - TIMER2_SYNCISEL"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
     }
-    #[doc = "Bits 6:8"]
+    #[doc = ""]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
-    #[doc = "Bit 9"]
+    #[doc = "Bit 9 - EXTERNAL_SYNCI0_INVERT"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
-    #[doc = "Bit 10"]
+    #[doc = "Bit 10 - EXTERNAL_SYNCI1_INVERT"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
-    #[doc = "Bit 11"]
+    #[doc = "Bit 11 - EXTERNAL_SYNCI2_INVERT"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/svd/patches/_mcpwm.yml b/esp32/svd/patches/_mcpwm.yml
new file mode 100644
index 0000000000..5a8fdc44c3
--- /dev/null
+++ b/esp32/svd/patches/_mcpwm.yml
@@ -0,0 +1,113 @@
+MCPWM0:
+  CAP_TIMER_PHASE:
+    _modify:
+      CAP_TIMER_PHASE:
+        name: CAP_PHASE
+
+  INT_RAW:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      OP?_TEA:
+        name: CMPR%s_TEA
+        description: The interrupt raw bit for the operator%s compare A event.
+      OP?_TEB:
+        name: CMPR%s_TEB
+        description: The interrupt raw bit for the operator%s compare B event.
+      FH?_CBC:
+        name: TZ%s_CBC
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      FH?_OST:
+        name: TZ%s_OST
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  INT_ST:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      OP?_TEA:
+        name: CMPR%s_TEA
+        description: The interrupt status bit for the operator%s compare A event.
+      OP?_TEB:
+        name: CMPR%s_TEB
+        description: The interrupt status bit for the operator%s compare B event.
+      FH?_CBC:
+        name: TZ%s_CBC
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      FH?_OST:
+        name: TZ%s_OST
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  INT_ENA:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      OP?_TEA:
+        name: CMPR%s_TEA
+        description: The interrupt enable bit for the operator%s compare A event.
+      OP?_TEB:
+        name: CMPR%s_TEB
+        description: The interrupt enable bit for the operator%s compare B event.
+      FH?_CBC:
+        name: TZ%s_CBC
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      FH?_OST:
+        name: TZ%s_OST
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  INT_CLR:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      OP?_TEA:
+        name: CMPR%s_TEA
+        description: The interrupt clear bit for the operator%s compare A event.
+      OP?_TEB:
+        name: CMPR%s_TEB
+        description: The interrupt clear bit for the operator%s compare B event.
+      FH?_CBC:
+        name: TZ%s_CBC
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      FH?_OST:
+        name: TZ%s_OST
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
\ No newline at end of file
diff --git a/esp32/svd/patches/esp32.yaml b/esp32/svd/patches/esp32.yaml
index 05d56b0634..ebf12a9a79 100644
--- a/esp32/svd/patches/esp32.yaml
+++ b/esp32/svd/patches/esp32.yaml
@@ -18,6 +18,7 @@ _include:
   - "_timg.yml"
   - "wifi.yaml"
   - "btdm.yml"
+  - _mcpwm.yml
   - "_mmu_table.yml"
 
 RNG:
@@ -172,7 +173,9 @@ UHCI0:
     ESC_CONF?: {}
 
 MCPWM0:
-  _include: ../../../common_patches/mcpwm_collect.yaml
+  _include:
+    - ../../../common_patches/mcpwm_collect.yaml
+    - ../../../common_patches/mcpwm.yaml
   INT_RAW:
     _modify:
       "*":
diff --git a/esp32c5/src/mcpwm0/cap_ch_cfg.rs b/esp32c5/src/mcpwm0/cap_ch_cfg.rs
index 96a513b375..4d68047375 100644
--- a/esp32c5/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32c5/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type CAP_EN_R = crate::BitReader;
 #[doc = "Field `CAP_EN` writer - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"]
 pub type CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP_MODE` reader - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
-pub type CAP_MODE_R = crate::FieldReader;
-#[doc = "Field `CAP_MODE` writer - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
-pub type CAP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP_MODE {}
+#[doc = "Field `CAP_MODE` reader - Describes which edges to trigger a capture event"]
+pub type CAP_MODE_R = crate::FieldReader<CAP_MODE>;
+impl CAP_MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP_MODE {
+        match self.bits {
+            0 => CAP_MODE::None,
+            1 => CAP_MODE::FallingEdge,
+            2 => CAP_MODE::RisingEdge,
+            3 => CAP_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP_MODE::AnyEdge
+    }
+}
+#[doc = "Field `CAP_MODE` writer - Describes which edges to trigger a capture event"]
+pub type CAP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP_MODE, crate::Safe>;
+impl<'a, REG> CAP_MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `CAP_PRESCALE` reader - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
 pub type CAP_PRESCALE_R = crate::FieldReader;
 #[doc = "Field `CAP_PRESCALE` writer - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
@@ -26,7 +109,7 @@ impl R {
     pub fn cap_en(&self) -> CAP_EN_R {
         CAP_EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn cap_mode(&self) -> CAP_MODE_R {
         CAP_MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn cap_en(&mut self) -> CAP_EN_W<'_, CAP_CH_CFG_SPEC> {
         CAP_EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn cap_mode(&mut self) -> CAP_MODE_W<'_, CAP_CH_CFG_SPEC> {
         CAP_MODE_W::new(self, 1)
diff --git a/esp32c5/src/mcpwm0/cap_status.rs b/esp32c5/src/mcpwm0/cap_status.rs
index 24f155edae..0f30853f16 100644
--- a/esp32c5/src/mcpwm0/cap_status.rs
+++ b/esp32c5/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0 - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1 - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32c5/src/mcpwm0/int_clr.rs b/esp32c5/src/mcpwm0/int_clr.rs
index 3b8bd0d82b..f381aa3c58 100644
--- a/esp32c5/src/mcpwm0/int_clr.rs
+++ b/esp32c5/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1 - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2 - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_CLR_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_CLR_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_CLR_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_CLR_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_CLR_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_CLR_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c5/src/mcpwm0/int_ena.rs b/esp32c5/src/mcpwm0/int_ena.rs
index 00aee76158..4d4239f276 100644
--- a/esp32c5/src/mcpwm0/int_ena.rs
+++ b/esp32c5/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c5/src/mcpwm0/int_raw.rs b/esp32c5/src/mcpwm0/int_raw.rs
index 11724cdacb..1e8a5a8b25 100644
--- a/esp32c5/src/mcpwm0/int_raw.rs
+++ b/esp32c5/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_RAW_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_RAW_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_RAW_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_RAW_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_RAW_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_RAW_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c5/src/mcpwm0/int_st.rs b/esp32c5/src/mcpwm0/int_st.rs
index cf415dd0b1..6c30c709bc 100644
--- a/esp32c5/src/mcpwm0/int_st.rs
+++ b/esp32c5/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32c5/src/mcpwm0/operator_timersel.rs b/esp32c5/src/mcpwm0/operator_timersel.rs
index d6b68f19e7..d4c4cfa797 100644
--- a/esp32c5/src/mcpwm0/operator_timersel.rs
+++ b/esp32c5/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - Configures which PWM timer will be the timing reference for PWM operator%s.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - Configures which PWM timer will be the timing reference for PWM operator%s.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[inline(always)]
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
+    }
     #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
     }
     #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
     }
     #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
     #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "PWM operator's timer select register\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c5/src/mcpwm0/timer_synci_cfg.rs b/esp32c5/src/mcpwm0/timer_synci_cfg.rs
index 1dff734e61..37647b692d 100644
--- a/esp32c5/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32c5/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - Configures the selection of sync input for PWM timer%s.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - Configures the selection of sync input for PWM timer%s.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - Configures whether or not to invert SYNC%s from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - Configures whether or not to invert SYNC%s from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[inline(always)]
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
     #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
     #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
     #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
     #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
     }
     #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
     }
     #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
     #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
     #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "Synchronization input selection register for PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c5/svd/patches/_mcpwm.yml b/esp32c5/svd/patches/_mcpwm.yml
new file mode 100644
index 0000000000..64ee4e593c
--- /dev/null
+++ b/esp32c5/svd/patches/_mcpwm.yml
@@ -0,0 +1,119 @@
+MCPWM0:
+  CAP_STATUS:
+    _array:
+      CAP?_EDGE:
+        description: Describes the last captured edge on channel%s.
+    CAP?_EDGE:
+      Rising: [0, "Rising edge"]
+      Falling: [1, "Falling edge"]
+
+  CAP_CH%s_CFG:
+    _modify:
+      CAP_MODE:
+        description: Describes which edges to trigger a capture event
+    CAP_MODE:
+      None: [0, "Capture nothing"]
+      FallingEdge: [1, "Capture falling edges"]
+      RisingEdge: [2, "Capture rising edges"]
+      AnyEdge: [3, "Capture any edges"]
+
+  TIMER_SYNCI_CFG:
+    _array:
+      TIMER?_SYNCISEL: {}
+      EXTERNAL_SYNCI?_INVERT: {}
+
+  OPERATOR_TIMERSEL:
+    _array:
+      OPERATOR?_TIMERSEL: {}
+
+  INT_RAW:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt raw bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt raw bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  INT_ST:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt status bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt status bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  INT_ENA:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt enable bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt enable bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  INT_CLR:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt clear bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt clear bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
\ No newline at end of file
diff --git a/esp32c5/svd/patches/esp32c5.yaml b/esp32c5/svd/patches/esp32c5.yaml
index 133a52ae9f..500a7a64be 100644
--- a/esp32c5/svd/patches/esp32c5.yaml
+++ b/esp32c5/svd/patches/esp32c5.yaml
@@ -17,6 +17,7 @@ _include:
   - _i2c.yml
   - _interrupt.yml
   - _lp_apm.yml
+  - _mcpwm.yml
   - _lp_io.yml
   - _modem_lpcon.yml
   - _modem_syscon.yml
@@ -640,7 +641,8 @@ PCNT:
   _include: pcnt.yaml
 
 MCPWM0:
-  _include: ../../../common_patches/int_strip.yaml
+  _include:
+    - ../../../common_patches/int_strip.yaml
 
 SOC_ETM:
   CH_ENA_AD?:
diff --git a/esp32c6/src/mcpwm0/cap_ch_cfg.rs b/esp32c6/src/mcpwm0/cap_ch_cfg.rs
index 3dbc408259..c4c19ab17d 100644
--- a/esp32c6/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32c6/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - When set, capture on channel 0 is enabled"]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP0_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP0_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP0_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP0_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP0_MODE {}
+#[doc = "Field `MODE` reader - Describes which edges to trigger a capture event"]
+pub type MODE_R = crate::FieldReader<CAP0_MODE>;
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_MODE {
+        match self.bits {
+            0 => CAP0_MODE::None,
+            1 => CAP0_MODE::FallingEdge,
+            2 => CAP0_MODE::RisingEdge,
+            3 => CAP0_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP0_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP0_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP0_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP0_MODE::AnyEdge
+    }
+}
+#[doc = "Field `MODE` writer - Describes which edges to trigger a capture event"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP0_MODE, crate::Safe>;
+impl<'a, REG> MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
@@ -26,7 +109,7 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
diff --git a/esp32c6/src/mcpwm0/cap_status.rs b/esp32c6/src/mcpwm0/cap_status.rs
index bca2493ef5..ca0a931292 100644
--- a/esp32c6/src/mcpwm0/cap_status.rs
+++ b/esp32c6/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0 - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1 - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32c6/src/mcpwm0/int_clr.rs b/esp32c6/src/mcpwm0/int_clr.rs
index 5c814d5712..5c5391ffcd 100644
--- a/esp32c6/src/mcpwm0/int_clr.rs
+++ b/esp32c6/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - Set this bit to clear the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - Set this bit to clear the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - Set this bit to clear the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - Set this bit to clear the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - Set this bit to clear the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - Set this bit to clear the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - Set this bit to clear the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - Set this bit to clear the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - Set this bit to clear the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - Set this bit to clear the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - Set this bit to clear the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - Set this bit to clear the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_CLR_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_CLR_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_CLR_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_CLR_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_CLR_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_CLR_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/mcpwm0/int_ena.rs b/esp32c6/src/mcpwm0/int_ena.rs
index a73ac34d34..2bca6aceb3 100644
--- a/esp32c6/src/mcpwm0/int_ena.rs
+++ b/esp32c6/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/mcpwm0/int_raw.rs b/esp32c6/src/mcpwm0/int_raw.rs
index a0188a82fd..171d7e95dd 100644
--- a/esp32c6/src/mcpwm0/int_raw.rs
+++ b/esp32c6/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_RAW_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_RAW_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_RAW_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_RAW_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_RAW_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_RAW_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/mcpwm0/int_st.rs b/esp32c6/src/mcpwm0/int_st.rs
index 4da0f0e2ca..cc4ed338f8 100644
--- a/esp32c6/src/mcpwm0/int_st.rs
+++ b/esp32c6/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The masked status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - The masked status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - The masked status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - The masked status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - The masked status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - The masked status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - The masked status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - The masked status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - The masked status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - The masked status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - The masked status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - The masked status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0 - The masked status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The masked status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The masked status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The masked status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The masked status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The masked status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The masked status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The masked status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The masked status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The masked status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The masked status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The masked status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32c6/src/mcpwm0/operator_timersel.rs b/esp32c6/src/mcpwm0/operator_timersel.rs
index 3b8f17223e..8b6e17a833 100644
--- a/esp32c6/src/mcpwm0/operator_timersel.rs
+++ b/esp32c6/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "Select specific timer for PWM operators.\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/mcpwm0/timer_synci_cfg.rs b/esp32c6/src/mcpwm0/timer_synci_cfg.rs
index 0ca677dcc7..951c07e8ac 100644
--- a/esp32c6/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32c6/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "Synchronization input selection for three PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/svd/patches/_mcpwm.yml b/esp32c6/svd/patches/_mcpwm.yml
new file mode 100644
index 0000000000..3cfce4870b
--- /dev/null
+++ b/esp32c6/svd/patches/_mcpwm.yml
@@ -0,0 +1,233 @@
+
+MCPWM0:
+  # Define a unified Event enum covering all 10 event types
+  _enums:
+    EVENT:
+      description: |
+        MCPWM event types representing all interrupt sources
+        Maps to register field bit positions across INT_RAW, INT_ST, INT_ENA, INT_CLR
+      variants:
+        TIMER_STOP:
+          value: 0
+          description: Timer stop event
+        TIMER_TEZ:
+          value: 1
+          description: Timer equal zero event
+        TIMER_TEP:
+          value: 2
+          description: Timer equal period event
+        CAPTURE:
+          value: 3
+          description: Capture event
+        CMPR_TEA:
+          value: 4
+          description: Compare A event
+        CMPR_TEB:
+          value: 5
+          description: Compare B event
+        FAULT:
+          value: 6
+          description: Fault event
+        FAULT_CLR:
+          value: 7
+          description: Fault clear event
+        TZ_CBC:
+          value: 8
+          description: Fault cycle-by-cycle event
+        TZ_OST:
+          value: 9
+          description: Fault one-shot event
+
+  # INT_RAW: Raw interrupt status (read-only)
+  INT_RAW:
+    _field_lookup:
+      # Tells the SVD/PAC generator to create a helper method
+      enum: EVENT
+      
+      # This mapping tells the generator how to convert Event variants to register fields
+      mapping:
+        TIMER_STOP: TIMER?_STOP
+        TIMER_TEZ: TIMER?_TEZ
+        TIMER_TEP: TIMER?_TEP
+        CAPTURE: CAP?
+        CMPR_TEA: CMPR?_TEA
+        CMPR_TEB: CMPR?_TEB
+        FAULT: FAULT?
+        FAULT_CLR: FAULT?_CLR
+        TZ_CBC: TZ?_CBC
+        TZ_OST: TZ?_OST
+      
+      # Helper method generation directive
+      generate_helpers:
+        # Generate: pub fn event_bit(&self, event: Event, unit: u8) -> bool
+        - name: event_bit
+          signature: "fn event_bit(&self, event: Event, unit: u8) -> bool"
+          implementation: |
+            match event {
+                Event::TimerStop => self.timer_stop(unit).bit(),
+                Event::TimerTez => self.timer_tez(unit).bit(),
+                Event::TimerTep => self.timer_tep(unit).bit(),
+                Event::Capture => self.cap(unit).bit(),
+                Event::CmprTea => self.cmpr_tea(unit).bit(),
+                Event::CmprTeb => self.cmpr_teb(unit).bit(),
+                Event::Fault => self.fault(unit).bit(),
+                Event::FaultClr => self.fault_clr(unit).bit(),
+                Event::TzCbc => self.tz_cbc(unit).bit(),
+                Event::TzOst => self.tz_ost(unit).bit(),
+            }
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt raw bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt raw bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  # INT_ST: Status register (read-only)
+  INT_ST:
+    _field_lookup:
+      enum: EVENT
+      mapping:
+        TIMER_STOP: TIMER?_STOP
+        TIMER_TEZ: TIMER?_TEZ
+        TIMER_TEP: TIMER?_TEP
+        CAPTURE: CAP?
+        CMPR_TEA: CMPR?_TEA
+        CMPR_TEB: CMPR?_TEB
+        FAULT: FAULT?
+        FAULT_CLR: FAULT?_CLR
+        TZ_CBC: TZ?_CBC
+        TZ_OST: TZ?_OST
+      
+      generate_helpers:
+        - name: event_bit
+          signature: "pub fn event_bit(&self, event: Event, unit: u8) -> bool"
+          description: |
+            Get interrupt status bit for the specified event and unit.
+            Returns true if the interrupt for this event is pending on the given unit.
+    
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt status bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt status bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  # INT_ENA: Enable register (read-write)
+  INT_ENA:
+    _field_lookup:
+      enum: EVENT
+      mapping:
+        TIMER_STOP: TIMER?_STOP
+        TIMER_TEZ: TIMER?_TEZ
+        TIMER_TEP: TIMER?_TEP
+        CAPTURE: CAP?
+        CMPR_TEA: CMPR?_TEA
+        CMPR_TEB: CMPR?_TEB
+        FAULT: FAULT?
+        FAULT_CLR: FAULT?_CLR
+        TZ_CBC: TZ?_CBC
+        TZ_OST: TZ?_OST
+      
+      generate_helpers:
+        - name: set_event_enable
+          signature: "pub fn set_event_enable(&mut self, event: Event, unit: u8, value: bool) -> &mut Self"
+          description: |
+            Enable or disable interrupt for the specified event and unit.
+            Returns self for method chaining in register writer context.
+    
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt enable bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt enable bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  # INT_CLR: Clear register (write-only)
+  INT_CLR:
+    _field_lookup:
+      enum: EVENT
+      mapping:
+        TIMER_STOP: TIMER?_STOP
+        TIMER_TEZ: TIMER?_TEZ
+        TIMER_TEP: TIMER?_TEP
+        CAPTURE: CAP?
+        CMPR_TEA: CMPR?_TEA
+        CMPR_TEB: CMPR?_TEB
+        FAULT: FAULT?
+        FAULT_CLR: FAULT?_CLR
+        TZ_CBC: TZ?_CBC
+        TZ_OST: TZ?_OST
+      
+      generate_helpers:
+        - name: clear_event
+          signature: "pub fn clear_event(&mut self, event: Event, unit: u8) -> &mut Self"
+          description: |
+            Clear interrupt status for the specified event and unit.
+            Returns self for method chaining in register writer context.
+    
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt clear bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt clear bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml
index e1007dd591..6f9998b8fa 100644
--- a/esp32c6/svd/patches/esp32c6.yaml
+++ b/esp32c6/svd/patches/esp32c6.yaml
@@ -28,6 +28,7 @@ _include:
   - "_twai.yml"
   - "_uart.yml"
   - "_wdt.yml"
+  - "_mcpwm.yml"
   - "_mmu_item_content.yml"
   - "_mmu_item_index.yml"
 
@@ -208,7 +209,9 @@ SPI1:
   _include: ../../../common_patches/spi_w.yaml
 
 MCPWM0:
-  _include: ../../../common_patches/mcpwm_collect.yaml
+  _include:
+    - ../../../common_patches/mcpwm_collect.yaml
+    - ../../../common_patches/mcpwm.yaml
 
 SOC_ETM:
   _include: ../../../common_patches/etm_collect.yaml
diff --git a/esp32h2/src/mcpwm0/cap_ch_cfg.rs b/esp32h2/src/mcpwm0/cap_ch_cfg.rs
index 3dbc408259..c4c19ab17d 100644
--- a/esp32h2/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32h2/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - When set, capture on channel 0 is enabled"]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP0_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP0_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP0_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP0_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP0_MODE {}
+#[doc = "Field `MODE` reader - Describes which edges to trigger a capture event"]
+pub type MODE_R = crate::FieldReader<CAP0_MODE>;
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_MODE {
+        match self.bits {
+            0 => CAP0_MODE::None,
+            1 => CAP0_MODE::FallingEdge,
+            2 => CAP0_MODE::RisingEdge,
+            3 => CAP0_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP0_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP0_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP0_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP0_MODE::AnyEdge
+    }
+}
+#[doc = "Field `MODE` writer - Describes which edges to trigger a capture event"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP0_MODE, crate::Safe>;
+impl<'a, REG> MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
@@ -26,7 +109,7 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
diff --git a/esp32h2/src/mcpwm0/cap_status.rs b/esp32h2/src/mcpwm0/cap_status.rs
index bca2493ef5..ca0a931292 100644
--- a/esp32h2/src/mcpwm0/cap_status.rs
+++ b/esp32h2/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0 - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1 - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32h2/src/mcpwm0/int_clr.rs b/esp32h2/src/mcpwm0/int_clr.rs
index 5c814d5712..5c5391ffcd 100644
--- a/esp32h2/src/mcpwm0/int_clr.rs
+++ b/esp32h2/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - Set this bit to clear the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - Set this bit to clear the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - Set this bit to clear the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - Set this bit to clear the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - Set this bit to clear the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - Set this bit to clear the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - Set this bit to clear the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - Set this bit to clear the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - Set this bit to clear the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - Set this bit to clear the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - Set this bit to clear the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - Set this bit to clear the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_CLR_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_CLR_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_CLR_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_CLR_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_CLR_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_CLR_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/mcpwm0/int_ena.rs b/esp32h2/src/mcpwm0/int_ena.rs
index a73ac34d34..2bca6aceb3 100644
--- a/esp32h2/src/mcpwm0/int_ena.rs
+++ b/esp32h2/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/mcpwm0/int_raw.rs b/esp32h2/src/mcpwm0/int_raw.rs
index a0188a82fd..171d7e95dd 100644
--- a/esp32h2/src/mcpwm0/int_raw.rs
+++ b/esp32h2/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_RAW_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_RAW_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_RAW_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_RAW_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_RAW_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_RAW_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/mcpwm0/int_st.rs b/esp32h2/src/mcpwm0/int_st.rs
index 4da0f0e2ca..cc4ed338f8 100644
--- a/esp32h2/src/mcpwm0/int_st.rs
+++ b/esp32h2/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The masked status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - The masked status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - The masked status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - The masked status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - The masked status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - The masked status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - The masked status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - The masked status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - The masked status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - The masked status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - The masked status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - The masked status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0 - The masked status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The masked status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The masked status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The masked status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The masked status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The masked status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The masked status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The masked status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The masked status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The masked status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The masked status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The masked status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32h2/src/mcpwm0/operator_timersel.rs b/esp32h2/src/mcpwm0/operator_timersel.rs
index 3b8f17223e..8b6e17a833 100644
--- a/esp32h2/src/mcpwm0/operator_timersel.rs
+++ b/esp32h2/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "Select specific timer for PWM operators.\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/mcpwm0/timer_synci_cfg.rs b/esp32h2/src/mcpwm0/timer_synci_cfg.rs
index 0ca677dcc7..951c07e8ac 100644
--- a/esp32h2/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32h2/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "Synchronization input selection for three PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/svd/patches/_mcpwm.yml b/esp32h2/svd/patches/_mcpwm.yml
new file mode 100644
index 0000000000..079b7a87ee
--- /dev/null
+++ b/esp32h2/svd/patches/_mcpwm.yml
@@ -0,0 +1,92 @@
+MCPWM0:
+  INT_RAW:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt raw bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt raw bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  INT_ST:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt status bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt status bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  INT_ENA:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt enable bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt enable bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  INT_CLR:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt clear bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt clear bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
\ No newline at end of file
diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml
index 7c4a61fb52..7e8035dc3b 100644
--- a/esp32h2/svd/patches/esp32h2.yaml
+++ b/esp32h2/svd/patches/esp32h2.yaml
@@ -17,6 +17,7 @@ _include:
   - "_ledc.yml"
   - "_lp_wdt.yml"
   - "_pcnt.yml"
+  - "_mcpwm.yml"
   - "_pcr.yml"
   - "_pmu.yml"
   - "_rmt.yml"
@@ -962,7 +963,9 @@ PCR:
   _include: ../../../common_patches/pcr.yaml
 
 MCPWM0:
-  _include: ../../../common_patches/mcpwm_collect.yaml
+  _include:
+    - ../../../common_patches/mcpwm_collect.yaml
+    - ../../../common_patches/mcpwm.yaml
 
 SOC_ETM:
   _include: ../../../common_patches/etm_collect.yaml
diff --git a/esp32p4/src/mcpwm0/cap_ch_cfg.rs b/esp32p4/src/mcpwm0/cap_ch_cfg.rs
index 6e21f7771b..62600b54a9 100644
--- a/esp32p4/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32p4/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP_MODE {}
+#[doc = "Field `CAP_MODE` reader - Describes which edges to trigger a capture event"]
+pub type CAP_MODE_R = crate::FieldReader<CAP_MODE>;
+impl CAP_MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP_MODE {
+        match self.bits {
+            0 => CAP_MODE::None,
+            1 => CAP_MODE::FallingEdge,
+            2 => CAP_MODE::RisingEdge,
+            3 => CAP_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP_MODE::AnyEdge
+    }
+}
+#[doc = "Field `CAP_MODE` writer - Describes which edges to trigger a capture event"]
+pub type CAP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP_MODE, crate::Safe>;
+impl<'a, REG> CAP_MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
@@ -26,10 +109,10 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
-    pub fn mode(&self) -> MODE_R {
-        MODE_R::new(((self.bits >> 1) & 3) as u8)
+    pub fn cap_mode(&self) -> CAP_MODE_R {
+        CAP_MODE_R::new(((self.bits >> 1) & 3) as u8)
     }
     #[doc = "Bits 3:10 - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
     #[inline(always)]
@@ -47,7 +130,7 @@ impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
             .field("en", &self.en())
-            .field("mode", &self.mode())
+            .field("cap_mode", &self.cap_mode())
             .field("prescale", &self.prescale())
             .field("in_invert", &self.in_invert())
             .finish()
@@ -59,10 +142,10 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
-    pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
-        MODE_W::new(self, 1)
+    pub fn cap_mode(&mut self) -> CAP_MODE_W<'_, CAP_CH_CFG_SPEC> {
+        CAP_MODE_W::new(self, 1)
     }
     #[doc = "Bits 3:10 - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/cap_status.rs b/esp32p4/src/mcpwm0/cap_status.rs
index 24f155edae..0f30853f16 100644
--- a/esp32p4/src/mcpwm0/cap_status.rs
+++ b/esp32p4/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0 - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1 - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32p4/src/mcpwm0/int_clr.rs b/esp32p4/src/mcpwm0/int_clr.rs
index 3b8bd0d82b..f381aa3c58 100644
--- a/esp32p4/src/mcpwm0/int_clr.rs
+++ b/esp32p4/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEA` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEB` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_CBC` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_OST` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1 - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2 - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_CLR_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_CLR_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_CLR_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_CLR_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_CLR_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_CLR_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/mcpwm0/int_ena.rs b/esp32p4/src/mcpwm0/int_ena.rs
index 00aee76158..4d4239f276 100644
--- a/esp32p4/src/mcpwm0/int_ena.rs
+++ b/esp32p4/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/mcpwm0/int_raw.rs b/esp32p4/src/mcpwm0/int_raw.rs
index 11724cdacb..1e8a5a8b25 100644
--- a/esp32p4/src/mcpwm0/int_raw.rs
+++ b/esp32p4/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_RAW_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_RAW_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_RAW_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_RAW_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_RAW_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_RAW_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/mcpwm0/int_st.rs b/esp32p4/src/mcpwm0/int_st.rs
index cf415dd0b1..6c30c709bc 100644
--- a/esp32p4/src/mcpwm0/int_st.rs
+++ b/esp32p4/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32p4/src/mcpwm0/operator_timersel.rs b/esp32p4/src/mcpwm0/operator_timersel.rs
index d6b68f19e7..d4c4cfa797 100644
--- a/esp32p4/src/mcpwm0/operator_timersel.rs
+++ b/esp32p4/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - Configures which PWM timer will be the timing reference for PWM operator%s.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - Configures which PWM timer will be the timing reference for PWM operator%s.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[inline(always)]
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
+    }
     #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
     }
     #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
     }
     #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Configures which PWM timer will be the timing reference for PWM operator(0-2).\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
     #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "PWM operator's timer select register\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/mcpwm0/timer_synci_cfg.rs b/esp32p4/src/mcpwm0/timer_synci_cfg.rs
index 1dff734e61..37647b692d 100644
--- a/esp32p4/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32p4/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - Configures the selection of sync input for PWM timer%s.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - Configures the selection of sync input for PWM timer%s.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - Configures whether or not to invert SYNC%s from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - Configures whether or not to invert SYNC%s from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[inline(always)]
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
     #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
     #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
     #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
     #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
     }
     #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
     }
     #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Configures the selection of sync input for PWM timer(0-2).\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
     #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "Configures whether or not to invert SYNC(0-2) from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
     #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "Synchronization input selection register for PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/svd/patches/_mcpwm.yml b/esp32p4/svd/patches/_mcpwm.yml
new file mode 100644
index 0000000000..8e902d6adb
--- /dev/null
+++ b/esp32p4/svd/patches/_mcpwm.yml
@@ -0,0 +1,120 @@
+MCPWM0:
+  CAP_STATUS:
+    _array:
+      CAP?_EDGE:
+        description: Describes the last captured edge on channel%s.
+    CAP?_EDGE:
+      Rising: [0, "Rising edge"]
+      Falling: [1, "Falling edge"]
+
+  CAP_CH%s_CFG:
+    _modify:
+      MODE:
+        description: Describes which edges to trigger a capture event
+        name: CAP_MODE
+    CAP_MODE:
+      None: [0, "Capture nothing"]
+      FallingEdge: [1, "Capture falling edges"]
+      RisingEdge: [2, "Capture rising edges"]
+      AnyEdge: [3, "Capture any edges"]
+
+  TIMER_SYNCI_CFG:
+    _array:
+      TIMER?_SYNCISEL: {}
+      EXTERNAL_SYNCI?_INVERT: {}
+
+  OPERATOR_TIMERSEL:
+    _array:
+      OPERATOR?_TIMERSEL: {}
+
+  INT_RAW:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt raw bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt raw bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  INT_ST:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt status bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt status bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  INT_ENA:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt enable bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt enable bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  INT_CLR:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt clear bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt clear bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
\ No newline at end of file
diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml
index 3a44c79ab0..9a40dac46d 100644
--- a/esp32p4/svd/patches/esp32p4.yaml
+++ b/esp32p4/svd/patches/esp32p4.yaml
@@ -29,6 +29,7 @@ _include:
   - "_pvt.yml"
   - "_rsa.yml"
   - "_sha.yml"
+  - "_mcpwm.yml"
   - "_spi0.yml"
   - "_mmu_item_content.yml"
   - "_mmu_item_index.yml"
diff --git a/esp32s3/src/mcpwm0/cap_ch_cfg.rs b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
index 3dbc408259..c4c19ab17d 100644
--- a/esp32s3/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
@@ -6,10 +6,93 @@ pub type W = crate::W<CAP_CH_CFG_SPEC>;
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - When set, capture on channel 0 is enabled"]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MODE` reader - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
-pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Describes which edges to trigger a capture event\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CAP0_MODE {
+    #[doc = "0: Capture nothing"]
+    None = 0,
+    #[doc = "1: Capture falling edges"]
+    FallingEdge = 1,
+    #[doc = "2: Capture rising edges"]
+    RisingEdge = 2,
+    #[doc = "3: Capture any edges"]
+    AnyEdge = 3,
+}
+impl From<CAP0_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CAP0_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CAP0_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CAP0_MODE {}
+#[doc = "Field `MODE` reader - Describes which edges to trigger a capture event"]
+pub type MODE_R = crate::FieldReader<CAP0_MODE>;
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_MODE {
+        match self.bits {
+            0 => CAP0_MODE::None,
+            1 => CAP0_MODE::FallingEdge,
+            2 => CAP0_MODE::RisingEdge,
+            3 => CAP0_MODE::AnyEdge,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == CAP0_MODE::None
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == CAP0_MODE::FallingEdge
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == CAP0_MODE::RisingEdge
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn is_any_edge(&self) -> bool {
+        *self == CAP0_MODE::AnyEdge
+    }
+}
+#[doc = "Field `MODE` writer - Describes which edges to trigger a capture event"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CAP0_MODE, crate::Safe>;
+impl<'a, REG> MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Capture nothing"]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::None)
+    }
+    #[doc = "Capture falling edges"]
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::FallingEdge)
+    }
+    #[doc = "Capture rising edges"]
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::RisingEdge)
+    }
+    #[doc = "Capture any edges"]
+    #[inline(always)]
+    pub fn any_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(CAP0_MODE::AnyEdge)
+    }
+}
 #[doc = "Field `PRESCALE` reader - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
 pub type PRESCALE_R = crate::FieldReader;
 #[doc = "Field `PRESCALE` writer - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
@@ -26,7 +109,7 @@ impl R {
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new(((self.bits >> 1) & 3) as u8)
@@ -59,7 +142,7 @@ impl W {
     pub fn en(&mut self) -> EN_W<'_, CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[doc = "Bits 1:2 - Describes which edges to trigger a capture event"]
     #[inline(always)]
     pub fn mode(&mut self) -> MODE_W<'_, CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
diff --git a/esp32s3/src/mcpwm0/cap_status.rs b/esp32s3/src/mcpwm0/cap_status.rs
index bca2493ef5..ca0a931292 100644
--- a/esp32s3/src/mcpwm0/cap_status.rs
+++ b/esp32s3/src/mcpwm0/cap_status.rs
@@ -1,26 +1,72 @@
 #[doc = "Register `CAP_STATUS` reader"]
 pub type R = crate::R<CAP_STATUS_SPEC>;
-#[doc = "Field `CAP0_EDGE` reader - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
-pub type CAP0_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP1_EDGE` reader - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
-pub type CAP1_EDGE_R = crate::BitReader;
-#[doc = "Field `CAP2_EDGE` reader - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
-pub type CAP2_EDGE_R = crate::BitReader;
+#[doc = "Describes the last captured edge on channel%s.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAP0_EDGE {
+    #[doc = "0: Rising edge"]
+    Rising = 0,
+    #[doc = "1: Falling edge"]
+    Falling = 1,
+}
+impl From<CAP0_EDGE> for bool {
+    #[inline(always)]
+    fn from(variant: CAP0_EDGE) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CAP_EDGE(0-2)` reader - Describes the last captured edge on channel%s."]
+pub type CAP_EDGE_R = crate::BitReader<CAP0_EDGE>;
+impl CAP_EDGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CAP0_EDGE {
+        match self.bits {
+            false => CAP0_EDGE::Rising,
+            true => CAP0_EDGE::Falling,
+        }
+    }
+    #[doc = "Rising edge"]
+    #[inline(always)]
+    pub fn is_rising(&self) -> bool {
+        *self == CAP0_EDGE::Rising
+    }
+    #[doc = "Falling edge"]
+    #[inline(always)]
+    pub fn is_falling(&self) -> bool {
+        *self == CAP0_EDGE::Falling
+    }
+}
 impl R {
-    #[doc = "Bit 0 - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0_EDGE` field.</div>"]
+    #[inline(always)]
+    pub fn cap_edge(&self, n: u8) -> CAP_EDGE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_EDGE_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Describes the last captured edge on channel(0-2)."]
+    #[inline(always)]
+    pub fn cap_edge_iter(&self) -> impl Iterator<Item = CAP_EDGE_R> + '_ {
+        (0..3).map(move |n| CAP_EDGE_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Describes the last captured edge on channel0."]
     #[inline(always)]
-    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
-        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    pub fn cap0_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 1 - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
+    #[doc = "Bit 1 - Describes the last captured edge on channel1."]
     #[inline(always)]
-    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
-        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cap1_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
+    #[doc = "Bit 2 - Describes the last captured edge on channel2."]
     #[inline(always)]
-    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
-        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cap2_edge(&self) -> CAP_EDGE_R {
+        CAP_EDGE_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32s3/src/mcpwm0/int_clr.rs b/esp32s3/src/mcpwm0/int_clr.rs
index 5c814d5712..5c5391ffcd 100644
--- a/esp32s3/src/mcpwm0/int_clr.rs
+++ b/esp32s3/src/mcpwm0/int_clr.rs
@@ -1,65 +1,25 @@
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `TIMER0_STOP` writer - Set this bit to clear the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_STOP` writer - Set this bit to clear the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_STOP` writer - Set this bit to clear the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER0_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER1_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TIMER2_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0` writer - Set this bit to clear the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1` writer - Set this bit to clear the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2` writer - Set this bit to clear the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT0_CLR` writer - Set this bit to clear the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT1_CLR` writer - Set this bit to clear the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `FAULT2_CLR` writer - Set this bit to clear the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR0_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR1_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CMPR2_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ0_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ1_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `TZ2_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP0` writer - Set this bit to clear the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP1` writer - Set this bit to clear the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
-#[doc = "Field `CAP2` writer - Set this bit to clear the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt clear bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt clear bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt clear bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt clear bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt clear bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt clear bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt clear bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt clear bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt clear bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP(0-2)` writer - The interrupt clear bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -67,155 +27,245 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt clear bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
     }
-    #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 0 - The interrupt clear bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 0)
     }
-    #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 1 - The interrupt clear bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_CLR_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 1)
     }
-    #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 2 - The interrupt clear bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_CLR_SPEC> {
+        TIMER_STOP_W::new(self, 2)
     }
-    #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
     }
-    #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 3 - The interrupt clear bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
     }
-    #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Bit 4 - The interrupt clear bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
     }
-    #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 5 - The interrupt clear bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_CLR_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
     }
-    #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "The interrupt clear bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_CLR_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
     }
-    #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 6 - The interrupt clear bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_CLR_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 6)
     }
-    #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
+    #[doc = "Bit 7 - The interrupt clear bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_CLR_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 8 - The interrupt clear bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_CLR_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_CLR_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
+    #[doc = "The interrupt clear bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 9 - The interrupt clear bit for the fault0 event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 10 - The interrupt clear bit for the fault1 event."]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_CLR_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 11 - The interrupt clear bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_CLR_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "The interrupt clear bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 12 - The interrupt clear bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 13 - The interrupt clear bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 14 - The interrupt clear bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_CLR_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_CLR_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 15 - The interrupt clear bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_CLR_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 16 - The interrupt clear bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_CLR_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 17 - The interrupt clear bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_CLR_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_CLR_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "The interrupt clear bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_CLR_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 18 - The interrupt clear bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_CLR_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Bit 19 - The interrupt clear bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_CLR_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 20 - The interrupt clear bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_CLR_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_CLR_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
+    #[doc = "The interrupt clear bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_CLR_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 21 - The interrupt clear bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_CLR_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The interrupt clear bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The interrupt clear bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_CLR_SPEC> {
+        TZ_CBC_W::new(self, 23)
+    }
+    #[doc = "The interrupt clear bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
+    }
+    #[doc = "Bit 24 - The interrupt clear bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The interrupt clear bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The interrupt clear bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_CLR_SPEC> {
+        TZ_OST_W::new(self, 26)
+    }
+    #[doc = "The interrupt clear bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
+    }
+    #[doc = "Bit 27 - The interrupt clear bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The interrupt clear bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The interrupt clear bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_CLR_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/mcpwm0/int_ena.rs b/esp32s3/src/mcpwm0/int_ena.rs
index a73ac34d34..2bca6aceb3 100644
--- a/esp32s3/src/mcpwm0/int_ena.rs
+++ b/esp32s3/src/mcpwm0/int_ena.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_ENA_SPEC>;
 #[doc = "Register `INT_ENA` writer"]
 pub type W = crate::W<INT_ENA_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The enable bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The enable bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The enable bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The enable bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The enable bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The enable bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The enable bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The enable bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The enable bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The enable bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The enable bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The enable bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt enable bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt enable bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt enable bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt enable bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt enable bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt enable bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt enable bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt enable bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt enable bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt enable bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt enable bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt enable bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt enable bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_ENA_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_ENA_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt enable bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt enable bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_ENA_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt enable bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt enable bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt enable bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt enable bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_ENA_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt enable bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt enable bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt enable bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt enable bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_ENA_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt enable bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt enable bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt enable bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_ENA_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt enable bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt enable bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt enable bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt enable bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_ENA_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt enable bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt enable bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt enable bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_ENA_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt enable bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt enable bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt enable bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt enable bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_ENA_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt enable bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt enable bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt enable bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt enable bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_ENA_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/mcpwm0/int_raw.rs b/esp32s3/src/mcpwm0/int_raw.rs
index a0188a82fd..171d7e95dd 100644
--- a/esp32s3/src/mcpwm0/int_raw.rs
+++ b/esp32s3/src/mcpwm0/int_raw.rs
@@ -2,276 +2,346 @@
 pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Register `INT_RAW` writer"]
 pub type W = crate::W<INT_RAW_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_STOP` writer - The raw status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_STOP` reader - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` writer - The raw status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_STOP` reader - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` writer - The raw status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER0_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER1_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TIMER2_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0` reader - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT0` writer - The raw status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1` reader - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT1` writer - The raw status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2` reader - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT2` writer - The raw status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT0_CLR` reader - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` writer - The raw status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT1_CLR` reader - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` writer - The raw status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `FAULT2_CLR` reader - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` writer - The raw status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR0_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR1_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CMPR2_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ0_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ1_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TZ2_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP0` reader - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP0` writer - The raw status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP1` reader - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP1` writer - The raw status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAP2` reader - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
-#[doc = "Field `CAP2` writer - The raw status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` writer - The interrupt raw bit for the timer%s stop event."]
+pub type TIMER_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` writer - The interrupt raw bit for the timer%s zero event."]
+pub type TIMER_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` writer - The interrupt raw bit for the timer%s period event."]
+pub type TIMER_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt raw bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` writer - The interrupt raw bit for the fault%s event."]
+pub type FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` writer - The interrupt raw bit for the fault%s clear event."]
+pub type FAULT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` writer - The interrupt raw bit for the operator%s compare A event."]
+pub type CMPR_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` writer - The interrupt raw bit for the operator%s compare B event."]
+pub type CMPR_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` writer - The interrupt raw bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` writer - The interrupt raw bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP(0-2)` reader - The interrupt raw bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` writer - The interrupt raw bit for the capture%s event."]
+pub type CAP_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -312,155 +382,245 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt raw bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_stop(&mut self, n: u8) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt raw bit for the timer0 stop event."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt raw bit for the timer1 stop event."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt raw bit for the timer2 stop event."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER_STOP_W<'_, INT_RAW_SPEC> {
+        TIMER_STOP_W::new(self, 2)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tez(&mut self, n: u8) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_W::new(self, n + 3)
+    }
+    #[doc = "Bit 3 - The interrupt raw bit for the timer0 zero event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt raw bit for the timer1 zero event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt raw bit for the timer2 zero event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER_TEZ_W<'_, INT_RAW_SPEC> {
+        TIMER_TEZ_W::new(self, 5)
+    }
+    #[doc = "The interrupt raw bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
+    #[inline(always)]
+    pub fn timer_tep(&mut self, n: u8) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_W::new(self, n + 6)
+    }
+    #[doc = "Bit 6 - The interrupt raw bit for the timer0 period event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt raw bit for the timer1 period event."]
     #[inline(always)]
-    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER0_STOP_W::new(self, 0)
+    pub fn timer1_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 7)
     }
-    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Bit 8 - The interrupt raw bit for the timer2 period event."]
     #[inline(always)]
-    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER1_STOP_W::new(self, 1)
+    pub fn timer2_tep(&mut self) -> TIMER_TEP_W<'_, INT_RAW_SPEC> {
+        TIMER_TEP_W::new(self, 8)
     }
-    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "The interrupt raw bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_RAW_SPEC> {
-        TIMER2_STOP_W::new(self, 2)
+    pub fn fault(&mut self, n: u8) -> FAULT_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_W::new(self, n + 9)
     }
-    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 9 - The interrupt raw bit for the fault0 event."]
     #[inline(always)]
-    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEZ_W::new(self, 3)
+    pub fn fault0(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 9)
     }
-    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 10 - The interrupt raw bit for the fault1 event."]
     #[inline(always)]
-    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEZ_W::new(self, 4)
+    pub fn fault1(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 10)
     }
-    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "Bit 11 - The interrupt raw bit for the fault2 event."]
     #[inline(always)]
-    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEZ_W::new(self, 5)
+    pub fn fault2(&mut self) -> FAULT_W<'_, INT_RAW_SPEC> {
+        FAULT_W::new(self, 11)
     }
-    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "The interrupt raw bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER0_TEP_W::new(self, 6)
+    pub fn fault_clr(&mut self, n: u8) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_W::new(self, n + 12)
     }
-    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 12 - The interrupt raw bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER1_TEP_W::new(self, 7)
+    pub fn fault0_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 12)
     }
-    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 13 - The interrupt raw bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_RAW_SPEC> {
-        TIMER2_TEP_W::new(self, 8)
+    pub fn fault1_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 13)
     }
-    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 14 - The interrupt raw bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn fault0(&mut self) -> FAULT0_W<'_, INT_RAW_SPEC> {
-        FAULT0_W::new(self, 9)
+    pub fn fault2_clr(&mut self) -> FAULT_CLR_W<'_, INT_RAW_SPEC> {
+        FAULT_CLR_W::new(self, 14)
     }
-    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&mut self) -> FAULT1_W<'_, INT_RAW_SPEC> {
-        FAULT1_W::new(self, 10)
+    pub fn cmpr_tea(&mut self, n: u8) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_W::new(self, n + 15)
     }
-    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Bit 15 - The interrupt raw bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn fault2(&mut self) -> FAULT2_W<'_, INT_RAW_SPEC> {
-        FAULT2_W::new(self, 11)
+    pub fn cmpr0_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 15)
     }
-    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 16 - The interrupt raw bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT0_CLR_W::new(self, 12)
+    pub fn cmpr1_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 16)
     }
-    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 17 - The interrupt raw bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT1_CLR_W::new(self, 13)
+    pub fn cmpr2_tea(&mut self) -> CMPR_TEA_W<'_, INT_RAW_SPEC> {
+        CMPR_TEA_W::new(self, 17)
     }
-    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "The interrupt raw bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
     #[inline(always)]
-    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_RAW_SPEC> {
-        FAULT2_CLR_W::new(self, 14)
+    pub fn cmpr_teb(&mut self, n: u8) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_W::new(self, n + 18)
     }
-    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "Bit 18 - The interrupt raw bit for the operator0 compare B event."]
     #[inline(always)]
-    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEA_W::new(self, 15)
+    pub fn cmpr0_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 18)
     }
-    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Bit 19 - The interrupt raw bit for the operator1 compare B event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEA_W::new(self, 16)
+    pub fn cmpr1_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 19)
     }
-    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 20 - The interrupt raw bit for the operator2 compare B event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEA_W::new(self, 17)
+    pub fn cmpr2_teb(&mut self) -> CMPR_TEB_W<'_, INT_RAW_SPEC> {
+        CMPR_TEB_W::new(self, 20)
     }
-    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR0_TEB_W::new(self, 18)
+    pub fn tz_cbc(&mut self, n: u8) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_W::new(self, n + 21)
     }
-    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 21 - The interrupt raw bit for the fault handler0 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR1_TEB_W::new(self, 19)
+    pub fn tz0_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 21)
     }
-    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "Bit 22 - The interrupt raw bit for the fault handler1 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_RAW_SPEC> {
-        CMPR2_TEB_W::new(self, 20)
+    pub fn tz1_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 22)
     }
-    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Bit 23 - The interrupt raw bit for the fault handler2 cycle-by-cycle mode action."]
     #[inline(always)]
-    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_RAW_SPEC> {
-        TZ0_CBC_W::new(self, 21)
+    pub fn tz2_cbc(&mut self) -> TZ_CBC_W<'_, INT_RAW_SPEC> {
+        TZ_CBC_W::new(self, 23)
     }
-    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "The interrupt raw bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
     #[inline(always)]
-    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_RAW_SPEC> {
-        TZ1_CBC_W::new(self, 22)
+    pub fn tz_ost(&mut self, n: u8) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_W::new(self, n + 24)
     }
-    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 24 - The interrupt raw bit for the fault handler0 one-shot mode action."]
     #[inline(always)]
-    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_RAW_SPEC> {
-        TZ2_CBC_W::new(self, 23)
+    pub fn tz0_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 24)
     }
-    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 25 - The interrupt raw bit for the fault handler1 one-shot mode action."]
     #[inline(always)]
-    pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_RAW_SPEC> {
-        TZ0_OST_W::new(self, 24)
+    pub fn tz1_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 25)
     }
-    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "Bit 26 - The interrupt raw bit for the fault handler2 one-shot mode action."]
     #[inline(always)]
-    pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_RAW_SPEC> {
-        TZ1_OST_W::new(self, 25)
+    pub fn tz2_ost(&mut self) -> TZ_OST_W<'_, INT_RAW_SPEC> {
+        TZ_OST_W::new(self, 26)
     }
-    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "The interrupt raw bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
     #[inline(always)]
-    pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_RAW_SPEC> {
-        TZ2_OST_W::new(self, 26)
+    pub fn cap(&mut self, n: u8) -> CAP_W<'_, INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_W::new(self, n + 27)
     }
-    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 27 - The interrupt raw bit for the capture0 event."]
     #[inline(always)]
-    pub fn cap0(&mut self) -> CAP0_W<'_, INT_RAW_SPEC> {
-        CAP0_W::new(self, 27)
+    pub fn cap0(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 27)
     }
-    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 28 - The interrupt raw bit for the capture1 event."]
     #[inline(always)]
-    pub fn cap1(&mut self) -> CAP1_W<'_, INT_RAW_SPEC> {
-        CAP1_W::new(self, 28)
+    pub fn cap1(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 28)
     }
-    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 29 - The interrupt raw bit for the capture2 event."]
     #[inline(always)]
-    pub fn cap2(&mut self) -> CAP2_W<'_, INT_RAW_SPEC> {
-        CAP2_W::new(self, 29)
+    pub fn cap2(&mut self) -> CAP_W<'_, INT_RAW_SPEC> {
+        CAP_W::new(self, 29)
     }
 }
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/mcpwm0/int_st.rs b/esp32s3/src/mcpwm0/int_st.rs
index 4da0f0e2ca..cc4ed338f8 100644
--- a/esp32s3/src/mcpwm0/int_st.rs
+++ b/esp32s3/src/mcpwm0/int_st.rs
@@ -1,215 +1,325 @@
 #[doc = "Register `INT_ST` reader"]
 pub type R = crate::R<INT_ST_SPEC>;
-#[doc = "Field `TIMER0_STOP` reader - The masked status bit for the interrupt triggered when the timer 0 stops."]
-pub type TIMER0_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER1_STOP` reader - The masked status bit for the interrupt triggered when the timer 1 stops."]
-pub type TIMER1_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER2_STOP` reader - The masked status bit for the interrupt triggered when the timer 2 stops."]
-pub type TIMER2_STOP_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
-pub type TIMER0_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
-pub type TIMER1_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
-pub type TIMER2_TEZ_R = crate::BitReader;
-#[doc = "Field `TIMER0_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
-pub type TIMER0_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER1_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
-pub type TIMER1_TEP_R = crate::BitReader;
-#[doc = "Field `TIMER2_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
-pub type TIMER2_TEP_R = crate::BitReader;
-#[doc = "Field `FAULT0` reader - The masked status bit for the interrupt triggered when event_f0 starts."]
-pub type FAULT0_R = crate::BitReader;
-#[doc = "Field `FAULT1` reader - The masked status bit for the interrupt triggered when event_f1 starts."]
-pub type FAULT1_R = crate::BitReader;
-#[doc = "Field `FAULT2` reader - The masked status bit for the interrupt triggered when event_f2 starts."]
-pub type FAULT2_R = crate::BitReader;
-#[doc = "Field `FAULT0_CLR` reader - The masked status bit for the interrupt triggered when event_f0 ends."]
-pub type FAULT0_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT1_CLR` reader - The masked status bit for the interrupt triggered when event_f1 ends."]
-pub type FAULT1_CLR_R = crate::BitReader;
-#[doc = "Field `FAULT2_CLR` reader - The masked status bit for the interrupt triggered when event_f2 ends."]
-pub type FAULT2_CLR_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
-pub type CMPR0_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
-pub type CMPR1_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
-pub type CMPR2_TEA_R = crate::BitReader;
-#[doc = "Field `CMPR0_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
-pub type CMPR0_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR1_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
-pub type CMPR1_TEB_R = crate::BitReader;
-#[doc = "Field `CMPR2_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
-pub type CMPR2_TEB_R = crate::BitReader;
-#[doc = "Field `TZ0_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
-pub type TZ0_CBC_R = crate::BitReader;
-#[doc = "Field `TZ1_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
-pub type TZ1_CBC_R = crate::BitReader;
-#[doc = "Field `TZ2_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
-pub type TZ2_CBC_R = crate::BitReader;
-#[doc = "Field `TZ0_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
-pub type TZ0_OST_R = crate::BitReader;
-#[doc = "Field `TZ1_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
-pub type TZ1_OST_R = crate::BitReader;
-#[doc = "Field `TZ2_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
-pub type TZ2_OST_R = crate::BitReader;
-#[doc = "Field `CAP0` reader - The masked status bit for the interrupt triggered by capture on channel 0."]
-pub type CAP0_R = crate::BitReader;
-#[doc = "Field `CAP1` reader - The masked status bit for the interrupt triggered by capture on channel 1."]
-pub type CAP1_R = crate::BitReader;
-#[doc = "Field `CAP2` reader - The masked status bit for the interrupt triggered by capture on channel 2."]
-pub type CAP2_R = crate::BitReader;
+#[doc = "Field `TIMER_STOP(0-2)` reader - The interrupt status bit for the timer%s stop event."]
+pub type TIMER_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER_TEZ(0-2)` reader - The interrupt status bit for the timer%s zero event."]
+pub type TIMER_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER_TEP(0-2)` reader - The interrupt status bit for the timer%s period event."]
+pub type TIMER_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT(0-2)` reader - The interrupt status bit for the fault%s event."]
+pub type FAULT_R = crate::BitReader;
+#[doc = "Field `FAULT_CLR(0-2)` reader - The interrupt status bit for the fault%s clear event."]
+pub type FAULT_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR_TEA(0-2)` reader - The interrupt status bit for the operator%s compare A event."]
+pub type CMPR_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR_TEB(0-2)` reader - The interrupt status bit for the operator%s compare B event."]
+pub type CMPR_TEB_R = crate::BitReader;
+#[doc = "Field `TZ_CBC(0-2)` reader - The interrupt status bit for the fault handler%s cycle-by-cycle mode action."]
+pub type TZ_CBC_R = crate::BitReader;
+#[doc = "Field `TZ_OST(0-2)` reader - The interrupt status bit for the fault handler%s one-shot mode action."]
+pub type TZ_OST_R = crate::BitReader;
+#[doc = "Field `CAP(0-2)` reader - The interrupt status bit for the capture%s event."]
+pub type CAP_R = crate::BitReader;
 impl R {
-    #[doc = "Bit 0 - The masked status bit for the interrupt triggered when the timer 0 stops."]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_STOP` field.</div>"]
     #[inline(always)]
-    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
-        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    pub fn timer_stop(&self, n: u8) -> TIMER_STOP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_STOP_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - The masked status bit for the interrupt triggered when the timer 1 stops."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) stop event."]
     #[inline(always)]
-    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
-        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn timer_stop_iter(&self) -> impl Iterator<Item = TIMER_STOP_R> + '_ {
+        (0..3).map(move |n| TIMER_STOP_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - The masked status bit for the interrupt triggered when the timer 2 stops."]
+    #[doc = "Bit 0 - The interrupt status bit for the timer0 stop event."]
     #[inline(always)]
-    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
-        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn timer0_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 3 - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[doc = "Bit 1 - The interrupt status bit for the timer1 stop event."]
     #[inline(always)]
-    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
-        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn timer1_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[doc = "Bit 2 - The interrupt status bit for the timer2 stop event."]
     #[inline(always)]
-    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
-        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn timer2_stop(&self) -> TIMER_STOP_R {
+        TIMER_STOP_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 5 - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEZ` field.</div>"]
     #[inline(always)]
-    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
-        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn timer_tez(&self, n: u8) -> TIMER_TEZ_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0)
     }
-    #[doc = "Bit 6 - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) zero event."]
     #[inline(always)]
-    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
-        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    pub fn timer_tez_iter(&self) -> impl Iterator<Item = TIMER_TEZ_R> + '_ {
+        (0..3).map(move |n| TIMER_TEZ_R::new(((self.bits >> (n + 3)) & 1) != 0))
     }
-    #[doc = "Bit 7 - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[doc = "Bit 3 - The interrupt status bit for the timer0 zero event."]
     #[inline(always)]
-    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
-        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    pub fn timer0_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[doc = "Bit 4 - The interrupt status bit for the timer1 zero event."]
     #[inline(always)]
-    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
-        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    pub fn timer1_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 9 - The masked status bit for the interrupt triggered when event_f0 starts."]
+    #[doc = "Bit 5 - The interrupt status bit for the timer2 zero event."]
     #[inline(always)]
-    pub fn fault0(&self) -> FAULT0_R {
-        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn timer2_tez(&self) -> TIMER_TEZ_R {
+        TIMER_TEZ_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 10 - The masked status bit for the interrupt triggered when event_f1 starts."]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_TEP` field.</div>"]
     #[inline(always)]
-    pub fn fault1(&self) -> FAULT1_R {
-        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn timer_tep(&self, n: u8) -> TIMER_TEP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0)
     }
-    #[doc = "Bit 11 - The masked status bit for the interrupt triggered when event_f2 starts."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the timer(0-2) period event."]
     #[inline(always)]
-    pub fn fault2(&self) -> FAULT2_R {
-        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn timer_tep_iter(&self) -> impl Iterator<Item = TIMER_TEP_R> + '_ {
+        (0..3).map(move |n| TIMER_TEP_R::new(((self.bits >> (n + 6)) & 1) != 0))
     }
-    #[doc = "Bit 12 - The masked status bit for the interrupt triggered when event_f0 ends."]
+    #[doc = "Bit 6 - The interrupt status bit for the timer0 period event."]
     #[inline(always)]
-    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
-        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn timer0_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 13 - The masked status bit for the interrupt triggered when event_f1 ends."]
+    #[doc = "Bit 7 - The interrupt status bit for the timer1 period event."]
     #[inline(always)]
-    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
-        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    pub fn timer1_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bit 14 - The masked status bit for the interrupt triggered when event_f2 ends."]
+    #[doc = "Bit 8 - The interrupt status bit for the timer2 period event."]
     #[inline(always)]
-    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
-        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    pub fn timer2_tep(&self) -> TIMER_TEP_R {
+        TIMER_TEP_R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 15 - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0` field.</div>"]
     #[inline(always)]
-    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
-        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    pub fn fault(&self, n: u8) -> FAULT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0)
     }
-    #[doc = "Bit 16 - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) event."]
     #[inline(always)]
-    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
-        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    pub fn fault_iter(&self) -> impl Iterator<Item = FAULT_R> + '_ {
+        (0..3).map(move |n| FAULT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
-    #[doc = "Bit 17 - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[doc = "Bit 9 - The interrupt status bit for the fault0 event."]
     #[inline(always)]
-    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
-        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    pub fn fault0(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 18 - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[doc = "Bit 10 - The interrupt status bit for the fault1 event."]
     #[inline(always)]
-    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
-        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    pub fn fault1(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 19 - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[doc = "Bit 11 - The interrupt status bit for the fault2 event."]
     #[inline(always)]
-    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
-        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    pub fn fault2(&self) -> FAULT_R {
+        FAULT_R::new(((self.bits >> 11) & 1) != 0)
     }
-    #[doc = "Bit 20 - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `FAULT0_CLR` field.</div>"]
     #[inline(always)]
-    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
-        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    pub fn fault_clr(&self, n: u8) -> FAULT_CLR_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0)
     }
-    #[doc = "Bit 21 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault(0-2) clear event."]
     #[inline(always)]
-    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
-        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    pub fn fault_clr_iter(&self) -> impl Iterator<Item = FAULT_CLR_R> + '_ {
+        (0..3).map(move |n| FAULT_CLR_R::new(((self.bits >> (n + 12)) & 1) != 0))
     }
-    #[doc = "Bit 22 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[doc = "Bit 12 - The interrupt status bit for the fault0 clear event."]
     #[inline(always)]
-    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
-        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    pub fn fault0_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 23 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[doc = "Bit 13 - The interrupt status bit for the fault1 clear event."]
     #[inline(always)]
-    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
-        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    pub fn fault1_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 24 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[doc = "Bit 14 - The interrupt status bit for the fault2 clear event."]
     #[inline(always)]
-    pub fn tz0_ost(&self) -> TZ0_OST_R {
-        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    pub fn fault2_clr(&self) -> FAULT_CLR_R {
+        FAULT_CLR_R::new(((self.bits >> 14) & 1) != 0)
     }
-    #[doc = "Bit 25 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEA` field.</div>"]
     #[inline(always)]
-    pub fn tz1_ost(&self) -> TZ1_OST_R {
-        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    pub fn cmpr_tea(&self, n: u8) -> CMPR_TEA_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0)
     }
-    #[doc = "Bit 26 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare A event."]
     #[inline(always)]
-    pub fn tz2_ost(&self) -> TZ2_OST_R {
-        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    pub fn cmpr_tea_iter(&self) -> impl Iterator<Item = CMPR_TEA_R> + '_ {
+        (0..3).map(move |n| CMPR_TEA_R::new(((self.bits >> (n + 15)) & 1) != 0))
     }
-    #[doc = "Bit 27 - The masked status bit for the interrupt triggered by capture on channel 0."]
+    #[doc = "Bit 15 - The interrupt status bit for the operator0 compare A event."]
     #[inline(always)]
-    pub fn cap0(&self) -> CAP0_R {
-        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    pub fn cmpr0_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 15) & 1) != 0)
     }
-    #[doc = "Bit 28 - The masked status bit for the interrupt triggered by capture on channel 1."]
+    #[doc = "Bit 16 - The interrupt status bit for the operator1 compare A event."]
     #[inline(always)]
-    pub fn cap1(&self) -> CAP1_R {
-        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    pub fn cmpr1_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 29 - The masked status bit for the interrupt triggered by capture on channel 2."]
+    #[doc = "Bit 17 - The interrupt status bit for the operator2 compare A event."]
     #[inline(always)]
-    pub fn cap2(&self) -> CAP2_R {
-        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    pub fn cmpr2_tea(&self) -> CMPR_TEA_R {
+        CMPR_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CMPR0_TEB` field.</div>"]
+    #[inline(always)]
+    pub fn cmpr_teb(&self, n: u8) -> CMPR_TEB_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the operator(0-2) compare B event."]
+    #[inline(always)]
+    pub fn cmpr_teb_iter(&self) -> impl Iterator<Item = CMPR_TEB_R> + '_ {
+        (0..3).map(move |n| CMPR_TEB_R::new(((self.bits >> (n + 18)) & 1) != 0))
+    }
+    #[doc = "Bit 18 - The interrupt status bit for the operator0 compare B event."]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The interrupt status bit for the operator1 compare B event."]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The interrupt status bit for the operator2 compare B event."]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR_TEB_R {
+        CMPR_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_CBC` field.</div>"]
+    #[inline(always)]
+    pub fn tz_cbc(&self, n: u8) -> TZ_CBC_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz_cbc_iter(&self) -> impl Iterator<Item = TZ_CBC_R> + '_ {
+        (0..3).map(move |n| TZ_CBC_R::new(((self.bits >> (n + 21)) & 1) != 0))
+    }
+    #[doc = "Bit 21 - The interrupt status bit for the fault handler0 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The interrupt status bit for the fault handler1 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The interrupt status bit for the fault handler2 cycle-by-cycle mode action."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ_CBC_R {
+        TZ_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TZ0_OST` field.</div>"]
+    #[inline(always)]
+    pub fn tz_ost(&self, n: u8) -> TZ_OST_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the fault handler(0-2) one-shot mode action."]
+    #[inline(always)]
+    pub fn tz_ost_iter(&self) -> impl Iterator<Item = TZ_OST_R> + '_ {
+        (0..3).map(move |n| TZ_OST_R::new(((self.bits >> (n + 24)) & 1) != 0))
+    }
+    #[doc = "Bit 24 - The interrupt status bit for the fault handler0 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The interrupt status bit for the fault handler1 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The interrupt status bit for the fault handler2 one-shot mode action."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ_OST_R {
+        TZ_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CAP0` field.</div>"]
+    #[inline(always)]
+    pub fn cap(&self, n: u8) -> CAP_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CAP_R::new(((self.bits >> (n + 27)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt status bit for the capture(0-2) event."]
+    #[inline(always)]
+    pub fn cap_iter(&self) -> impl Iterator<Item = CAP_R> + '_ {
+        (0..3).map(move |n| CAP_R::new(((self.bits >> (n + 27)) & 1) != 0))
+    }
+    #[doc = "Bit 27 - The interrupt status bit for the capture0 event."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The interrupt status bit for the capture1 event."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The interrupt status bit for the capture2 event."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP_R {
+        CAP_R::new(((self.bits >> 29) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
diff --git a/esp32s3/src/mcpwm0/operator_timersel.rs b/esp32s3/src/mcpwm0/operator_timersel.rs
index 3b8f17223e..8b6e17a833 100644
--- a/esp32s3/src/mcpwm0/operator_timersel.rs
+++ b/esp32s3/src/mcpwm0/operator_timersel.rs
@@ -2,33 +2,40 @@
 pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
 #[doc = "Register `OPERATOR_TIMERSEL` writer"]
 pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
-#[doc = "Field `OPERATOR0_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR0_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR1_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR1_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `OPERATOR2_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
-#[doc = "Field `OPERATOR2_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
-pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` reader - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR_TIMERSEL(0-2)` writer - Select which PWM timer's is the timing reference for PWM operator%s, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 impl R {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&self, n: u8) -> OPERATOR_TIMERSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator_timersel_iter(&self) -> impl Iterator<Item = OPERATOR_TIMERSEL_R> + '_ {
+        (0..3).map(move |n| OPERATOR_TIMERSEL_R::new(((self.bits >> (n * 2)) & 3) as u8))
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
-        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    pub fn operator0_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new((self.bits & 3) as u8)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
-        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    pub fn operator1_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
-        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    pub fn operator2_timersel(&self) -> OPERATOR_TIMERSEL_R {
+        OPERATOR_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -42,20 +49,29 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "Select which PWM timer's is the timing reference for PWM operator(0-2), 0: timer0, 1: timer1, 2: timer2"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OPERATOR0_TIMERSEL` field.</div>"]
+    #[inline(always)]
+    pub fn operator_timersel(&mut self, n: u8) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        OPERATOR_TIMERSEL_W::new(self, n * 2)
+    }
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR0_TIMERSEL_W::new(self, 0)
+    pub fn operator0_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR1_TIMERSEL_W::new(self, 2)
+    pub fn operator1_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
-        OPERATOR2_TIMERSEL_W::new(self, 4)
+    pub fn operator2_timersel(&mut self) -> OPERATOR_TIMERSEL_W<'_, OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR_TIMERSEL_W::new(self, 4)
     }
 }
 #[doc = "Select specific timer for PWM operators.\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/mcpwm0/timer_synci_cfg.rs b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
index 0ca677dcc7..951c07e8ac 100644
--- a/esp32s3/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
@@ -2,60 +2,74 @@
 pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
 #[doc = "Register `TIMER_SYNCI_CFG` writer"]
 pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
-#[doc = "Field `TIMER0_SYNCISEL` reader - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER0_SYNCISEL` writer - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER1_SYNCISEL` reader - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER1_SYNCISEL` writer - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `TIMER2_SYNCISEL` reader - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_R = crate::FieldReader;
-#[doc = "Field `TIMER2_SYNCISEL` writer - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
-pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - invert SYNC0 from GPIO matrix"]
-pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - invert SYNC1 from GPIO matrix"]
-pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
-#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - invert SYNC2 from GPIO matrix"]
-pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` reader - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER_SYNCISEL(0-2)` writer - select sync input for PWM timer%s, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` reader - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI_INVERT(0-2)` writer - invert SYNC%s from GPIO matrix"]
+pub type EXTERNAL_SYNCI_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&self, n: u8) -> TIMER_SYNCISEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer_syncisel_iter(&self) -> impl Iterator<Item = TIMER_SYNCISEL_R> + '_ {
+        (0..3).map(move |n| TIMER_SYNCISEL_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
-        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    pub fn timer0_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new((self.bits & 7) as u8)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
-        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    pub fn timer1_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
-        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    pub fn timer2_syncisel(&self) -> TIMER_SYNCISEL_R {
+        TIMER_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(&self, n: u8) -> EXTERNAL_SYNCI_INVERT_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci_invert_iter(&self) -> impl Iterator<Item = EXTERNAL_SYNCI_INVERT_R> + '_ {
+        (0..3).map(move |n| EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> (n + 9)) & 1) != 0))
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
-        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 9) & 1) != 0)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
-        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 10) & 1) != 0)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
-        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI_INVERT_R {
+        EXTERNAL_SYNCI_INVERT_R::new(((self.bits >> 11) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
@@ -72,35 +86,56 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
+    #[doc = "select sync input for PWM timer(0-2), 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_SYNCISEL` field.</div>"]
+    #[inline(always)]
+    pub fn timer_syncisel(&mut self, n: u8) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TIMER_SYNCISEL_W::new(self, n * 3)
+    }
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER0_SYNCISEL_W::new(self, 0)
+    pub fn timer0_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER1_SYNCISEL_W::new(self, 3)
+    pub fn timer1_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        TIMER2_SYNCISEL_W::new(self, 6)
+    pub fn timer2_syncisel(&mut self) -> TIMER_SYNCISEL_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        TIMER_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "invert SYNC(0-2) from GPIO matrix"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `EXTERNAL_SYNCI0_INVERT` field.</div>"]
+    #[inline(always)]
+    pub fn external_synci_invert(
+        &mut self,
+        n: u8,
+    ) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        EXTERNAL_SYNCI_INVERT_W::new(self, n + 9)
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
-        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI_INVERT_W<'_, TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI_INVERT_W::new(self, 11)
     }
 }
 #[doc = "Synchronization input selection for three PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/svd/patches/_mcpwm.yml b/esp32s3/svd/patches/_mcpwm.yml
index 7a3725e4e8..c5e568ebbd 100644
--- a/esp32s3/svd/patches/_mcpwm.yml
+++ b/esp32s3/svd/patches/_mcpwm.yml
@@ -34,3 +34,95 @@ MCPWM0:
         bitOffset: 20
         bitWidth: 1
         access: read-write
+
+  INT_RAW:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt raw bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt raw bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt raw bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt raw bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt raw bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt raw bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt raw bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt raw bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt raw bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt raw bit for the fault handler%s one-shot mode action.
+
+  INT_ST:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt status bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt status bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt status bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt status bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt status bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt status bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt status bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt status bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt status bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt status bit for the fault handler%s one-shot mode action.
+
+  INT_ENA:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt enable bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt enable bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt enable bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt enable bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt enable bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt enable bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt enable bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt enable bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt enable bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt enable bit for the fault handler%s one-shot mode action.
+
+  INT_CLR:
+    _array:
+      TIMER?_STOP:
+        description: The interrupt clear bit for the timer%s stop event.
+      TIMER?_TEZ:
+        description: The interrupt clear bit for the timer%s zero event.
+      TIMER?_TEP:
+        description: The interrupt clear bit for the timer%s period event.
+      FAULT?:
+        description: The interrupt clear bit for the fault%s event.
+      FAULT?_CLR:
+        description: The interrupt clear bit for the fault%s clear event.
+      CAP?:
+        description: The interrupt clear bit for the capture%s event.
+      CMPR?_TEA:
+        description: The interrupt clear bit for the operator%s compare A event.
+      CMPR?_TEB:
+        description: The interrupt clear bit for the operator%s compare B event.
+      TZ?_CBC:
+        description: The interrupt clear bit for the fault handler%s cycle-by-cycle mode action.
+      TZ?_OST:
+        description: The interrupt clear bit for the fault handler%s one-shot mode action.
\ No newline at end of file
diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml
index e2180e5a4c..8e45c7ea66 100644
--- a/esp32s3/svd/patches/esp32s3.yaml
+++ b/esp32s3/svd/patches/esp32s3.yaml
@@ -505,7 +505,9 @@ MCPWM0:
       description: Value of last capture on channel %s
       _strip: CAP?_
 
-  _include: ../../../common_patches/int_strip.yaml
+  _include: 
+    - ../../../common_patches/int_strip.yaml
+    - ../../../common_patches/mcpwm.yaml
 
 USB_FS:
   _include: ../../../common_patches/usb0.yaml