From 47b93a0d7741eda59abd43f310a6dfeed44f93e8 Mon Sep 17 00:00:00 2001 From: CordlessCoder Date: Wed, 29 Jul 2026 09:13:00 +0100 Subject: [PATCH 1/4] Update mspm0-metapac to mspm0-data-f78bc71 chiptool now generates register values in PascalCase rather than SCREAMING_SNAKE, and emits the key/index fieldsets as newtypes carrying associated constants instead of enums. No functional change. --- embassy-mspm0/Cargo.toml | 4 +- embassy-mspm0/build.rs | 4 +- embassy-mspm0/src/adc.rs | 50 +++++++++---------- embassy-mspm0/src/dma.rs | 36 ++++++------- embassy-mspm0/src/gpio.rs | 12 ++--- embassy-mspm0/src/i2c.rs | 50 +++++++++---------- embassy-mspm0/src/i2c_target.rs | 18 +++---- embassy-mspm0/src/lib.rs | 40 +++++++-------- embassy-mspm0/src/low_power/c110x.rs | 4 +- embassy-mspm0/src/low_power/full.rs | 4 +- embassy-mspm0/src/low_power/h321x.rs | 4 +- embassy-mspm0/src/low_power/mod.rs | 4 +- embassy-mspm0/src/mathacl.rs | 24 ++++----- embassy-mspm0/src/sysctl/c1103_1104.rs | 10 ++-- embassy-mspm0/src/sysctl/c1105_1106.rs | 10 ++-- .../src/sysctl/g110x_150x_310x_350x.rs | 12 ++--- embassy-mspm0/src/sysctl/g151x_351x.rs | 12 ++--- embassy-mspm0/src/sysctl/g511x_518x.rs | 12 ++--- embassy-mspm0/src/sysctl/h321x.rs | 10 ++-- embassy-mspm0/src/sysctl/l_typea.rs | 8 +-- embassy-mspm0/src/sysctl/l_typeb.rs | 10 ++-- embassy-mspm0/src/sysctl/mod.rs | 18 +++---- embassy-mspm0/src/time_driver/tim.rs | 18 +++---- embassy-mspm0/src/trng.rs | 44 ++++++++-------- embassy-mspm0/src/uart/mod.rs | 44 ++++++++-------- embassy-mspm0/src/wwdt.rs | 50 +++++++++---------- 26 files changed, 255 insertions(+), 257 deletions(-) diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml index e23582c7f9..1c73fde859 100644 --- a/embassy-mspm0/Cargo.toml +++ b/embassy-mspm0/Cargo.toml @@ -74,7 +74,7 @@ critical-section = "1.2.0" micromath = "2.0.0" # mspm0-metapac = { version = "" } -mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-1da5eda11bf1ae69a604ba62df6242884df15d68" } +mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df" } rand_core = "0.9" # Force no cache padding or the types are too large. maitake-sync = { version = "0.3.0", default-features = false, features = ["critical-section", "no-cache-pad"]} @@ -88,7 +88,7 @@ quote = "1.0.40" cfg_aliases = "0.2.1" # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] } -mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-1da5eda11bf1ae69a604ba62df6242884df15d68", default-features = false, features = ["metadata"] } +mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df", default-features = false, features = ["metadata"] } [features] default = ["rt"] diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs index 856a2e9633..edea53541b 100644 --- a/embassy-mspm0/build.rs +++ b/embassy-mspm0/build.rs @@ -202,11 +202,11 @@ fn generate_groups() -> TokenStream { let stat = group.iidx().read().stat(); // check for spurious interrupts - if stat == crate::pac::cpuss::vals::Iidx::NO_INTR { + if stat == crate::pac::cpuss::vals::Iidx::NoIntr { return; } - // MUST subtract by 1 because NO_INTR offsets IIDX values. + // MUST subtract by 1 because NoIntr offsets IIDX values. let iidx = stat.to_bits() - 1; let Ok(group) = #group_enum::try_from(iidx as u8) else { diff --git a/embassy-mspm0/src/adc.rs b/embassy-mspm0/src/adc.rs index 0c29ecc970..5f5743045f 100644 --- a/embassy-mspm0/src/adc.rs +++ b/embassy-mspm0/src/adc.rs @@ -211,7 +211,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> { }); r.ctl1().modify(|w| { - w.set_sc(vals::Sc::START); + w.set_sc(vals::Sc::Start); }); // Wait for conversion @@ -297,7 +297,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> { }); r.ctl1().modify(|w| { - w.set_sc(vals::Sc::START); + w.set_sc(vals::Sc::Start); }); Self::wait_for_conversion().await; @@ -344,7 +344,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> { }); r.ctl1().modify(|w| { - w.set_sc(vals::Sc::START); + w.set_sc(vals::Sc::Start); }); Self::wait_for_conversion().await; @@ -432,20 +432,20 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> { r.gprcm(0).rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(vals::ResetKey::KEY); + w.set_key(vals::ResetKey::Key); }); r.gprcm(0).pwren().modify(|reg| { reg.set_enable(true); - reg.set_key(vals::PwrenKey::KEY); + reg.set_key(vals::PwrenKey::Key); }); // Wait for power up cortex_m::asm::delay(16); r.gprcm(0).clkcfg().write(|w| { - w.set_key(vals::ClkcfgKey::KEY); - w.set_sampclk(vals::Sampclk::SYSOSC); + w.set_key(vals::ClkcfgKey::Key); + w.set_sampclk(vals::Sampclk::Sysosc); }); // FIXME: Consider clock config @@ -453,20 +453,20 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> { r.ctl0().write(|w| { w.set_enc(false); // TODO: power down config - w.set_pwrdn(vals::Pwrdn::MANUAL); - w.set_sclkdiv(vals::Sclkdiv::DIV_BY_4); + w.set_pwrdn(vals::Pwrdn::Manual); + w.set_sclkdiv(vals::Sclkdiv::DivBy4); }); r.clkfreq().write(|w| { - w.set_frange(vals::Frange::RANGE24TO32); + w.set_frange(vals::Frange::Range24to32); }); r.ctl1().write(|w| { - w.set_trigsrc(vals::Trigsrc::SOFTWARE); - w.set_sc(vals::Sc::STOP); - w.set_conseq(vals::Conseq::SEQUENCE); - w.set_sampmode(vals::Sampmode::AUTO); - w.set_avgn(vals::Avgn::DISABLE); + w.set_trigsrc(vals::Trigsrc::Software); + w.set_sc(vals::Sc::Stop); + w.set_conseq(vals::Conseq::Sequence); + w.set_sampmode(vals::Sampmode::Auto); + w.set_avgn(vals::Avgn::Disable); w.set_avgd(0); }); @@ -477,7 +477,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> { w.set_rstsampcapen(false); w.set_dmaen(false); w.set_fifoen(false); - w.set_sampcnt(vals::Sampcnt::MIN); + w.set_sampcnt(vals::Sampcnt::Min); w.set_startadd(0); w.set_endadd(0); }); @@ -510,7 +510,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> { // TODO: More parameters w.set_avgen(false); w.set_bcsen(false); - w.set_trig(vals::Trig::AUTO_NEXT); + w.set_trig(vals::Trig::AutoNext); w.set_wincomp(false); }); } @@ -576,17 +576,17 @@ trait SealedBorrowedChannel<'a, T> { const fn to_res(resolution: Resolution) -> vals::Res { match resolution { - Resolution::Bits12 => vals::Res::BIT_12, - Resolution::Bits10 => vals::Res::BIT_10, - Resolution::Bits8 => vals::Res::BIT_8, + Resolution::Bits12 => vals::Res::Bit12, + Resolution::Bits10 => vals::Res::Bit10, + Resolution::Bits8 => vals::Res::Bit8, } } const fn from_res(res: vals::Res) -> Resolution { match res { - vals::Res::BIT_12 => Resolution::Bits12, - vals::Res::BIT_10 => Resolution::Bits10, - vals::Res::BIT_8 => Resolution::Bits8, + vals::Res::Bit12 => Resolution::Bits12, + vals::Res::Bit10 => Resolution::Bits10, + vals::Res::Bit8 => Resolution::Bits8, // SAFETY: The HAL will never program an invalid valid. vals::Res::_RESERVED_3 => unsafe { unreachable_unchecked() }, } @@ -594,8 +594,8 @@ const fn from_res(res: vals::Res) -> Resolution { const fn convert_stime(stime: SampleTimeComparator) -> vals::Stime { match stime { - SampleTimeComparator::Scomp0 => vals::Stime::SEL_SCOMP0, - SampleTimeComparator::Scomp1 => vals::Stime::SEL_SCOMP1, + SampleTimeComparator::Scomp0 => vals::Stime::SelScomp0, + SampleTimeComparator::Scomp1 => vals::Stime::SelScomp1, } } diff --git a/embassy-mspm0/src/dma.rs b/embassy-mspm0/src/dma.rs index 1a30094c46..652c74bde9 100644 --- a/embassy-mspm0/src/dma.rs +++ b/embassy-mspm0/src/dma.rs @@ -202,7 +202,7 @@ pub trait Word: SealedWord + 'static { impl SealedWord for u8 { fn width() -> vals::Wdth { - vals::Wdth::BYTE + vals::Wdth::Byte } } impl Word for u8 { @@ -213,7 +213,7 @@ impl Word for u8 { impl SealedWord for u16 { fn width() -> vals::Wdth { - vals::Wdth::HALF + vals::Wdth::Half } } impl Word for u16 { @@ -224,7 +224,7 @@ impl Word for u16 { impl SealedWord for u32 { fn width() -> vals::Wdth { - vals::Wdth::WORD + vals::Wdth::Word } } impl Word for u32 { @@ -235,7 +235,7 @@ impl Word for u32 { impl SealedWord for u64 { fn width() -> vals::Wdth { - vals::Wdth::LONG + vals::Wdth::Long } } impl Word for u64 { @@ -399,17 +399,17 @@ fn verify_transfer(ptr: *const [W]) -> Result<(), Error> { fn convert_burst_size(value: BurstSize) -> vals::Burstsz { match value { - BurstSize::Complete => vals::Burstsz::INFINITI, - BurstSize::_8 => vals::Burstsz::BURST_8, - BurstSize::_16 => vals::Burstsz::BURST_16, - BurstSize::_32 => vals::Burstsz::BURST_32, + BurstSize::Complete => vals::Burstsz::Infiniti, + BurstSize::_8 => vals::Burstsz::Burst8, + BurstSize::_16 => vals::Burstsz::Burst16, + BurstSize::_32 => vals::Burstsz::Burst32, } } fn convert_mode(mode: TransferMode) -> vals::Tm { match mode { - TransferMode::Single => vals::Tm::SINGLE, - TransferMode::Block => vals::Tm::BLOCK, + TransferMode::Single => vals::Tm::Single, + TransferMode::Block => vals::Tm::Block, } } @@ -517,22 +517,22 @@ impl<'d> Channel<'d> { w.set_req(false); // Not every part supports auto enable, so force its value to 0. - w.set_autoen(Autoen::NONE); - w.set_preirq(Preirq::PREIRQ_DISABLE); + w.set_autoen(Autoen::None); + w.set_preirq(Preirq::PreirqDisable); w.set_srcwdth(src_wdth); w.set_dstwdth(dst_wdth); w.set_srcincr(if increment_src { - Incr::INCREMENT + Incr::Increment } else { - Incr::UNCHANGED + Incr::Unchanged }); w.set_dstincr(if increment_dst { - Incr::INCREMENT + Incr::Increment } else { - Incr::UNCHANGED + Incr::Unchanged }); - w.set_em(Em::NORMAL); + w.set_em(Em::Normal); // Single and block will clear the enable bit when the transfers finish. w.set_tm(convert_mode(options.mode)); }); @@ -540,7 +540,7 @@ impl<'d> Channel<'d> { self.tctl().write(|w| { w.set_tsel(trigger_sel); // Basic channels do not implement cross triggering. - w.set_tint(vals::Tint::EXTERNAL); + w.set_tint(vals::Tint::External); }); self.sz().write(|w| { diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs index ebae411945..795b0ddb43 100644 --- a/embassy-mspm0/src/gpio.rs +++ b/embassy-mspm0/src/gpio.rs @@ -318,19 +318,19 @@ impl<'d> Flex<'d> { // Per https://tweedegolf.nl/en/blog/235/debloat-your-async-rust // // We match the async pass-through suggestion to reduce async bloat. - self.wait_inner(Polarity::RISE) + self.wait_inner(Polarity::Rise) } /// Wait for the pin to undergo a transition from high to low. #[inline] pub fn wait_for_falling_edge(&mut self) -> impl Future { - self.wait_inner(Polarity::FALL) + self.wait_inner(Polarity::Fall) } /// Wait for the pin to undergo any transition, i.e low to high OR high to low. #[inline] pub fn wait_for_any_edge(&mut self) -> impl Future { - self.wait_inner(Polarity::RISE_FALL) + self.wait_inner(Polarity::RiseFall) } async fn wait_inner(&mut self, polarity: Polarity) { @@ -1029,17 +1029,17 @@ pub(crate) fn init(gpio: gpio::Gpio) { gpio.gprcm().rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(ResetKey::KEY); + w.set_key(ResetKey::Key); }); gpio.gprcm().pwren().write(|w| { w.set_enable(true); - w.set_key(PwrenKey::KEY); + w.set_key(PwrenKey::Key); }); gpio.evt_mode().modify(|w| { // The CPU will clear it's own interrupts - w.set_cpu_cfg(EvtCfg::SOFTWARE); + w.set_cpu_cfg(EvtCfg::Software); }); } diff --git a/embassy-mspm0/src/i2c.rs b/embassy-mspm0/src/i2c.rs index 28193a1d3a..0ae92779af 100644 --- a/embassy-mspm0/src/i2c.rs +++ b/embassy-mspm0/src/i2c.rs @@ -58,14 +58,14 @@ pub enum ClockDiv { impl ClockDiv { pub(crate) fn into(self) -> vals::Ratio { match self { - Self::DivBy1 => vals::Ratio::DIV_BY_1, - Self::DivBy2 => vals::Ratio::DIV_BY_2, - Self::DivBy3 => vals::Ratio::DIV_BY_3, - Self::DivBy4 => vals::Ratio::DIV_BY_4, - Self::DivBy5 => vals::Ratio::DIV_BY_5, - Self::DivBy6 => vals::Ratio::DIV_BY_6, - Self::DivBy7 => vals::Ratio::DIV_BY_7, - Self::DivBy8 => vals::Ratio::DIV_BY_8, + Self::DivBy1 => vals::Ratio::DivBy1, + Self::DivBy2 => vals::Ratio::DivBy2, + Self::DivBy3 => vals::Ratio::DivBy3, + Self::DivBy4 => vals::Ratio::DivBy4, + Self::DivBy5 => vals::Ratio::DivBy5, + Self::DivBy6 => vals::Ratio::DivBy6, + Self::DivBy7 => vals::Ratio::DivBy7, + Self::DivBy8 => vals::Ratio::DivBy8, } } @@ -406,7 +406,7 @@ impl<'d, M: Mode> I2c<'d, M> { // set up glitch filter self.info.regs.gfctl().modify(|w| { w.set_agfen(false); - w.set_agfsel(vals::Agfsel::AGLIT_50); + w.set_agfsel(vals::Agfsel::Aglit50); w.set_chain(true); }); @@ -436,13 +436,13 @@ impl<'d, M: Mode> I2c<'d, M> { .regs .controller(0) .cfifoctl() - .write(|w| w.set_txtrig(vals::CfifoctlTxtrig::EMPTY)); + .write(|w| w.set_txtrig(vals::CfifoctlTxtrig::Empty)); // Set Rx Fifo threshold, follow TI example self.info .regs .controller(0) .cfifoctl() - .write(|w| w.set_rxtrig(vals::CfifoctlRxtrig::LEVEL_1)); + .write(|w| w.set_rxtrig(vals::CfifoctlRxtrig::Level1)); // Enable controller clock stretching, follow TI example self.info.regs.controller(0).ccr().modify(|w| { @@ -498,8 +498,8 @@ impl<'d, M: Mode> I2c<'d, M> { // is BUSY or I2C is in slave mode. self.info.regs.controller(0).csa().modify(|w| { w.set_taddr(address as u16); - w.set_cmode(vals::Mode::MODE7); - w.set_dir(vals::Dir::RECEIVE); + w.set_cmode(vals::Mode::Mode7); + w.set_dir(vals::Dir::Receive); }); self.info.regs.controller(0).cctr().modify(|w| { @@ -517,8 +517,8 @@ impl<'d, M: Mode> I2c<'d, M> { // Start transfer of length amount of bytes self.info.regs.controller(0).csa().modify(|w| { w.set_taddr(address as u16); - w.set_cmode(vals::Mode::MODE7); - w.set_dir(vals::Dir::TRANSMIT); + w.set_cmode(vals::Mode::Mode7); + w.set_dir(vals::Dir::Transmit); }); self.info.regs.controller(0).cctr().modify(|w| { w.set_cblen(length as u16); @@ -751,10 +751,10 @@ impl<'d> I2c<'d, Async> { self.state.waker.register(cx.waker()); let result = match self.info.regs.cpu_int(0).iidx().read().stat() { - CpuIntIidxStat::NO_INTR => Poll::Pending, - CpuIntIidxStat::CNACKFG => Poll::Ready(Err(Error::Nack)), - CpuIntIidxStat::CARBLOSTFG => Poll::Ready(Err(Error::Arbitration)), - CpuIntIidxStat::CTXDONEFG => Poll::Ready(Ok(())), + CpuIntIidxStat::NoIntr => Poll::Pending, + CpuIntIidxStat::Cnackfg => Poll::Ready(Err(Error::Nack)), + CpuIntIidxStat::Carblostfg => Poll::Ready(Err(Error::Arbitration)), + CpuIntIidxStat::Ctxdonefg => Poll::Ready(Ok(())), _ => Poll::Pending, }; @@ -812,10 +812,10 @@ impl<'d> I2c<'d, Async> { self.state.waker.register(cx.waker()); let result = match self.info.regs.cpu_int(0).iidx().read().stat() { - CpuIntIidxStat::NO_INTR => Poll::Pending, - CpuIntIidxStat::CNACKFG => Poll::Ready(Err(Error::Nack)), - CpuIntIidxStat::CARBLOSTFG => Poll::Ready(Err(Error::Arbitration)), - CpuIntIidxStat::CRXDONEFG => Poll::Ready(Ok(())), + CpuIntIidxStat::NoIntr => Poll::Pending, + CpuIntIidxStat::Cnackfg => Poll::Ready(Err(Error::Nack)), + CpuIntIidxStat::Carblostfg => Poll::Ready(Err(Error::Arbitration)), + CpuIntIidxStat::Crxdonefg => Poll::Ready(Ok(())), _ => Poll::Pending, }; @@ -1054,12 +1054,12 @@ impl<'d, M: Mode> I2c<'d, M> { T::info().regs.gprcm(0).rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(vals::ResetKey::KEY); + w.set_key(vals::ResetKey::Key); }); T::info().regs.gprcm(0).pwren().write(|w| { w.set_enable(true); - w.set_key(vals::PwrenKey::KEY); + w.set_key(vals::PwrenKey::Key); }); // init delay, 16 cycles diff --git a/embassy-mspm0/src/i2c_target.rs b/embassy-mspm0/src/i2c_target.rs index e371fa9033..02498064de 100644 --- a/embassy-mspm0/src/i2c_target.rs +++ b/embassy-mspm0/src/i2c_target.rs @@ -258,12 +258,12 @@ impl<'d, M: Mode> I2cTarget<'d, M> { regs.gprcm(0).rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(vals::ResetKey::KEY); + w.set_key(vals::ResetKey::Key); }); regs.gprcm(0).pwren().write(|w| { w.set_enable(true); - w.set_key(vals::PwrenKey::KEY); + w.set_key(vals::PwrenKey::Key); }); self.info.interrupt.disable(); @@ -349,7 +349,7 @@ impl<'d> I2cTarget<'d, Async> { // Set the rx fifo interrupt to avoid a fifo overflow regs.target(0).tfifoctl().modify(|r| { - r.set_rxtrig(vals::TfifoctlRxtrig::LEVEL_6); + r.set_rxtrig(vals::TfifoctlRxtrig::Level6); }); self.wait_on( @@ -370,13 +370,13 @@ impl<'d> I2cTarget<'d, Async> { } let iidx = regs.cpu_int(0).iidx().read().stat(); - trace!("ls:{} len:{}", iidx as u8, len); + trace!("ls:{} len:{}", iidx.to_bits(), len); let result = match iidx { - CpuIntIidxStat::TTXEMPTY => match len { + CpuIntIidxStat::Ttxempty => match len { 0 => Poll::Ready(Ok(Command::Read)), w => Poll::Ready(Ok(Command::WriteRead(w))), }, - CpuIntIidxStat::TSTOPFG => match (is_gencall, len) { + CpuIntIidxStat::Tstopfg => match (is_gencall, len) { (_, 0) => Poll::Pending, (true, w) => Poll::Ready(Ok(Command::GeneralCall(w))), (false, w) => Poll::Ready(Ok(Command::Write(w))), @@ -423,11 +423,11 @@ impl<'d> I2cTarget<'d, Async> { let iidx = regs.cpu_int(0).iidx().read().stat(); let fifo_bytes = fifo_size - regs.target(0).tfifosr().read().txfifocnt() as usize; - trace!("rs:{}, fifo:{}", iidx as u8, fifo_bytes); + trace!("rs:{}, fifo:{}", iidx.to_bits(), fifo_bytes); let result = match iidx { - CpuIntIidxStat::TTXEMPTY => Poll::Ready(Ok(ReadStatus::NeedMoreBytes)), - CpuIntIidxStat::TSTOPFG => match fifo_bytes { + CpuIntIidxStat::Ttxempty => Poll::Ready(Ok(ReadStatus::NeedMoreBytes)), + CpuIntIidxStat::Tstopfg => match fifo_bytes { 0 => Poll::Ready(Ok(ReadStatus::Done)), w => Poll::Ready(Ok(ReadStatus::LeftoverBytes(w as u16))), }, diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs index 1a8574d7f1..3d4ed4c17e 100644 --- a/embassy-mspm0/src/lib.rs +++ b/embassy-mspm0/src/lib.rs @@ -323,12 +323,12 @@ pub fn read_reset_cause() -> Result { use pac::sysctl::vals::Id; match cause_raw { - Id::NORST => Ok(NoReset), - Id::PORHWFAIL => Ok(PorHwFailure), - Id::POREXNRST => Ok(PorExternalNrst), - Id::PORSW => Ok(PorSwTriggered), - Id::BORSUPPLY => Ok(BorSupplyFailure), - Id::BORWAKESHUTDN => Ok(BorWakeFromShutdown), + Id::Norst => Ok(NoReset), + Id::Porhwfail => Ok(PorHwFailure), + Id::Porexnrst => Ok(PorExternalNrst), + Id::Porsw => Ok(PorSwTriggered), + Id::Borsupply => Ok(BorSupplyFailure), + Id::Borwakeshutdn => Ok(BorWakeFromShutdown), #[cfg(not(any( mspm0c110x, mspm0c1105_c1106, @@ -340,22 +340,22 @@ pub fn read_reset_cause() -> Result { mspm0g351x, mspm0g518x, )))] - Id::BOOTNONPMUPARITY => Ok(BootrstNonPmuParityFault), - Id::BOOTCLKFAIL => Ok(BootrstClockFault), - Id::BOOTSW => Ok(BootrstSwTriggered), - Id::BOOTEXNRST => Ok(BootrstExternalNrst), - Id::BOOTWWDT0 => Ok(BootrstWwdt0Violation), - Id::SYSBSLEXIT => Ok(SysrstBslExit), - Id::SYSBSLENTRY => Ok(SysrstBslEntry), + Id::Bootnonpmuparity => Ok(BootrstNonPmuParityFault), + Id::Bootclkfail => Ok(BootrstClockFault), + Id::Bootsw => Ok(BootrstSwTriggered), + Id::Bootexnrst => Ok(BootrstExternalNrst), + Id::Bootwwdt0 => Ok(BootrstWwdt0Violation), + Id::Sysbslexit => Ok(SysrstBslExit), + Id::Sysbslentry => Ok(SysrstBslEntry), #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0g518x))] - Id::SYSWWDT1 => Ok(SysrstWwdt1Violation), + Id::Syswwdt1 => Ok(SysrstWwdt1Violation), #[cfg(not(any(mspm0c110x, mspm0c1105_c1106, mspm0g351x, mspm0g151x)))] - Id::SYSFLASHECC => Ok(SysrstFlashEccError), - Id::SYSCPULOCK => Ok(SysrstCpuLockupViolation), - Id::SYSDBG => Ok(SysrstDebugTriggered), - Id::SYSSW => Ok(SysrstSwTriggered), - Id::CPUDBG => Ok(CpurstDebugTriggered), - Id::CPUSW => Ok(CpurstSwTriggered), + Id::Sysflashecc => Ok(SysrstFlashEccError), + Id::Syscpulock => Ok(SysrstCpuLockupViolation), + Id::Sysdbg => Ok(SysrstDebugTriggered), + Id::Syssw => Ok(SysrstSwTriggered), + Id::Cpudbg => Ok(CpurstDebugTriggered), + Id::Cpusw => Ok(CpurstSwTriggered), other => Err(other as u8), } } diff --git a/embassy-mspm0/src/low_power/c110x.rs b/embassy-mspm0/src/low_power/c110x.rs index af1988c879..9be6f29f49 100644 --- a/embassy-mspm0/src/low_power/c110x.rs +++ b/embassy-mspm0/src/low_power/c110x.rs @@ -39,8 +39,8 @@ pub unsafe fn enter_sleep(_cs: CriticalSection, mode: SleepMode) { let sysctl = pac::SYSCTL; let dsleep = match mode { - SleepMode::Stop0 | SleepMode::Stop2 => Dsleep::STOP, - SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::STANDBY, + SleepMode::Stop0 | SleepMode::Stop2 => Dsleep::Stop, + SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::Standby, }; sysctl.pmodecfg().modify(|w| w.set_dsleep(dsleep)); diff --git a/embassy-mspm0/src/low_power/full.rs b/embassy-mspm0/src/low_power/full.rs index 37deeaf810..301eff683d 100644 --- a/embassy-mspm0/src/low_power/full.rs +++ b/embassy-mspm0/src/low_power/full.rs @@ -41,8 +41,8 @@ pub unsafe fn enter_sleep(_cs: CriticalSection, mode: SleepMode) { let sysctl = pac::SYSCTL; let dsleep = match mode { - SleepMode::Stop0 | SleepMode::Stop1 | SleepMode::Stop2 => Dsleep::STOP, - SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::STANDBY, + SleepMode::Stop0 | SleepMode::Stop1 | SleepMode::Stop2 => Dsleep::Stop, + SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::Standby, }; sysctl.pmodecfg().modify(|w| w.set_dsleep(dsleep)); diff --git a/embassy-mspm0/src/low_power/h321x.rs b/embassy-mspm0/src/low_power/h321x.rs index a7b9fb9c49..6887b19ba8 100644 --- a/embassy-mspm0/src/low_power/h321x.rs +++ b/embassy-mspm0/src/low_power/h321x.rs @@ -38,8 +38,8 @@ pub unsafe fn enter_sleep(_cs: CriticalSection, mode: SleepMode) { let sysctl = pac::SYSCTL; let dsleep = match mode { - SleepMode::Stop0 | SleepMode::Stop2 => Dsleep::STOP, - SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::STANDBY, + SleepMode::Stop0 | SleepMode::Stop2 => Dsleep::Stop, + SleepMode::Standby0 | SleepMode::Standby1 => Dsleep::Standby, }; sysctl.pmodecfg().modify(|w| w.set_dsleep(dsleep)); diff --git a/embassy-mspm0/src/low_power/mod.rs b/embassy-mspm0/src/low_power/mod.rs index f3d2199443..b7d220069f 100644 --- a/embassy-mspm0/src/low_power/mod.rs +++ b/embassy-mspm0/src/low_power/mod.rs @@ -147,7 +147,7 @@ pub unsafe fn sleep(cs: CriticalSection) { // then `WFI`. This is identical across every MSPM0 family. pub fn shutdown(_cs: CriticalSection) -> ! { let sysctl = pac::SYSCTL; - sysctl.pmodecfg().modify(|w| w.set_dsleep(Dsleep::SHUTDOWN)); + sysctl.pmodecfg().modify(|w| w.set_dsleep(Dsleep::Shutdown)); let _prefetch = PrefetchSuspend::new(); @@ -169,7 +169,7 @@ impl PrefetchSuspend { fn new() -> Self { let saved = pac::CPUSS.ctl().read(); let mut disabled = saved; - disabled.set_prefetch(Prefetch::DISABLE); + disabled.set_prefetch(Prefetch::Disable); pac::CPUSS.ctl().write_value(disabled); // CPU_ERR_02 means the prefetcher will not be disabled until pending flash access is finished. diff --git a/embassy-mspm0/src/mathacl.rs b/embassy-mspm0/src/mathacl.rs index e79e099be1..636e933c57 100644 --- a/embassy-mspm0/src/mathacl.rs +++ b/embassy-mspm0/src/mathacl.rs @@ -42,15 +42,15 @@ impl<'d> Mathacl<'d> { pub fn new(_instance: Peri<'d, T>) -> Self { // Init power T::regs().gprcm(0).rstctl().write(|w| { - w.set_resetstkyclr(vals::Resetstkyclr::CLR); - w.set_resetassert(vals::Resetassert::ASSERT); - w.set_key(vals::ResetKey::KEY); + w.set_resetstkyclr(vals::Resetstkyclr::Clr); + w.set_resetassert(vals::Resetassert::Assert); + w.set_key(vals::ResetKey::Key); }); // Enable power T::regs().gprcm(0).pwren().write(|w| { w.set_enable(true); - w.set_key(vals::PwrenKey::KEY); + w.set_key(vals::PwrenKey::Key); }); // init delay, 16 cycles @@ -72,7 +72,7 @@ impl<'d> Mathacl<'d> { let native = self.div_iq(IQType::from_f32(rad, 15, true)?, IQType::from_f32(PI, 15, true)?)?; self.regs.ctl().write(|w| { - w.set_func(vals::Func::SINCOS); + w.set_func(vals::Func::Sincos); w.set_numiter(precision as u8); }); @@ -82,7 +82,7 @@ impl<'d> Mathacl<'d> { }); // check if done - while self.regs.status().read().busy() == vals::Busy::NOTDONE {} + while self.regs.status().read().busy() == vals::Busy::Notdone {} match sin { true => Ok(IQType::from_reg(self.regs.res2().read().data(), 0, true) @@ -113,7 +113,7 @@ impl<'d> Mathacl<'d> { let signed = true; self.regs.ctl().write(|w| { - w.set_func(vals::Func::DIV); + w.set_func(vals::Func::Div); w.set_optype(signed); }); @@ -126,7 +126,7 @@ impl<'d> Mathacl<'d> { }); // check if done - while self.regs.status().read().busy() == vals::Busy::NOTDONE {} + while self.regs.status().read().busy() == vals::Busy::Notdone {} // read quotient Ok(self.regs.res1().read().data() as i32) @@ -141,7 +141,7 @@ impl<'d> Mathacl<'d> { let signed = false; self.regs.ctl().write(|w| { - w.set_func(vals::Func::DIV); + w.set_func(vals::Func::Div); w.set_optype(signed); }); @@ -154,7 +154,7 @@ impl<'d> Mathacl<'d> { }); // check if done - while self.regs.status().read().busy() == vals::Busy::NOTDONE {} + while self.regs.status().read().busy() == vals::Busy::Notdone {} // read quotient Ok(self.regs.res1().read().data()) @@ -178,7 +178,7 @@ impl<'d> Mathacl<'d> { } self.regs.ctl().write(|w| { - w.set_func(vals::Func::DIV); + w.set_func(vals::Func::Div); w.set_optype(dividend.signed); w.set_qval(dividend.f_bits.into()); }); @@ -192,7 +192,7 @@ impl<'d> Mathacl<'d> { }); // check if done - while self.regs.status().read().busy() == vals::Busy::NOTDONE {} + while self.regs.status().read().busy() == vals::Busy::Notdone {} // read quotient return Ok( diff --git a/embassy-mspm0/src/sysctl/c1103_1104.rs b/embassy-mspm0/src/sysctl/c1103_1104.rs index a841bf4875..dbcca47556 100644 --- a/embassy-mspm0/src/sysctl/c1103_1104.rs +++ b/embassy-mspm0/src/sysctl/c1103_1104.rs @@ -47,12 +47,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, // FIXME: Wrong name from SVD - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, } } } diff --git a/embassy-mspm0/src/sysctl/c1105_1106.rs b/embassy-mspm0/src/sysctl/c1105_1106.rs index 47e71c405a..262fc2147a 100644 --- a/embassy-mspm0/src/sysctl/c1105_1106.rs +++ b/embassy-mspm0/src/sysctl/c1105_1106.rs @@ -47,12 +47,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, // FIXME: Wrong name from SVD - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, } } } diff --git a/embassy-mspm0/src/sysctl/g110x_150x_310x_350x.rs b/embassy-mspm0/src/sysctl/g110x_150x_310x_350x.rs index cf3bf55735..ab60c57ee4 100644 --- a/embassy-mspm0/src/sysctl/g110x_150x_310x_350x.rs +++ b/embassy-mspm0/src/sysctl/g110x_150x_310x_350x.rs @@ -53,12 +53,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, - ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, + ClkOutSource::SysPllClk1(_) => vals::Exclksrc::Syspllout1, } } } diff --git a/embassy-mspm0/src/sysctl/g151x_351x.rs b/embassy-mspm0/src/sysctl/g151x_351x.rs index 5f078af89a..6a3ccbfef0 100644 --- a/embassy-mspm0/src/sysctl/g151x_351x.rs +++ b/embassy-mspm0/src/sysctl/g151x_351x.rs @@ -53,12 +53,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, - ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, + ClkOutSource::SysPllClk1(_) => vals::Exclksrc::Syspllout1, } } } diff --git a/embassy-mspm0/src/sysctl/g511x_518x.rs b/embassy-mspm0/src/sysctl/g511x_518x.rs index eeb2716641..4de49a73f1 100644 --- a/embassy-mspm0/src/sysctl/g511x_518x.rs +++ b/embassy-mspm0/src/sysctl/g511x_518x.rs @@ -59,12 +59,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, - ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, + ClkOutSource::SysPllClk1(_) => vals::Exclksrc::Syspllout1, // FIXME: Update SVD to define _RESERVED_6 as USBFLL ClkOutSource::UsbFll(_) => vals::Exclksrc::_RESERVED_6, } diff --git a/embassy-mspm0/src/sysctl/h321x.rs b/embassy-mspm0/src/sysctl/h321x.rs index 4a4ca72ae7..fffe53c988 100644 --- a/embassy-mspm0/src/sysctl/h321x.rs +++ b/embassy-mspm0/src/sysctl/h321x.rs @@ -47,12 +47,12 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, // FIXME: Wrong name from SVD - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, } } } diff --git a/embassy-mspm0/src/sysctl/l_typea.rs b/embassy-mspm0/src/sysctl/l_typea.rs index e52b21550e..aed84ab219 100644 --- a/embassy-mspm0/src/sysctl/l_typea.rs +++ b/embassy-mspm0/src/sysctl/l_typea.rs @@ -41,10 +41,10 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, } } } diff --git a/embassy-mspm0/src/sysctl/l_typeb.rs b/embassy-mspm0/src/sysctl/l_typeb.rs index caf35d483d..474f05b773 100644 --- a/embassy-mspm0/src/sysctl/l_typeb.rs +++ b/embassy-mspm0/src/sysctl/l_typeb.rs @@ -47,11 +47,11 @@ impl ClkOutSource { pub(super) fn convert_src(self) -> vals::Exclksrc { match self { - ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC, - ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK, - ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK, - ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK, - ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK, + ClkOutSource::Sysosc(_) => vals::Exclksrc::Sysosc, + ClkOutSource::UlpClk(_) => vals::Exclksrc::Ulpclk, + ClkOutSource::LfClk(_) => vals::Exclksrc::Lfclk, + ClkOutSource::MfpClk(_) => vals::Exclksrc::Mfpclk, + ClkOutSource::Hfclk(_) => vals::Exclksrc::Hfclk, } } } diff --git a/embassy-mspm0/src/sysctl/mod.rs b/embassy-mspm0/src/sysctl/mod.rs index d0a7085fdb..41bc48a7e8 100644 --- a/embassy-mspm0/src/sysctl/mod.rs +++ b/embassy-mspm0/src/sysctl/mod.rs @@ -248,15 +248,15 @@ macro_rules! impl_clk_out_pin { /// (DIVEN, DIVVAL) fn div_to_pac(div: Option) -> (bool, vals::Exclkdivval) { match div { - Some(ClkOutDiv::Div2) => (true, vals::Exclkdivval::DIV2), - Some(ClkOutDiv::Div4) => (true, vals::Exclkdivval::DIV4), - Some(ClkOutDiv::Div6) => (true, vals::Exclkdivval::DIV6), - Some(ClkOutDiv::Div8) => (true, vals::Exclkdivval::DIV8), - Some(ClkOutDiv::Div10) => (true, vals::Exclkdivval::DIV10), - Some(ClkOutDiv::Div12) => (true, vals::Exclkdivval::DIV12), - Some(ClkOutDiv::Div14) => (true, vals::Exclkdivval::DIV14), - Some(ClkOutDiv::Div16) => (true, vals::Exclkdivval::DIV16), + Some(ClkOutDiv::Div2) => (true, vals::Exclkdivval::Div2), + Some(ClkOutDiv::Div4) => (true, vals::Exclkdivval::Div4), + Some(ClkOutDiv::Div6) => (true, vals::Exclkdivval::Div6), + Some(ClkOutDiv::Div8) => (true, vals::Exclkdivval::Div8), + Some(ClkOutDiv::Div10) => (true, vals::Exclkdivval::Div10), + Some(ClkOutDiv::Div12) => (true, vals::Exclkdivval::Div12), + Some(ClkOutDiv::Div14) => (true, vals::Exclkdivval::Div14), + Some(ClkOutDiv::Div16) => (true, vals::Exclkdivval::Div16), // divider is ignored. set to default value - None => (false, vals::Exclkdivval::DIV2), + None => (false, vals::Exclkdivval::Div2), } } diff --git a/embassy-mspm0/src/time_driver/tim.rs b/embassy-mspm0/src/time_driver/tim.rs index b006366f4a..0783c8fdcc 100644 --- a/embassy-mspm0/src/time_driver/tim.rs +++ b/embassy-mspm0/src/time_driver/tim.rs @@ -100,14 +100,14 @@ impl TimxDriver { // Reset timer regs.gprcm(0).rstctl().write(|w| { w.set_resetassert(true); - w.set_key(ResetKey::KEY); + w.set_key(ResetKey::Key); w.set_resetstkyclr(true); }); // Power up timer regs.gprcm(0).pwren().write(|w| { w.set_enable(true); - w.set_key(PwrenKey::KEY); + w.set_key(PwrenKey::Key); }); // Following the instructions according to SLAU847D 23.2.1: TIMCLK Configuration @@ -139,9 +139,9 @@ impl TimxDriver { }); regs.counterregs(0).ctrctl().modify(|w| { - w.set_repeat(Repeat::REPEAT_1); - w.set_cvae(Cvae::NOCHANGE); - w.set_cm(Cm::UP); + w.set_repeat(Repeat::Repeat1); + w.set_cvae(Cvae::Nochange); + w.set_cm(Cm::Up); // Must explicitly set CZC, CAC and CLC to 0 in order for all the timers to count. // @@ -150,9 +150,9 @@ impl TimxDriver { // Looking at a bit representation of the reset value, this appears to be an AND // of 2-input QEI mode and CCCTL_3 ACOND. Given that TIMG14 and TIMA0 have no QEI // and 4 capture and compare channels, this works by accident for those timer units. - w.set_czc(CxC::CCTL0); - w.set_cac(CxC::CCTL0); - w.set_clc(CxC::CCTL0); + w.set_czc(CxC::Cctl0); + w.set_cac(CxC::Cctl0); + w.set_clc(CxC::Cctl0); }); // Middle @@ -165,7 +165,7 @@ impl TimxDriver { // // This does not appear to ever be set for CPU_INT in the TI SDK and is not technically needed. regs.evt_mode().modify(|w| { - w.set_evt_cfg(0, EvtCfg::SOFTWARE); + w.set_evt_cfg(0, EvtCfg::Software); }); regs.cpu_int(0).imask().modify(|w| { diff --git a/embassy-mspm0/src/trng.rs b/embassy-mspm0/src/trng.rs index 3b520976ba..6fde0529cb 100644 --- a/embassy-mspm0/src/trng.rs +++ b/embassy-mspm0/src/trng.rs @@ -60,9 +60,9 @@ impl sealed::Sealed for FastDecimRate {} impl Into for FastDecimRate { fn into(self) -> vals::DecimRate { match self { - Self::Decim1 => vals::DecimRate::DECIM_1, - Self::Decim2 => vals::DecimRate::DECIM_2, - Self::Decim3 => vals::DecimRate::DECIM_3, + Self::Decim1 => vals::DecimRate::Decim1, + Self::Decim2 => vals::DecimRate::Decim2, + Self::Decim3 => vals::DecimRate::Decim3, } } } @@ -84,11 +84,11 @@ impl sealed::Sealed for CryptoDecimRate {} impl Into for CryptoDecimRate { fn into(self) -> vals::DecimRate { match self { - Self::Decim4 => vals::DecimRate::DECIM_4, - Self::Decim5 => vals::DecimRate::DECIM_5, - Self::Decim6 => vals::DecimRate::DECIM_6, - Self::Decim7 => vals::DecimRate::DECIM_7, - Self::Decim8 => vals::DecimRate::DECIM_8, + Self::Decim4 => vals::DecimRate::Decim4, + Self::Decim5 => vals::DecimRate::Decim5, + Self::Decim6 => vals::DecimRate::Decim6, + Self::Decim7 => vals::DecimRate::Decim7, + Self::Decim8 => vals::DecimRate::Decim8, } } } @@ -303,7 +303,7 @@ impl TrngInner<'_> { fn fail_reset(&mut self) -> Result<(), Error> { regs().iclr().write(|w| w.set_irq_health_fail(true)); - self.set_cmd(PWR_OFF); + self.set_cmd(PwrOff); self.init() } @@ -311,32 +311,32 @@ impl TrngInner<'_> { // L-series TRM 13.2.5.2 self.set_div(); // 2. Set the clock divider. regs().imask().write_value(Int::default()); // 3. Disable all interrupts. - self.set_cmd(NORM_FUNC); // 4. Set to normal function mode. + self.set_cmd(NormFunc); // 4. Set to normal function mode. self.dig_test()?; // 5. Perform digital block start-up self-tests. self.ana_test()?; // 6. Perform analog block start-up self-test. self.clr_rdy(); // 7.a Clear IRQ_CAPTURED_RDY_IRQ. self.set_decim_rate(); // 7.b Set decimation rate. - self.set_cmd(NORM_FUNC); // 7.b Set to normal function mode again after changing decimation rate. + self.set_cmd(NormFunc); // 7.b Set to normal function mode again after changing decimation rate. _ = self.read(); // 8. By 13.2.4.1, must discard first value. Ok(()) } fn reset(&mut self) { regs().gprcm().rstctl().write(|w| { - w.set_key(RstctlKey::KEY); + w.set_key(RstctlKey::Key); w.set_resetassert(true); }); } fn power_on(&mut self) { regs().gprcm().pwren().write(|w| { - w.set_key(PwrenKey::KEY); + w.set_key(PwrenKey::Key); w.set_enable(true); }); } fn power_off(&mut self) { - regs().gprcm().pwren().write(|w| w.set_key(PwrenKey::KEY)); + regs().gprcm().pwren().write(|w| w.set_key(PwrenKey::Key)); } fn set_div(&mut self) { @@ -345,15 +345,15 @@ impl TrngInner<'_> { let ratio = if freq > 160_000_000 { panic!("MCLK frequency {} > 160 MHz is not compatible with the TRNG", freq) } else if freq >= 80_000_000 { - Ratio::DIV_BY_8 + Ratio::DivBy8 } else if freq >= 60_000_000 { - Ratio::DIV_BY_6 + Ratio::DivBy6 } else if freq >= 40_000_000 { - Ratio::DIV_BY_4 + Ratio::DivBy4 } else if freq >= 20_000_000 { - Ratio::DIV_BY_2 + Ratio::DivBy2 } else if freq >= 9_500_000 { - Ratio::DIV_BY_1 + Ratio::DivBy1 } else { panic!("MCLK frequency {} < 9.5 MHz is not compatible with the TRNG", freq) }; @@ -375,7 +375,7 @@ impl TrngInner<'_> { } fn dig_test(&mut self) -> Result<(), Error> { - self.set_cmd(PWRUP_DIG); + self.set_cmd(PwrupDig); let results = regs().test_results().read(); for n in 0..8u8 { // 13.2.4.1: Digital tests must pass. @@ -389,10 +389,10 @@ impl TrngInner<'_> { fn ana_test(&mut self) -> Result<(), Error> { // 13.2.4.2: Analog tests have a small chance to fail, so try up to 3 times. for _ in 0..3 { - self.set_cmd(PWRUP_ANA); + self.set_cmd(PwrupAna); let results = regs().test_results().read(); if !results.ana_test() { - self.set_cmd(PWR_OFF); + self.set_cmd(PwrOff); } else { return Ok(()); } diff --git a/embassy-mspm0/src/uart/mod.rs b/embassy-mspm0/src/uart/mod.rs index 03e68d297e..d05b326e35 100644 --- a/embassy-mspm0/src/uart/mod.rs +++ b/embassy-mspm0/src/uart/mod.rs @@ -732,12 +732,12 @@ fn enable(regs: Regs) { gprcm.rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(vals::ResetKey::KEY); + w.set_key(vals::ResetKey::Key); }); gprcm.pwren().write(|w| { w.set_enable(true); - w.set_key(vals::PwrenKey::KEY); + w.set_key(vals::PwrenKey::Key); }); } @@ -784,7 +784,7 @@ fn configure( w.set_txe(enable_tx); // RXD_OUT_EN and TXD_OUT_EN? w.set_menc(false); - w.set_mode(vals::Mode::UART); + w.set_mode(vals::Mode::Uart); w.set_rtsen(enable_rts); w.set_ctsen(enable_cts); // oversampling is set later @@ -796,22 +796,22 @@ fn configure( info.regs.ifls().modify(|w| { // TODO: Need power domain info for other options. - w.set_txiflsel(vals::Iflssel::AT_LEAST_ONE); - w.set_rxiflsel(vals::Iflssel::AT_LEAST_ONE); + w.set_txiflsel(vals::Iflssel::AtLeastOne); + w.set_rxiflsel(vals::Iflssel::AtLeastOne); }); info.regs.lcrh().modify(|w| { let eps = if matches!(config.parity, Parity::ParityEven) { - vals::Eps::EVEN + vals::Eps::Even } else { - vals::Eps::ODD + vals::Eps::Odd }; let wlen = match config.data_bits { - DataBits::DataBits5 => vals::Wlen::DATABIT5, - DataBits::DataBits6 => vals::Wlen::DATABIT6, - DataBits::DataBits7 => vals::Wlen::DATABIT7, - DataBits::DataBits8 => vals::Wlen::DATABIT8, + DataBits::DataBits5 => vals::Wlen::Databit5, + DataBits::DataBits6 => vals::Wlen::Databit6, + DataBits::DataBits7 => vals::Wlen::Databit7, + DataBits::DataBits8 => vals::Wlen::Databit8, }; // Used in LIN mode only @@ -890,14 +890,14 @@ fn set_baudrate_inner(regs: Regs, clock: u32, baudrate: u32) -> Result<(), Confi const MAX_FBRD: u8 = 2_u8.pow(6); const DIVS: [(u8, vals::Clkdiv); 8] = [ - (1, vals::Clkdiv::DIV_BY_1), - (2, vals::Clkdiv::DIV_BY_2), - (3, vals::Clkdiv::DIV_BY_3), - (4, vals::Clkdiv::DIV_BY_4), - (5, vals::Clkdiv::DIV_BY_5), - (6, vals::Clkdiv::DIV_BY_6), - (7, vals::Clkdiv::DIV_BY_7), - (8, vals::Clkdiv::DIV_BY_8), + (1, vals::Clkdiv::DivBy1), + (2, vals::Clkdiv::DivBy2), + (3, vals::Clkdiv::DivBy3), + (4, vals::Clkdiv::DivBy4), + (5, vals::Clkdiv::DivBy5), + (6, vals::Clkdiv::DivBy6), + (7, vals::Clkdiv::DivBy7), + (8, vals::Clkdiv::DivBy8), ]; // Quoting from SLAU 846 section 18.2.3.4: @@ -910,19 +910,19 @@ fn set_baudrate_inner(regs: Regs, clock: u32, baudrate: u32) -> Result<(), Confi // Based on these requirements, prioritize higher oversampling first to increase tolerance to clock // deviation. If no valid BRD value can be found satisifying the highest sample rate, then reduce // sample rate until valid parameters are found. - const OVS: [(u8, vals::Hse); 3] = [(16, vals::Hse::OVS16), (8, vals::Hse::OVS8), (3, vals::Hse::OVS3)]; + const OVS: [(u8, vals::Hse); 3] = [(16, vals::Hse::Ovs16), (8, vals::Hse::Ovs8), (3, vals::Hse::Ovs3)]; // 3x oversampling is not supported with manchester coding, DALI or IrDA. let x3_invalid = { let ctl0 = regs.ctl0().read(); let irctl = regs.irctl().read(); - ctl0.menc() || matches!(ctl0.mode(), vals::Mode::DALI) || irctl.iren() + ctl0.menc() || matches!(ctl0.mode(), vals::Mode::Dali) || irctl.iren() }; let mut found = None; 'outer: for &(oversampling, hse_value) in &OVS { - if matches!(hse_value, vals::Hse::OVS3) && x3_invalid { + if matches!(hse_value, vals::Hse::Ovs3) && x3_invalid { continue; } diff --git a/embassy-mspm0/src/wwdt.rs b/embassy-mspm0/src/wwdt.rs index 92aeb8b408..850a3b97d2 100644 --- a/embassy-mspm0/src/wwdt.rs +++ b/embassy-mspm0/src/wwdt.rs @@ -84,7 +84,7 @@ impl Timeout { | Self::Sec5120 | Self::Sec6144 | Self::Sec7168 - | Self::Sec8192 => vals::Per::EN_25, + | Self::Sec8192 => vals::Per::En25, // period count is 2**21 Self::Sec64 | Self::Sec128 @@ -93,15 +93,13 @@ impl Timeout { | Self::Sec320 | Self::Sec384 | Self::Sec448 - | Self::Sec512 => vals::Per::EN_21, + | Self::Sec512 => vals::Per::En21, // period count is 2**18 Self::Sec8 | Self::Sec16 | Self::Sec24 | Self::Sec32 | Self::Sec40 | Self::Sec48 | Self::Sec56 => { - vals::Per::EN_18 + vals::Per::En18 } // period count is 2**15 - Self::Sec1 | Self::Sec2 | Self::Sec3 | Self::Sec4 | Self::Sec5 | Self::Sec6 | Self::Sec7 => { - vals::Per::EN_15 - } + Self::Sec1 | Self::Sec2 | Self::Sec3 | Self::Sec4 | Self::Sec5 | Self::Sec6 | Self::Sec7 => vals::Per::En15, // period count is 2**12 Self::MSec130 | Self::MSec250 @@ -109,7 +107,7 @@ impl Timeout { | Self::MSec500 | Self::MSec630 | Self::MSec750 - | Self::MSec880 => vals::Per::EN_12, + | Self::MSec880 => vals::Per::En12, // period count is 2**10 Self::USec31250 | Self::USec62500 @@ -117,7 +115,7 @@ impl Timeout { | Self::USec125000 | Self::USec156250 | Self::USec187500 - | Self::USec218750 => vals::Per::EN_10, + | Self::USec218750 => vals::Per::En10, // period count is 2**8 Self::USec7810 | Self::USec15630 @@ -125,10 +123,10 @@ impl Timeout { | Self::USec32250 | Self::USec39060 | Self::USec46880 - | Self::USec54690 => vals::Per::EN_8, + | Self::USec54690 => vals::Per::En8, // period count is 2**6 Self::USec1950 | Self::USec3910 | Self::USec5860 | Self::USec9770 | Self::USec11720 | Self::USec13670 => { - vals::Per::EN_6 + vals::Per::En6 } } } @@ -228,14 +226,14 @@ pub enum ClosedWindowPercentage { impl ClosedWindowPercentage { fn get_native_size(self) -> vals::Window { match self { - Self::Zero => vals::Window::SIZE_0, - Self::Twelve => vals::Window::SIZE_12, - Self::Eighteen => vals::Window::SIZE_18, - Self::TwentyFive => vals::Window::SIZE_25, - Self::Fifty => vals::Window::SIZE_50, - Self::SeventyFive => vals::Window::SIZE_75, - Self::EightyOne => vals::Window::SIZE_81, - Self::EightySeven => vals::Window::SIZE_87, + Self::Zero => vals::Window::Size0, + Self::Twelve => vals::Window::Size12, + Self::Eighteen => vals::Window::Size18, + Self::TwentyFive => vals::Window::Size25, + Self::Fifty => vals::Window::Size50, + Self::SeventyFive => vals::Window::Size75, + Self::EightyOne => vals::Window::Size81, + Self::EightySeven => vals::Window::Size87, } } } @@ -271,13 +269,13 @@ impl Watchdog { T::regs().gprcm(0).rstctl().write(|w| { w.set_resetstkyclr(true); w.set_resetassert(true); - w.set_key(vals::ResetKey::KEY); + w.set_key(vals::ResetKey::Key); }); // Enable power for watchdog T::regs().gprcm(0).pwren().write(|w| { w.set_enable(true); - w.set_key(vals::PwrenKey::KEY); + w.set_key(vals::PwrenKey::Key); }); // init delay, 16 cycles @@ -301,16 +299,16 @@ impl Watchdog { T::regs().wwdtctl0().write(|w| { w.set_clkdiv(config.timeout.get_clkdiv()); w.set_per(config.timeout.get_period()); - w.set_mode(vals::Mode::WINDOW); + w.set_mode(vals::Mode::Window); w.set_window0(config.closed_window.get_native_size()); - w.set_window1(vals::Window::SIZE_0); - w.set_key(vals::Wwdtctl0Key::KEY); + w.set_window1(vals::Window::Size0); + w.set_key(vals::Wwdtctl0Key::Key); }); // Set Window0 as active window T::regs().wwdtctl1().write(|w| { - w.set_winsel(vals::Winsel::WIN0); - w.set_key(vals::Wwdtctl1Key::KEY); + w.set_winsel(vals::Winsel::Win0); + w.set_key(vals::Wwdtctl1Key::Key); }); Self { regs: T::regs() } @@ -319,7 +317,7 @@ impl Watchdog { /// Pet (reload, refresh) the watchdog. pub fn pet(&mut self) { self.regs.wwdtcntrst().write(|w| { - w.set_restart(vals::WwdtcntrstRestart::RESTART); + w.set_restart(vals::WwdtcntrstRestart::Restart); }); } } From d192ce2d9530615ae23da76d79461d70c9b482fe Mon Sep 17 00:00:00 2001 From: Siarhei B Date: Sun, 2 Aug 2026 00:22:28 +0200 Subject: [PATCH 2/4] Update mspm0-metapac to mspm0-data-4be4996 --- embassy-mspm0/Cargo.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml index 1c73fde859..acf1153c7a 100644 --- a/embassy-mspm0/Cargo.toml +++ b/embassy-mspm0/Cargo.toml @@ -74,7 +74,7 @@ critical-section = "1.2.0" micromath = "2.0.0" # mspm0-metapac = { version = "" } -mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df" } +mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-4be499610ef6e0d40ab18a5d362171e9a07310e1" } rand_core = "0.9" # Force no cache padding or the types are too large. maitake-sync = { version = "0.3.0", default-features = false, features = ["critical-section", "no-cache-pad"]} @@ -88,7 +88,7 @@ quote = "1.0.40" cfg_aliases = "0.2.1" # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] } -mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f78bc71fcc6d74b25c2cae58220d8bf443fb12df", default-features = false, features = ["metadata"] } +mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-4be499610ef6e0d40ab18a5d362171e9a07310e1", default-features = false, features = ["metadata"] } [features] default = ["rt"] From 85d9a01aff2891754b9cf4306f7c5541a502c902 Mon Sep 17 00:00:00 2001 From: Siarhei B Date: Sun, 2 Aug 2026 00:22:40 +0200 Subject: [PATCH 3/4] mspm0: add internal temperature sensor channel Add `TempSensorChannel`, an `AdcChannel` for the internal temperature sensor, and `read_temp_calibration_constant()` for the factory trim constant used to convert its readings to a temperature. The sensor is present on every supported family, but the ADC0 channel it is connected to is device specific (11, 28 or 29 per SysConfig's SYS_TEMP_SENSE_CHANNEL), so gate both on a new `temp_sensor` cfg and select the channel per family. --- embassy-mspm0/CHANGELOG.md | 1 + embassy-mspm0/build.rs | 23 +++++++++++++++++++++++ embassy-mspm0/src/adc.rs | 32 ++++++++++++++++++++++++++++++++ embassy-mspm0/src/lib.rs | 15 +++++++++++++++ 4 files changed, 71 insertions(+) diff --git a/embassy-mspm0/CHANGELOG.md b/embassy-mspm0/CHANGELOG.md index 7e9ccaf9c2..e10cfb6eee 100644 --- a/embassy-mspm0/CHANGELOG.md +++ b/embassy-mspm0/CHANGELOG.md @@ -26,3 +26,4 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - fix: feature guard pins used for NRST and SWD (#5257) - feat: Move from GPIO waker arrays to maitake-sync wait map - fix: Flush the I2C controller FIFOs on the NACK/error paths, to prevent stale data +- feat: Add `TempSensorChannel` and `read_temp_calibration_constant()` for the internal temperature sensor \ No newline at end of file diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs index edea53541b..b659fb85b7 100644 --- a/embassy-mspm0/build.rs +++ b/embassy-mspm0/build.rs @@ -145,6 +145,29 @@ fn get_chip_cfgs(chip_name: &str) -> Vec { cfgs.push("mspm0l222x".to_string()); } + // Devices with an internal temperature sensor, see `TEMP_SENSOR_CHANNEL` in `adc.rs`. + const TEMP_SENSOR_FAMILIES: &[&str] = &[ + "mspm0c110x", + "mspm0c1105_c1106", + "mspm0g110x", + "mspm0g150x", + "mspm0g151x", + "mspm0g310x", + "mspm0g350x", + "mspm0g351x", + "mspm0g518x", + "mspm0h321x", + "mspm0l110x", + "mspm0l122x", + "mspm0l130x", + "mspm0l134x", + "mspm0l222x", + ]; + + if cfgs.iter().any(|cfg| TEMP_SENSOR_FAMILIES.contains(&cfg.as_str())) { + cfgs.push("temp_sensor".to_string()); + } + cfgs } diff --git a/embassy-mspm0/src/adc.rs b/embassy-mspm0/src/adc.rs index 5f5743045f..d8fb7af85d 100644 --- a/embassy-mspm0/src/adc.rs +++ b/embassy-mspm0/src/adc.rs @@ -641,3 +641,35 @@ macro_rules! impl_adc_pin { } }; } + +/// The ADC0 channel the temperature sensor is connected to. +/// +/// See `SYS_TEMP_SENSE_CHANNEL` in the device specific data sheet. ADC1 uses a different +/// channel (12 on the G-series), which is not exposed. +#[cfg(any( + mspm0c110x, mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0l110x, mspm0l130x, + mspm0l134x +))] +const TEMP_SENSOR_CHANNEL: u8 = 11; + +#[cfg(any(mspm0c1105_c1106, mspm0h321x))] +const TEMP_SENSOR_CHANNEL: u8 = 28; + +#[cfg(any(mspm0g518x, mspm0l122x, mspm0l222x))] +const TEMP_SENSOR_CHANNEL: u8 = 29; + +/// Internal temperature sensor channel. +/// +/// Uses an internal ADC0 channel, no external pin is required. It can be sampled like a +/// regular [`AdcChannel`]. +#[cfg(temp_sensor)] +pub struct TempSensorChannel; + +#[cfg(temp_sensor)] +impl crate::adc::AdcChannel for TempSensorChannel {} +#[cfg(temp_sensor)] +impl crate::adc::SealedAdcChannel for TempSensorChannel { + fn channel(&self) -> u8 { + TEMP_SENSOR_CHANNEL + } +} diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs index 3d4ed4c17e..4c4888e46a 100644 --- a/embassy-mspm0/src/lib.rs +++ b/embassy-mspm0/src/lib.rs @@ -359,3 +359,18 @@ pub fn read_reset_cause() -> Result { other => Err(other as u8), } } + +/// Read the factory-region temperature sensor calibration constant. +/// +/// This reads `FACTORYREGION.TEMP_SENSE0`, the reading of the internal temperature sensor +/// at the factory trim temperature, used to convert raw ADC readings to a temperature. +/// +/// The value is a right-aligned 12-bit ADC code sampled with the 1.4V internal reference. +/// +/// Only available on devices with an internal temperature sensor, see +/// [`adc::TempSensorChannel`]. +#[cfg(temp_sensor)] +#[must_use = "The calibration constant should be used to convert ADC readings to temperature"] +pub fn read_temp_calibration_constant() -> u32 { + pac::FACTORYREGION.temp_sense0().read() +} From e3ce63836ed702ab8bb2e94cea2d9df1a30c23b2 Mon Sep 17 00:00:00 2001 From: Siarhei B Date: Sun, 2 Aug 2026 00:22:49 +0200 Subject: [PATCH 4/4] mspm0: add internal temperature sensor example for g3507 Port TI's `adc12_internal_temp_sensor_mathacl` example, converting the sensor reading to degrees Celsius and Fahrenheit with MATHACL. --- .../mspm0g3507/src/bin/adc_temp_sensor.rs | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 examples/mspm0g3507/src/bin/adc_temp_sensor.rs diff --git a/examples/mspm0g3507/src/bin/adc_temp_sensor.rs b/examples/mspm0g3507/src/bin/adc_temp_sensor.rs new file mode 100644 index 0000000000..49c6bbe741 --- /dev/null +++ b/examples/mspm0g3507/src/bin/adc_temp_sensor.rs @@ -0,0 +1,70 @@ +//! Example of reading the internal temperature sensor of the MSPM0G3507. +//! +//! This ports the TI C example `adc12_internal_temp_sensor_mathacl` to embassy. It reads +//! the factory calibration constant, samples the sensor and converts the result to degrees +//! Celsius and Fahrenheit, using the MATHACL accelerator for the divisions. + +#![no_std] +#![no_main] + +use defmt::*; +use defmt_rtt as _; +use embassy_executor::Spawner; +use embassy_mspm0::adc::{self, Adc, Conversion, TempSensorChannel}; +use embassy_mspm0::mathacl::{IQType, Mathacl}; +use embassy_mspm0::{bind_interrupts, peripherals, read_temp_calibration_constant}; +use embassy_time::Timer; +use panic_halt as _; + +bind_interrupts!(struct Irqs { + ADC0 => adc::InterruptHandler; +}); + +// Temperature sensor trim parameters from the device datasheet ("Temperature Sensor"). +const TEMP_TS_TRIM_C: f32 = 30.0; +// 1 / TSc, where TSc is the temperature sensor coefficient from the datasheet. +const TEMP_TS_COEF_MV_C: f32 = -555.55; +const ADC_VREF_VOLTAGE: f32 = 3.3; +const ADC_BIT_RESOLUTION: f32 = 4096.0; // 2^12 + +#[embassy_executor::main] +async fn main(_spawner: Spawner) -> ! { + info!("Hello world!"); + + let d = embassy_mspm0::init(Default::default()); + + let mut adc = Adc::new_async(d.ADC0, Irqs, Default::default()); + let mut mathacl = Mathacl::new(d.MATHACL); + let mut temp_sensor = TempSensorChannel; + + // 12-bit ADC code of the temp sensor at 30 C. + let cal = read_temp_calibration_constant(); + + // Vtrim = ADC_VREF * (TEMP_SENSE0 - 0.5) / 2^12, computed with MATHACL division. + let vtrim = mathacl + .div_iq( + IQType::from_f32((cal as f32 - 0.5) * ADC_VREF_VOLTAGE, 15, true).unwrap(), + IQType::from_f32(ADC_BIT_RESOLUTION, 15, true).unwrap(), + ) + .unwrap(); + + loop { + let adc_result = adc.blocking_read(&mut temp_sensor, Conversion::default()); + + // Vsample = ADC_VREF * (adcResult - 0.5) / 2^12, computed with MATHACL division. + let vsample = mathacl + .div_iq( + IQType::from_f32((adc_result as f32 - 0.5) * ADC_VREF_VOLTAGE, 15, true).unwrap(), + IQType::from_f32(ADC_BIT_RESOLUTION, 15, true).unwrap(), + ) + .unwrap(); + + // TSAMPLE = TEMP_TS_COEF_mV_C * (Vsample - Vtrim) + TEMP_TS_TRIM_C + let temp_deg_c = TEMP_TS_COEF_MV_C * (vsample - vtrim) + TEMP_TS_TRIM_C; + let temp_deg_f = temp_deg_c * 1.8 + 32.0; + + info!("Temperature: {} C, {} F", temp_deg_c, temp_deg_f); + + Timer::after_millis(500).await; + } +}