RELOGIO.bdf

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
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		(text "a1" (rect 104 155 115 167)(font "Arial" ))
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		(text "b1" (rect 104 171 115 183)(font "Arial" ))
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		(text "c1" (rect 104 187 115 199)(font "Arial" ))
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	(pt 536 192)
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	(pt 432 240)
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	(pt 344 1648)
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	(pt 784 568)
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	(pt 784 680)
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	(pt 784 696)
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	(pt 784 712)
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	(pt 784 728)
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	(pt 784 760)
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	(pt 784 744)
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	(pt 784 664)
)
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	(pt 696 776)
	(pt 784 776)
)
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	(pt 784 896)
)
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	(pt 784 912)
)
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	(pt 696 928)
	(pt 784 928)
)
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	(pt 696 944)
	(pt 784 944)
)
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	(pt 696 960)
	(pt 784 960)
)
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	(pt 696 976)
	(pt 784 976)
)
(connector
	(pt 696 992)
	(pt 784 992)
)
(connector
	(pt 696 1128)
	(pt 784 1128)
)
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	(pt 696 1144)
	(pt 784 1144)
)
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	(pt 696 1160)
	(pt 784 1160)
)
(connector
	(pt 696 1176)
	(pt 784 1176)
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	(pt 696 1192)
	(pt 784 1192)
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	(pt 696 1208)
	(pt 784 1208)
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	(pt 696 1224)
	(pt 784 1224)
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	(pt 696 1376)
	(pt 784 1376)
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	(pt 784 1360)
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	(pt 696 1392)
	(pt 784 1392)
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	(pt 696 1408)
	(pt 784 1408)
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	(pt 784 1424)
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	(pt 696 1440)
	(pt 784 1440)
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	(pt 784 1456)
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	(pt 784 1584)
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	(pt 688 1600)
	(pt 784 1600)
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	(pt 784 1616)
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