From 0e85da6454c18c4a076f8e166baf3d9c04a41b8c Mon Sep 17 00:00:00 2001 From: Ashcon Mohseninia Date: Fri, 13 Mar 2026 08:32:17 +0000 Subject: [PATCH 1/4] Add free methods to Tc,Tcc,Nvm and Trng peripherals --- hal/src/peripherals/nvm/mod.rs | 6 ++++++ hal/src/peripherals/pwm/d11.rs | 8 ++++++++ hal/src/peripherals/pwm/d5x.rs | 8 ++++++++ hal/src/peripherals/timer/d11.rs | 9 +++++++++ hal/src/peripherals/timer/d5x.rs | 9 +++++++++ hal/src/peripherals/trng.rs | 5 +++++ 6 files changed, 45 insertions(+) diff --git a/hal/src/peripherals/nvm/mod.rs b/hal/src/peripherals/nvm/mod.rs index e4082db3f19f..b41284b5739a 100644 --- a/hal/src/peripherals/nvm/mod.rs +++ b/hal/src/peripherals/nvm/mod.rs @@ -176,6 +176,12 @@ impl Nvm { Self { nvm } } + /// Releases the NvmCtrl resource + #[inline] + pub fn free(self) -> Nvmctrl { + self.nvm + } + /// Raw access to the registers. /// /// # Safety diff --git a/hal/src/peripherals/pwm/d11.rs b/hal/src/peripherals/pwm/d11.rs index 0b1b2bfb8497..e82847a79aef 100644 --- a/hal/src/peripherals/pwm/d11.rs +++ b/hal/src/peripherals/pwm/d11.rs @@ -57,6 +57,14 @@ impl $TYPE { } } + #[inline] + // Disables the TCC, then releases it + pub fn free(self) -> $TC { + self.tcc.ctrla().write(|w| w.swrst().set_bit()); + while self.tcc.syncbusy().read().swrst().bit_is_set() {} + self.tcc + } + pub fn set_period(&mut self, period: Hertz) { let params = TimerParams::new(period, self.clock_freq); diff --git a/hal/src/peripherals/pwm/d5x.rs b/hal/src/peripherals/pwm/d5x.rs index f101e3b494b2..7fad49c7f044 100644 --- a/hal/src/peripherals/pwm/d5x.rs +++ b/hal/src/peripherals/pwm/d5x.rs @@ -606,6 +606,14 @@ impl $TYPE { pinout, } } + + #[inline] + // Disables the TCC, then releases it + pub fn free(self) -> $TCC { + self.tcc.ctrla().write(|w| w.swrst().set_bit()); + while self.tcc.syncbusy().read().swrst().bit_is_set() {} + self.tcc + } } impl $crate::ehal_02::Pwm for $TYPE { diff --git a/hal/src/peripherals/timer/d11.rs b/hal/src/peripherals/timer/d11.rs index 8b36b16fa233..f38f79c657f5 100644 --- a/hal/src/peripherals/timer/d11.rs +++ b/hal/src/peripherals/timer/d11.rs @@ -129,6 +129,15 @@ impl TimerCounter<$TC> tc, } } + + #[inline] + // Disables the TC, then releases it + pub fn free(self) -> $TC { + let count = self.tc.count_16(); + count.ctrla().write(|w| w.swrst().set_bit()); + while count.syncbusy().read().swrst().bit_is_set() {} + self.tc + } } )+ } diff --git a/hal/src/peripherals/timer/d5x.rs b/hal/src/peripherals/timer/d5x.rs index 4290e9c3b225..31b457166d98 100644 --- a/hal/src/peripherals/timer/d5x.rs +++ b/hal/src/peripherals/timer/d5x.rs @@ -128,6 +128,15 @@ impl TimerCounter<$TC> tc, } } + + #[inline] + // Disables the TC, then releases it + pub fn free(self) -> $TC { + let count = self.tc.count_16(); + count.ctrla().write(|w| w.swrst().set_bit()); + while count.syncbusy().read().swrst().bit_is_set() {} + self.tc + } } )+ } diff --git a/hal/src/peripherals/trng.rs b/hal/src/peripherals/trng.rs index e6f76e14b32d..f4e7706d8037 100644 --- a/hal/src/peripherals/trng.rs +++ b/hal/src/peripherals/trng.rs @@ -13,6 +13,11 @@ impl Trng { Self(trng) } + /// Releases the Trng resource + pub fn free(self) -> pac::Trng { + self.0 + } + pub fn random(&self, buf: &mut [u8]) { for chunk in buf.chunks_mut(4) { chunk.copy_from_slice(&self.random_u32().to_le_bytes()[..chunk.len()]); From 181f92e30731e9cf670d8549656a7fd03b0971b1 Mon Sep 17 00:00:00 2001 From: Ashcon Mohseninia Date: Fri, 13 Mar 2026 08:44:35 +0000 Subject: [PATCH 2/4] Fix TCC macro references --- hal/src/peripherals/pwm/d11.rs | 2 +- hal/src/peripherals/pwm/d5x.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/src/peripherals/pwm/d11.rs b/hal/src/peripherals/pwm/d11.rs index e82847a79aef..8a60fa6022a1 100644 --- a/hal/src/peripherals/pwm/d11.rs +++ b/hal/src/peripherals/pwm/d11.rs @@ -59,7 +59,7 @@ impl $TYPE { #[inline] // Disables the TCC, then releases it - pub fn free(self) -> $TC { + pub fn free(self) -> crate::pac::$TC { self.tcc.ctrla().write(|w| w.swrst().set_bit()); while self.tcc.syncbusy().read().swrst().bit_is_set() {} self.tcc diff --git a/hal/src/peripherals/pwm/d5x.rs b/hal/src/peripherals/pwm/d5x.rs index 7fad49c7f044..30e4286a46cf 100644 --- a/hal/src/peripherals/pwm/d5x.rs +++ b/hal/src/peripherals/pwm/d5x.rs @@ -609,7 +609,7 @@ impl $TYPE { #[inline] // Disables the TCC, then releases it - pub fn free(self) -> $TCC { + pub fn free(self) -> crate::pac::$TCC { self.tcc.ctrla().write(|w| w.swrst().set_bit()); while self.tcc.syncbusy().read().swrst().bit_is_set() {} self.tcc From 890ed1bd14fa66e6bd583495c54721da6b372070 Mon Sep 17 00:00:00 2001 From: Ashcon Mohseninia Date: Fri, 13 Mar 2026 08:48:32 +0000 Subject: [PATCH 3/4] Fix D11 PWM free --- hal/src/peripherals/pwm/d11.rs | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hal/src/peripherals/pwm/d11.rs b/hal/src/peripherals/pwm/d11.rs index 8a60fa6022a1..49ef1c285475 100644 --- a/hal/src/peripherals/pwm/d11.rs +++ b/hal/src/peripherals/pwm/d11.rs @@ -58,11 +58,12 @@ impl $TYPE { } #[inline] - // Disables the TCC, then releases it + // Disables the TC, then releases it pub fn free(self) -> crate::pac::$TC { - self.tcc.ctrla().write(|w| w.swrst().set_bit()); - while self.tcc.syncbusy().read().swrst().bit_is_set() {} - self.tcc + let count = self.tc.count16(); + count.ctrla().write(|w| w.swrst().set_bit()); + while count.ctrla().read().bits() & 1 != 0 {} + self.tc } pub fn set_period(&mut self, period: Hertz) From 714098eb84bb0ce7806c2dfff19faa8f430439a7 Mon Sep 17 00:00:00 2001 From: Ashcon Mohseninia Date: Fri, 13 Mar 2026 08:54:02 +0000 Subject: [PATCH 4/4] Fix D11 Timer compile --- hal/src/peripherals/timer/d11.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/src/peripherals/timer/d11.rs b/hal/src/peripherals/timer/d11.rs index f38f79c657f5..dd79f19f6477 100644 --- a/hal/src/peripherals/timer/d11.rs +++ b/hal/src/peripherals/timer/d11.rs @@ -133,9 +133,9 @@ impl TimerCounter<$TC> #[inline] // Disables the TC, then releases it pub fn free(self) -> $TC { - let count = self.tc.count_16(); + let count = self.tc.count16(); count.ctrla().write(|w| w.swrst().set_bit()); - while count.syncbusy().read().swrst().bit_is_set() {} + while count.ctrla().read().bits() & 1 != 0 {} self.tc } }