From 71852667f233295398358cdef9f35c5fdb7270a2 Mon Sep 17 00:00:00 2001 From: Lucas Ste <38472950+LucasSte@users.noreply.github.com> Date: Tue, 4 Nov 2025 16:41:12 -0300 Subject: [PATCH 01/19] [SOL] Remove `syscall` and `return` instructions (#174) --- .../SBF/Disassembler/SBFDisassembler.cpp | 3 +- llvm/lib/Target/SBF/GISel/SBFCallLowering.cpp | 2 +- llvm/lib/Target/SBF/SBFInstrInfo.td | 36 +------------- llvm/lib/Target/SBF/SBFMIPeephole.cpp | 48 ++----------------- llvm/test/CodeGen/SBF/call_internal.ll | 14 +++--- llvm/test/CodeGen/SBF/objdump_trivial.ll | 4 +- llvm/test/CodeGen/SBF/return_instr.ll | 14 ------ llvm/test/CodeGen/SBF/static_syscall.ll | 16 +++---- llvm/test/CodeGen/SBF/static_syscall_2.ll | 4 +- llvm/test/CodeGen/SBF/unreachable_return.ll | 2 +- llvm/test/MC/Disassembler/SBF/sbf-jmp.txt | 9 ---- llvm/test/MC/SBF/sbf-return-syscall.s | 8 ---- 12 files changed, 25 insertions(+), 135 deletions(-) delete mode 100644 llvm/test/CodeGen/SBF/return_instr.ll delete mode 100644 llvm/test/MC/SBF/sbf-return-syscall.s diff --git a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp index 377309414e462..530073dd48571 100644 --- a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp +++ b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp @@ -211,8 +211,7 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, decodeInstruction(DecoderTableSBFALU32MEMv264, Instr, Insn, Address, this, STI); } - else if ((isNewMem(Insn) && STI.hasFeature(SBF::FeatureNewMemEncoding)) || - (isSyscallOrExit(Insn) && STI.hasFeature(SBF::FeatureStaticSyscalls))) { + else if (isNewMem(Insn) && STI.hasFeature(SBF::FeatureNewMemEncoding)) { Result = decodeInstruction(DecoderTableSBFv264, Instr, Insn, Address, this, STI); diff --git a/llvm/lib/Target/SBF/GISel/SBFCallLowering.cpp b/llvm/lib/Target/SBF/GISel/SBFCallLowering.cpp index fd893f5f4160a..8ddb4054bea5c 100644 --- a/llvm/lib/Target/SBF/GISel/SBFCallLowering.cpp +++ b/llvm/lib/Target/SBF/GISel/SBFCallLowering.cpp @@ -29,7 +29,7 @@ bool SBFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, Register SwiftErrorVReg) const { if (!VRegs.empty()) return false; - MIRBuilder.buildInstr(SBF::RETURN_v3); + MIRBuilder.buildInstr(SBF::EXIT); return true; } diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index b020ce38a9d46..daca7c1220222 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -60,8 +60,6 @@ def SBFExplicitSignExt : Predicate<"Subtarget->getHasExplicitSignExt()">; def SBFNoExplicitSignExt : Predicate<"!Subtarget->getHasExplicitSignExt()">; def SBFNewMemEncoding : Predicate<"Subtarget->getNewMemEncoding()">, AssemblerPredicate<(all_of FeatureNewMemEncoding)>; def SBFOldMemEncoding : Predicate<"!Subtarget->getNewMemEncoding()">; -def SBFHasStaticSyscalls : Predicate<"Subtarget->getHasStaticSyscalls()">; -def SBFNoStaticSyscalls : Predicate<"!Subtarget->getHasStaticSyscalls()">; def brtarget : Operand { let PrintMethod = "printBrTargetOperand"; @@ -800,19 +798,6 @@ class CALL let SBFClass = SBF_JMP; } -class SYSCALL - : TYPE_ALU_JMP { - bits<32> imm; - - let Inst{31-0} = imm; - let SBFClass = SBF_JMP; -} - - class CALLX : TYPE_ALU_JMP, Requires<[SBFNoCallxSrc]>; let DecoderNamespace = "SBFv2" in { def JALX_v2 : CALLX_SRC_REG<"callx">, Requires<[SBFCallxSrc]>; - def SYSCALL_v3 : SYSCALL<"syscall">, Requires<[SBFHasStaticSyscalls]>; } } @@ -880,25 +864,10 @@ class EXIT } let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, - isNotDuplicable = 1, Predicates = [SBFNoStaticSyscalls] in { + isNotDuplicable = 1 in { def EXIT : EXIT<"exit">; } -class RETURN - : TYPE_ALU_JMP { - let Inst{31-0} = 0; - let SBFClass = SBF_JMP; -} - -let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, - isNotDuplicable = 1, Predicates = [SBFHasStaticSyscalls] in { - def RETURN_v3 : RETURN<"return">; -} - // ADJCALLSTACKDOWN/UP pseudo insns let Defs = [R10], Uses = [R10], isCodeGenOnly = 1 in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), @@ -959,10 +928,9 @@ def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)), // Calls def : Pat<(SBFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>; def : Pat<(SBFcall texternalsym:$dst), (JAL texternalsym:$dst)>; -def : Pat<(SBFcall imm:$dst), (JAL imm:$dst)>, Requires<[SBFNoStaticSyscalls]>; +def : Pat<(SBFcall imm:$dst), (JAL imm:$dst)>; def : Pat<(SBFcall GPR:$dst), (JALX GPR:$dst)>, Requires<[SBFNoCallxSrc]>; def : Pat<(SBFcall GPR:$dst), (JALX_v2 GPR:$dst)>, Requires<[SBFCallxSrc]>; -def : Pat<(SBFcall imm:$imm), (SYSCALL_v3 imm:$imm)>, Requires<[SBFHasStaticSyscalls]>; // Loads let Predicates = [SBFNoALU32, SBFOldMemEncoding] in { diff --git a/llvm/lib/Target/SBF/SBFMIPeephole.cpp b/llvm/lib/Target/SBF/SBFMIPeephole.cpp index d09df5513b254..5439e0476ebf3 100644 --- a/llvm/lib/Target/SBF/SBFMIPeephole.cpp +++ b/llvm/lib/Target/SBF/SBFMIPeephole.cpp @@ -145,26 +145,16 @@ struct SBFMIPreEmitPeephole : public MachineFunctionPass { void initialize(MachineFunction &MFParm); bool eliminateRedundantMov(); - bool addReturn(); public: // Main entry point for this pass. bool runOnMachineFunction(MachineFunction &MF) override { - initialize(MF); - - bool PeepholeExecuted = false; - if (SubTarget->getHasStaticSyscalls()) - PeepholeExecuted |= addReturn(); - - // We shall not skip adding the return to SBPFv3 functions - if (skipFunction(MF.getFunction()) || OptLevel == CodeGenOptLevel::None || - DisablePeephole) - return PeepholeExecuted; - - PeepholeExecuted |= eliminateRedundantMov(); + if (skipFunction(MF.getFunction())) + return false; - return PeepholeExecuted; + initialize(MF); + return eliminateRedundantMov(); } }; @@ -177,36 +167,6 @@ void SBFMIPreEmitPeephole::initialize(MachineFunction &MFParm) { LLVM_DEBUG(dbgs() << "*** SBF PreEmit peephole pass ***\n\n"); } -bool SBFMIPreEmitPeephole::addReturn() { - bool Added = false; - - // In SBFv3, every function must either end with either a JA or a RETURN - // instruction. When we call a function that will never return the control - // flow (e.g. when the callee aborts execution), the caller last instruction - // will be a CALL, failing validation. - // - // Although we can change ISelLowering and manually add the return for an - // LLVM-IR unreachable instruction, LLVM codegen uses the target machine's - // return instruction to determine whether a function needs an epilogue. - // This setting increases code size, even when we know the call won't - // trasnfer control back to the caller. - // - // In that case, we can analyze every function before emitting machine code - // and include a useless return instruction. - - // PreEmitPeephole happens after block placement, so the last block in - // the ELF layout is also the last one in MF. - MachineBasicBlock &MBB = MF->back(); - MachineInstr &MI = MBB.back(); - unsigned Opcode = MI.getOpcode(); - if (Opcode != SBF::RETURN_v3 && Opcode != SBF::JMP) { - BuildMI(&MBB, MI.getDebugLoc(), TII->get(SBF::RETURN_v3)); - Added = true; - } - - return Added; -} - bool SBFMIPreEmitPeephole::eliminateRedundantMov() { MachineInstr* ToErase = nullptr; bool Eliminated = false; diff --git a/llvm/test/CodeGen/SBF/call_internal.ll b/llvm/test/CodeGen/SBF/call_internal.ll index d4e1dc7844fd4..bc2230a54b823 100644 --- a/llvm/test/CodeGen/SBF/call_internal.ll +++ b/llvm/test/CodeGen/SBF/call_internal.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=sbf --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-V0 %s -; RUN: llc -march=sbf --filetype=obj -o - %s | llvm-objdump -d - | FileCheck --check-prefixes=CHECK-OBJ,CHECK-OBJ-V0 %s -; RUN: llc < %s -march=sbf -mcpu=v3 --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-V3 %s +; RUN: llc < %s -march=sbf --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM %s +; RUN: llc -march=sbf --filetype=obj -o - %s | llvm-objdump -d - | FileCheck --check-prefixes=CHECK-OBJ %s +; RUN: llc < %s -march=sbf -mcpu=v3 --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM %s ; RUN: llc -march=sbf -mcpu=v3 --filetype=obj -o - %s | llvm-objdump -d - -; | FileCheck --check-prefixes=CHECK-OBJ,CHECK-OBJ-V3 %s +; | FileCheck --check-prefixes=CHECK-OBJ %s @.str = private unnamed_addr constant [5 x i8] c"foo\0A\00", align 1 @@ -16,11 +16,9 @@ entry: ; Function Attrs: nounwind define dso_local i64 @entrypoint(ptr noundef %input) local_unnamed_addr #1 { entry: -; CHECK-ASM-V0: call 1811268606 # encoding: [0x85,0x00,0x00,0x00,0xfe,0xc3,0xf5,0x6b] -; CHECK-ASM-V3: syscall 1811268606 # encoding: [0x95,0x00,0x00,0x00,0xfe,0xc3,0xf5,0x6b] +; CHECK-ASM: call 1811268606 # encoding: [0x85,0x00,0x00,0x00,0xfe,0xc3,0xf5,0x6b] -; CHECK-OBJ-V0: 85 00 00 00 fe c3 f5 6b call 0x6bf5c3fe -; CHECK-OBJ-V3: 95 00 00 00 fe c3 f5 6b syscall 0x6bf5c3fe +; CHECK-OBJ: 85 00 00 00 fe c3 f5 6b call 0x6bf5c3fe tail call void inttoptr (i64 1811268606 to ptr)(ptr noundef nonnull @.str, i64 noundef 4) #3 %add.ptr = getelementptr inbounds i8, ptr %input, i64 4 diff --git a/llvm/test/CodeGen/SBF/objdump_trivial.ll b/llvm/test/CodeGen/SBF/objdump_trivial.ll index 388c3be7a373b..5f29a19d7a72f 100644 --- a/llvm/test/CodeGen/SBF/objdump_trivial.ll +++ b/llvm/test/CodeGen/SBF/objdump_trivial.ll @@ -2,9 +2,9 @@ ; CHECK: jslt r1, 0x0, ; CHECK: call 0x1 -; CHECK: return +; CHECK: exit ; CHECK: call 0x2 -; CHECK: return +; CHECK: exit define void @foo(i32 %a) { %b = icmp sgt i32 %a, -1 diff --git a/llvm/test/CodeGen/SBF/return_instr.ll b/llvm/test/CodeGen/SBF/return_instr.ll deleted file mode 100644 index b3dcd72410142..0000000000000 --- a/llvm/test/CodeGen/SBF/return_instr.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: llc < %s -march=sbf -show-mc-encoding | FileCheck --check-prefix=CHECK-V1 %s -; RUN: llc < %s -march=sbf -mattr=+static-syscalls -show-mc-encoding | FileCheck --check-prefix=CHECK-V2 %s - -define dso_local i64 @rem(i64 %a) local_unnamed_addr #0 { -entry: -; CHECK-LABEL: rem - %rem = urem i64 %a, 15 - -; CHECK-V1: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00] -; CHECK-V2: return # encoding: [0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00] - - - ret i64 %rem -} \ No newline at end of file diff --git a/llvm/test/CodeGen/SBF/static_syscall.ll b/llvm/test/CodeGen/SBF/static_syscall.ll index 9f60ff5a9c243..366d9ec1d240a 100644 --- a/llvm/test/CodeGen/SBF/static_syscall.ll +++ b/llvm/test/CodeGen/SBF/static_syscall.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=sbf < %s | FileCheck --check-prefixes=CHECK,CHECK-V0 %s -; RUN: llc -march=sbf -mattr=+static-syscalls -show-mc-encoding < %s | FileCheck --check-prefixes=CHECK,CHECK-V3 %s +; RUN: llc -march=sbf < %s | FileCheck --check-prefixes=CHECK %s +; RUN: llc -march=sbf -mattr=+static-syscalls -show-mc-encoding < %s | FileCheck --check-prefixes=CHECK %s ; Function Attrs: nounwind @@ -7,22 +7,18 @@ define dso_local i32 @test(i32 noundef %a, i32 noundef %b) { entry: ; CHECK-LABEL: test -; CHECK-V0: call 2 -; CHECK-V3 syscall 2 # encoding: [0x95,0x00,0x00,0x00,0x01,0x00,0x00,0x00] +; CHECK: call 2 %syscall_1 = tail call i32 inttoptr (i64 2 to ptr)(i32 noundef %a, i32 noundef %b) -; CHECK-V0: call 11 -; CHECK-V3: syscall 11 # encoding: [0x95,0x00,0x00,0x00,0x0b,0x00,0x00,0x00] +; CHECK: call 11 %syscall_2 = tail call i32 inttoptr (i64 11 to ptr)(i32 noundef %a, i32 noundef %b) -; CHECK-V0: call 112 -; CHECK-V3: syscall 112 +; CHECK: call 112 %syscall_3 = tail call i32 inttoptr (i64 112 to ptr)(i32 noundef %a, i32 noundef %b) ; CHECK: mov64 r1, 89 ; CHECK: mov64 r2, 87 -; CHECK-V0: call 112 -; CHECK-V3: syscall 112 +; CHECK: call 112 %syscall_4 = tail call i32 inttoptr (i64 112 to ptr)(i32 89, i32 87) %add_1 = add i32 %syscall_1, %syscall_2 diff --git a/llvm/test/CodeGen/SBF/static_syscall_2.ll b/llvm/test/CodeGen/SBF/static_syscall_2.ll index 6c7ac56b5a873..df7616cb939c3 100644 --- a/llvm/test/CodeGen/SBF/static_syscall_2.ll +++ b/llvm/test/CodeGen/SBF/static_syscall_2.ll @@ -20,7 +20,7 @@ entry: %1 = load i32, ptr %b.addr, align 4 ; Ensure the syscall instruction is emitted -; CHECK: syscall 50 +; CHECK: call 50 %call = call i32 inttoptr (i64 50 to ptr)(i32 noundef %0, i32 noundef %1) ret i32 %call @@ -43,7 +43,7 @@ start: store ptr getelementptr (i8, ptr null, i64 60), ptr %syscall.dbg.spill, align 8 ; Ensure the syscall instruction is emitted -; CHECK: syscall 60 +; CHECK: call 60 %_0 = call i32 getelementptr (i8, ptr null, i64 60)(i64 %b) ret i32 %_0 diff --git a/llvm/test/CodeGen/SBF/unreachable_return.ll b/llvm/test/CodeGen/SBF/unreachable_return.ll index c20560fe6f9e0..0c8459fb81b01 100644 --- a/llvm/test/CodeGen/SBF/unreachable_return.ll +++ b/llvm/test/CodeGen/SBF/unreachable_return.ll @@ -14,5 +14,5 @@ start: unreachable ; CHECK: call dummy_func ; CHECK-NOT: add64 r10, 64 -; CHECK: return +; CHECK-NOT: exit } \ No newline at end of file diff --git a/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt b/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt index a51c1230ea430..33a35d36a7a63 100644 --- a/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt +++ b/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt @@ -1,7 +1,5 @@ # RUN: llvm-mc --disassemble %s -triple=sbf-solana-solana \ # RUN: | FileCheck %s --check-prefix=CHECK-NEW -# RUN: llvm-mc --disassemble %s -triple=sbf-solana-solana -mattr=+static-syscalls \ -# RUN: | FileCheck %s --check-prefix=CHECK-V2 # TODO: Test immediate field ranges. @@ -110,10 +108,3 @@ # CHECK-NEW: exit 0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - -# CHECK-V2: syscall 5 -0x95,0x00,0x00,0x00,0x05,0x00,0x00,0x00 - - -# CHECK-NEW: return -0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/llvm/test/MC/SBF/sbf-return-syscall.s b/llvm/test/MC/SBF/sbf-return-syscall.s deleted file mode 100644 index 1e13462e1b48a..0000000000000 --- a/llvm/test/MC/SBF/sbf-return-syscall.s +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: llvm-mc -triple=sbf-solana-solana --mcpu=v3 -filetype=obj -o %t %s -# RUN: llvm-objdump -d -r %t | FileCheck --check-prefix=CHECK %s - -syscall 9 -return - -// CHECK: 95 00 00 00 09 00 00 00 syscall 0x9 -// CHECK: 9d 00 00 00 00 00 00 00 return \ No newline at end of file From a515a68d51e0c1ab9ca5ac328f8ba78fa95b4071 Mon Sep 17 00:00:00 2001 From: Lucas Ste <38472950+LucasSte@users.noreply.github.com> Date: Wed, 5 Nov 2025 11:32:01 -0300 Subject: [PATCH 02/19] [SOL] Change `callx` encoding for sBPFv3 (#175) --- .../SBF/Disassembler/SBFDisassembler.cpp | 3 +++ llvm/lib/Target/SBF/SBFInstrInfo.td | 23 +++++++++++++++++-- llvm/lib/Target/SBF/SBFSubtarget.cpp | 1 + llvm/lib/Target/SBF/SBFSubtarget.h | 4 ++++ llvm/lib/Target/SBF/SBFTargetFeatures.td | 11 +++++---- llvm/test/CodeGen/SBF/callx.ll | 3 +++ llvm/test/MC/Disassembler/SBF/sbf-jmp.txt | 10 ++++++++ llvm/test/MC/SBF/sbf-jmp.s | 9 +++++++- 8 files changed, 57 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp index 530073dd48571..49fd5376ed235 100644 --- a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp +++ b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp @@ -245,6 +245,9 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, if (STI.hasFeature(SBF::FeatureCallxRegSrc)) { Result = decodeInstruction(DecoderTableSBFv264, Instr, Insn, Address, this, STI); + } else if (STI.hasFeature(SBF::FeatureCallxRegDst)) { + Result = decodeInstruction(DecoderTableSBFv364, Instr, Insn, Address, + this, STI); } } } diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index daca7c1220222..90432ff4ab8e9 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -51,8 +51,11 @@ def SBFHasNeg : Predicate<"!Subtarget->getDisableNeg()">; def SBFNoNeg: Predicate<"Subtarget->getDisableNeg()">; def SBFRevSub : Predicate<"Subtarget->getReverseSubImm()">; def SBFNoRevSub : Predicate<"!Subtarget->getReverseSubImm()">; -def SBFCallxSrc : Predicate<"Subtarget->getCallXRegSrc()">, AssemblerPredicate<(all_of FeatureCallxRegSrc)>; -def SBFNoCallxSrc : Predicate<"!Subtarget->getCallXRegSrc()">; +def SBFCallxSrc : Predicate<"Subtarget->getCallXRegSrc() && !Subtarget->getCallXRegDst()">, + AssemblerPredicate<(all_of FeatureCallxRegSrc)>; +def SBFCallxDst : Predicate<"Subtarget->getCallXRegDst() && !Subtarget->getCallXRegSrc()">, + AssemblerPredicate<(all_of FeatureCallxRegDst)>; +def SBFNoCallxSrc : Predicate<"!Subtarget->getCallXRegSrc() && !Subtarget->getCallXRegDst()">; def SBFPqrInstr : Predicate<"Subtarget->getHasPqrClass()">; def SBFNoPqrInstr : Predicate<"!Subtarget->getHasPqrClass()">; def SBFHasStoreImm : Predicate<"Subtarget->getHasStoreImm()">; @@ -822,6 +825,18 @@ class CALLX_SRC_REG let SBFClass = SBF_JMP; } +class CALLX_DST_REG + : TYPE_ALU_JMP { + bits<4> BrDst; + + let Inst{51-48} = BrDst; + let SBFClass = SBF_JMP; +} + // Jump always let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { def JMP : BRANCH; @@ -836,6 +851,9 @@ let isCall=1, hasDelaySlot=0, Uses = [R10], let DecoderNamespace = "SBFv2" in { def JALX_v2 : CALLX_SRC_REG<"callx">, Requires<[SBFCallxSrc]>; } + let DecoderNamespace = "SBFv3" in { + def JALX_v3 : CALLX_DST_REG<"callx">, Requires<[SBFCallxDst]>; + } } class NOP_I @@ -931,6 +949,7 @@ def : Pat<(SBFcall texternalsym:$dst), (JAL texternalsym:$dst)>; def : Pat<(SBFcall imm:$dst), (JAL imm:$dst)>; def : Pat<(SBFcall GPR:$dst), (JALX GPR:$dst)>, Requires<[SBFNoCallxSrc]>; def : Pat<(SBFcall GPR:$dst), (JALX_v2 GPR:$dst)>, Requires<[SBFCallxSrc]>; +def : Pat<(SBFcall GPR:$dst), (JALX_v3 GPR:$dst)>, Requires<[SBFCallxDst]>; // Loads let Predicates = [SBFNoALU32, SBFOldMemEncoding] in { diff --git a/llvm/lib/Target/SBF/SBFSubtarget.cpp b/llvm/lib/Target/SBF/SBFSubtarget.cpp index 93979cb1c68e7..ea47676996887 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.cpp +++ b/llvm/lib/Target/SBF/SBFSubtarget.cpp @@ -50,6 +50,7 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) { ReverseSubImm = false; NoLddw = false; CallxRegSrc = false; + CallxRegDst = false; HasPqrClass = false; HasStoreImm = false; HasAlu32 = false; diff --git a/llvm/lib/Target/SBF/SBFSubtarget.h b/llvm/lib/Target/SBF/SBFSubtarget.h index 19208b061f03f..bef1db6d133b0 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.h +++ b/llvm/lib/Target/SBF/SBFSubtarget.h @@ -76,6 +76,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // Whether to encode destination register in Callx's src field bool CallxRegSrc; + // Whether to encode destination register in Callx's dst field + bool CallxRegDst; + // Whether we have the PQR instruction class bool HasPqrClass; @@ -116,6 +119,7 @@ class SBFSubtarget : public SBFGenSubtargetInfo { bool getReverseSubImm() const { return ReverseSubImm; } bool getNoLddw() const { return NoLddw; } bool getCallXRegSrc() const { return CallxRegSrc; } + bool getCallXRegDst() const { return CallxRegDst; } bool getHasPqrClass() const { return HasPqrClass; } bool getHasStoreImm() const { return HasStoreImm; } bool getHasExplicitSignExt() const { return HasExplicitSignExt; } diff --git a/llvm/lib/Target/SBF/SBFTargetFeatures.td b/llvm/lib/Target/SBF/SBFTargetFeatures.td index ab302f6022890..30370e6bfbf62 100644 --- a/llvm/lib/Target/SBF/SBFTargetFeatures.td +++ b/llvm/lib/Target/SBF/SBFTargetFeatures.td @@ -37,6 +37,9 @@ def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true", def FeatureCallxRegSrc : SubtargetFeature<"callx-reg-src", "CallxRegSrc", "true", "Encode Callx destination register in the src field">; +def FeatureCallxRegDst : SubtargetFeature<"callx-reg-dst", "CallxRegDst", "true", + "Encode Callx destination register in the dst field">; + def FeaturePqrInstr : SubtargetFeature<"pqr-instr", "HasPqrClass", "true", "Enable the PQR instruction class">; @@ -67,11 +70,11 @@ def : Proc<"v2", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt, Feature FeatureNewMemEncoding, FeatureCallxRegSrc, FeaturePqrInstr, FeatureExplicitSext, FeatureDisableNeg, FeatureReverseSubImm, ALU32]>; -def : Proc<"v3", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt, FeatureDisableLddw, - FeatureNewMemEncoding, FeatureCallxRegSrc, FeaturePqrInstr, FeatureExplicitSext, +def : Proc<"v3", [FeatureDynamicFrames, FeatureDisableLddw, + FeatureNewMemEncoding, FeatureCallxRegDst, FeaturePqrInstr, FeatureExplicitSext, FeatureDisableNeg, FeatureReverseSubImm, ALU32, FeatureStaticSyscalls, FeatureRelocAbs64]>; -def : Proc<"v4", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt, FeatureDisableLddw, - FeatureNewMemEncoding, FeatureCallxRegSrc, FeaturePqrInstr, FeatureExplicitSext, +def : Proc<"v4", [FeatureDynamicFrames, FeatureDisableLddw, + FeatureNewMemEncoding, FeatureCallxRegDst, FeaturePqrInstr, FeatureExplicitSext, FeatureDisableNeg, FeatureReverseSubImm, ALU32, FeatureStaticSyscalls, FeatureRelocAbs64, FeatureAbiV2]>; \ No newline at end of file diff --git a/llvm/test/CodeGen/SBF/callx.ll b/llvm/test/CodeGen/SBF/callx.ll index 5923cdc155843..e59071537d958 100644 --- a/llvm/test/CodeGen/SBF/callx.ll +++ b/llvm/test/CodeGen/SBF/callx.ll @@ -2,6 +2,8 @@ ; RUN: | FileCheck %s -check-prefixes=CHECK-v0 ; RUN: llc < %s -march=sbf --mcpu=v2 --show-mc-encoding \ ; RUN: | FileCheck %s -check-prefixes=CHECK-v2 +; RUN: llc < %s -march=sbf --mcpu=v3 --show-mc-encoding \ +; RUN: | FileCheck %s -check-prefixes=CHECK-v3 ; source: ; int test(int (*f)(void)) { return f(); } @@ -11,6 +13,7 @@ entry: %call = tail call i32 %f() #1 ; CHECK-v0: callx r{{[0-9]+}} # encoding: [0x8d,0x00,0x00,0x00,0x0{{[0-9]|a|b}},0x00,0x00,0x00] ; CHECK-v2: callx r{{[0-9]+}} # encoding: [0x8d,0x{{[0-9]}}0,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK-v3: callx r{{[0-9]+}} # encoding: [0x8d,0x0{{[0-9]}},0x00,0x00,0x00,0x00,0x00,0x00] ret i32 %call } diff --git a/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt b/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt index 33a35d36a7a63..cdd850b619b1f 100644 --- a/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt +++ b/llvm/test/MC/Disassembler/SBF/sbf-jmp.txt @@ -1,5 +1,9 @@ # RUN: llvm-mc --disassemble %s -triple=sbf-solana-solana \ # RUN: | FileCheck %s --check-prefix=CHECK-NEW +# RUN: llvm-mc --disassemble %s -triple=sbpfv2-solana-solana \ +# RUN: | FileCheck %s --check-prefix=CHECK-V2 +# RUN: llvm-mc --disassemble %s -triple=sbpfv3-solana-solana \ +# RUN: | FileCheck %s --check-prefix=CHECK-V3 # TODO: Test immediate field ranges. @@ -103,6 +107,12 @@ # CHECK-NEW: callx r4 0x8d,0x00,0x00,0x00,0x04,0x00,0x00,0x00 +# CHECK-V2: callx r4 +0x8d,0x40,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK-V3: callx r4 +0x8d,0x04,0x00,0x00,0x00,0x00,0x00,0x00 + # CHECK-NEW: call -1 0x85,0x10,0x00,0x00,0xff,0xff,0xff,0xff diff --git a/llvm/test/MC/SBF/sbf-jmp.s b/llvm/test/MC/SBF/sbf-jmp.s index 0f03aed0a874f..407a8cc3a105c 100644 --- a/llvm/test/MC/SBF/sbf-jmp.s +++ b/llvm/test/MC/SBF/sbf-jmp.s @@ -2,11 +2,16 @@ # RUN: | FileCheck %s --check-prefix=CHECK-ASM-NEW # RUN: llvm-mc %s -triple=sbpfv3-solana-solana --show-encoding \ # RUN: | FileCheck %s --check-prefix=CHECK-ASM-NEW +# RUN: llvm-mc %s -triple=sbpfv2-solana-solana --show-encoding \ +# RUN: | FileCheck %s --check-prefix=CHECK-ASM-V2 # RUN: llvm-mc %s -triple=sbf-solana-solana --show-encoding \ # RUN: | FileCheck %s --check-prefix=CHECK-ASM-OLD # RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=v3 -filetype=obj \ # RUN: | llvm-objdump -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-OBJ-NEW %s +# RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=v2 -filetype=obj \ +# RUN: | llvm-objdump -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-OBJ-V2 %s # RUN: llvm-mc %s -triple=sbf-solana-solana -filetype=obj \ # RUN: | llvm-objdump -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-OBJ-OLD %s @@ -161,8 +166,10 @@ call 8 # CHECK-OBJ-NEW: callx r4 # CHECK-OBJ-OLD: callx r4 -# CHECK-ASM-NEW: encoding: [0x8d,0x40,0x00,0x00,0x00,0x00,0x00,0x00] +# CHECK-OBJ-V2: callx r4 +# CHECK-ASM-NEW: encoding: [0x8d,0x04,0x00,0x00,0x00,0x00,0x00,0x00] # CHECK-ASM-OLD: encoding: [0x8d,0x00,0x00,0x00,0x04,0x00,0x00,0x00] +# CHECK-ASM-V2: encoding: [0x8d,0x40,0x00,0x00,0x00,0x00,0x00,0x00] callx r4 # CHECK-OBJ-OLD: exit From c9974c634577bab1736b40ee02d1c5664c3bc1d2 Mon Sep 17 00:00:00 2001 From: Lucas Ste <38472950+LucasSte@users.noreply.github.com> Date: Mon, 24 Nov 2025 19:00:58 -0300 Subject: [PATCH 03/19] [SOL] Invert indexes for dynamic stack frames in v3 (#178) * Invert indexes for dynamic stack frames in v3 * Fix rebase conflicts --- llvm/lib/Target/SBF/SBFFrameLowering.cpp | 12 +++-- llvm/lib/Target/SBF/SBFRegisterInfo.cpp | 11 ++++- llvm/lib/Target/SBF/SBFSubtarget.cpp | 1 + llvm/lib/Target/SBF/SBFSubtarget.h | 10 ++++- llvm/lib/Target/SBF/SBFTargetFeatures.td | 3 ++ ....ll => dynamic_stack_frame_add_and_sub.ll} | 3 +- llvm/test/CodeGen/SBF/many_args_new_conv.ll | 44 +++++++++++++++++-- llvm/test/CodeGen/SBF/many_args_value_size.ll | 15 ++++++- 8 files changed, 87 insertions(+), 12 deletions(-) rename llvm/test/CodeGen/SBF/{dynamic_stack_frame_add_not_sub.ll => dynamic_stack_frame_add_and_sub.ll} (87%) diff --git a/llvm/lib/Target/SBF/SBFFrameLowering.cpp b/llvm/lib/Target/SBF/SBFFrameLowering.cpp index 2e12afe18ec4a..0f61cea8fd2ee 100644 --- a/llvm/lib/Target/SBF/SBFFrameLowering.cpp +++ b/llvm/lib/Target/SBF/SBFFrameLowering.cpp @@ -23,19 +23,25 @@ bool SBFFrameLowering::hasFP(const MachineFunction &MF) const { return true; } void SBFFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { - if (!MF.getSubtarget().getHasDynamicFrames()) { + const SBFSubtarget& Subtarget = MF.getSubtarget(); + if (!Subtarget.getHasDynamicFrames()) { return; } + MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo &MFI = MF.getFrameInfo(); int NumBytes = (int)MFI.getStackSize(); - if (NumBytes || MF.getSubtarget().getHasStaticSyscalls()) { + if (NumBytes && MBBI != MBB.end()) { DebugLoc Dl = MBBI->getDebugLoc(); const SBFInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); + + if (Subtarget.isDynamicFramesV1()) + NumBytes = -NumBytes; + BuildMI(MBB, MBBI, Dl, TII.get(SBF::ADD_ri), SBF::R10) .addReg(SBF::R10) - .addImm(-NumBytes); + .addImm(NumBytes); } } diff --git a/llvm/lib/Target/SBF/SBFRegisterInfo.cpp b/llvm/lib/Target/SBF/SBFRegisterInfo.cpp index 4179e302c6dd6..b6500e1f8ac10 100644 --- a/llvm/lib/Target/SBF/SBFRegisterInfo.cpp +++ b/llvm/lib/Target/SBF/SBFRegisterInfo.cpp @@ -167,13 +167,20 @@ int SBFRegisterInfo::resolveInternalFrameIndex( if (SubTarget.getHasDynamicFrames() && SBFFuncInfo->containsFrameIndex(FI)) { - return -Offset; + if (SubTarget.isDynamicFramesV1()) + return -Offset; + + return Offset; } Offset += Imm.value_or(0); if (SubTarget.getHasDynamicFrames()) { - return static_cast(StackSize) + Offset; + Offset += static_cast(StackSize); + if (SubTarget.isDynamicFramesV1()) + return Offset; + + return -Offset; } return Offset; diff --git a/llvm/lib/Target/SBF/SBFSubtarget.cpp b/llvm/lib/Target/SBF/SBFSubtarget.cpp index ea47676996887..4745a00656a42 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.cpp +++ b/llvm/lib/Target/SBF/SBFSubtarget.cpp @@ -58,6 +58,7 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) { NewMemEncoding = false; HasStaticSyscalls = false; IsAbiV2 = false; + HasDynamicFramesV3 = false; } void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { diff --git a/llvm/lib/Target/SBF/SBFSubtarget.h b/llvm/lib/Target/SBF/SBFSubtarget.h index bef1db6d133b0..67e5f04f5cd9e 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.h +++ b/llvm/lib/Target/SBF/SBFSubtarget.h @@ -94,6 +94,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // Whether we are using AbiV2 bool IsAbiV2; + // Whether we are dealing with dynamic stack frames in SBPFv3 + bool HasDynamicFramesV3; + std::unique_ptr CallLoweringInfo; std::unique_ptr InstSelector; std::unique_ptr Legalizer; @@ -113,7 +116,12 @@ class SBFSubtarget : public SBFGenSubtargetInfo { void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); bool getHasJmpExt() const { return HasJmpExt; } bool getHasAlu32() const { return HasAlu32; } - bool getHasDynamicFrames() const { return HasDynamicFrames; } + bool getHasDynamicFrames() const { + return HasDynamicFrames || HasDynamicFramesV3; + } + bool isDynamicFramesV1() const { + return HasDynamicFrames; + } bool getUseDwarfRIS() const { return UseDwarfRIS; } bool getDisableNeg() const { return DisableNeg; } bool getReverseSubImm() const { return ReverseSubImm; } diff --git a/llvm/lib/Target/SBF/SBFTargetFeatures.td b/llvm/lib/Target/SBF/SBFTargetFeatures.td index 30370e6bfbf62..a7d819e49b56b 100644 --- a/llvm/lib/Target/SBF/SBFTargetFeatures.td +++ b/llvm/lib/Target/SBF/SBFTargetFeatures.td @@ -59,6 +59,9 @@ def FeatureAbiV2 : SubtargetFeature<"abi-v2", "IsAbiV2", "true", "Enables AbiV2 in SBF (no-op in LLVM)">; +def FeatureDynamicFramesV3 : SubtargetFeature<"dynamic-frames-v3", "HasDynamicFramesV3", "true", + "Enable dynamic frames in SBPFv3">; + class Proc Features> : Processor; diff --git a/llvm/test/CodeGen/SBF/dynamic_stack_frame_add_not_sub.ll b/llvm/test/CodeGen/SBF/dynamic_stack_frame_add_and_sub.ll similarity index 87% rename from llvm/test/CodeGen/SBF/dynamic_stack_frame_add_not_sub.ll rename to llvm/test/CodeGen/SBF/dynamic_stack_frame_add_and_sub.ll index f39e992055b9f..109420429b06f 100644 --- a/llvm/test/CodeGen/SBF/dynamic_stack_frame_add_not_sub.ll +++ b/llvm/test/CodeGen/SBF/dynamic_stack_frame_add_and_sub.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=sbf -mattr=+dynamic-frames | FileCheck %s +; RUN: llc -O3 -march=sbf -mattr=+dynamic-frames-v3,+alu32 < %s | FileCheck --check-prefix=CHECK-V3 %s ; ; Source: ; int test_func(int * vec, int idx) { @@ -13,7 +14,7 @@ define i32 @test_func(ptr noundef %vec, i32 noundef %idx) #0 { ; CHECK-LABEL: test_func: ; CHECK: add64 r10, -128 -; CHECK-NOT: add64 r10, 128 +; CHECK-V3: add64 r10, 128 entry: %vec.addr = alloca ptr, align 8 %idx.addr = alloca i512, align 4 diff --git a/llvm/test/CodeGen/SBF/many_args_new_conv.ll b/llvm/test/CodeGen/SBF/many_args_new_conv.ll index 20e1922ea9c3c..83446b8703bb8 100644 --- a/llvm/test/CodeGen/SBF/many_args_new_conv.ll +++ b/llvm/test/CodeGen/SBF/many_args_new_conv.ll @@ -1,7 +1,7 @@ ; RUN: llc -O2 -march=sbf -mcpu=v1 < %s | FileCheck %s ; RUN: llc -O2 -mtriple=sbpfv1-solana-solana < %s | FileCheck %s ; RUN: llc -O2 -march=sbf -mcpu=v1 -mattr=+mem-encoding < %s | FileCheck %s -; RUN: llc -O3 -march=sbf -mcpu=v3 < %s | FileCheck --check-prefix=CHECK-V3 %s +; RUN: llc -O3 -march=sbf -mattr=+dynamic-frames-v3 < %s | FileCheck --check-prefix=CHECK-V3 %s ; Function Attrs: nounwind uwtable define i32 @caller_no_alloca(i32 %a, i32 %b, i32 %c) #0 { @@ -10,8 +10,6 @@ entry: ; No changes to the stack pointer ; CHECK-NOT: add64 r10 -; Add zero to stack pointer from V3 onwards -; CHECK-V3: add64 r10, 0 ; Saving arguments on the stack ; CHECK: stdw [r10 - 40], 60 @@ -19,6 +17,13 @@ entry: ; CHECK: stdw [r10 - 24], 50 ; CHECK: stdw [r10 - 16], 4 ; CHECK: stdw [r10 - 8], 3 + +; CHECK-V3: stdw [r10 + 40], 60 +; CHECK-V3: stdw [r10 + 32], 55 +; CHECK-V3: stdw [r10 + 24], 50 +; CHECK-V3: stdw [r10 + 16], 4 +; CHECK-V3: stdw [r10 + 8], 3 + ; CHECK: mov64 r4, 1 ; CHECK: mov64 r5, 2 ; CHECK: call callee_alloca @@ -45,6 +50,18 @@ define i32 @caller_alloca(i32 %a, i32 %b, i32 %c) #0 { ; CHECK: stdw [r10 - 16], 4 ; Offset in the callee: frame_size - 8 ; CHECK: stdw [r10 - 8], 3 + +; Offset in the callee: frame_size - 40 +; CHECK-V3: stdw [r10 + 40], 60 +; Offset in the callee: frame_size - 32 +; CHECK-V3: stdw [r10 + 32], 55 +; Offset in the callee: frame_size - 24 +; CHECK-V3: stdw [r10 + 24], 50 +; Offset in the callee: frame_size - 16 +; CHECK-V3: stdw [r10 + 16], 4 +; Offset in the callee: frame_size - 8 +; CHECK-V3: stdw [r10 + 8], 3 + ; CHECK: mov64 r4, 1 ; CHECK: mov64 r5, 2 ; CHECK: call callee_no_alloca @@ -63,6 +80,8 @@ entry: define i32 @callee_alloca(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %p, i32 %y, i32 %a1, i32 %a2) #1 { ; CHECK-LABEL: callee_alloca ; CHECK: add64 r10, -128 +; CHECK-V3: add64 r10, 128 + ; Loading arguments ; CHECK: ldxdw r2, [r10 + 120] ; CHECK: ldxdw r2, [r10 + 112] @@ -71,6 +90,16 @@ define i32 @callee_alloca(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %p ; CHECK: ldxdw r2, [r10 + 88] ; Loading allocated i32 ; CHECK: ldxw r0, [r10 + 24] + +; CHECK-V3: ldxw r2, [r10 - 120] +; CHECK-V3: ldxw r2, [r10 - 112] +; CHECK-V3: ldxw r2, [r10 - 104] +; CHECK-V3: ldxw r2, [r10 - 96] +; CHECK-V3: ldxw r2, [r10 - 88] +; Loading allocated i32 +; CHECK-V3: ldxw r0, [r10 - 24] + + ; CHECK-NOT: add64 r10, 128 entry: @@ -93,6 +122,8 @@ entry: define i32 @callee_no_alloca(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %p, i32 %y, i32 %a1, i32 %a2) #1 { ; CHECK-LABEL: callee_no_alloca ; CHECK: add64 r10, -64 +; CHECK-V3: add64 r10, 64 + ; Loading arguments ; CHECK: ldxdw r1, [r10 + 56] ; CHECK: ldxdw r1, [r10 + 48] @@ -100,6 +131,13 @@ define i32 @callee_no_alloca(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 ; CHECK: ldxdw r1, [r10 + 32] ; CHECK: ldxdw r1, [r10 + 24] +; Loading arguments +; CHECK-V3: ldxw r1, [r10 - 56] +; CHECK-V3: ldxw r1, [r10 - 48] +; CHECK-V3: ldxw r1, [r10 - 40] +; CHECK-V3: ldxw r1, [r10 - 32] +; CHECK-V3: ldxw r1, [r10 - 24] + ; CHECK-NOT: add64 r10, 64 entry: %g = add i32 %a, %b diff --git a/llvm/test/CodeGen/SBF/many_args_value_size.ll b/llvm/test/CodeGen/SBF/many_args_value_size.ll index 71c59c60b0914..927405c5d943d 100644 --- a/llvm/test/CodeGen/SBF/many_args_value_size.ll +++ b/llvm/test/CodeGen/SBF/many_args_value_size.ll @@ -1,5 +1,6 @@ ; RUN: llc -march=sbf -mcpu=v2 < %s | FileCheck %s ; RUN: llc -mtriple=sbpfv2-solana-solana < %s | FileCheck %s +; RUN: llc -O3 -march=sbf -mattr=+dynamic-frames-v3,+alu32 < %s | FileCheck --check-prefix=CHECK-V3 %s define i64 @test_func(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) { start: @@ -10,6 +11,11 @@ start: ; CHECK: stw [r10 - 12], 65516 ; CHECK: stw [r10 - 4], 5 +; CHECK-V3: stdw [r10 + 32], 5400 +; CHECK-V3: stw [r10 + 20], 300 +; CHECK-V3: stw [r10 + 12], 65516 +; CHECK-V3: stw [r10 + 4], 5 + %res = call i64 @func(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i8 5, i16 -20, i32 300, i64 5400) ret i64 %res } @@ -18,6 +24,7 @@ define i64 @func(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i8 %b8, i16 %b16, i32 % start: ; CHECK-LABEL: func: ; CHECK: add64 r10, -64 +; CHECK-V3: add64 r10, 64 %a1 = add i64 %a, %b %a2 = sub i64 %a1, %c %a3 = mul i64 %a2, %d @@ -25,19 +32,23 @@ start: ; -64 + 32 = -32, so this is 5400 in %a5 ; CHECK: ldxdw r4, [r10 + 32] +; CHECK-V3: ldxdw r4, [r10 - 32] ; -64 + 60 = -4, so this is 5 in %b8 -; CHECK: ldxw w4, [r10 + 60] +; CHECK: ldxb w4, [r10 + 60] +; CHECK-V3: ldxb w4, [r10 - 60] %c0 = trunc i64 %a to i8 %b1 = add i8 %b8, %c0 ; -64 + 52 = -12, so this is -20 in %b16 -; ldxw w1, [r10 + 52] +; CHECK: ldxh w1, [r10 + 52] +; CHECK-V3: ldxh w1, [r10 - 52] %c1 = trunc i64 %b to i16 %b2 = add i16 %b16, %c1 ; -64 + 44 = -20, so this is 300 in %b32 ; CHECK: ldxw w1, [r10 + 44] +; CHECK-V3: ldxw w1, [r10 - 44] %c2 = trunc i64 %c to i32 %b3 = add i32 %b32, %c2 From 4c91743d687822586419cabb88e97dfc57e90dff Mon Sep 17 00:00:00 2001 From: Lucas Ste <38472950+LucasSte@users.noreply.github.com> Date: Tue, 2 Dec 2025 16:01:58 -0300 Subject: [PATCH 04/19] [SOL] Emit EM_BPF for SBPFv3 (#180) --- lld/ELF/InputFiles.cpp | 2 + lld/ELF/InputSection.cpp | 2 +- lldb/source/Utility/ArchSpec.cpp | 152 +++++++++--------- llvm/lib/Object/ELF.cpp | 2 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 2 +- .../SBF/MCTargetDesc/SBFELFObjectWriter.cpp | 2 +- llvm/test/CodeGen/BPF/reloc-2.ll | 3 +- llvm/test/CodeGen/BPF/reloc-3.ll | 1 + llvm/test/CodeGen/BPF/reloc-btf-2.ll | 1 + llvm/test/CodeGen/BPF/reloc-btf.ll | 1 + llvm/test/CodeGen/BPF/reloc.ll | 1 + llvm/test/CodeGen/SBF/reloc-btf.ll | 2 +- llvm/test/CodeGen/SBF/reloc.ll | 2 +- llvm/test/MC/BPF/insn-unit.s | 2 +- llvm/test/MC/SBF/elf-header.s | 39 ++--- .../test/Object/BPF/yaml2obj-elf-bpf-rel.yaml | 8 +- .../llvm-objdump/BPF/core-relo-formatting.s | 18 +-- llvm/tools/llvm-objdump/llvm-objdump.cpp | 15 +- 18 files changed, 139 insertions(+), 116 deletions(-) diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp index f921246bf65d9..165ecef2a9eb7 100644 --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -1678,6 +1678,8 @@ static uint16_t getBitcodeMachineKind(StringRef path, const Triple &t) { return t.isOSIAMCU() ? EM_IAMCU : EM_386; case Triple::x86_64: return EM_X86_64; + case Triple::bpfel: + case Triple::bpfeb: case Triple::sbf: return EM_SBF; default: diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index dcef330f0958e..43845ca1a5c8d 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -974,7 +974,7 @@ void InputSection::relocateNonAlloc(uint8_t *buf, Relocs rels) { const uint64_t offset = rel.r_offset; // FIX: Temporary remap BPF_64_64 relocations in debug sections. - if (config->emachine == EM_SBF && type == R_SBF_64_64 && isDebug) + if ((ctx.arg.emachine == EM_SBF || ctx.arg.emachine == EM_BPF) && type == R_SBF_64_64 && isDebug) type = R_BPF_64_ABS64; uint8_t *bufLoc = buf + offset; diff --git a/lldb/source/Utility/ArchSpec.cpp b/lldb/source/Utility/ArchSpec.cpp index 0d8e76eb0c044..941253904d2d3 100644 --- a/lldb/source/Utility/ArchSpec.cpp +++ b/lldb/source/Utility/ArchSpec.cpp @@ -366,82 +366,82 @@ static const ArchDefinition g_macho_arch_def = {eArchTypeMachO, // architecture names to cpu types and subtypes. The ordering is important and // allows the precedence to be set when the table is built. static const ArchDefinitionEntry g_elf_arch_entries[] = { - {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc - {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 - {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? - {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC - {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, - ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le - {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, - ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 - {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM - {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 - {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ - {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, - LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 - {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 - {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 - {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 - {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 - {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el - {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el - {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el - {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 - {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 - {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 - {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el - {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el - {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, - ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el - {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430 - {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, - LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON - {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC - {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, - 0xFFFFFFFFu}, // AVR - {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, - ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 - {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, - ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 - {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, - ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu, - 0xFFFFFFFFu}, // loongarch32 - {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, - ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu, - 0xFFFFFFFFu}, // loongarch64 - {ArchSpec::eCore_bpf, llvm::ELF::EM_BPF, LLDB_INVALID_CPUTYPE, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // bpf - {ArchSpec::eCore_sbfv0, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv0, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbf - {ArchSpec::eCore_sbfv1, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv1, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv1 - {ArchSpec::eCore_sbfv2, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv2, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv2 - {ArchSpec::eCore_sbfv3, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv3, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv3 - {ArchSpec::eCore_sbfv4, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv4, - 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv3 + {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc + {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 + {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? + {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC + {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, + ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le + {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, + ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 + {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM + {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 + {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ + {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, + LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 + {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 + {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 + {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 + {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 + {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el + {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el + {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el + {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 + {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 + {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 + {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el + {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el + {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, + ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el + {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430 + {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, + LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON + {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC + {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, + 0xFFFFFFFFu}, // AVR + {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, + ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 + {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, + ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 + {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, + ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu, + 0xFFFFFFFFu}, // loongarch32 + {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, + ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu, + 0xFFFFFFFFu}, // loongarch64 + {ArchSpec::eCore_bpf, llvm::ELF::EM_BPF, LLDB_INVALID_CPUTYPE, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // bpf + {ArchSpec::eCore_sbfv0, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv0, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbf + {ArchSpec::eCore_sbfv1, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv1, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv1 + {ArchSpec::eCore_sbfv2, llvm::ELF::EM_SBF, ArchSpec::eSBFSubType_sbfv2, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv2 + {ArchSpec::eCore_sbfv3, llvm::ELF::EM_BPF, ArchSpec::eSBFSubType_sbfv3, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv3 + {ArchSpec::eCore_sbfv4, llvm::ELF::EM_BPF, ArchSpec::eSBFSubType_sbfv4, + 0xFFFFFFFFu, 0xFFFFFFFFu}, // sbfv4 }; static const ArchDefinition g_elf_arch_def = { diff --git a/llvm/lib/Object/ELF.cpp b/llvm/lib/Object/ELF.cpp index 8d72faf2a781a..d4c8e14cfe2e1 100644 --- a/llvm/lib/Object/ELF.cpp +++ b/llvm/lib/Object/ELF.cpp @@ -141,7 +141,7 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine, break; case ELF::EM_BPF: switch (Type) { -#include "llvm/BinaryFormat/ELFRelocs/BPF.def" +#include "llvm/BinaryFormat/ELFRelocs/SBF.def" default: break; } diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp index 5036cf512e6ce..9ee24e65d403f 100644 --- a/llvm/lib/ObjectYAML/ELFYAML.cpp +++ b/llvm/lib/ObjectYAML/ELFYAML.cpp @@ -918,7 +918,7 @@ void ScalarEnumerationTraits::enumeration( #include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def" break; case ELF::EM_BPF: -#include "llvm/BinaryFormat/ELFRelocs/BPF.def" +#include "llvm/BinaryFormat/ELFRelocs/SBF.def" break; case ELF::EM_SBF: #include "llvm/BinaryFormat/ELFRelocs/SBF.def" diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp b/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp index 15c1ae681402d..4fbd0fbcca22d 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp @@ -48,7 +48,7 @@ bool SBFELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val, } SBFELFObjectWriter::SBFELFObjectWriter(uint8_t OSABI, bool relocAbs64) - : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI,ELF::EM_SBF, + : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, relocAbs64? ELF::EM_BPF : ELF::EM_SBF, /*HasRelocationAddend*/ false), relocAbs64(relocAbs64) {} diff --git a/llvm/test/CodeGen/BPF/reloc-2.ll b/llvm/test/CodeGen/BPF/reloc-2.ll index 50baef7faf22c..5ced421606be7 100644 --- a/llvm/test/CodeGen/BPF/reloc-2.ll +++ b/llvm/test/CodeGen/BPF/reloc-2.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=bpfel -filetype=obj -o %t.el < %s +; XFAIL: * +; RUN: llc -mtriple=bpfel -mcpu=v1 -filetype=obj -o %t.el < %s ; RUN: llvm-objdump -r %t.el | FileCheck --check-prefix=RELOC %s ; RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t.el | FileCheck --check-prefix=DUMP %s ; RUN: llc -mtriple=bpfeb -filetype=obj -o %t.eb < %s diff --git a/llvm/test/CodeGen/BPF/reloc-3.ll b/llvm/test/CodeGen/BPF/reloc-3.ll index e4bb18c5c286c..374dad43504e0 100644 --- a/llvm/test/CodeGen/BPF/reloc-3.ll +++ b/llvm/test/CodeGen/BPF/reloc-3.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -mtriple=bpfel -filetype=obj -o %t.el < %s ; RUN: llvm-readelf -r %t.el | FileCheck %s ; RUN: llc -mtriple=bpfeb -filetype=obj -o %t.eb < %s diff --git a/llvm/test/CodeGen/BPF/reloc-btf-2.ll b/llvm/test/CodeGen/BPF/reloc-btf-2.ll index 7398257e43a91..3381805d7412b 100644 --- a/llvm/test/CodeGen/BPF/reloc-btf-2.ll +++ b/llvm/test/CodeGen/BPF/reloc-btf-2.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s ; RUN: llc -mtriple=bpfeb -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s diff --git a/llvm/test/CodeGen/BPF/reloc-btf.ll b/llvm/test/CodeGen/BPF/reloc-btf.ll index b9f6e3af6d72c..beeb4c5913ca1 100644 --- a/llvm/test/CodeGen/BPF/reloc-btf.ll +++ b/llvm/test/CodeGen/BPF/reloc-btf.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s ; Function Attrs: norecurse nounwind readnone diff --git a/llvm/test/CodeGen/BPF/reloc.ll b/llvm/test/CodeGen/BPF/reloc.ll index f1b957d3eb868..00cab8d0c8b0b 100644 --- a/llvm/test/CodeGen/BPF/reloc.ll +++ b/llvm/test/CodeGen/BPF/reloc.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s %struct.bpf_context = type { i64, i64, i64, i64, i64, i64, i64 } diff --git a/llvm/test/CodeGen/SBF/reloc-btf.ll b/llvm/test/CodeGen/SBF/reloc-btf.ll index 579fba7cc99ac..b31342b425905 100644 --- a/llvm/test/CodeGen/SBF/reloc-btf.ll +++ b/llvm/test/CodeGen/SBF/reloc-btf.ll @@ -6,7 +6,7 @@ entry: ret i32 0, !dbg !11 } -; CHECK-RELOC: file format elf64-sbf +; CHECK-RELOC: file format elf64-bpf ; CHECK-RELOC: RELOCATION RECORDS FOR [.debug_info]: ; CHECK-RELOC: R_SBF_64_ABS32 .debug_abbrev ; CHECK-RELOC: R_SBF_64_ABS64 diff --git a/llvm/test/CodeGen/SBF/reloc.ll b/llvm/test/CodeGen/SBF/reloc.ll index 9c0b789151321..9f4902114bbe6 100644 --- a/llvm/test/CodeGen/SBF/reloc.ll +++ b/llvm/test/CodeGen/SBF/reloc.ll @@ -32,7 +32,7 @@ define i32 @bpf_prog1(%struct.bpf_context* nocapture %ctx) #0 section "events/ne ;