From a211e0358850afd276c469c89a7121844df7b0df Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Sat, 16 Mar 2019 06:43:43 +0000 Subject: [PATCH 1/4] Add optional memory2 stage. --- src/main/scala/vexriscv/VexRiscv.scala | 11 +++++++++-- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 3 ++- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 ++ src/main/scala/vexriscv/plugin/DivPlugin.scala | 1 + .../scala/vexriscv/plugin/HazardSimplePlugin.scala | 4 +++- src/main/scala/vexriscv/plugin/IntAluPlugin.scala | 5 ++++- .../scala/vexriscv/plugin/MulDivIterativePlugin.scala | 1 + src/main/scala/vexriscv/plugin/MulPlugin.scala | 1 + src/main/scala/vexriscv/plugin/ShiftPlugins.scala | 2 ++ 9 files changed, 25 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 9665a31c0..645eaeede 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -6,19 +6,21 @@ import spinal.core._ import scala.collection.mutable.ArrayBuffer object VexRiscvConfig{ - def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { + def apply(withMemoryStage : Boolean, withMemory2Stage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { val config = VexRiscvConfig() config.plugins ++= plugins config.withMemoryStage = withMemoryStage + config.withMemory2Stage = withMemory2Stage config.withWriteBackStage = withWriteBackStage config } - def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = apply(true,true,plugins) + def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = apply(true,true,true,plugins) } case class VexRiscvConfig(){ var withMemoryStage = true + var withMemory2Stage = true var withWriteBackStage = true val plugins = ArrayBuffer[Plugin[VexRiscv]]() @@ -28,6 +30,7 @@ case class VexRiscvConfig(){ object IS_RVC extends Stageable(Bool) object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool) object BYPASSABLE_MEMORY_STAGE extends Stageable(Bool) + object BYPASSABLE_MEMORY2_STAGE extends Stageable(Bool) object RS1 extends Stageable(Bits(32 bits)) object RS2 extends Stageable(Bits(32 bits)) object RS1_USE extends Stageable(Bool) @@ -89,6 +92,7 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ val decode = newStage() val execute = newStage() val memory = ifGen(config.withMemoryStage) (newStage()) + val memory2 = ifGen(config.withMemory2Stage) (newStage()) val writeBack = ifGen(config.withWriteBackStage) (newStage()) def stagesFromExecute = stages.dropWhile(_ != execute) @@ -111,6 +115,9 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ if(withMemoryStage){ memory.arbitration.removeIt.noBackendCombMerge } + if(withMemory2Stage){ + memory2.arbitration.removeIt.noBackendCombMerge + } execute.arbitration.flushAll.noBackendCombMerge this(RVC_GEN) = false diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index ab59360af..91a004cd8 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -300,7 +300,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception IS_CSR -> True, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> True + BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) val nonImmediatActions = defaultCsrActions ++ List( diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 752552a6c..316c5581b 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -51,6 +51,7 @@ class DBusCachedPlugin(config : DataCacheConfig, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> False, + BYPASSABLE_MEMORY2_STAGE -> False, MEMORY_WR -> False, MEMORY_MANAGMENT -> False ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil) @@ -85,6 +86,7 @@ class DBusCachedPlugin(config : DataCacheConfig, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> False, + BYPASSABLE_MEMORY2_STAGE -> False, MEMORY_ATOMIC -> True ) ) diff --git a/src/main/scala/vexriscv/plugin/DivPlugin.scala b/src/main/scala/vexriscv/plugin/DivPlugin.scala index c20dcb3b0..8771b24be 100644 --- a/src/main/scala/vexriscv/plugin/DivPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DivPlugin.scala @@ -21,6 +21,7 @@ class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mul // REGFILE_WRITE_VALID -> True, // BYPASSABLE_EXECUTE_STAGE -> False, // BYPASSABLE_MEMORY_STAGE -> True, +// BYPASSABLE_MEMORY2_STAGE -> True, // RS1_USE -> True, // RS2_USE -> True, // IS_DIV -> True diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index c051aa033..1e1735aae 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -10,6 +10,7 @@ trait HazardService{ class HazardSimplePlugin(bypassExecute : Boolean = false, bypassMemory: Boolean = false, + bypassMemory2: Boolean = false, bypassWriteBack: Boolean = false, bypassWriteBackBuffer : Boolean = false, pessimisticUseSrc : Boolean = false, @@ -95,6 +96,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, } if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null) + if(withMemory2Stage) trackHazardWithStage(memory2 ,bypassMemory2 ,BYPASSABLE_MEMORY2_STAGE) if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE) if(readStage != execute) trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE) @@ -119,4 +121,4 @@ class NoHazardPlugin extends Plugin[VexRiscv] with HazardService { override def build(pipeline: VexRiscv): Unit = {} def hazardOnExecuteRS = False -} \ No newline at end of file +} diff --git a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala index 1b7467e6c..b769b21f4 100644 --- a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala @@ -28,6 +28,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{ REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> True, BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True, RS1_USE -> True ) @@ -37,6 +38,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{ REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> True, BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True, RS1_USE -> True, RS2_USE -> True ) @@ -44,7 +46,8 @@ class IntAluPlugin extends Plugin[VexRiscv]{ val otherAction = List[(Stageable[_ <: BaseType],Any)]( REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> True, - BYPASSABLE_MEMORY_STAGE -> True + BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True ) diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index f366854ca..0110dc14b 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -33,6 +33,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True, RS1_USE -> True, RS2_USE -> True ) diff --git a/src/main/scala/vexriscv/plugin/MulPlugin.scala b/src/main/scala/vexriscv/plugin/MulPlugin.scala index ab4d828ad..64b04d7fe 100644 --- a/src/main/scala/vexriscv/plugin/MulPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulPlugin.scala @@ -24,6 +24,7 @@ class MulPlugin extends Plugin[VexRiscv]{ REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> False, + BYPASSABLE_MEMORY2_STAGE -> False, RS1_USE -> True, RS2_USE -> True, IS_MUL -> True diff --git a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala index 086528df1..1be09b0b7 100644 --- a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala +++ b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala @@ -26,6 +26,7 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection), BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True, RS1_USE -> True ) @@ -35,6 +36,7 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection), BYPASSABLE_MEMORY_STAGE -> True, + BYPASSABLE_MEMORY2_STAGE -> True, RS1_USE -> True, RS2_USE -> True ) From e75efbb7728b6c16ebcbe3d9b289aa47c9b73e39 Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Sat, 16 Mar 2019 12:06:05 -0700 Subject: [PATCH 2/4] Fix bypassMemory2. --- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index eb4ce4681..b61e54ffa 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -233,7 +233,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection) + BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection), + BYPASSABLE_MEMORY2_STAGE -> Bool(earlyInjection) ) ++ (if(catchAccessFault || catchAddressMisaligned) List(HAS_SIDE_EFFECT -> True) else Nil) val storeActions = stdActions ++ List( From 89de3fe5aed3b94e01a4c5d5f25b98dfd1a0eecb Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Tue, 7 May 2019 06:59:43 -0700 Subject: [PATCH 3/4] Fix memory2 compilation. --- src/main/scala/vexriscv/demo/GenMicroNoCsr.scala | 1 + src/test/scala/vexriscv/TestIndividualFeatures.scala | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/GenMicroNoCsr.scala b/src/main/scala/vexriscv/demo/GenMicroNoCsr.scala index bcd1b7750..5fa4deb7f 100644 --- a/src/main/scala/vexriscv/demo/GenMicroNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenMicroNoCsr.scala @@ -11,6 +11,7 @@ object GenMicroNoCsr extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( withMemoryStage = false, + withMemory2Stage = false, withWriteBackStage = false, plugins = List( new IBusSimplePlugin( diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index 52097e9e6..aa71a91c3 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -579,6 +579,7 @@ class TestIndividualFeatures extends FunSuite { SpinalVerilog{ val config = VexRiscvConfig( withMemoryStage = !noMemory, + withMemory2Stage = false, withWriteBackStage = !noWriteback, plugins = List( new IntAluPlugin, @@ -682,4 +683,4 @@ FAIL AltQTest_rv32i_O3 val seed = 4331444545509090137l 1 => flops i O0 - */ \ No newline at end of file + */ From 39471ed29ccedeb00b97d97f3beab99abec50bbc Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Tue, 7 May 2019 07:04:05 -0700 Subject: [PATCH 4/4] Disable memory2Stage by default. --- src/main/scala/vexriscv/VexRiscv.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 821b5f1b0..e0f9920cf 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -20,7 +20,7 @@ object VexRiscvConfig{ case class VexRiscvConfig(){ var withMemoryStage = true - var withMemory2Stage = true + var withMemory2Stage = false var withWriteBackStage = true val plugins = ArrayBuffer[Plugin[VexRiscv]]()