From 4b43c60007793bf75753a3b0671724e11625ed76 Mon Sep 17 00:00:00 2001 From: noliete Date: Mon, 19 Jun 2023 12:10:34 +0200 Subject: [PATCH 01/37] Added ariane+HPDC repository --- .gitmodules | 6 +++--- piton/design/chip/tile/ariane | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index 5958d6fe0..bd5a7edf3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ -[submodule "piton/design/chip/tile/ariane"] - path = piton/design/chip/tile/ariane - url = https://github.com/pulp-platform/ariane.git [submodule "aws"] path = piton/design/aws url = https://github.com/PrincetonUniversity/openpiton-aws.git @@ -13,3 +10,6 @@ [submodule "piton/design/chip/tile/sparc"] path = piton/design/chip/tile/sparc url = git@github.com:openpiton/ost1-core.git +[submodule "piton/design/chip/tile/ariane"] + path = piton/design/chip/tile/ariane + url = https://github.com/AileonN/cva6_openpiton_noliete.git diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 4c01614f8..074bc3313 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 4c01614f83cd9dd91d115aa190bd4fc6a284b59e +Subproject commit 074bc331378ed55be33bd86b84db4f31f805a5dc From 1887cc574c34a12bc3f785565b77964453200b09 Mon Sep 17 00:00:00 2001 From: AileonN Date: Mon, 19 Jun 2023 15:50:58 +0200 Subject: [PATCH 02/37] Support for building the HPDC files --- piton/piton_settings.bash | 1 + piton/tools/src/sims/manycore.config | 2 ++ 2 files changed, 3 insertions(+) diff --git a/piton/piton_settings.bash b/piton/piton_settings.bash index 253a4d705..a326c25f5 100644 --- a/piton/piton_settings.bash +++ b/piton/piton_settings.bash @@ -12,6 +12,7 @@ export DV_ROOT=$PITON_ROOT/piton export MODEL_DIR=$PITON_ROOT/build export OST1_ROOT=$DV_ROOT/design/chip/tile/sparc export ARIANE_ROOT=$DV_ROOT/design/chip/tile/ariane +export HPDCACHE_DIR=$ARIANE_ROOT/cv-hpdcache if [ `uname -s` = "SunOS" ] then diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 24abdd071..5aae61048 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -34,6 +34,8 @@ -flist=$DV_ROOT/design/chip/tile/rtl/Flist.tile -flist=$DV_ROOT/design/chip/tile/rtap/rtl/Flist.rtap -flist=$DV_ROOT/design/chip/tile/l15/rtl/Flist.l15 + -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist + -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist #ifdef FLIST_PICO -flist=$DV_ROOT/design/chip/tile/pico/rtl/Flist.pico -rv32 From 9aaaecfd9d714a499d70f3ec52dd4a8466c2e5e9 Mon Sep 17 00:00:00 2001 From: AileonN Date: Thu, 20 Jul 2023 19:09:04 +0200 Subject: [PATCH 03/37] Update ariane submodule commit --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 074bc3313..5925e3b8b 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 074bc331378ed55be33bd86b84db4f31f805a5dc +Subproject commit 5925e3b8b3af0efebb5055a3c84e4bc1d5e93881 From 0c9b4eb63e5d4eacb00e8d68c7172652e0a275bb Mon Sep 17 00:00:00 2001 From: AileonN Date: Fri, 21 Jul 2023 10:31:55 +0200 Subject: [PATCH 04/37] Update ariane submodule commit --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 5925e3b8b..ba219c099 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 5925e3b8b3af0efebb5055a3c84e4bc1d5e93881 +Subproject commit ba219c099a9672e2d9f743f6b0ffe3a6412e860c From 949cdbbfd5bac959d29d5f1fb349092cceb1952d Mon Sep 17 00:00:00 2001 From: AileonN Date: Mon, 31 Jul 2023 17:55:21 +0200 Subject: [PATCH 05/37] Invalidation first draft --- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/l15/rtl/l15.v | 5 +++++ piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv | 8 ++++++-- piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv | 15 +++++++++++++-- piton/design/chip/tile/l15/rtl/l15_wrap.v | 2 ++ piton/design/chip/tile/rtl/tile.v.pyv | 3 +++ piton/design/include/l15.h.pyv | 2 +- 7 files changed, 31 insertions(+), 6 deletions(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index ba219c099..e3683c5b2 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit ba219c099a9672e2d9f743f6b0ffe3a6412e860c +Subproject commit e3683c5b243b02c5a01b5dc6ef3b5689b5aacf52 diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index 4e567de3c..1909a2285 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -85,6 +85,7 @@ module l15 ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, + output [`L15_PADDR_MASK] l15_transducer_address, output [15:4] l15_transducer_inval_address_15_4, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, @@ -486,6 +487,7 @@ wire [`L15_MSHR_ID_WIDTH-1:0] pipe_mshr_readreq_mshrid_s1; wire [`L15_CONTROL_WIDTH-1:0] mshr_pipe_readres_control_s1; wire [`PACKET_HOME_ID_WIDTH-1:0] mshr_pipe_readres_homeid_s1; wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1; +wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address; wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address; wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address; wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1; @@ -522,6 +524,7 @@ l15_mshr mshr( .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1), .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1), .mshr_pipe_vals_s1(mshr_pipe_vals_s1), + .mshr_pipe_ifill_address(mshr_pipe_ifill_address), .mshr_pipe_ld_address(mshr_pipe_ld_address), .mshr_pipe_st_address(mshr_pipe_st_address), .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1), @@ -751,6 +754,7 @@ l15_pipeline pipeline( .l15_cpxencoder_data_3 (l15_transducer_data_3), .l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way), .l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way), + .l15_cpxencoder_address (l15_transducer_address), .l15_cpxencoder_inval_address_15_4 (l15_transducer_inval_address_15_4), .l15_cpxencoder_cross_invalidate (l15_transducer_cross_invalidate), .l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way), @@ -834,6 +838,7 @@ l15_pipeline pipeline( .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1), .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1), .mshr_pipe_vals_s1(mshr_pipe_vals_s1), + .mshr_pipe_ifill_address(mshr_pipe_ifill_address), .mshr_pipe_ld_address(mshr_pipe_ld_address), .mshr_pipe_st_address(mshr_pipe_st_address), .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1), diff --git a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv index bd340d26c..b33c3ce1e 100644 --- a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv @@ -66,6 +66,7 @@ module l15_mshr( // s1/2/3 (address conflict checking) output reg [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1, + output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address, output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address, output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address, output reg [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1, @@ -118,7 +119,7 @@ reg [`L15_CONTROL_WIDTH-1:0] ld_control [0:`L15_NUM_THREADS-1]; reg [`L15_NUM_THREADS-1:0] ld_val; reg [`PACKET_HOME_ID_WIDTH-1:0] ld_homeid [0:`L15_NUM_THREADS-1]; -// reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1]; +reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1]; reg [`L15_CONTROL_WIDTH-1:0] ifill_control [0:`L15_NUM_THREADS-1]; reg [`L15_NUM_THREADS-1:0] ifill_val; // reg [`PACKET_HOME_ID_WIDTH-1:0] ifill_homeid [0:`L15_NUM_THREADS-1]; @@ -156,6 +157,7 @@ end reg [`L15_NUM_MSHRID_PER_THREAD-1:0] tmp_vals [`L15_NUM_THREADS-1:0]; reg [`L15_PADDR_HI:0] tmp_st_address [`L15_NUM_THREADS-1:0]; reg [`L15_PADDR_HI:0] tmp_ld_address [`L15_NUM_THREADS-1:0]; +reg [`L15_PADDR_HI:0] tmp_ifill_address [`L15_NUM_THREADS-1:0]; reg [2-1:0] tmp_st_way [`L15_NUM_THREADS-1:0]; reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] tmp_st_state [`L15_NUM_THREADS-1:0]; always @ * @@ -169,6 +171,7 @@ begin tmp_st_address[THREADID] = st_address[THREADID]; tmp_ld_address[THREADID] = ld_address[THREADID]; + tmp_ifill_address[THREADID] = ifill_address[THREADID]; tmp_st_way[THREADID] = st_way[THREADID]; tmp_st_state[THREADID] =st_state[THREADID]; ''' @@ -178,6 +181,7 @@ begin print(tt) %> mshr_pipe_vals_s1 = {tmp_vals[1], tmp_vals[0]}; + mshr_pipe_ifill_address = {tmp_ifill_address[1], tmp_ifill_address[0]}; mshr_pipe_ld_address = {tmp_ld_address[1], tmp_ld_address[0]}; mshr_pipe_st_address = {tmp_st_address[1], tmp_st_address[0]}; mshr_pipe_st_way_s1 = {tmp_st_way[1], tmp_st_way[0]}; @@ -238,7 +242,7 @@ begin case (mshrid_s1) `L15_MSHR_ID_IFILL: begin - // ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1; + ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1; ifill_control[threadid_s1] <= pipe_mshr_writereq_control_s1; end `L15_MSHR_ID_LD: diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index ce8a871ff..7b26b882d 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -178,6 +178,7 @@ module l15_pipeline( // s1/2/3 (address conflict checking) // tcov: 4 mshr per thread but 1 is unused input wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1, + input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address, input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address, input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address, input wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1, @@ -212,6 +213,7 @@ module l15_pipeline( output reg [`L15_UNPARAM_63_0] l15_cpxencoder_data_3, output reg l15_cpxencoder_inval_icache_all_way, output reg l15_cpxencoder_inval_dcache_all_way, // tcov: to core but not utilized, inval individually + output reg [`L15_PADDR_MASK] l15_cpxencoder_address, output reg [15:4] l15_cpxencoder_inval_address_15_4, output reg l15_cpxencoder_cross_invalidate, // tcov: to core but not utilized output reg [`L15_UNPARAM_1_0] l15_cpxencoder_cross_invalidate_way, // tcov: to core but not utilized @@ -392,6 +394,7 @@ reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] mshr_st_state_array [`L15_THREAD_ARRAY_MAS `endif reg [`L15_PADDR_MASK] mshr_st_address_array [`L15_THREAD_ARRAY_MASK]; reg [`L15_PADDR_MASK] mshr_ld_address_array [`L15_THREAD_ARRAY_MASK]; +reg [`L15_PADDR_MASK] mshr_ifill_address_array [`L15_THREAD_ARRAY_MASK]; reg [`L15_WAY_MASK] mshr_st_way_array [`L15_THREAD_ARRAY_MASK]; always @ * begin @@ -407,12 +410,14 @@ begin mshr_st_state_array[0] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*1 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; mshr_st_address_array[0] = mshr_pipe_st_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; mshr_ld_address_array[0] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; + mshr_ifill_address_array[0] = mshr_pipe_ifill_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; mshr_st_way_array[0] = mshr_pipe_st_way_s1[2*1 - 1 -: 2]; mshr_val_array[1] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*2 - 1 -: `L15_NUM_MSHRID_PER_THREAD]; mshr_st_state_array[1] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*2 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; mshr_st_address_array[1] = mshr_pipe_st_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; mshr_ld_address_array[1] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; + mshr_ifill_address_array[1] = mshr_pipe_ifill_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; mshr_st_way_array[1] = mshr_pipe_st_way_s1[2*2 - 1 -: 2]; end @@ -599,8 +604,10 @@ begin else if (predecode_non_cacheable_s1) begin - if (predecode_icache_bit_s1) + if (predecode_icache_bit_s1) begin predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_IFILL; + predecode_address_s1 = mshr_ifill_address_array[noc2decoder_l15_threadid]; + end else if (predecode_dcache_load_s1) predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_LD_NC; else if (predecode_atomic_s1) @@ -610,8 +617,10 @@ begin end else begin - if (predecode_icache_bit_s1) + if (predecode_icache_bit_s1) begin predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_IFILL; + predecode_address_s1 = mshr_ifill_address_array[noc2decoder_l15_threadid]; + end else if (predecode_atomic_s1) predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_LR; // Only Load Reserve is both Cacheable and AMO @@ -3877,6 +3886,7 @@ reg [`L15_UNPARAM_1_0] cpx_inval_way_s3; reg [`L15_CPX_SOURCE_WIDTH-1:0] cpx_data_source_s3; reg cpx_atomic_bit_s3; reg cpx_icache_inval_s3; + always @ * begin cpx_req_val_s3 = 0; @@ -4039,6 +4049,7 @@ begin l15_cpxencoder_atomic = 0; l15_cpxencoder_inval_icache_all_way = 0; l15_cpxencoder_inval_dcache_all_way = 0; + l15_cpxencoder_address = address_s3; l15_cpxencoder_inval_address_15_4[15:4] = 0; l15_cpxencoder_cross_invalidate = 0; l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 0; diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 932d2c04e..7c7c0cc2b 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -67,6 +67,7 @@ module l15_wrap ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, + output [`L15_PADDR_MASK] l15_transducer_address, output [15:4] l15_transducer_inval_address_15_4, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, @@ -156,6 +157,7 @@ module l15_wrap ( .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), + .l15_transducer_address (l15_transducer_address), .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index f6f0dd040..8baef3647 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -307,6 +307,7 @@ print(s) wire [63:0] l15_transducer_data_3; wire l15_transducer_inval_icache_all_way; wire l15_transducer_inval_dcache_all_way; + wire [`L15_PADDR_MASK] l15_transducer_address; wire [15:4] l15_transducer_inval_address_15_4; wire l15_transducer_cross_invalidate; wire [1:0] l15_transducer_cross_invalidate_way; @@ -841,6 +842,7 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core l15_transducer_data_3, l15_transducer_inval_icache_all_way, l15_transducer_inval_dcache_all_way, + l15_transducer_address, l15_transducer_inval_address_15_4, l15_transducer_cross_invalidate, l15_transducer_cross_invalidate_way, @@ -1020,6 +1022,7 @@ print(str) .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), + .l15_transducer_address (l15_transducer_address), .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 08ea642b0..8eedef15c 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -368,7 +368,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `define L15_RTRN_WIDTH (16 + 4*64 + (15 - 4 + 1) + \ `CPX_RESTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ - 2 * `L15_WAY_WIDTH) + 2 * `L15_WAY_WIDTH + `L15_PADDR_WIDTH) `define L15_FETCH_STATE_WIDTH 3 `define L15_FETCH_STATE_NORMAL 3'd0 From e1b7ac00029dbb5f0642726fb729edbcb91c215a Mon Sep 17 00:00:00 2001 From: AileonN Date: Tue, 1 Aug 2023 21:16:29 +0200 Subject: [PATCH 06/37] Fix: Store requests must send the data replicated --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index e3683c5b2..38a48a38a 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit e3683c5b243b02c5a01b5dc6ef3b5689b5aacf52 +Subproject commit 38a48a38ac8ecb940f1ddca54a2418ca264521fc From 34b3d210393a37df9e8e1b171002ba61bf30c148 Mon Sep 17 00:00:00 2001 From: AileonN Date: Mon, 7 Aug 2023 12:30:31 +0200 Subject: [PATCH 07/37] Fix: Invalidations asserts --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 38a48a38a..619a3867e 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 38a48a38ac8ecb940f1ddca54a2418ca264521fc +Subproject commit 619a3867e1b2492de3208e621346613b73042861 From a7597011c5b2b038063cdf99be0e4cd381ece6e8 Mon Sep 17 00:00:00 2001 From: AileonN Date: Mon, 7 Aug 2023 14:51:27 +0200 Subject: [PATCH 08/37] Fix: Uncached L1.5 responses --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 619a3867e..a3cda7a0a 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 619a3867e1b2492de3208e621346613b73042861 +Subproject commit a3cda7a0ac19eba83c1c362ccd9affdab90efacd From 8df64ba03d121d90f734e9fd7ecd35c02efbc8e4 Mon Sep 17 00:00:00 2001 From: AileonN Date: Thu, 10 Aug 2023 16:55:53 +0200 Subject: [PATCH 09/37] Added support for AMOs --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index a3cda7a0a..42a563e19 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit a3cda7a0ac19eba83c1c362ccd9affdab90efacd +Subproject commit 42a563e19808bf39450f5c6be9710ba5cc313d30 From b0c6f1642ba06ec16a72bae4d9227c46d7540c5b Mon Sep 17 00:00:00 2001 From: AileonN Date: Tue, 22 Aug 2023 14:49:26 +0200 Subject: [PATCH 10/37] Bug fix: Inval address when L1.5 evicts and Back-off for lrsc added --- piton/design/chip/tile/ariane | 2 +- .../design/chip/tile/l15/rtl/l15_pipeline.v.pyv | 16 ++++++++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 42a563e19..1b1d93cf9 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 42a563e19808bf39450f5c6be9710ba5cc313d30 +Subproject commit 1b1d93cf9ef385354b38f3e86ba29a5708a8ec06 diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index 7b26b882d..2b1fdf07b 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -3886,6 +3886,7 @@ reg [`L15_UNPARAM_1_0] cpx_inval_way_s3; reg [`L15_CPX_SOURCE_WIDTH-1:0] cpx_data_source_s3; reg cpx_atomic_bit_s3; reg cpx_icache_inval_s3; +reg [`L15_PADDR_MASK] cpx_inval_address_s3; always @ * begin @@ -3897,6 +3898,7 @@ begin cpx_data_source_s3 = 0; cpx_atomic_bit_s3 = 0; cpx_icache_inval_s3 = 0; + cpx_inval_address_s3[`L15_PADDR_MASK] = address_s3[`L15_PADDR_MASK]; case(cpx_operation_s3) `L15_CPX_GEN_ICACHE_INVALIDATION: begin @@ -3913,21 +3915,22 @@ begin end `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = tagcheck_state_mes_s3 && wmt_compare_match_s3; + cpx_req_val_s3 = tagcheck_state_mes_s3; // && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; end `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = lru_state_mes_s3 && wmt_compare_match_s3; + cpx_req_val_s3 = lru_state_mes_s3; // && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; + cpx_inval_address_s3[`L15_PADDR_MASK] = lru_way_address_s3[`L15_PADDR_MASK]; end `L15_CPX_GEN_INVALIDATION_IF_FLUSH_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = flush_state_mes_s3 && wmt_compare_match_s3; + cpx_req_val_s3 = flush_state_mes_s3; // && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; @@ -3978,7 +3981,7 @@ begin // third, stbuffer's L1-mapped way must be valid cpx_req_val_s3 = 1'b1; - cpx_invalidate_l1_s3 = wmt_compare_match_s3 && stbuf_compare_match_val_s3; + cpx_invalidate_l1_s3 = stbuf_compare_match_val_s3; // && wmt_compare_match_s3 ; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; cpx_inval_way_s3 = wmt_compare_match_way_s3; end @@ -3986,7 +3989,7 @@ begin begin cpx_req_val_s3 = tagcheck_state_me_s3; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; - cpx_invalidate_l1_s3 = wmt_compare_match_s3; + cpx_invalidate_l1_s3 = 1'b1; // wmt_compare_match_s3; cpx_inval_way_s3 = wmt_compare_match_way_s3; end `L15_CPX_GEN_IFILL_RESPONSE_FROM_NOC2: @@ -4049,7 +4052,7 @@ begin l15_cpxencoder_atomic = 0; l15_cpxencoder_inval_icache_all_way = 0; l15_cpxencoder_inval_dcache_all_way = 0; - l15_cpxencoder_address = address_s3; + l15_cpxencoder_address = '0; l15_cpxencoder_inval_address_15_4[15:4] = 0; l15_cpxencoder_cross_invalidate = 0; l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 0; @@ -4068,6 +4071,7 @@ begin l15_cpxencoder_atomic = cpx_atomic_bit_s3; l15_cpxencoder_inval_icache_all_way = cpx_icache_inval_s3; // l15_cpxencoder_inval_dcache_all_way = cpx_dcache_inval_all_s3; + l15_cpxencoder_address[`L15_PADDR_MASK] = cpx_inval_address_s3[`L15_PADDR_MASK]; l15_cpxencoder_inval_address_15_4[15:4] = address_s3[15:4]; l15_cpxencoder_cross_invalidate = 0; // Don't think we will be cross invalidating l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 2'b0; From 114d9d7042efb75175f9e009e14d577dbd9b31f9 Mon Sep 17 00:00:00 2001 From: AileonN Date: Wed, 23 Aug 2023 16:23:34 +0200 Subject: [PATCH 11/37] Bug fix: Onehot access to cache directory (invals and amo) --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 1b1d93cf9..58998f9a4 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 1b1d93cf9ef385354b38f3e86ba29a5708a8ec06 +Subproject commit 58998f9a4f3f2fbd00fdfac52b01b79c5392b5ec From e4e33b0493668199bf799565a1d08eb718ec3969 Mon Sep 17 00:00:00 2001 From: AileonN Date: Wed, 30 Aug 2023 11:53:07 +0200 Subject: [PATCH 12/37] Bug fixed: WBUF coalescing --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 58998f9a4..4332b862e 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 58998f9a4f3f2fbd00fdfac52b01b79c5392b5ec +Subproject commit 4332b862e866a0f3c0c0402ac6e231a045946060 From 0f0f62764e1fbdfeb1e6f77b9f096d2864e5b38d Mon Sep 17 00:00:00 2001 From: AileonN Date: Thu, 7 Sep 2023 19:03:59 +0200 Subject: [PATCH 13/37] Write coalescing enabled (WRITE_BYTE_MASK) --- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/l15/rtl/l15.v | 6 +++++ .../chip/tile/l15/rtl/l15_pipeline.v.pyv | 26 +++++++++++++------ piton/design/chip/tile/l15/rtl/l15_wrap.v | 4 +++ piton/design/chip/tile/rtl/tile.v.pyv | 12 ++++++++- piton/design/include/l15.h.pyv | 14 ++++++++-- 6 files changed, 52 insertions(+), 12 deletions(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 4332b862e..2a8a5c31e 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 4332b862e866a0f3c0c0402ac6e231a045946060 +Subproject commit 2a8a5c31e061155b3425c576fdd4b2e45e70003e diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index 1909a2285..e1b8b5a0b 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -66,6 +66,9 @@ module l15 ( input [63:0] transducer_l15_data, input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, + `ifdef WRITE_BYTE_MASK + input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + `endif output l15_transducer_ack, output l15_transducer_header_ack, @@ -678,6 +681,9 @@ l15_pipeline pipeline( .pcxdecoder_l15_data (transducer_l15_data), .pcxdecoder_l15_data_next_entry (transducer_l15_data_next_entry), .pcxdecoder_l15_csm_data (transducer_l15_csm_data), + `ifdef WRITE_BYTE_MASK + .pcxdecoder_l15_be (transducer_l15_be), + `endif .noc2decoder_l15_val(noc2decoder_l15_val), .noc2decoder_l15_mshrid(noc2decoder_l15_mshrid), .noc2decoder_l15_l2miss(noc2decoder_l15_l2miss), diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index 2b1fdf07b..d64e3ebd4 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -73,6 +73,9 @@ module l15_pipeline( input wire [`L15_UNPARAM_63_0] pcxdecoder_l15_data, input wire [`L15_UNPARAM_63_0] pcxdecoder_l15_data_next_entry, input wire pcxdecoder_l15_invalidate_cacheline, + `ifdef WRITE_BYTE_MASK + input wire [`L15_BYTE_MASK_WIDHT-1:0] pcxdecoder_l15_be, + `endif // noc2 input wire noc2decoder_l15_val, input wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid, @@ -2104,13 +2107,15 @@ reg [`L15_PADDR_MASK] s1_mshr_write_address_s1; reg [`L15_CONTROL_WIDTH-1:0] s1_mshr_write_control_s1; reg [`L15_MSHR_ID_WIDTH-1:0] s1_mshr_write_mshrid_s1; reg [`L15_THREADID_MASK] s1_mshr_write_threadid_s1; -reg [`L15_UNPARAM_15_0] unshifted_write_mask_s1; reg [`L15_UNPARAM_15_0] write_mask_s1; -reg [`L15_UNPARAM_15_0] write_mask_1B_s1; -reg [`L15_UNPARAM_15_0] write_mask_2B_s1; -reg [`L15_UNPARAM_15_0] write_mask_4B_s1; -reg [`L15_UNPARAM_15_0] write_mask_8B_s1; -reg [`L15_UNPARAM_15_0] write_mask_16B_s1; +`ifndef WRITE_BYTE_MASK + reg [`L15_UNPARAM_15_0] unshifted_write_mask_s1; + reg [`L15_UNPARAM_15_0] write_mask_1B_s1; + reg [`L15_UNPARAM_15_0] write_mask_2B_s1; + reg [`L15_UNPARAM_15_0] write_mask_4B_s1; + reg [`L15_UNPARAM_15_0] write_mask_8B_s1; + reg [`L15_UNPARAM_15_0] write_mask_16B_s1; +`endif // reg odd_extended_word_s1; always @ * begin @@ -2143,6 +2148,12 @@ begin end endcase +`ifdef WRITE_BYTE_MASK + + write_mask_s1 = (predecode_address_s1[3]) ? {8'b0,pcxdecoder_l15_be} : {pcxdecoder_l15_be,8'b0}; + +`else // ifndef WRITE_BYTE_MASK + unshifted_write_mask_s1 = (predecode_size_s1 == `MSG_DATA_SIZE_1B) ? 16'b1000_0000_0000_0000 : (predecode_size_s1 == `MSG_DATA_SIZE_2B) ? 16'b1100_0000_0000_0000 : (predecode_size_s1 == `MSG_DATA_SIZE_4B) ? 16'b1111_0000_0000_0000 : @@ -2182,8 +2193,7 @@ begin write_mask_s1 = write_mask_16B_s1; end endcase - - +`endif // s1 write pipe_mshr_writereq_val_s1 = s1_mshr_write_val_s1 && !stall_s1 && val_s1; pipe_mshr_writereq_op_s1[`L15_MSHR_WRITE_TYPE_WIDTH-1:0] = s1_mshr_write_type_s1[`L15_MSHR_WRITE_TYPE_WIDTH-1:0]; diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 7c7c0cc2b..30747b6ef 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -48,6 +48,9 @@ module l15_wrap ( input [63:0] transducer_l15_data, input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, + `ifdef WRITE_BYTE_MASK + input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + `endif output l15_transducer_ack, output l15_transducer_header_ack, @@ -138,6 +141,7 @@ module l15_wrap ( .transducer_l15_csm_data (transducer_l15_csm_data), .transducer_l15_data (transducer_l15_data), .transducer_l15_data_next_entry (transducer_l15_data_next_entry), + .transducer_l15_be (transducer_l15_be), .l15_transducer_ack (l15_transducer_ack), .l15_transducer_header_ack (l15_transducer_header_ack), diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index 8baef3647..1d726fbb5 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -274,6 +274,9 @@ print(s) wire [`PCX_REQTYPE_WIDTH-1:0] transducer_l15_rqtype; wire [`L15_AMO_OP_WIDTH-1:0] transducer_l15_amo_op; + `ifdef WRITE_BYTE_MASK + wire [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be; + `endif wire transducer_l15_nc; wire [`PCX_SIZE_FIELD_WIDTH-1:0] transducer_l15_size; @@ -869,7 +872,11 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core transducer_l15_data, transducer_l15_data_next_entry, transducer_l15_csm_data, - transducer_l15_amo_op} = l15_req; + transducer_l15_amo_op + `ifdef WRITE_BYTE_MASK + , + transducer_l15_be + `endif } = l15_req; // Could remove this converter after Ariane is changed to send the // PMesh standard data size @@ -1003,6 +1010,9 @@ print(str) .transducer_l15_csm_data (transducer_l15_csm_data), .transducer_l15_data (transducer_l15_data), .transducer_l15_data_next_entry (transducer_l15_data_next_entry), + `ifdef WRITE_BYTE_MASK + .transducer_l15_be (transducer_l15_be), + `endif .l15_transducer_ack (l15_transducer_ack), .l15_transducer_header_ack (l15_transducer_header_ack), diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 8eedef15c..4699406ba 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -358,13 +358,23 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `define L15_CONTROL_BLOCKSTORE_1B (`L15_CONTROL_NC_1B + 1) `define L15_CONTROL_WIDTH (`L15_CONTROL_BLOCKSTORE_1B + 1) +`ifdef WRITE_BYTE_MASK +// Byte mask +`define L15_BYTE_MASK_WIDHT 8 + +`define L15_REQ_WIDTH (14 + 40 + 2*64 + \ + `PCX_REQTYPE_WIDTH + \ + `L15_THREADID_WIDTH + \ + `L15_WAY_WIDTH + \ + `TLB_CSM_WIDTH + `L15_BYTE_MASK_WIDHT) +`else // define the width of the flattened, native L15 interface, used for ARIANE_RV64 option `define L15_REQ_WIDTH (14 + 40 + 2*64 + \ `PCX_REQTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ `L15_WAY_WIDTH + \ - `TLB_CSM_WIDTH ) - + `TLB_CSM_WIDTH) +`endif `define L15_RTRN_WIDTH (16 + 4*64 + (15 - 4 + 1) + \ `CPX_RESTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ From 95020e3b7ca9896a36b7f14d4459bfcbca069c5b Mon Sep 17 00:00:00 2001 From: AileonN Date: Tue, 12 Sep 2023 11:17:19 +0200 Subject: [PATCH 14/37] Bug fix: PITON_NO_CHIP_BRIDGE --- piton/design/chipset/rtl/chipset.v | 5 ++++- piton/verif/env/manycore/manycore_top.v.pyv | 6 +++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index fdbfddf60..e72bdd944 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -700,8 +700,11 @@ end `ifndef PITON_BOARD `ifndef PITONSYS_INC_PASSTHRU + `ifndef PITON_NO_CHIP_BRIDGE assign io_clk_loopback = io_clk; - `endif + `endif // PITON_NO_CHIP_BRIDGE + `endif // PITONSYS_INC_PASSTHRU + `ifdef PITON_CLKS_CHIPSET // If we are generating clocks, they are just the same as diff --git a/piton/verif/env/manycore/manycore_top.v.pyv b/piton/verif/env/manycore/manycore_top.v.pyv index 97bad28c0..7c400fcda 100644 --- a/piton/verif/env/manycore/manycore_top.v.pyv +++ b/piton/verif/env/manycore/manycore_top.v.pyv @@ -301,10 +301,14 @@ system system( `endif // endif PITON_CHIPSET_DIFF_CLK `else // ifndef PITON_CHIPSET_CLKS_GEN `ifndef VERILATOR +`ifndef PITON_NO_CHIP_BRIDGE .chipset_clk(chipset_clk), `else .chipset_clk(core_ref_clk), -`endif +`endif // endif PITON_NO_CHIP_BRIDGE +`else + .chipset_clk(core_ref_clk), +`endif // endif VERILATOR `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 .mc_clk(mem_clk), From be4cb324fb6a882a153da5dd84ef6a510de79f8b Mon Sep 17 00:00:00 2001 From: AileonN Date: Thu, 14 Sep 2023 19:49:40 +0200 Subject: [PATCH 15/37] ft added: Free thid list --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 2a8a5c31e..376eb3fc7 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 2a8a5c31e061155b3425c576fdd4b2e45e70003e +Subproject commit 376eb3fc7d9d08fae4da7d014d432d984a457fb5 From 58c528888a23df3e619c90165e324f391a322fef Mon Sep 17 00:00:00 2001 From: AileonN Date: Tue, 19 Sep 2023 17:10:37 +0200 Subject: [PATCH 16/37] Enabled the possibility to use or not WRITE_BYTE_MASK --- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/l15/rtl/l15_wrap.v | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 376eb3fc7..bd9c4c63c 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 376eb3fc7d9d08fae4da7d014d432d984a457fb5 +Subproject commit bd9c4c63c61a112c0372f6105b45cc5f29baca4d diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 30747b6ef..6293b354e 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -141,7 +141,9 @@ module l15_wrap ( .transducer_l15_csm_data (transducer_l15_csm_data), .transducer_l15_data (transducer_l15_data), .transducer_l15_data_next_entry (transducer_l15_data_next_entry), + `ifdef WRITE_BYTE_MASK .transducer_l15_be (transducer_l15_be), + `endif .l15_transducer_ack (l15_transducer_ack), .l15_transducer_header_ack (l15_transducer_header_ack), From 1c83647d918516959ca49bcc857c0ab1764c660e Mon Sep 17 00:00:00 2001 From: AileonN Date: Thu, 21 Sep 2023 11:35:41 +0200 Subject: [PATCH 17/37] Added some comments & parametric thid free list --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index bd9c4c63c..921745778 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit bd9c4c63c61a112c0372f6105b45cc5f29baca4d +Subproject commit 9217457787dce69c3be08a2bbe22bcf656185298 From cfdb343c54475853699e024a0cd00b172eab45dc Mon Sep 17 00:00:00 2001 From: AileonN Date: Fri, 27 Oct 2023 11:42:41 +0200 Subject: [PATCH 18/37] ft added: Parametric size of I$ non cachable requests --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 921745778..180f1d3af 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 9217457787dce69c3be08a2bbe22bcf656185298 +Subproject commit 180f1d3aff73de9ea2da6a25e52bb822a86440c4 From 1d96ead6069bbf6398576a5249c6dc40a4a19e27 Mon Sep 17 00:00:00 2001 From: AileonN Date: Fri, 27 Oct 2023 18:12:06 +0200 Subject: [PATCH 19/37] INVAL fifo entries increased to a high value. It's necessary to analyze the proper value of the FIFO --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 180f1d3af..d28026d60 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 180f1d3aff73de9ea2da6a25e52bb822a86440c4 +Subproject commit d28026d60379ab4ee665b79d01695722827620d7 From 2b9ed8df98c8dc0a5218904badec0ad1d8c0ef20 Mon Sep 17 00:00:00 2001 From: AileonN Date: Sat, 28 Oct 2023 15:17:53 +0200 Subject: [PATCH 20/37] Changing inval address signal + Added PITON_ARIANE_HPDC macro --- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/l15/rtl/l15.v | 14 +- .../chip/tile/l15/rtl/l15_pipeline.v.pyv | 139 ++++++++++++++---- piton/design/chip/tile/l15/rtl/l15_wrap.v | 6 +- piton/design/chip/tile/rtl/tile.v.pyv | 11 +- piton/design/include/l15.h.pyv | 2 +- piton/tools/src/sims/manycore.config | 4 +- 7 files changed, 127 insertions(+), 51 deletions(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index d28026d60..8bcc018f5 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit d28026d60379ab4ee665b79d01695722827620d7 +Subproject commit 8bcc018f558daf9fe4b4221fc3a5e3a2d0a7a9e7 diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index e1b8b5a0b..2d94e1bf5 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -88,8 +88,7 @@ module l15 ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, - output [`L15_PADDR_MASK] l15_transducer_address, - output [15:4] l15_transducer_inval_address_15_4, + output [`L15_PADDR_MASK] l15_transducer_inval_address, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, output l15_transducer_inval_dcache_inval, @@ -614,7 +613,7 @@ rf_l15_lrsc_flag lrsc_flag( // ); - +`ifndef PITON_ARIANE_HPDC // L1D is NOT HPDC // way map table wire l15_wmt_read_val_s2; wire [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2; @@ -634,7 +633,7 @@ rf_l15_wmt wmc( .write_data(l15_wmt_write_data_s3), .read_data(wmt_l15_data_s3) ); - +`endif // lru array, psuedo wire l15_lruarray_read_val_s1; wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1; @@ -664,7 +663,6 @@ l15_pipeline pipeline( .mesi_l15_dout_s2(mesi_l15_dout_s2), .lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2), .lruarray_l15_dout_s2(lruarray_l15_dout_s2), - .wmt_l15_data_s3(wmt_l15_data_s3), .pcxdecoder_l15_rqtype (transducer_l15_rqtype), .pcxdecoder_l15_amo_op (transducer_l15_amo_op), .pcxdecoder_l15_nc (transducer_l15_nc), @@ -733,12 +731,15 @@ l15_pipeline pipeline( .l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2), .l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2), .l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2), + `ifndef PITON_ARIANE_HPDC .l15_wmt_read_val_s2(l15_wmt_read_val_s2), .l15_wmt_read_index_s2(l15_wmt_read_index_s2), + .wmt_l15_data_s3(wmt_l15_data_s3), .l15_wmt_write_val_s3(l15_wmt_write_val_s3), .l15_wmt_write_index_s3(l15_wmt_write_index_s3), .l15_wmt_write_mask_s3(l15_wmt_write_mask_s3), .l15_wmt_write_data_s3(l15_wmt_write_data_s3), + `endif .l15_lruarray_read_val_s1(l15_lruarray_read_val_s1), .l15_lruarray_read_index_s1(l15_lruarray_read_index_s1), .l15_lruarray_write_val_s3(l15_lruarray_write_val_s3), @@ -760,8 +761,7 @@ l15_pipeline pipeline( .l15_cpxencoder_data_3 (l15_transducer_data_3), .l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way), .l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way), - .l15_cpxencoder_address (l15_transducer_address), - .l15_cpxencoder_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_cpxencoder_inval_address (l15_transducer_inval_address), .l15_cpxencoder_cross_invalidate (l15_transducer_cross_invalidate), .l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way), .l15_cpxencoder_inval_dcache_inval (l15_transducer_inval_dcache_inval), diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index d64e3ebd4..5944d6d7b 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -154,6 +154,7 @@ module l15_pipeline( output reg [`L15_CSM_GHID_WIDTH-1:0] l15_hmt_write_mask_s2, `endif + `ifndef PITON_ARIANE_HPDC // wmt output reg l15_wmt_read_val_s2, output reg [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2, @@ -162,7 +163,7 @@ module l15_pipeline( output reg [`L1D_SET_IDX_MASK] l15_wmt_write_index_s3, output reg [`L15_WMT_MASK] l15_wmt_write_mask_s3, output reg [`L15_WMT_MASK] l15_wmt_write_data_s3, - + `endif // MSHR //s1 (allocating) output reg pipe_mshr_writereq_val_s1, @@ -216,8 +217,7 @@ module l15_pipeline( output reg [`L15_UNPARAM_63_0] l15_cpxencoder_data_3, output reg l15_cpxencoder_inval_icache_all_way, output reg l15_cpxencoder_inval_dcache_all_way, // tcov: to core but not utilized, inval individually - output reg [`L15_PADDR_MASK] l15_cpxencoder_address, - output reg [15:4] l15_cpxencoder_inval_address_15_4, + output reg [`L15_PADDR_MASK] l15_cpxencoder_inval_address, output reg l15_cpxencoder_cross_invalidate, // tcov: to core but not utilized output reg [`L15_UNPARAM_1_0] l15_cpxencoder_cross_invalidate_way, // tcov: to core but not utilized output reg l15_cpxencoder_inval_dcache_inval, @@ -1111,9 +1111,11 @@ reg [`L15_S2_MESI_OP_WIDTH-1:0]decoder_mesi_read_op_s1; reg [`L15_DCACHE_OP_WIDTH-1:0]decoder_dcache_operation_s1; reg [`L15_S3_MSHR_OP_WIDTH-1:0]decoder_s3_mshr_operation_s1; reg [`L15_S3_MESI_OP_WIDTH-1:0]decoder_mesi_write_op_s1; +`ifndef PITON_ARIANE_HPDC reg [`L15_WMT_READ_OP_WIDTH-1:0]decoder_wmt_read_op_s1; reg [`L15_WMT_WRITE_OP_WIDTH-1:0]decoder_wmt_write_op_s1; reg [`L15_WMT_COMPARE_OP_WIDTH-1:0]decoder_wmt_compare_op_s1; +`endif reg [`L15_LRUARRAY_WRITE_OP_WIDTH-1:0]decoder_lruarray_write_op_s1; reg [`L15_CPX_OP_WIDTH-1:0]decoder_cpx_operation_s1; `ifndef NO_RTL_CSM @@ -1144,9 +1146,11 @@ begin decoder_dcache_operation_s1 = 1'b0; decoder_s3_mshr_operation_s1 = 1'b0; decoder_mesi_write_op_s1 = 1'b0; +`ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = 1'b0; decoder_wmt_write_op_s1 = 1'b0; decoder_wmt_compare_op_s1 = 1'b0; +`endif decoder_lruarray_write_op_s1 = 1'b0; decoder_cpx_operation_s1 = 1'b0; decoder_noc1_operation_s1 = 1'b0; @@ -1179,9 +1183,11 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_dcache_operation_s1 = `L15_DCACHE_READ_TAGCHECK_WAY_IF_M; // decoder_hmt_op_s1 = `L15_HMT_READ_TAGCHECK_WAY_IF_M; @@ -1247,9 +1253,11 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_READ_TAGCHECK_WAY_IF_MES; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION_IF_TAGCHECK_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_LD_RESPONSE_IF_TAGCHECK_MES_FROM_DCACHE; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_UPDATE_TAGCHECK_WAY_AND_DEDUP_ENTRY_IF_TAGCHECK_WAY_IS_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_MISS; decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_IS_MES; decoder_noc1_operation_s1 = `L15_NOC1_GEN_DATA_LD_REQUEST_IF_TAGCHECK_MISS; @@ -1303,10 +1311,12 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1344,8 +1354,10 @@ begin decoder_mshr_allocation_type_s1 = `L15_MSHR_ID_ST; decoder_s1_mshr_operation_s1 = `L15_S1_MSHR_OP_UPDATE_WRITECACHE; decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_STBUF; + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_ST_ACK_WITH_POSSIBLE_INVAL; end else @@ -1361,10 +1373,10 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_s2_mshr_operation_s1 = `L15_S2_MSHR_OP_READ_WRITE_CACHE; decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_TAGCHECK_WAY_IF_ME_FROM_MSHR; - + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; - + `endif decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_IS_MES; decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_SI; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION_IF_TAGCHECK_M_E_ELSE_UPDATE_STATE_STMSHR; @@ -1402,9 +1414,11 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_FLUSH_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_FLUSH_WAY; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_FLUSH_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_FLUSH; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_FLUSH_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_FLUSH_MES_AND_WAYMAP_VALID; @@ -1432,9 +1446,10 @@ begin decoder_s2_mshr_operation_s1 = `L15_S2_MSHR_OP_READ_WRITE_CACHE; decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_TAGCHECK_WAY_IF_LRSC_SET_FROM_MSHR; - + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_LRSC_SET; //decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_SI; @@ -1473,10 +1488,12 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1566,6 +1583,7 @@ begin decoder_pcx_ack_stage_s1 = `L15_ACK_STAGE_S1; decoder_stall_on_matched_bypassed_index_s1 = 1; decoder_dtag_operation_s1 = `L15_DTAG_OP_READ; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; @@ -1574,7 +1592,7 @@ begin `else decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug 3/28/16 `endif - + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_DCACHE_INVALIDATION; end // todo @@ -1604,11 +1622,12 @@ begin decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_TAGCHECK_WAY_MATCHES; decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; - + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1661,10 +1680,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_LRU_WAY; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; @@ -1681,6 +1702,7 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_LRU_WAY_FROM_NOC2; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_LRU_WAY_ACK_STATE; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_WRITE_LRU_WAY_L1_REPL_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_UPDATE_LRU_WAY_AND_DEDUP_ENTRY; @@ -1690,6 +1712,7 @@ begin // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug fix 3/28/16 decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; `endif + `endif decoder_lruarray_write_op_s1 = `L15_LRU_REPLACEMENT; decoder_cpx_operation_s1 = `L15_CPX_GEN_LD_RESPONSE_FROM_NOC2; `ifndef NO_RTL_CSM @@ -1723,10 +1746,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_LRU_WAY; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; @@ -1760,8 +1785,10 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_MSHR_WAY_FROM_MSHR; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_MSHR_WAY_ACK_STATE; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_STBUF; // wmt todo // WTF + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_ST_ACK_WITH_POSSIBLE_INVAL; decoder_creditman_noc1_unreserve_s1 = 1'b1; end @@ -1799,10 +1826,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; decoder_noc1_operation_s1 = `L15_NOC1_GEN_WRITEBACK_GUARD_IF_LRU_M; @@ -1819,6 +1848,7 @@ begin decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_LRU_WAY_ACK_STATE; // do this for unity, it can be set to M directly. decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_SET_LRU_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_WRITE_LRU_WAY_L1_REPL_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; // L1 won't save the line after an LR, so L15 should not update the wmt @@ -1829,6 +1859,7 @@ begin // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug fix 3/28/16 decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; `endif + `endif decoder_lruarray_write_op_s1 = `L15_LRU_REPLACEMENT; decoder_cpx_operation_s1 = `L15_CPX_GEN_ATOMIC_ACK_FROM_NOC2; `ifndef NO_RTL_CSM @@ -2270,12 +2301,9 @@ s2floplist = [ ('blockstoreinit', '1'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), ('decoder_dtag_operation', '`L15_DTAG_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), ('lruarray_write_op','`L15_LRUARRAY_WRITE_OP_WIDTH'), ('csm_op','`L15_CSM_OP_WIDTH'), ('config_op','`L15_CONFIG_OP_WIDTH'), - ('wmt_read_op','`L15_WMT_READ_OP_WIDTH'), ('noc2_src_homeid','`PACKET_HOME_ID_WIDTH'), ('hmt_fill_homeid','`PACKET_HOME_ID_WIDTH'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), @@ -2312,12 +2340,9 @@ s2floplist_no_rtl_csm = [ ('blockstoreinit', '1'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), ('decoder_dtag_operation', '`L15_DTAG_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), ('lruarray_write_op','`L15_LRUARRAY_WRITE_OP_WIDTH'), ('csm_op','`L15_CSM_OP_WIDTH'), ('config_op','`L15_CONFIG_OP_WIDTH'), - ('wmt_read_op','`L15_WMT_READ_OP_WIDTH'), ('noc2_src_homeid','`PACKET_HOME_ID_WIDTH'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), ('cpx_operation','`L15_CPX_OP_WIDTH'), @@ -2335,6 +2360,14 @@ s2floplist_no_rtl_csm = [ %> `endif reg val_s2_next; +`ifndef PITON_ARIANE_HPDC +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s2; +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s2_next; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s2; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s2_next; +reg [`L15_WMT_READ_OP_WIDTH-1:0] wmt_read_op_s2; +reg [`L15_WMT_READ_OP_WIDTH-1:0] wmt_read_op_s2_next; +`endif <% for e in s2floplist: @@ -2354,6 +2387,11 @@ begin name = e[0] + '_s2' print("%s <= 0;" % (name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2 <= 0; + wmt_compare_op_s2 <= 0; + wmt_read_op_s2 <= 0; + `endif end else begin @@ -2363,6 +2401,11 @@ begin name = e[0] + '_s2' print("%s <= %s_next;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2 <= wmt_write_op_s2_next; + wmt_compare_op_s2 <= wmt_compare_op_s2_next; + wmt_read_op_s2 <= wmt_read_op_s2_next; + `endif end end @@ -2386,12 +2429,22 @@ begin name = e[0] + '_s2' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2_next = wmt_write_op_s2; + wmt_compare_op_s2_next = wmt_compare_op_s2; + wmt_read_op_s2_next = wmt_read_op_s2; + `endif `else <% for e in s2floplist_no_rtl_csm: name = e[0] + '_s2' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2_next = wmt_write_op_s2; + wmt_compare_op_s2_next = wmt_compare_op_s2; + wmt_read_op_s2_next = wmt_read_op_s2; + `endif `endif end else @@ -2407,8 +2460,11 @@ begin l2_miss_s2_next = predecode_l2_miss_s1; f4b_s2_next = predecode_f4b_s1; // atomic_s2_next = predecode_atomic_s1; + `ifndef PITON_ARIANE_HPDC wmt_write_op_s2_next = decoder_wmt_write_op_s1; wmt_compare_op_s2_next = decoder_wmt_compare_op_s1; + wmt_read_op_s2_next = decoder_wmt_read_op_s1; + `endif lruarray_write_op_s2_next = decoder_lruarray_write_op_s1; csm_op_s2_next = decoder_csm_op_s1; config_op_s2_next = decoder_config_op_s1; @@ -2436,7 +2492,6 @@ begin `endif csm_pcx_data_s2_next = pcxdecoder_l15_csm_data; decoder_dtag_operation_s2_next = decoder_dtag_operation_s1; - wmt_read_op_s2_next = decoder_wmt_read_op_s1; `ifndef NO_RTL_CSM hmt_op_s2_next = decoder_hmt_op_s1; `endif @@ -3113,7 +3168,7 @@ begin l15_csm_req_pcx_data_s2 = csm_pcx_data_s2; end - +`ifndef PITON_ARIANE_HPDC /////////////////////// // WMT read op /////////////////////// @@ -3136,6 +3191,7 @@ begin l15_wmt_read_val_s2 = wmt_read_val_s2 && val_s2 && !stall_s2; l15_wmt_read_index_s2 = wmt_read_index_s2; end +`endif //////////////////////////// // config operation @@ -3205,8 +3261,6 @@ s3floplist = [ ('predecode_fwd_subcacheline_vector', '4'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), #('wmt_read_operation','`L15_WMT_READ_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), #('wmt_read_data','12'), ('csm_ticket','`L15_CSM_NUM_TICKETS_LOG2'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), @@ -3255,6 +3309,12 @@ reg flush_state_mes_s3; reg [`L15_PADDR_MASK] lru_way_address_s3; reg [`L15_PADDR_MASK] flush_way_address_s3; +`ifndef PITON_ARIANE_HPDC +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s3; +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s3_next; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s3; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s3_next; +`endif always @ (posedge clk) begin @@ -3270,6 +3330,10 @@ begin name = e[0] + '_s3' print("%s <= 0;" % (name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3 <= 0; + wmt_compare_op_s3 <= 0; + `endif end else begin @@ -3283,6 +3347,10 @@ begin name = e[0] + '_s3' print("%s <= %s_next;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3 <= wmt_write_op_s3_next; + wmt_compare_op_s3 <= wmt_compare_op_s3_next; + `endif end end @@ -3394,6 +3462,10 @@ always @* begin name = e[0] + '_s3' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3_next = wmt_write_op_s3; + wmt_compare_op_s3_next = wmt_compare_op_s3; + `endif end else begin @@ -3404,6 +3476,10 @@ always @* begin names2 = e[0] + '_s2' print("%s_next = %s;" % (name,names2)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3_next = wmt_write_op_s2; + wmt_compare_op_s3_next = wmt_compare_op_s2; + `endif end end @@ -3463,9 +3539,15 @@ end // CALCULATED INPUTS IN S3 // stbuf_way_s3 // LOCAL VARIABLES +`ifndef PITON_ARIANE_HPDC // L1D is HPDC reg [`L15_WMT_DATA_MASK] wmt_compare_data_s3; reg [`L15_WAY_MASK] wmt_compare_way_s3; +`endif // OUTPUTS +`ifdef PITON_ARIANE_HPDC // L1D is HPDC +reg wmt_compare_match_s3 = 1'b1; +reg [`L1D_WAY_MASK] wmt_compare_match_way_s3 = {`L1D_WAY_WIDTH{1'b0}}; +`else reg [`L15_WMT_ENTRY_MASK] wmt_data_s3 [0:`L1D_WAY_COUNT-1]; reg [`L1D_WAY_COUNT-1:0] wmt_compare_mask_s3; reg wmt_compare_match_s3; @@ -3538,7 +3620,7 @@ begin GenEncoder("wmt_compare_mask_s3[__WAY]", "wmt_compare_match_way_s3", CONFIG_L1D_ASSOCIATIVITY) %> end - +`endif ////////////////////// // LRU write logic ////////////////////// @@ -3624,6 +3706,7 @@ begin l15_lruarray_write_index_s3 = lruarray_write_index_s3; end +`ifndef PITON_ARIANE_HPDC /////////////////////// // WMT write op /////////////////////// @@ -3797,7 +3880,7 @@ begin l15_wmt_write_mask_s3 = wmt_write_mask_s3; l15_wmt_write_data_s3 = wmt_write_data_s3; end - +`endif @@ -3925,14 +4008,14 @@ begin end `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = tagcheck_state_mes_s3; // && wmt_compare_match_s3; + cpx_req_val_s3 = tagcheck_state_mes_s3 && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; end `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = lru_state_mes_s3; // && wmt_compare_match_s3; + cpx_req_val_s3 = lru_state_mes_s3 && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; @@ -3940,7 +4023,7 @@ begin end `L15_CPX_GEN_INVALIDATION_IF_FLUSH_MES_AND_WAYMAP_VALID: begin - cpx_req_val_s3 = flush_state_mes_s3; // && wmt_compare_match_s3; + cpx_req_val_s3 = flush_state_mes_s3 && wmt_compare_match_s3; cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; @@ -3991,7 +4074,7 @@ begin // third, stbuffer's L1-mapped way must be valid cpx_req_val_s3 = 1'b1; - cpx_invalidate_l1_s3 = stbuf_compare_match_val_s3; // && wmt_compare_match_s3 ; + cpx_invalidate_l1_s3 = stbuf_compare_match_val_s3 && wmt_compare_match_s3 ; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; cpx_inval_way_s3 = wmt_compare_match_way_s3; end @@ -3999,7 +4082,7 @@ begin begin cpx_req_val_s3 = tagcheck_state_me_s3; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; - cpx_invalidate_l1_s3 = 1'b1; // wmt_compare_match_s3; + cpx_invalidate_l1_s3 = wmt_compare_match_s3; cpx_inval_way_s3 = wmt_compare_match_way_s3; end `L15_CPX_GEN_IFILL_RESPONSE_FROM_NOC2: @@ -4062,8 +4145,7 @@ begin l15_cpxencoder_atomic = 0; l15_cpxencoder_inval_icache_all_way = 0; l15_cpxencoder_inval_dcache_all_way = 0; - l15_cpxencoder_address = '0; - l15_cpxencoder_inval_address_15_4[15:4] = 0; + l15_cpxencoder_inval_address = 0; l15_cpxencoder_cross_invalidate = 0; l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 0; l15_cpxencoder_inval_dcache_inval = 0; @@ -4081,8 +4163,7 @@ begin l15_cpxencoder_atomic = cpx_atomic_bit_s3; l15_cpxencoder_inval_icache_all_way = cpx_icache_inval_s3; // l15_cpxencoder_inval_dcache_all_way = cpx_dcache_inval_all_s3; - l15_cpxencoder_address[`L15_PADDR_MASK] = cpx_inval_address_s3[`L15_PADDR_MASK]; - l15_cpxencoder_inval_address_15_4[15:4] = address_s3[15:4]; + l15_cpxencoder_inval_address[`L15_PADDR_MASK] = cpx_inval_address_s3[`L15_PADDR_MASK]; l15_cpxencoder_cross_invalidate = 0; // Don't think we will be cross invalidating l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 2'b0; l15_cpxencoder_inval_dcache_inval = cpx_invalidate_l1_s3; // default diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 6293b354e..2d357e3c9 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -70,8 +70,7 @@ module l15_wrap ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, - output [`L15_PADDR_MASK] l15_transducer_address, - output [15:4] l15_transducer_inval_address_15_4, + output [`L15_PADDR_MASK] l15_transducer_inval_address, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, output l15_transducer_inval_dcache_inval, @@ -163,8 +162,7 @@ module l15_wrap ( .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), - .l15_transducer_address (l15_transducer_address), - .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_transducer_inval_address (l15_transducer_inval_address), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), .l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval), diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index 1d726fbb5..b35c530a4 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -310,8 +310,7 @@ print(s) wire [63:0] l15_transducer_data_3; wire l15_transducer_inval_icache_all_way; wire l15_transducer_inval_dcache_all_way; - wire [`L15_PADDR_MASK] l15_transducer_address; - wire [15:4] l15_transducer_inval_address_15_4; + wire [`L15_PADDR_MASK] l15_transducer_inval_address; wire l15_transducer_cross_invalidate; wire [1:0] l15_transducer_cross_invalidate_way; wire l15_transducer_inval_dcache_inval; @@ -705,7 +704,7 @@ if (TILE_TYPE == `SPARC_TILE) begin : g_sparc_core ,.l15_transducer_data_3 (l15_transducer_data_3) ,.l15_transducer_inval_icache_all_way (l15_transducer_inval_icache_all_way) ,.l15_transducer_inval_dcache_all_way (l15_transducer_inval_dcache_all_way) - ,.l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4) + ,.l15_transducer_inval_address_15_4 (l15_transducer_inval_address[15:4]) ,.l15_transducer_cross_invalidate (l15_transducer_cross_invalidate) ,.l15_transducer_cross_invalidate_way (l15_transducer_cross_invalidate_way) ,.l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval) @@ -845,8 +844,7 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core l15_transducer_data_3, l15_transducer_inval_icache_all_way, l15_transducer_inval_dcache_all_way, - l15_transducer_address, - l15_transducer_inval_address_15_4, + l15_transducer_inval_address, l15_transducer_cross_invalidate, l15_transducer_cross_invalidate_way, l15_transducer_inval_dcache_inval, @@ -1032,8 +1030,7 @@ print(str) .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), - .l15_transducer_address (l15_transducer_address), - .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_transducer_inval_address (l15_transducer_inval_address), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), .l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval), diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 4699406ba..7309ab53e 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -375,7 +375,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `L15_WAY_WIDTH + \ `TLB_CSM_WIDTH) `endif -`define L15_RTRN_WIDTH (16 + 4*64 + (15 - 4 + 1) + \ +`define L15_RTRN_WIDTH (16 + 4*64 + \ `CPX_RESTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ 2 * `L15_WAY_WIDTH + `L15_PADDR_WIDTH) diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 5aae61048..bb47f742c 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -34,8 +34,6 @@ -flist=$DV_ROOT/design/chip/tile/rtl/Flist.tile -flist=$DV_ROOT/design/chip/tile/rtap/rtl/Flist.rtap -flist=$DV_ROOT/design/chip/tile/l15/rtl/Flist.l15 - -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist - -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist #ifdef FLIST_PICO -flist=$DV_ROOT/design/chip/tile/pico/rtl/Flist.pico -rv32 @@ -78,6 +76,8 @@ -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC -config_rtl=WT_DCACHE + -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist + -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist #endif -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dft_common From c16226473d0ae247c5a2de2ee9a120ec4fd4d7b6 Mon Sep 17 00:00:00 2001 From: AileonN Date: Sat, 28 Oct 2023 20:35:59 +0200 Subject: [PATCH 21/37] Solved compile errors due to monitor and flist --- piton/tools/src/sims/manycore.config | 4 +-- .../env/manycore/cmp_l15_messages_mon.v.pyv | 35 +++++++++++++------ 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index bb47f742c..f4df9eea0 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -64,6 +64,8 @@ -config_rtl=PITON_OST1 #endif #ifdef FLIST_ARIANE + -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist + -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist -flist=$ARIANE_ROOT/Flist.ariane -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" @@ -76,8 +78,6 @@ -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC -config_rtl=WT_DCACHE - -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist - -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist #endif -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dft_common diff --git a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv index 70e0937fb..24de361c1 100644 --- a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv +++ b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv @@ -351,9 +351,14 @@ reg [`L15_WMT_ENTRY_MASK] wmt_read_data_TILE0 [0:3]; integer j_TILE0; reg is_csm_mshrid_TILE0; + reg wmt_read_val_s3_TILE0; always @ (posedge clk) + `ifdef PITON_ARIANE_HPDC + wmt_read_val_s3_TILE0 <= 0; + `else wmt_read_val_s3_TILE0 <= `L15_PIPE0.l15_wmt_read_val_s2; + `endif always @ (negedge clk) begin @@ -920,19 +925,27 @@ begin // $display(" WMT way3: %x 0x%x", `L15_PIPE0.wmt_data_s3[3][`L15_WMT_VALID_MASK], `L15_PIPE0.wmt_data_s3[3][`L15_WMT_DATA_MASK]); for (i = 0; i < `L1D_WAY_COUNT; i = i + 1) begin + `ifdef PITON_ARIANE_HPDC + $display(" WMT way%d: %x 0x%x", i, 0, 0); + `else $display(" WMT way%d: %x 0x%x", i, `L15_PIPE0.wmt_data_s3[i][`L15_WMT_VALID_MASK], `L15_PIPE0.wmt_data_s3[i][`L15_WMT_DATA_MASK]); + `endif end end - if (`L15_PIPE0.l15_wmt_write_val_s3) - begin - $display(" TILE0 WMT write index: %x", `L15_PIPE0.cache_index_l1d_s3[`L1D_SET_IDX_MASK]); - // $display(" WMT write mask: %x", `L15_PIPE0.l15_wmt_write_mask_s3); - // $display(" WMT write data: %x", `L15_PIPE0.l15_wmt_write_data_s3); - // $display(" WMT way0 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_0_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_0_MASK]); - // $display(" WMT way1 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_1_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_1_MASK]); - // $display(" WMT way2 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_2_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_2_MASK]); - // $display(" WMT way3 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_3_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_3_MASK]); - end + `ifdef PITON_ARIANE_HPDC + $display(" TILE0 WMT write index: %x", 0); + `else + if (`L15_PIPE0.l15_wmt_write_val_s3) + begin + $display(" TILE0 WMT write index: %x", `L15_PIPE0.cache_index_l1d_s3[`L1D_SET_IDX_MASK]); + // $display(" WMT write mask: %x", `L15_PIPE0.l15_wmt_write_mask_s3); + // $display(" WMT write data: %x", `L15_PIPE0.l15_wmt_write_data_s3); + // $display(" WMT way0 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_0_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_0_MASK]); + // $display(" WMT way1 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_1_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_1_MASK]); + // $display(" WMT way2 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_2_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_2_MASK]); + // $display(" WMT way3 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_3_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_3_MASK]); + end + `endif end $display ("L15_MON_END"); $display (""); @@ -1174,6 +1187,7 @@ begin end // Monitor WMT duplicate error + `ifndef PITON_ARIANE_HPDC if (`L15_PIPE0.val_s3) begin {wmt_read_data_TILE0[3], wmt_read_data_TILE0[2], wmt_read_data_TILE0[1], wmt_read_data_TILE0[0]} = `L15_PIPE0.wmt_l15_data_s3; @@ -1192,6 +1206,7 @@ begin end end end + `endif // Monitor tags duplication error (bug #86) if (`L15_PIPE0.val_s2 && `L15_PIPE0.decoder_dtag_operation_s2 == `L15_DTAG_OP_READ) From 1785a7b7544d124d575a5c5e22548ec7656ec569 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Fri, 1 Dec 2023 11:26:47 +0100 Subject: [PATCH 22/37] Add -hpdc option for Ariane builds --- piton/tools/src/sims/manycore.config | 1 - piton/tools/src/sims/sims,2.0 | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index f4df9eea0..7c04ae767 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -77,7 +77,6 @@ -config_rtl=PITON_RV64_DEBUGUNIT -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC - -config_rtl=WT_DCACHE #endif -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dft_common diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 0b6076fec..e1456ced7 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -173,6 +173,7 @@ Getopt::Long::Configure ('no_auto_abbrev') ; 'parallel' => 0, 'ost1' => 0, 'ariane' => 0, + 'hpdc' => 0, 'pico' => 0, 'pico_het' => 0, 'post_process_cmd' => [], @@ -326,6 +327,7 @@ GetOptions (\%opt, 'parallel!', 'ost1!', 'ariane!', + 'hpdc!', 'pico!', 'pico_het!', 'sparcv9!', @@ -363,6 +365,14 @@ push (@{$opt{diaglist_cpp_args}}, "-DSPARCV9") if ($opt{ost1} || $opt{pico_ push (@{$opt{diaglist_cpp_args}}, "-DRISCV32") if ($opt{pico} || $opt{pico_het}) ; push (@{$opt{diaglist_cpp_args}}, "-DRISCV64") if ($opt{ariane}) ; +if ($opt{ariane}) { + if ($opt{hpdc}) { + push (@{$opt{config_rtl}}, "PITON_ARIANE_HPDC") + } else { + push (@{$opt{config_rtl}}, "WT_DCACHE") + } +} + ################################################################################ # define $result_dir ################################################################################ @@ -3062,6 +3072,10 @@ VERILOG COMPILATION RELATED this specifies that the ARIANE RV64GC core shall be used in this case, programs are compiled and assembled using the RISCV GCC toolchain. + -hpdc + with -ariane, this specifies that the HPDCache will be used with the Ariane core. + If not specified, Ariane will use its default dCache (WT_DCACHE) + VERILOG RUNTIME RELATED -vcs_run/-novcs_run From d22ee4067d259e43eb186a899fef5f2f68147e57 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Fri, 13 Sep 2024 11:45:57 +0200 Subject: [PATCH 23/37] Fix makefiles -march variables depending on RVV compiler version --- .../chipset/rv64_platform/bootrom/baremetal/Makefile | 10 +++++++++- .../chipset/rv64_platform/bootrom/linux/Makefile | 9 ++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/piton/design/chipset/rv64_platform/bootrom/baremetal/Makefile b/piton/design/chipset/rv64_platform/bootrom/baremetal/Makefile index 61734cdfb..f9e3d570c 100644 --- a/piton/design/chipset/rv64_platform/bootrom/baremetal/Makefile +++ b/piton/design/chipset/rv64_platform/bootrom/baremetal/Makefile @@ -1,9 +1,17 @@ bootrom_img = bootrom.img bootrom.sv GCC=riscv64-unknown-elf-gcc +GCC_VERSION_GTEQ_12 = $(shell expr `$(GCC) -dumpversion | cut -f1 -d.` \>= 12) OBJCOPY=riscv64-unknown-elf-objcopy DTB=rv64_platform.dtb PYTHON=python3 +CFLAGS=-mabi=lp64d -Tlinker.ld -nostdlib -static -Wl,--no-gc-sections + +ifeq "$(GCC_VERSION_GTEQ_12)" "1" + CFLAGS += -march=rv64imafd_zicsr +else + CFLAGS += -march=rv64imafd +endif all: $(bootrom_img) @@ -14,7 +22,7 @@ all: $(bootrom_img) $(OBJCOPY) -O binary $< $@ %.elf: %.S linker.ld $(DTB) - $(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@ + $(GCC) $(CFLAGS) $< -o $@ rv64_platform.dts: FORCE $(PYTHON) ${DV_ROOT}/tools/bin/riscvlib.py diff --git a/piton/design/chipset/rv64_platform/bootrom/linux/Makefile b/piton/design/chipset/rv64_platform/bootrom/linux/Makefile index e634d8423..1c1c18055 100644 --- a/piton/design/chipset/rv64_platform/bootrom/linux/Makefile +++ b/piton/design/chipset/rv64_platform/bootrom/linux/Makefile @@ -2,12 +2,19 @@ UART_FREQ ?= 30000000 MAX_HARTS ?= 1 CROSSCOMPILE ?= riscv64-unknown-elf- CC = ${CROSSCOMPILE}gcc +GCC_VERSION_GTEQ_12 = $(shell expr `$(CC) -dumpversion | cut -f1 -d.` \>= 12) PYTHON=python3 -CFLAGS = -DMAX_HARTS=$(MAX_HARTS) -DUART_FREQ=$(UART_FREQ) -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs +CFLAGS = -DMAX_HARTS=$(MAX_HARTS) -DUART_FREQ=$(UART_FREQ) -Os -ggdb -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs CCASFLAGS = -mcmodel=medany -mexplicit-relocs LDFLAGS = -nostdlib -nodefaultlibs -nostartfiles +ifeq "$(GCC_VERSION_GTEQ_12)" "1" + CFLAGS += -march=rv64ima_zicsr +else + CFLAGS += -march=rv64ima +endif + INCLUDES = -I./ -I./src SRCS_C = src/main.c src/uart.c src/spi.c src/sd.c src/gpt.c From 44c4202b267acac0bddef556e3ffd2f5fc894420 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 30 Nov 2023 15:45:14 +0100 Subject: [PATCH 24/37] Enable usage of verilator 5 --- piton/tools/src/sims/sims,2.0 | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index e1456ced7..2393e2424 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -1557,6 +1557,21 @@ sub generic_sim_build $build_cmd .= "-CFLAGS -lstdc++ " ; $build_cmd .= "-CFLAGS -I$dv_root/tools/pli/iop " ; $build_cmd .= "-CFLAGS -I$dv_root/tools/verilator " ; + + # Run the verilator --version command and capture the output + my $verilator_version = `verilator --version`; + + # Extract the major version from the output + if ($verilator_version =~ /Verilator (\d)\.\d+/) { + # Print the major version + print "Verilator Major Version: $1\n"; + if ($1 == 5) { + $build_cmd .= "--no-timing " ; + } + } else { + # Handle the case where the version format doesn't match + die ("Error: Unable to extract Verilator major version.\n"); + } } if ($opt{other_sim_build}) { if (($opt{other_sim_build_cmd}) eq "") { From 28f2884110837f5f9d56537ae0ef5d7ed7f1dbe2 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Wed, 22 Oct 2025 19:12:09 +0200 Subject: [PATCH 25/37] Force linux risc-v bootrom makefile to make dtb before compiling anything --- piton/design/chipset/rv64_platform/bootrom/linux/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chipset/rv64_platform/bootrom/linux/Makefile b/piton/design/chipset/rv64_platform/bootrom/linux/Makefile index 1c1c18055..b1265d920 100644 --- a/piton/design/chipset/rv64_platform/bootrom/linux/Makefile +++ b/piton/design/chipset/rv64_platform/bootrom/linux/Makefile @@ -44,7 +44,7 @@ $(MAIN): rv64_platform.dtb $(OBJS_C) $(OBJS_S) linker.lds @$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@ @echo "CC <= $<" -%.o: %.S +%.o: %.S rv64_platform.dtb @echo "MAX_HARTS = $(MAX_HARTS)" @$(CC) $(CFLAGS) $(CCASFLAGS) $(INCLUDES) -c $< -o $@ @echo "CC <= $<" From bee1ceb20ebaeb83ec947530b0ef85cd465ee049 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Wed, 22 Oct 2025 19:13:34 +0200 Subject: [PATCH 26/37] Update riscv-tests, rv64 util.h & fix symlink paths in ariane_build_tools --- piton/ariane_build_tools.sh | 6 +++--- piton/verif/diag/riscv/rv64/include/util.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/piton/ariane_build_tools.sh b/piton/ariane_build_tools.sh index bf23965e6..71d60a595 100755 --- a/piton/ariane_build_tools.sh +++ b/piton/ariane_build_tools.sh @@ -70,7 +70,7 @@ else ci/install-verilator.sh # build the RISCV tests if necessary - VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f" + VERSION="master" cd tmp [ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git @@ -83,8 +83,8 @@ else # link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB cd benchmarks/common/ rm syscalls.c util.h - ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c - ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h + ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/syscalls.c + ln -s ${PITON_ROOT}/piton/verif/diag/riscv/rv64/include/util.h cd - cd build diff --git a/piton/verif/diag/riscv/rv64/include/util.h b/piton/verif/diag/riscv/rv64/include/util.h index 25f01831d..e854c641a 100644 --- a/piton/verif/diag/riscv/rv64/include/util.h +++ b/piton/verif/diag/riscv/rv64/include/util.h @@ -105,6 +105,22 @@ static int verifyDouble(int n, const volatile double* test, const double* verify return 0; } +static int verifyFloat(int n, const volatile float* test, const float* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + float t0 = test[i], t1 = test[i+1]; + float v0 = verify[i], v1 = verify[i+1]; + int eq1 = t0 == v0, eq2 = t1 == v1; + if (!(eq1 & eq2)) return i+1+eq1; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + static void __attribute__((noinline)) barrier(int ncores) { static volatile int sense; From 8ff301f3ba567fdc0ce5344aed99d4ea69b91acd Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Tue, 28 Oct 2025 10:37:04 +0100 Subject: [PATCH 27/37] Fix sims not substituting env variables in curly brackets --- piton/tools/src/sims/sims,2.0 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 2393e2424..b45f04d42 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -1160,7 +1160,7 @@ sub gen_flist next ; } - $line =~ s/\$(\w+)/$ENV{$1}/g ; + $line =~ s/\${?(\w+)}?/$ENV{$1}/g ; if ($line =~ /^\+incdir\+\//) { } From d471578fb821efcb26a7854fdb389e0a25cccdf3 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Fri, 6 Sep 2024 15:16:41 +0200 Subject: [PATCH 28/37] Add verilator VCD & FST tracing options to sims --- piton/tools/src/sims/sims,2.0 | 16 ++++++++++++++++ piton/tools/verilator/my_top.cpp | 20 ++++++++++++++------ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index b45f04d42..4dd7e0c7d 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -1558,6 +1558,16 @@ sub generic_sim_build $build_cmd .= "-CFLAGS -I$dv_root/tools/pli/iop " ; $build_cmd .= "-CFLAGS -I$dv_root/tools/verilator " ; + if ($opt{log_all}) { + $build_cmd .= "--trace --trace-structs --trace-params --trace-max-array 512 --trace-max-width 512 " ; + if ($opt{fst}) { + $build_cmd .= "--trace-fst --trace-threads 2 " ; + $build_cmd .= "-CFLAGS -DVERILATOR_FST " ; + } else { + $build_cmd .= "-CFLAGS -DVERILATOR_VCD " ; + } + } + # Run the verilator --version command and capture the output my $verilator_version = `verilator --version`; @@ -2635,6 +2645,7 @@ sub parse_args 'dynamic_csm=s', 'gui!', 'log_all!', + 'fst!', 'debug_all!', 'ibm!', 'ed_enable!', @@ -2977,6 +2988,11 @@ OPENPITON ARGUMENTS -log_all in a msm_run, this command logs all signals and dumps them to the "all-waves.wlf" file for later inspection with a wave viewer. + In a vlt_build, this command enables the tracing of all signals and dumps them to the my_top.vcd file for later inspection with a wave viewer. + + -fst + in a vlt_build, this command enables the usage of the FST format for the waves, allowing for smaller files and faster tracing. + Most be used with -log_all. -slurm -sim_q_command=sbatch specifies simulations should be submitted with the Simple Linux diff --git a/piton/tools/verilator/my_top.cpp b/piton/tools/verilator/my_top.cpp index ef9479f07..16f32ffd9 100644 --- a/piton/tools/verilator/my_top.cpp +++ b/piton/tools/verilator/my_top.cpp @@ -28,15 +28,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "verilated.h" #include #include -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) #include "verilated_vcd_c.h" +#elif defined(VERILATOR_FST) +#include "verilated_fst_c.h" #endif uint64_t main_time = 0; // Current simulation time uint64_t clk = 0; Vcmp_top* top; -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) VerilatedVcdC* tfp; +#elif defined(VERILATOR_FST) +VerilatedFstC* tfp; #endif extern "C" void init_jbus_model_call(char *str, int oram); @@ -52,13 +56,13 @@ void tick() { top->core_ref_clk = !top->core_ref_clk; main_time += 250; top->eval(); -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) || defined(VERILATOR_FST) tfp->dump(main_time); #endif top->core_ref_clk = !top->core_ref_clk; main_time += 250; top->eval(); -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) || defined(VERILATOR_FST) tfp->dump(main_time); #endif } @@ -161,9 +165,13 @@ Verilated::commandArgs(argc, argv); top = new Vcmp_top; std::cout << "Vcmp_top created" << std::endl << std::flush; -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) || defined(VERILATOR_FST) Verilated::traceEverOn(true); +#if defined(VERILATOR_VCD) tfp = new VerilatedVcdC; +#elif defined(VERILATOR_FST) +tfp = new VerilatedFstC; +#endif top->trace (tfp, 99); tfp->open ("my_top.vcd"); @@ -180,7 +188,7 @@ reset_and_init(); while (!Verilated::gotFinish()) { tick(); } -#ifdef VERILATOR_VCD +#if defined(VERILATOR_VCD) || defined(VERILATOR_FST) std::cout << "Trace done" << std::endl; tfp->close(); #endif From fdd5d9ec313122347f42a442b1d2b9cf94e1c411 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 30 Oct 2025 16:42:05 +0100 Subject: [PATCH 29/37] Fix hpdc paths in setup and flist order --- piton/ariane_setup.sh | 3 ++- piton/tools/src/sims/manycore.config | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/piton/ariane_setup.sh b/piton/ariane_setup.sh index b151d10e7..65e0ef6ce 100755 --- a/piton/ariane_setup.sh +++ b/piton/ariane_setup.sh @@ -70,7 +70,8 @@ fi # set root directory export PITON_ROOT=`pwd` -export ARIANE_ROOT=${PITON_ROOT}/piton/design/chip/tile/ariane/ +export ARIANE_ROOT=${PITON_ROOT}/piton/design/chip/tile/ariane +export HPDCACHE_DIR=$ARIANE_ROOT/core/cache_subsystem/hpdcache ## GCC and RISCV GCC setup export CXX=g++ CC=gcc diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 7c04ae767..c4d18f9fe 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -64,9 +64,8 @@ -config_rtl=PITON_OST1 #endif #ifdef FLIST_ARIANE - -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist - -flist=$HPDCACHE_DIR/rtl/hpdcache_cva6.Flist -flist=$ARIANE_ROOT/Flist.ariane + -flist=$HPDCACHE_DIR/rtl/hpdcache.Flist -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" -vcs_build_args=-timescale=1ps/1ps From 5d1e22d35409128c46b0bae5db79986c6ca96be5 Mon Sep 17 00:00:00 2001 From: Noelia Oliete Escuin Date: Thu, 14 Mar 2024 11:19:24 +0100 Subject: [PATCH 30/37] Update HPDC with refill & invalidation FIFO --- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/rtl/tile.v.pyv | 30 ++++++++------------------- piton/design/include/l15.h.pyv | 11 +--------- piton/piton_settings.bash | 2 -- piton/tools/src/sims/sims,2.0 | 6 ++++-- 5 files changed, 15 insertions(+), 36 deletions(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 8bcc018f5..39d297936 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 8bcc018f558daf9fe4b4221fc3a5e3a2d0a7a9e7 +Subproject commit 39d297936ec1035d587834436fed9b52be1d8b32 diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index b35c530a4..ad345d611 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -274,9 +274,7 @@ print(s) wire [`PCX_REQTYPE_WIDTH-1:0] transducer_l15_rqtype; wire [`L15_AMO_OP_WIDTH-1:0] transducer_l15_amo_op; - `ifdef WRITE_BYTE_MASK wire [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be; - `endif wire transducer_l15_nc; wire [`PCX_SIZE_FIELD_WIDTH-1:0] transducer_l15_size; @@ -852,14 +850,13 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core l15_transducer_inval_way, l15_transducer_blockinitstore }; - wire [2:0] transducer_l15_size_pcx_standard; - // see serpent_cache_pkg.sv for definition of the packed struct type "l15_req_t", - // note that the constants defined in l15.tmp.h and serpent_cache_pkg.sv need to coincide! + // see wt_cache_pkg.sv for definition of the packed struct type "l15_req_t", + // note that the constants defined in l15.tmp.h and wt_cache_pkg.sv need to coincide! assign { transducer_l15_val, transducer_l15_req_ack, transducer_l15_rqtype, transducer_l15_nc, - transducer_l15_size_pcx_standard, + transducer_l15_size[2:0], transducer_l15_threadid, transducer_l15_prefetch, transducer_l15_invalidate_cacheline, @@ -870,21 +867,8 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core transducer_l15_data, transducer_l15_data_next_entry, transducer_l15_csm_data, - transducer_l15_amo_op - `ifdef WRITE_BYTE_MASK - , - transducer_l15_be - `endif } = l15_req; - - // Could remove this converter after Ariane is changed to send the - // PMesh standard data size - assign transducer_l15_size = (transducer_l15_size_pcx_standard == 3'b000) ? `MSG_DATA_SIZE_1B : - (transducer_l15_size_pcx_standard == 3'b001) ? `MSG_DATA_SIZE_2B : - (transducer_l15_size_pcx_standard == 3'b010) ? `MSG_DATA_SIZE_4B : - (transducer_l15_size_pcx_standard == 3'b011) ? `MSG_DATA_SIZE_8B : - (transducer_l15_size_pcx_standard == 3'b111 && - transducer_l15_rqtype == `PCX_REQTYPE_IFILL && - ~transducer_l15_invalidate_cacheline) ? `MSG_DATA_SIZE_32B : `MSG_DATA_SIZE_16B; + transducer_l15_amo_op, + transducer_l15_be} = l15_req; wire [63:0] ariane_bootaddr; @@ -959,6 +943,10 @@ str = ''' .ExecuteRegionAddrBase ( %s ), .ExecuteRegionLength ( %s ), .NrCachedRegionRules ( 1 ), + `ifdef WRITE_BYTE_MASK + .WriteCoalescingEn (1'b1), + .WriteCoalescingTh (32'd2), + `endif .CachedRegionAddrBase ( {64'h%s} ), .CachedRegionLength ( {64'h%s} )''' % (dmBase, numRules, execBase, execLength, cacheBase, cacheLength) print(str) diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 7309ab53e..0695324d8 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -358,23 +358,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `define L15_CONTROL_BLOCKSTORE_1B (`L15_CONTROL_NC_1B + 1) `define L15_CONTROL_WIDTH (`L15_CONTROL_BLOCKSTORE_1B + 1) -`ifdef WRITE_BYTE_MASK // Byte mask `define L15_BYTE_MASK_WIDHT 8 - `define L15_REQ_WIDTH (14 + 40 + 2*64 + \ `PCX_REQTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ `L15_WAY_WIDTH + \ `TLB_CSM_WIDTH + `L15_BYTE_MASK_WIDHT) -`else -// define the width of the flattened, native L15 interface, used for ARIANE_RV64 option -`define L15_REQ_WIDTH (14 + 40 + 2*64 + \ - `PCX_REQTYPE_WIDTH + \ - `L15_THREADID_WIDTH + \ - `L15_WAY_WIDTH + \ - `TLB_CSM_WIDTH) -`endif + `define L15_RTRN_WIDTH (16 + 4*64 + \ `CPX_RESTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ diff --git a/piton/piton_settings.bash b/piton/piton_settings.bash index a326c25f5..7af1cd247 100644 --- a/piton/piton_settings.bash +++ b/piton/piton_settings.bash @@ -11,8 +11,6 @@ export DV_ROOT=$PITON_ROOT/piton export MODEL_DIR=$PITON_ROOT/build export OST1_ROOT=$DV_ROOT/design/chip/tile/sparc -export ARIANE_ROOT=$DV_ROOT/design/chip/tile/ariane -export HPDCACHE_DIR=$ARIANE_ROOT/cv-hpdcache if [ `uname -s` = "SunOS" ] then diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 4dd7e0c7d..1a70592d6 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -367,9 +367,10 @@ push (@{$opt{diaglist_cpp_args}}, "-DRISCV64") if ($opt{ariane}) ; if ($opt{ariane}) { if ($opt{hpdc}) { - push (@{$opt{config_rtl}}, "PITON_ARIANE_HPDC") + push (@{$opt{config_rtl}}, "PITON_ARIANE_HPDC"); + push (@{$opt{config_rtl}}, "HPDCACHE_OPENPITON"); } else { - push (@{$opt{config_rtl}}, "WT_DCACHE") + push (@{$opt{config_rtl}}, "WT_DCACHE"); } } @@ -1117,6 +1118,7 @@ sub gen_config print OCONF "`timescale 1ps/1ps\n" ; foreach my $unit (@{$opt{config_rtl}}) { + $unit =~ tr/"//d; # Remove " to allow preprocessing macros: config_rtl="ADDR_SIZE 50" print OCONF "`define $unit\n"; } From 8e9652d218b2ab33c6216ee9af9f5af5f2df550f Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Tue, 4 Nov 2025 18:43:51 +0100 Subject: [PATCH 31/37] Add l15 SystemVerilog pkg to expose types & interfaces to the cores --- piton/design/chip/tile/l15/rtl/Flist.l15 | 2 + piton/design/chip/tile/l15/rtl/l15_pkg.sv | 115 ++++++++++++++++++++++ piton/tools/src/sims/manycore.config | 4 +- 3 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 piton/design/chip/tile/l15/rtl/l15_pkg.sv diff --git a/piton/design/chip/tile/l15/rtl/Flist.l15 b/piton/design/chip/tile/l15/rtl/Flist.l15 index 91b1efa96..f6802539a 100644 --- a/piton/design/chip/tile/l15/rtl/Flist.l15 +++ b/piton/design/chip/tile/l15/rtl/Flist.l15 @@ -48,3 +48,5 @@ l15_priority_encoder.v sram_wrappers/sram_l15_tag.v sram_wrappers/sram_l15_data.v sram_wrappers/sram_l15_hmt.v + +l15_pkg.sv \ No newline at end of file diff --git a/piton/design/chip/tile/l15/rtl/l15_pkg.sv b/piton/design/chip/tile/l15/rtl/l15_pkg.sv new file mode 100644 index 000000000..3ba573dd6 --- /dev/null +++ b/piton/design/chip/tile/l15/rtl/l15_pkg.sv @@ -0,0 +1,115 @@ +`include "l15.tmp.h" + +package l15_pkg; + +parameter int unsigned L15_PADDR_WIDTH = 40; // Physical address bus in OpenPiton is 40 +parameter int unsigned L15_WORD_WIDTH = 64; +parameter int unsigned L15_DATA_BUS_WIDTH = 256; // Hardcoded for the moment, changed on parametric cachelines +parameter int unsigned L15_DATA_BUS_WORDS = L15_DATA_BUS_WIDTH/L15_WORD_WIDTH; +parameter int unsigned L15_BE_WIDTH = `L15_BYTE_MASK_WIDHT; +parameter int unsigned L15_TID_WIDTH = `L15_THREADID_WIDTH; +parameter int unsigned L15_SET_ASSOC = `CONFIG_L15_ASSOCIATIVITY; +parameter int unsigned L15_WAY_WIDTH = $clog2(L15_SET_ASSOC); +parameter int unsigned L15_TLB_CSM_WIDTH = `TLB_CSM_WIDTH; + +typedef enum logic [4:0] { + L15_LOAD_RQ = 5'b00000, // load request + L15_IMISS_RQ = 5'b10000, // instruction fill request + L15_STORE_RQ = 5'b00001, // store request + L15_ATOMIC_RQ = 5'b00110, // atomic op + //L15_CAS1_RQ = 5'b00010, // compare and swap1 packet (OpenSparc atomics) + //L15_CAS2_RQ = 5'b00011, // compare and swap2 packet (OpenSparc atomics) + //L15_SWAP_RQ = 5'b00110, // swap packet (OpenSparc atomics) + L15_STRLOAD_RQ = 5'b00100, // unused + L15_STRST_RQ = 5'b00101, // unused + L15_STQ_RQ = 5'b00111, // unused + L15_INT_RQ = 5'b01001, // interrupt request + L15_FWD_RQ = 5'b01101, // unused + L15_FWD_RPY = 5'b01110, // unused + L15_RSVD_RQ = 5'b11111 // unused +} l15_reqtypes_e; + +typedef enum logic [3:0] { + L15_LOAD_RET = 4'b0000, // load packet + //L15_INV_RET = 4'b0011, // invalidate packet, not unique... + L15_ST_ACK = 4'b0100, // store ack packet + //L15_AT_ACK = 4'b0011, // unused, not unique... + L15_INT_RET = 4'b0111, // interrupt packet + L15_TEST_RET = 4'b0101, // unused + L15_FP_RET = 4'b1000, // unused + L15_IFILL_RET = 4'b0001, // instruction fill packet + L15_EVICT_REQ = 4'b0011, // eviction request + L15_ERR_RET = 4'b1100, // unused + L15_STRLOAD_RET = 4'b0010, // unused + L15_STRST_ACK = 4'b0110, // unused + L15_FWD_RQ_RET = 4'b1010, // unused + L15_FWD_RPY_RET = 4'b1011, // unused + L15_RSVD_RET = 4'b1111, // unused + L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses +} l15_rtrntypes_e; + +typedef enum logic [3:0] { + AMO_NONE = 4'b0000, + AMO_LR = 4'b0001, + AMO_SC = 4'b0010, + AMO_SWAP = 4'b0011, + AMO_ADD = 4'b0100, + AMO_AND = 4'b0101, + AMO_OR = 4'b0110, + AMO_XOR = 4'b0111, + AMO_MAX = 4'b1000, + AMO_MAXU = 4'b1001, + AMO_MIN = 4'b1010, + AMO_MINU = 4'b1011, + AMO_CAS1 = 4'b1100, // unused, not part of riscv spec, but provided in OpenPiton + AMO_CAS2 = 4'b1101 // unused, not part of riscv spec, but provided in OpenPiton +} l15_amo_e; + +typedef struct packed { + logic l15_val; // valid signal, asserted with request + logic l15_req_ack; // ack for response + l15_reqtypes_e l15_rqtype; // see below for encoding + logic l15_nc; // non-cacheable bit + logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 + logic l15_prefetch; // unused in openpiton + logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment + logic l15_blockstore; // unused in openpiton + logic l15_blockinitstore; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace + logic [L15_PADDR_WIDTH-1:0] l15_address; // physical address + logic [L15_WORD_WIDTH-1:0] l15_data; // word to write + logic [L15_WORD_WIDTH-1:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) + logic [L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane + l15_amo_e l15_amo_op; // atomic operation type + logic [L15_BE_WIDTH-1:0] l15_be; +} l15_req_t; + +typedef struct packed { + logic l15_ack; // ack for request struct + logic l15_header_ack; // ack for request struct + logic l15_val; // valid signal for return struct + l15_rtrntypes_e l15_returntype; // see below for encoding + logic l15_l2miss; // unused in Ariane + logic [1:0] l15_error; // unused in openpiton + logic l15_noncacheable; // non-cacheable bit + logic l15_atomic; // asserted in load return and store ack packets of atomic tx + logic [L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID + logic l15_prefetch; // unused in openpiton + logic l15_f4b; // 4byte instruction fill from I/O space (nc). + logic [L15_WORD_WIDTH-1:0] l15_data_0; // used for both caches + logic [L15_WORD_WIDTH-1:0] l15_data_1; // used for both caches + logic [L15_WORD_WIDTH-1:0] l15_data_2; // currently only used for I$ + logic [L15_WORD_WIDTH-1:0] l15_data_3; // currently only used for I$ + logic l15_inval_icache_all_way; // invalidate all ways + logic l15_inval_dcache_all_way; // unused in openpiton + logic [L15_PADDR_WIDTH-1:0] l15_inval_address; // invalidate selected cacheline + logic l15_cross_invalidate; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton + logic l15_inval_dcache_inval; // invalidate selected cacheline and way + logic l15_inval_icache_inval; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate + logic l15_blockinitstore; // unused in openpiton +} l15_rtrn_t; + +endpackage; diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index c4d18f9fe..6f55bac50 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -33,7 +33,6 @@ -flist=$DV_ROOT/design/chip/jtag/rtl/Flist.jtag -flist=$DV_ROOT/design/chip/tile/rtl/Flist.tile -flist=$DV_ROOT/design/chip/tile/rtap/rtl/Flist.rtap - -flist=$DV_ROOT/design/chip/tile/l15/rtl/Flist.l15 #ifdef FLIST_PICO -flist=$DV_ROOT/design/chip/tile/pico/rtl/Flist.pico -rv32 @@ -77,6 +76,9 @@ -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC #endif + // l15 + -flist=$DV_ROOT/design/chip/tile/l15/rtl/Flist.l15 + // misc -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dft_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.ucb_common From 2bef9316e05cd292544d69d4da7b15b0af894430 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Tue, 4 Nov 2025 18:45:19 +0100 Subject: [PATCH 32/37] Update with working & upstream-ish ariane+hpdc --- .gitmodules | 2 +- piton/design/chip/tile/ariane | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index bd5a7edf3..27166615f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -12,4 +12,4 @@ url = git@github.com:openpiton/ost1-core.git [submodule "piton/design/chip/tile/ariane"] path = piton/design/chip/tile/ariane - url = https://github.com/AileonN/cva6_openpiton_noliete.git + url = https://github.com/bsc-loca/cva6.git diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 39d297936..cc16066ae 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 39d297936ec1035d587834436fed9b52be1d8b32 +Subproject commit cc16066aeddbc0e7caf580758595972f4f759885 From a097e6062de77598faef92323a67f35525a00871 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 6 Nov 2025 17:05:55 +0100 Subject: [PATCH 33/37] Update ariane with multidriven signal fix --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index cc16066ae..e9167b098 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit cc16066aeddbc0e7caf580758595972f4f759885 +Subproject commit e9167b098d136027f16e97c63b5a386f44e5422e From b16f8ad4bce9a1eec858d805259b1239e4dded52 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 7 May 2026 15:45:49 +0200 Subject: [PATCH 34/37] Update Ariane to latest upstream --- piton/design/chip/tile/ariane | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index e9167b098..eb6ff337b 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit e9167b098d136027f16e97c63b5a386f44e5422e +Subproject commit eb6ff337b5477aa352b714ebcce184d64dada2df From f6e5b9cd70336ad065aba7bfb3adfb5ad10c3a69 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 7 May 2026 15:52:12 +0200 Subject: [PATCH 35/37] Fix typo WIDHT -> WIDTH --- piton/design/chip/tile/l15/rtl/l15.v | 2 +- piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv | 2 +- piton/design/chip/tile/l15/rtl/l15_pkg.sv | 2 +- piton/design/chip/tile/l15/rtl/l15_wrap.v | 2 +- piton/design/chip/tile/rtl/tile.v.pyv | 7 ++++++- piton/design/include/l15.h.pyv | 4 ++-- 6 files changed, 12 insertions(+), 7 deletions(-) diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index 2d94e1bf5..2e00c93ff 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -67,7 +67,7 @@ module l15 ( input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, `ifdef WRITE_BYTE_MASK - input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + input [`L15_BYTE_MASK_WIDTH-1:0] transducer_l15_be, `endif output l15_transducer_ack, diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index 5944d6d7b..8b4b03b24 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -74,7 +74,7 @@ module l15_pipeline( input wire [`L15_UNPARAM_63_0] pcxdecoder_l15_data_next_entry, input wire pcxdecoder_l15_invalidate_cacheline, `ifdef WRITE_BYTE_MASK - input wire [`L15_BYTE_MASK_WIDHT-1:0] pcxdecoder_l15_be, + input wire [`L15_BYTE_MASK_WIDTH-1:0] pcxdecoder_l15_be, `endif // noc2 input wire noc2decoder_l15_val, diff --git a/piton/design/chip/tile/l15/rtl/l15_pkg.sv b/piton/design/chip/tile/l15/rtl/l15_pkg.sv index 3ba573dd6..52e325962 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pkg.sv +++ b/piton/design/chip/tile/l15/rtl/l15_pkg.sv @@ -6,7 +6,7 @@ parameter int unsigned L15_PADDR_WIDTH = 40; // Physical address bus in OpenP parameter int unsigned L15_WORD_WIDTH = 64; parameter int unsigned L15_DATA_BUS_WIDTH = 256; // Hardcoded for the moment, changed on parametric cachelines parameter int unsigned L15_DATA_BUS_WORDS = L15_DATA_BUS_WIDTH/L15_WORD_WIDTH; -parameter int unsigned L15_BE_WIDTH = `L15_BYTE_MASK_WIDHT; +parameter int unsigned L15_BE_WIDTH = `L15_BYTE_MASK_WIDTH; parameter int unsigned L15_TID_WIDTH = `L15_THREADID_WIDTH; parameter int unsigned L15_SET_ASSOC = `CONFIG_L15_ASSOCIATIVITY; parameter int unsigned L15_WAY_WIDTH = $clog2(L15_SET_ASSOC); diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 2d357e3c9..d035bb5d4 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -49,7 +49,7 @@ module l15_wrap ( input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, `ifdef WRITE_BYTE_MASK - input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + input [`L15_BYTE_MASK_WIDTH-1:0] transducer_l15_be, `endif output l15_transducer_ack, diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index ad345d611..69b1c7e35 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -274,7 +274,7 @@ print(s) wire [`PCX_REQTYPE_WIDTH-1:0] transducer_l15_rqtype; wire [`L15_AMO_OP_WIDTH-1:0] transducer_l15_amo_op; - wire [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be; + wire [`L15_BYTE_MASK_WIDTH-1:0] transducer_l15_be; wire transducer_l15_nc; wire [`PCX_SIZE_FIELD_WIDTH-1:0] transducer_l15_size; @@ -947,6 +947,11 @@ str = ''' .WriteCoalescingEn (1'b1), .WriteCoalescingTh (32'd2), `endif + `ifdef HPDCACHE_OPENPITON + .UseHPDcache(1'b1), + `else + .UseHPDcache(1'b0), + `endif .CachedRegionAddrBase ( {64'h%s} ), .CachedRegionLength ( {64'h%s} )''' % (dmBase, numRules, execBase, execLength, cacheBase, cacheLength) print(str) diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 0695324d8..e7ca0ae61 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -359,12 +359,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `define L15_CONTROL_WIDTH (`L15_CONTROL_BLOCKSTORE_1B + 1) // Byte mask -`define L15_BYTE_MASK_WIDHT 8 +`define L15_BYTE_MASK_WIDTH 8 `define L15_REQ_WIDTH (14 + 40 + 2*64 + \ `PCX_REQTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ `L15_WAY_WIDTH + \ - `TLB_CSM_WIDTH + `L15_BYTE_MASK_WIDHT) + `TLB_CSM_WIDTH + `L15_BYTE_MASK_WIDTH) `define L15_RTRN_WIDTH (16 + 4*64 + \ `CPX_RESTYPE_WIDTH + \ From 3d7c49886671291256cba6541a500954027d30ea Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 7 May 2026 19:07:40 +0200 Subject: [PATCH 36/37] Fix gitmodules --- .gitmodules | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 27166615f..81c910c22 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ +[submodule "piton/design/chip/tile/ariane"] + path = piton/design/chip/tile/ariane + url = https://github.com/openhwgroup/cva6.git [submodule "aws"] path = piton/design/aws url = https://github.com/PrincetonUniversity/openpiton-aws.git @@ -10,6 +13,3 @@ [submodule "piton/design/chip/tile/sparc"] path = piton/design/chip/tile/sparc url = git@github.com:openpiton/ost1-core.git -[submodule "piton/design/chip/tile/ariane"] - path = piton/design/chip/tile/ariane - url = https://github.com/bsc-loca/cva6.git From d76dfa66c05d9a25f15f159a2f59778c5ef6fb29 Mon Sep 17 00:00:00 2001 From: Arnau Bigas Date: Thu, 7 May 2026 19:10:34 +0200 Subject: [PATCH 37/37] Revert ARIANE_ROOT location and update verilator version --- piton/ariane_setup.sh | 7 ++++--- piton/piton_settings.bash | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/piton/ariane_setup.sh b/piton/ariane_setup.sh index 65e0ef6ce..c3c64d8ec 100755 --- a/piton/ariane_setup.sh +++ b/piton/ariane_setup.sh @@ -70,8 +70,6 @@ fi # set root directory export PITON_ROOT=`pwd` -export ARIANE_ROOT=${PITON_ROOT}/piton/design/chip/tile/ariane -export HPDCACHE_DIR=$ARIANE_ROOT/core/cache_subsystem/hpdcache ## GCC and RISCV GCC setup export CXX=g++ CC=gcc @@ -81,7 +79,7 @@ if [ "$RISCV" == "" ] then export RISCV=$HOME/scratch/riscv_install fi -export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-4.014/ +export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-5.008/ # setup paths export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH @@ -94,6 +92,9 @@ export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include # note: customize this script to reflect your tool setup source ./piton/piton_settings.bash +# HPDCACHE dir depends on ariane +export HPDCACHE_DIR=$ARIANE_ROOT/core/cache_subsystem/hpdcache + if [[ $(readlink -e "${RISCV}/bin/spike") == "" ]] then echo diff --git a/piton/piton_settings.bash b/piton/piton_settings.bash index 7af1cd247..253a4d705 100644 --- a/piton/piton_settings.bash +++ b/piton/piton_settings.bash @@ -11,6 +11,7 @@ export DV_ROOT=$PITON_ROOT/piton export MODEL_DIR=$PITON_ROOT/build export OST1_ROOT=$DV_ROOT/design/chip/tile/sparc +export ARIANE_ROOT=$DV_ROOT/design/chip/tile/ariane if [ `uname -s` = "SunOS" ] then