diff --git a/.gitmodules b/.gitmodules index 2888e69d7..74e1fc72c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,9 @@ -[submodule "piton/design/chip/tile/ariane"] - path = piton/design/chip/tile/ariane - url = https://github.com/pulp-platform/ariane.git [submodule "aws"] path = piton/design/aws url = https://github.com/PrincetonUniversity/openpiton-aws.git [submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"] path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot url = git@github.com:u-boot/u-boot.git +[submodule "piton/design/chip/tile/ariane"] + path = piton/design/chip/tile/ariane + url = https://github.com/AileonN/cva6_openpiton_noliete.git diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 4c01614f8..11cd43c25 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 4c01614f83cd9dd91d115aa190bd4fc6a284b59e +Subproject commit 11cd43c257108e2ebc13ad8ffec9f66f5a67ae71 diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index 4e567de3c..2d94e1bf5 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -66,6 +66,9 @@ module l15 ( input [63:0] transducer_l15_data, input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, + `ifdef WRITE_BYTE_MASK + input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + `endif output l15_transducer_ack, output l15_transducer_header_ack, @@ -85,7 +88,7 @@ module l15 ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, - output [15:4] l15_transducer_inval_address_15_4, + output [`L15_PADDR_MASK] l15_transducer_inval_address, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, output l15_transducer_inval_dcache_inval, @@ -486,6 +489,7 @@ wire [`L15_MSHR_ID_WIDTH-1:0] pipe_mshr_readreq_mshrid_s1; wire [`L15_CONTROL_WIDTH-1:0] mshr_pipe_readres_control_s1; wire [`PACKET_HOME_ID_WIDTH-1:0] mshr_pipe_readres_homeid_s1; wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1; +wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address; wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address; wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address; wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1; @@ -522,6 +526,7 @@ l15_mshr mshr( .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1), .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1), .mshr_pipe_vals_s1(mshr_pipe_vals_s1), + .mshr_pipe_ifill_address(mshr_pipe_ifill_address), .mshr_pipe_ld_address(mshr_pipe_ld_address), .mshr_pipe_st_address(mshr_pipe_st_address), .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1), @@ -608,7 +613,7 @@ rf_l15_lrsc_flag lrsc_flag( // ); - +`ifndef PITON_ARIANE_HPDC // L1D is NOT HPDC // way map table wire l15_wmt_read_val_s2; wire [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2; @@ -628,7 +633,7 @@ rf_l15_wmt wmc( .write_data(l15_wmt_write_data_s3), .read_data(wmt_l15_data_s3) ); - +`endif // lru array, psuedo wire l15_lruarray_read_val_s1; wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1; @@ -658,7 +663,6 @@ l15_pipeline pipeline( .mesi_l15_dout_s2(mesi_l15_dout_s2), .lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2), .lruarray_l15_dout_s2(lruarray_l15_dout_s2), - .wmt_l15_data_s3(wmt_l15_data_s3), .pcxdecoder_l15_rqtype (transducer_l15_rqtype), .pcxdecoder_l15_amo_op (transducer_l15_amo_op), .pcxdecoder_l15_nc (transducer_l15_nc), @@ -675,6 +679,9 @@ l15_pipeline pipeline( .pcxdecoder_l15_data (transducer_l15_data), .pcxdecoder_l15_data_next_entry (transducer_l15_data_next_entry), .pcxdecoder_l15_csm_data (transducer_l15_csm_data), + `ifdef WRITE_BYTE_MASK + .pcxdecoder_l15_be (transducer_l15_be), + `endif .noc2decoder_l15_val(noc2decoder_l15_val), .noc2decoder_l15_mshrid(noc2decoder_l15_mshrid), .noc2decoder_l15_l2miss(noc2decoder_l15_l2miss), @@ -724,12 +731,15 @@ l15_pipeline pipeline( .l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2), .l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2), .l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2), + `ifndef PITON_ARIANE_HPDC .l15_wmt_read_val_s2(l15_wmt_read_val_s2), .l15_wmt_read_index_s2(l15_wmt_read_index_s2), + .wmt_l15_data_s3(wmt_l15_data_s3), .l15_wmt_write_val_s3(l15_wmt_write_val_s3), .l15_wmt_write_index_s3(l15_wmt_write_index_s3), .l15_wmt_write_mask_s3(l15_wmt_write_mask_s3), .l15_wmt_write_data_s3(l15_wmt_write_data_s3), + `endif .l15_lruarray_read_val_s1(l15_lruarray_read_val_s1), .l15_lruarray_read_index_s1(l15_lruarray_read_index_s1), .l15_lruarray_write_val_s3(l15_lruarray_write_val_s3), @@ -751,7 +761,7 @@ l15_pipeline pipeline( .l15_cpxencoder_data_3 (l15_transducer_data_3), .l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way), .l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way), - .l15_cpxencoder_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_cpxencoder_inval_address (l15_transducer_inval_address), .l15_cpxencoder_cross_invalidate (l15_transducer_cross_invalidate), .l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way), .l15_cpxencoder_inval_dcache_inval (l15_transducer_inval_dcache_inval), @@ -834,6 +844,7 @@ l15_pipeline pipeline( .mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1), .mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1), .mshr_pipe_vals_s1(mshr_pipe_vals_s1), + .mshr_pipe_ifill_address(mshr_pipe_ifill_address), .mshr_pipe_ld_address(mshr_pipe_ld_address), .mshr_pipe_st_address(mshr_pipe_st_address), .mshr_pipe_st_way_s1(mshr_pipe_st_way_s1), diff --git a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv index bd340d26c..b33c3ce1e 100644 --- a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv @@ -66,6 +66,7 @@ module l15_mshr( // s1/2/3 (address conflict checking) output reg [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1, + output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address, output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address, output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address, output reg [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1, @@ -118,7 +119,7 @@ reg [`L15_CONTROL_WIDTH-1:0] ld_control [0:`L15_NUM_THREADS-1]; reg [`L15_NUM_THREADS-1:0] ld_val; reg [`PACKET_HOME_ID_WIDTH-1:0] ld_homeid [0:`L15_NUM_THREADS-1]; -// reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1]; +reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1]; reg [`L15_CONTROL_WIDTH-1:0] ifill_control [0:`L15_NUM_THREADS-1]; reg [`L15_NUM_THREADS-1:0] ifill_val; // reg [`PACKET_HOME_ID_WIDTH-1:0] ifill_homeid [0:`L15_NUM_THREADS-1]; @@ -156,6 +157,7 @@ end reg [`L15_NUM_MSHRID_PER_THREAD-1:0] tmp_vals [`L15_NUM_THREADS-1:0]; reg [`L15_PADDR_HI:0] tmp_st_address [`L15_NUM_THREADS-1:0]; reg [`L15_PADDR_HI:0] tmp_ld_address [`L15_NUM_THREADS-1:0]; +reg [`L15_PADDR_HI:0] tmp_ifill_address [`L15_NUM_THREADS-1:0]; reg [2-1:0] tmp_st_way [`L15_NUM_THREADS-1:0]; reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] tmp_st_state [`L15_NUM_THREADS-1:0]; always @ * @@ -169,6 +171,7 @@ begin tmp_st_address[THREADID] = st_address[THREADID]; tmp_ld_address[THREADID] = ld_address[THREADID]; + tmp_ifill_address[THREADID] = ifill_address[THREADID]; tmp_st_way[THREADID] = st_way[THREADID]; tmp_st_state[THREADID] =st_state[THREADID]; ''' @@ -178,6 +181,7 @@ begin print(tt) %> mshr_pipe_vals_s1 = {tmp_vals[1], tmp_vals[0]}; + mshr_pipe_ifill_address = {tmp_ifill_address[1], tmp_ifill_address[0]}; mshr_pipe_ld_address = {tmp_ld_address[1], tmp_ld_address[0]}; mshr_pipe_st_address = {tmp_st_address[1], tmp_st_address[0]}; mshr_pipe_st_way_s1 = {tmp_st_way[1], tmp_st_way[0]}; @@ -238,7 +242,7 @@ begin case (mshrid_s1) `L15_MSHR_ID_IFILL: begin - // ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1; + ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1; ifill_control[threadid_s1] <= pipe_mshr_writereq_control_s1; end `L15_MSHR_ID_LD: diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index 547417467..06334a58b 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -73,6 +73,9 @@ module l15_pipeline( input wire [`L15_UNPARAM_63_0] pcxdecoder_l15_data, input wire [`L15_UNPARAM_63_0] pcxdecoder_l15_data_next_entry, input wire pcxdecoder_l15_invalidate_cacheline, + `ifdef WRITE_BYTE_MASK + input wire [`L15_BYTE_MASK_WIDHT-1:0] pcxdecoder_l15_be, + `endif // noc2 input wire noc2decoder_l15_val, input wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid, @@ -151,6 +154,7 @@ module l15_pipeline( output reg [`L15_CSM_GHID_WIDTH-1:0] l15_hmt_write_mask_s2, `endif + `ifndef PITON_ARIANE_HPDC // wmt output reg l15_wmt_read_val_s2, output reg [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2, @@ -159,7 +163,7 @@ module l15_pipeline( output reg [`L1D_SET_IDX_MASK] l15_wmt_write_index_s3, output reg [`L15_WMT_MASK] l15_wmt_write_mask_s3, output reg [`L15_WMT_MASK] l15_wmt_write_data_s3, - + `endif // MSHR //s1 (allocating) output reg pipe_mshr_writereq_val_s1, @@ -178,6 +182,7 @@ module l15_pipeline( // s1/2/3 (address conflict checking) // tcov: 4 mshr per thread but 1 is unused input wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1, + input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address, input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address, input wire [(`L15_PADDR_WIDTH*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address, input wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1, @@ -212,7 +217,7 @@ module l15_pipeline( output reg [`L15_UNPARAM_63_0] l15_cpxencoder_data_3, output reg l15_cpxencoder_inval_icache_all_way, output reg l15_cpxencoder_inval_dcache_all_way, // tcov: to core but not utilized, inval individually - output reg [15:4] l15_cpxencoder_inval_address_15_4, + output reg [`L15_PADDR_MASK] l15_cpxencoder_inval_address, output reg l15_cpxencoder_cross_invalidate, // tcov: to core but not utilized output reg [`L15_UNPARAM_1_0] l15_cpxencoder_cross_invalidate_way, // tcov: to core but not utilized output reg l15_cpxencoder_inval_dcache_inval, @@ -392,6 +397,7 @@ reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] mshr_st_state_array [`L15_THREAD_ARRAY_MAS `endif reg [`L15_PADDR_MASK] mshr_st_address_array [`L15_THREAD_ARRAY_MASK]; reg [`L15_PADDR_MASK] mshr_ld_address_array [`L15_THREAD_ARRAY_MASK]; +reg [`L15_PADDR_MASK] mshr_ifill_address_array [`L15_THREAD_ARRAY_MASK]; reg [`L15_WAY_MASK] mshr_st_way_array [`L15_THREAD_ARRAY_MASK]; always @ * begin @@ -407,12 +413,14 @@ begin mshr_st_state_array[0] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*1 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; mshr_st_address_array[0] = mshr_pipe_st_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; mshr_ld_address_array[0] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; + mshr_ifill_address_array[0] = mshr_pipe_ifill_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; mshr_st_way_array[0] = mshr_pipe_st_way_s1[2*1 - 1 -: 2]; mshr_val_array[1] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*2 - 1 -: `L15_NUM_MSHRID_PER_THREAD]; mshr_st_state_array[1] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*2 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; mshr_st_address_array[1] = mshr_pipe_st_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; mshr_ld_address_array[1] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; + mshr_ifill_address_array[1] = mshr_pipe_ifill_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; mshr_st_way_array[1] = mshr_pipe_st_way_s1[2*2 - 1 -: 2]; end @@ -599,8 +607,10 @@ begin else if (predecode_non_cacheable_s1) begin - if (predecode_icache_bit_s1) + if (predecode_icache_bit_s1) begin predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_IFILL; + predecode_address_s1 = mshr_ifill_address_array[noc2decoder_l15_threadid]; + end else if (predecode_dcache_load_s1) predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_LD_NC; else if (predecode_atomic_s1) @@ -610,8 +620,10 @@ begin end else begin - if (predecode_icache_bit_s1) + if (predecode_icache_bit_s1) begin predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_IFILL; + predecode_address_s1 = mshr_ifill_address_array[noc2decoder_l15_threadid]; + end else if (predecode_atomic_s1) predecode_reqtype_s1 = `L15_REQTYPE_ACKDT_LR; // Only Load Reserve is both Cacheable and AMO @@ -1099,9 +1111,11 @@ reg [`L15_S2_MESI_OP_WIDTH-1:0]decoder_mesi_read_op_s1; reg [`L15_DCACHE_OP_WIDTH-1:0]decoder_dcache_operation_s1; reg [`L15_S3_MSHR_OP_WIDTH-1:0]decoder_s3_mshr_operation_s1; reg [`L15_S3_MESI_OP_WIDTH-1:0]decoder_mesi_write_op_s1; +`ifndef PITON_ARIANE_HPDC reg [`L15_WMT_READ_OP_WIDTH-1:0]decoder_wmt_read_op_s1; reg [`L15_WMT_WRITE_OP_WIDTH-1:0]decoder_wmt_write_op_s1; reg [`L15_WMT_COMPARE_OP_WIDTH-1:0]decoder_wmt_compare_op_s1; +`endif reg [`L15_LRUARRAY_WRITE_OP_WIDTH-1:0]decoder_lruarray_write_op_s1; reg [`L15_CPX_OP_WIDTH-1:0]decoder_cpx_operation_s1; `ifndef NO_RTL_CSM @@ -1132,9 +1146,11 @@ begin decoder_dcache_operation_s1 = 1'b0; decoder_s3_mshr_operation_s1 = 1'b0; decoder_mesi_write_op_s1 = 1'b0; +`ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = 1'b0; decoder_wmt_write_op_s1 = 1'b0; decoder_wmt_compare_op_s1 = 1'b0; +`endif decoder_lruarray_write_op_s1 = 1'b0; decoder_cpx_operation_s1 = 1'b0; decoder_noc1_operation_s1 = 1'b0; @@ -1167,9 +1183,11 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_dcache_operation_s1 = `L15_DCACHE_READ_TAGCHECK_WAY_IF_M; // decoder_hmt_op_s1 = `L15_HMT_READ_TAGCHECK_WAY_IF_M; @@ -1235,9 +1253,11 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_READ_TAGCHECK_WAY_IF_MES; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION_IF_TAGCHECK_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_LD_RESPONSE_IF_TAGCHECK_MES_FROM_DCACHE; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_UPDATE_TAGCHECK_WAY_AND_DEDUP_ENTRY_IF_TAGCHECK_WAY_IS_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_MISS; decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_IS_MES; decoder_noc1_operation_s1 = `L15_NOC1_GEN_DATA_LD_REQUEST_IF_TAGCHECK_MISS; @@ -1291,10 +1311,12 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1332,8 +1354,10 @@ begin decoder_mshr_allocation_type_s1 = `L15_MSHR_ID_ST; decoder_s1_mshr_operation_s1 = `L15_S1_MSHR_OP_UPDATE_WRITECACHE; decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_STBUF; + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_ST_ACK_WITH_POSSIBLE_INVAL; end else @@ -1349,10 +1373,10 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_s2_mshr_operation_s1 = `L15_S2_MSHR_OP_READ_WRITE_CACHE; decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_TAGCHECK_WAY_IF_ME_FROM_MSHR; - + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; - + `endif decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_IS_MES; decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_SI; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION_IF_TAGCHECK_M_E_ELSE_UPDATE_STATE_STMSHR; @@ -1390,9 +1414,11 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_FLUSH_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_FLUSH_WAY; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_FLUSH_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_FLUSH; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_FLUSH_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_FLUSH_MES_AND_WAYMAP_VALID; @@ -1420,9 +1446,10 @@ begin decoder_s2_mshr_operation_s1 = `L15_S2_MSHR_OP_READ_WRITE_CACHE; decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_TAGCHECK_WAY_IF_LRSC_SET_FROM_MSHR; - + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_UPDATE_ACCESS_BITS_IF_TAGCHECK_WAY_LRSC_SET; //decoder_csm_op_s1 = `L15_CSM_OP_READ_GHID_IF_TAGCHECK_SI; @@ -1461,10 +1488,12 @@ begin decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1554,6 +1583,7 @@ begin decoder_pcx_ack_stage_s1 = `L15_ACK_STAGE_S1; decoder_stall_on_matched_bypassed_index_s1 = 1; decoder_dtag_operation_s1 = `L15_DTAG_OP_READ; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; @@ -1562,7 +1592,7 @@ begin `else decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug 3/28/16 `endif - + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_DCACHE_INVALIDATION; end // todo @@ -1592,11 +1622,12 @@ begin decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_TAGCHECK_WAY_MATCHES; decoder_mesi_write_op_s1 = `L15_S3_MESI_INVALIDATE_TAGCHECK_WAY_IF_MES; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_TAGCHECK_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_TAGCHECK_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_TAGCHECK_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; - + `endif decoder_lruarray_write_op_s1 = `L15_LRU_INVALIDATE_IF_TAGCHECK_WAY_IS_MES; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_TAGCHECK_MES_AND_WAYMAP_VALID; @@ -1649,10 +1680,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_LRU_WAY; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; @@ -1669,6 +1702,7 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_LRU_WAY_FROM_NOC2; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_LRU_WAY_ACK_STATE; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_WRITE_LRU_WAY_L1_REPL_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_UPDATE_LRU_WAY_AND_DEDUP_ENTRY; @@ -1678,6 +1712,7 @@ begin // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug fix 3/28/16 decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; `endif + `endif decoder_lruarray_write_op_s1 = `L15_LRU_REPLACEMENT; decoder_cpx_operation_s1 = `L15_CPX_GEN_LD_RESPONSE_FROM_NOC2; `ifndef NO_RTL_CSM @@ -1711,10 +1746,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_CLEAR_LRU_WAY; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; @@ -1748,8 +1785,10 @@ begin decoder_dcache_operation_s1 = `L15_DCACHE_WRITE_MSHR_WAY_FROM_MSHR; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_MSHR_WAY_ACK_STATE; + `ifndef PITON_ARIANE_HPDC decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_STBUF; // wmt todo // WTF + `endif decoder_cpx_operation_s1 = `L15_CPX_GEN_ST_ACK_WITH_POSSIBLE_INVAL; decoder_creditman_noc1_unreserve_s1 = 1'b1; end @@ -1787,10 +1826,12 @@ begin decoder_mesi_read_op_s1 = `L15_S2_MESI_READ; decoder_dcache_operation_s1 = `L15_DCACHE_READ_LRU_WAY_IF_M; decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_UPDATE_ST_MSHR_IM_IF_INDEX_LRU_WAY_MATCHES; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_READ_LRU_WAY_IF_MES_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; decoder_wmt_write_op_s1 = `L15_WMT_DEMAP_LRU_WAY_IF_MES; decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; + `endif decoder_lruarray_write_op_s1 = `L15_LRU_EVICTION; decoder_cpx_operation_s1 = `L15_CPX_GEN_INVALIDATION_IF_LRU_MES_AND_WAYMAP_VALID; decoder_noc1_operation_s1 = `L15_NOC1_GEN_WRITEBACK_GUARD_IF_LRU_M; @@ -1807,6 +1848,7 @@ begin decoder_s3_mshr_operation_s1 = `L15_S3_MSHR_OP_DEALLOCATION; decoder_mesi_write_op_s1 = `L15_S3_MESI_WRITE_LRU_WAY_ACK_STATE; // do this for unity, it can be set to M directly. decoder_lrsc_flag_write_op_s1 = `L15_S2_LRSC_FLAG_SET_LRU_WAY; + `ifndef PITON_ARIANE_HPDC // decoder_wmt_operation_s1 = `L15_WMT_WRITE_LRU_WAY_L1_REPL_AND_DEMAP_ENTRY; decoder_wmt_read_op_s1 = `L15_WMT_READ; // L1 won't save the line after an LR, so L15 should not update the wmt @@ -1817,6 +1859,7 @@ begin // decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_TAGCHECK; // bug fix 3/28/16 decoder_wmt_compare_op_s1 = `L15_WMT_COMPARE_LRU; `endif + `endif decoder_lruarray_write_op_s1 = `L15_LRU_REPLACEMENT; decoder_cpx_operation_s1 = `L15_CPX_GEN_ATOMIC_ACK_FROM_NOC2; `ifndef NO_RTL_CSM @@ -2095,13 +2138,15 @@ reg [`L15_PADDR_MASK] s1_mshr_write_address_s1; reg [`L15_CONTROL_WIDTH-1:0] s1_mshr_write_control_s1; reg [`L15_MSHR_ID_WIDTH-1:0] s1_mshr_write_mshrid_s1; reg [`L15_THREADID_MASK] s1_mshr_write_threadid_s1; -reg [`L15_UNPARAM_15_0] unshifted_write_mask_s1; reg [`L15_UNPARAM_15_0] write_mask_s1; -reg [`L15_UNPARAM_15_0] write_mask_1B_s1; -reg [`L15_UNPARAM_15_0] write_mask_2B_s1; -reg [`L15_UNPARAM_15_0] write_mask_4B_s1; -reg [`L15_UNPARAM_15_0] write_mask_8B_s1; -reg [`L15_UNPARAM_15_0] write_mask_16B_s1; +`ifndef WRITE_BYTE_MASK + reg [`L15_UNPARAM_15_0] unshifted_write_mask_s1; + reg [`L15_UNPARAM_15_0] write_mask_1B_s1; + reg [`L15_UNPARAM_15_0] write_mask_2B_s1; + reg [`L15_UNPARAM_15_0] write_mask_4B_s1; + reg [`L15_UNPARAM_15_0] write_mask_8B_s1; + reg [`L15_UNPARAM_15_0] write_mask_16B_s1; +`endif // reg odd_extended_word_s1; always @ * begin @@ -2134,6 +2179,12 @@ begin end endcase +`ifdef WRITE_BYTE_MASK + + write_mask_s1 = (predecode_address_s1[3]) ? {8'b0,pcxdecoder_l15_be} : {pcxdecoder_l15_be,8'b0}; + +`else // ifndef WRITE_BYTE_MASK + unshifted_write_mask_s1 = (predecode_size_s1 == `MSG_DATA_SIZE_1B) ? 16'b1000_0000_0000_0000 : (predecode_size_s1 == `MSG_DATA_SIZE_2B) ? 16'b1100_0000_0000_0000 : (predecode_size_s1 == `MSG_DATA_SIZE_4B) ? 16'b1111_0000_0000_0000 : @@ -2173,8 +2224,7 @@ begin write_mask_s1 = write_mask_16B_s1; end endcase - - +`endif // s1 write pipe_mshr_writereq_val_s1 = s1_mshr_write_val_s1 && !stall_s1 && val_s1; pipe_mshr_writereq_op_s1[`L15_MSHR_WRITE_TYPE_WIDTH-1:0] = s1_mshr_write_type_s1[`L15_MSHR_WRITE_TYPE_WIDTH-1:0]; @@ -2251,12 +2301,9 @@ s2floplist = [ ('blockstoreinit', '1'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), ('decoder_dtag_operation', '`L15_DTAG_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), ('lruarray_write_op','`L15_LRUARRAY_WRITE_OP_WIDTH'), ('csm_op','`L15_CSM_OP_WIDTH'), ('config_op','`L15_CONFIG_OP_WIDTH'), - ('wmt_read_op','`L15_WMT_READ_OP_WIDTH'), ('noc2_src_homeid','`PACKET_HOME_ID_WIDTH'), ('hmt_fill_homeid','`PACKET_HOME_ID_WIDTH'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), @@ -2293,12 +2340,9 @@ s2floplist_no_rtl_csm = [ ('blockstoreinit', '1'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), ('decoder_dtag_operation', '`L15_DTAG_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), ('lruarray_write_op','`L15_LRUARRAY_WRITE_OP_WIDTH'), ('csm_op','`L15_CSM_OP_WIDTH'), ('config_op','`L15_CONFIG_OP_WIDTH'), - ('wmt_read_op','`L15_WMT_READ_OP_WIDTH'), ('noc2_src_homeid','`PACKET_HOME_ID_WIDTH'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), ('cpx_operation','`L15_CPX_OP_WIDTH'), @@ -2316,6 +2360,14 @@ s2floplist_no_rtl_csm = [ %> `endif reg val_s2_next; +`ifndef PITON_ARIANE_HPDC +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s2; +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s2_next; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s2; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s2_next; +reg [`L15_WMT_READ_OP_WIDTH-1:0] wmt_read_op_s2; +reg [`L15_WMT_READ_OP_WIDTH-1:0] wmt_read_op_s2_next; +`endif <% for e in s2floplist: @@ -2335,6 +2387,11 @@ begin name = e[0] + '_s2' print("%s <= 0;" % (name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2 <= 0; + wmt_compare_op_s2 <= 0; + wmt_read_op_s2 <= 0; + `endif end else begin @@ -2344,6 +2401,11 @@ begin name = e[0] + '_s2' print("%s <= %s_next;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2 <= wmt_write_op_s2_next; + wmt_compare_op_s2 <= wmt_compare_op_s2_next; + wmt_read_op_s2 <= wmt_read_op_s2_next; + `endif end end @@ -2367,12 +2429,22 @@ begin name = e[0] + '_s2' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2_next = wmt_write_op_s2; + wmt_compare_op_s2_next = wmt_compare_op_s2; + wmt_read_op_s2_next = wmt_read_op_s2; + `endif `else <% for e in s2floplist_no_rtl_csm: name = e[0] + '_s2' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s2_next = wmt_write_op_s2; + wmt_compare_op_s2_next = wmt_compare_op_s2; + wmt_read_op_s2_next = wmt_read_op_s2; + `endif `endif end else @@ -2388,8 +2460,11 @@ begin l2_miss_s2_next = predecode_l2_miss_s1; f4b_s2_next = predecode_f4b_s1; // atomic_s2_next = predecode_atomic_s1; + `ifndef PITON_ARIANE_HPDC wmt_write_op_s2_next = decoder_wmt_write_op_s1; wmt_compare_op_s2_next = decoder_wmt_compare_op_s1; + wmt_read_op_s2_next = decoder_wmt_read_op_s1; + `endif lruarray_write_op_s2_next = decoder_lruarray_write_op_s1; csm_op_s2_next = decoder_csm_op_s1; config_op_s2_next = decoder_config_op_s1; @@ -2417,7 +2492,6 @@ begin `endif csm_pcx_data_s2_next = pcxdecoder_l15_csm_data; decoder_dtag_operation_s2_next = decoder_dtag_operation_s1; - wmt_read_op_s2_next = decoder_wmt_read_op_s1; `ifndef NO_RTL_CSM hmt_op_s2_next = decoder_hmt_op_s1; `endif @@ -3094,7 +3168,7 @@ begin l15_csm_req_pcx_data_s2 = csm_pcx_data_s2; end - +`ifndef PITON_ARIANE_HPDC /////////////////////// // WMT read op /////////////////////// @@ -3117,6 +3191,7 @@ begin l15_wmt_read_val_s2 = wmt_read_val_s2 && val_s2 && !stall_s2; l15_wmt_read_index_s2 = wmt_read_index_s2; end +`endif //////////////////////////// // config operation @@ -3186,8 +3261,6 @@ s3floplist = [ ('predecode_fwd_subcacheline_vector', '4'), ('predecode_reqtype', '`L15_REQTYPE_WIDTH'), #('wmt_read_operation','`L15_WMT_READ_OP_WIDTH'), - ('wmt_write_op','`L15_WMT_WRITE_OP_WIDTH'), - ('wmt_compare_op','`L15_WMT_COMPARE_OP_WIDTH'), #('wmt_read_data','12'), ('csm_ticket','`L15_CSM_NUM_TICKETS_LOG2'), ('s3_mshr_operation','`L15_S3_MSHR_OP_WIDTH'), @@ -3236,6 +3309,12 @@ reg flush_state_mes_s3; reg [`L15_PADDR_MASK] lru_way_address_s3; reg [`L15_PADDR_MASK] flush_way_address_s3; +`ifndef PITON_ARIANE_HPDC +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s3; +reg [`L15_WMT_WRITE_OP_WIDTH-1:0] wmt_write_op_s3_next; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s3; +reg [`L15_WMT_COMPARE_OP_WIDTH-1:0] wmt_compare_op_s3_next; +`endif always @ (posedge clk) begin @@ -3251,6 +3330,10 @@ begin name = e[0] + '_s3' print("%s <= 0;" % (name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3 <= 0; + wmt_compare_op_s3 <= 0; + `endif end else begin @@ -3264,6 +3347,10 @@ begin name = e[0] + '_s3' print("%s <= %s_next;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3 <= wmt_write_op_s3_next; + wmt_compare_op_s3 <= wmt_compare_op_s3_next; + `endif end end @@ -3375,6 +3462,10 @@ always @* begin name = e[0] + '_s3' print("%s_next = %s;" % (name,name)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3_next = wmt_write_op_s3; + wmt_compare_op_s3_next = wmt_compare_op_s3; + `endif end else begin @@ -3385,6 +3476,10 @@ always @* begin names2 = e[0] + '_s2' print("%s_next = %s;" % (name,names2)) %> + `ifndef PITON_ARIANE_HPDC + wmt_write_op_s3_next = wmt_write_op_s2; + wmt_compare_op_s3_next = wmt_compare_op_s2; + `endif end end @@ -3444,9 +3539,15 @@ end // CALCULATED INPUTS IN S3 // stbuf_way_s3 // LOCAL VARIABLES +`ifndef PITON_ARIANE_HPDC // L1D is HPDC reg [`L15_WMT_DATA_MASK] wmt_compare_data_s3; reg [`L15_WAY_MASK] wmt_compare_way_s3; +`endif // OUTPUTS +`ifdef PITON_ARIANE_HPDC // L1D is HPDC +reg wmt_compare_match_s3 = 1'b1; +reg [`L1D_WAY_MASK] wmt_compare_match_way_s3 = {`L1D_WAY_WIDTH{1'b0}}; +`else reg [`L15_WMT_ENTRY_MASK] wmt_data_s3 [0:`L1D_WAY_COUNT-1]; reg [`L1D_WAY_COUNT-1:0] wmt_compare_mask_s3; reg wmt_compare_match_s3; @@ -3519,7 +3620,7 @@ begin GenEncoder("wmt_compare_mask_s3[__WAY]", "wmt_compare_match_way_s3", CONFIG_L1D_ASSOCIATIVITY) %> end - +`endif ////////////////////// // LRU write logic ////////////////////// @@ -3605,6 +3706,7 @@ begin l15_lruarray_write_index_s3 = lruarray_write_index_s3; end +`ifndef PITON_ARIANE_HPDC /////////////////////// // WMT write op /////////////////////// @@ -3778,7 +3880,7 @@ begin l15_wmt_write_mask_s3 = wmt_write_mask_s3; l15_wmt_write_data_s3 = wmt_write_data_s3; end - +`endif @@ -3877,6 +3979,8 @@ reg [`L15_UNPARAM_1_0] cpx_inval_way_s3; reg [`L15_CPX_SOURCE_WIDTH-1:0] cpx_data_source_s3; reg cpx_atomic_bit_s3; reg cpx_icache_inval_s3; +reg [`L15_PADDR_MASK] cpx_inval_address_s3; + always @ * begin cpx_req_val_s3 = 0; @@ -3887,6 +3991,7 @@ begin cpx_data_source_s3 = 0; cpx_atomic_bit_s3 = 0; cpx_icache_inval_s3 = 0; + cpx_inval_address_s3[`L15_PADDR_MASK] = address_s3[`L15_PADDR_MASK]; case(cpx_operation_s3) `L15_CPX_GEN_ICACHE_INVALIDATION: begin @@ -3914,6 +4019,7 @@ begin cpx_type_s3 = `CPX_RESTYPE_INVAL; cpx_invalidate_l1_s3 = 1; cpx_inval_way_s3 = wmt_compare_match_way_s3; + cpx_inval_address_s3[`L15_PADDR_MASK] = lru_way_address_s3[`L15_PADDR_MASK]; end `L15_CPX_GEN_INVALIDATION_IF_FLUSH_MES_AND_WAYMAP_VALID: begin @@ -3968,7 +4074,7 @@ begin // third, stbuffer's L1-mapped way must be valid cpx_req_val_s3 = 1'b1; - cpx_invalidate_l1_s3 = wmt_compare_match_s3 && stbuf_compare_match_val_s3; + cpx_invalidate_l1_s3 = stbuf_compare_match_val_s3 && wmt_compare_match_s3 ; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; cpx_inval_way_s3 = wmt_compare_match_way_s3; end @@ -3976,7 +4082,7 @@ begin begin cpx_req_val_s3 = tagcheck_state_me_s3; cpx_type_s3 = `CPX_RESTYPE_STORE_ACK; - cpx_invalidate_l1_s3 = wmt_compare_match_s3; + cpx_invalidate_l1_s3 = wmt_compare_match_s3; cpx_inval_way_s3 = wmt_compare_match_way_s3; end `L15_CPX_GEN_IFILL_RESPONSE_FROM_NOC2: @@ -4039,7 +4145,7 @@ begin l15_cpxencoder_atomic = 0; l15_cpxencoder_inval_icache_all_way = 0; l15_cpxencoder_inval_dcache_all_way = 0; - l15_cpxencoder_inval_address_15_4[15:4] = 0; + l15_cpxencoder_inval_address = 0; l15_cpxencoder_cross_invalidate = 0; l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 0; l15_cpxencoder_inval_dcache_inval = 0; @@ -4057,7 +4163,7 @@ begin l15_cpxencoder_atomic = cpx_atomic_bit_s3; l15_cpxencoder_inval_icache_all_way = cpx_icache_inval_s3; // l15_cpxencoder_inval_dcache_all_way = cpx_dcache_inval_all_s3; - l15_cpxencoder_inval_address_15_4[15:4] = address_s3[15:4]; + l15_cpxencoder_inval_address[`L15_PADDR_MASK] = cpx_inval_address_s3[`L15_PADDR_MASK]; l15_cpxencoder_cross_invalidate = 0; // Don't think we will be cross invalidating l15_cpxencoder_cross_invalidate_way[`L15_UNPARAM_1_0] = 2'b0; l15_cpxencoder_inval_dcache_inval = cpx_invalidate_l1_s3; // default diff --git a/piton/design/chip/tile/l15/rtl/l15_wrap.v b/piton/design/chip/tile/l15/rtl/l15_wrap.v index 932d2c04e..2d357e3c9 100644 --- a/piton/design/chip/tile/l15/rtl/l15_wrap.v +++ b/piton/design/chip/tile/l15/rtl/l15_wrap.v @@ -48,6 +48,9 @@ module l15_wrap ( input [63:0] transducer_l15_data, input [63:0] transducer_l15_data_next_entry, input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data, + `ifdef WRITE_BYTE_MASK + input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be, + `endif output l15_transducer_ack, output l15_transducer_header_ack, @@ -67,7 +70,7 @@ module l15_wrap ( output [63:0] l15_transducer_data_3, output l15_transducer_inval_icache_all_way, output l15_transducer_inval_dcache_all_way, - output [15:4] l15_transducer_inval_address_15_4, + output [`L15_PADDR_MASK] l15_transducer_inval_address, output l15_transducer_cross_invalidate, output [1:0] l15_transducer_cross_invalidate_way, output l15_transducer_inval_dcache_inval, @@ -137,6 +140,9 @@ module l15_wrap ( .transducer_l15_csm_data (transducer_l15_csm_data), .transducer_l15_data (transducer_l15_data), .transducer_l15_data_next_entry (transducer_l15_data_next_entry), + `ifdef WRITE_BYTE_MASK + .transducer_l15_be (transducer_l15_be), + `endif .l15_transducer_ack (l15_transducer_ack), .l15_transducer_header_ack (l15_transducer_header_ack), @@ -156,7 +162,7 @@ module l15_wrap ( .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), - .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_transducer_inval_address (l15_transducer_inval_address), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), .l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval), diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index 4c6048b01..6d528de07 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -286,6 +286,7 @@ print(s) wire [`PCX_REQTYPE_WIDTH-1:0] transducer_l15_rqtype; wire [`L15_AMO_OP_WIDTH-1:0] transducer_l15_amo_op; + wire [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be; wire transducer_l15_nc; wire [`PCX_SIZE_FIELD_WIDTH-1:0] transducer_l15_size; @@ -319,7 +320,7 @@ print(s) wire [63:0] l15_transducer_data_3; wire l15_transducer_inval_icache_all_way; wire l15_transducer_inval_dcache_all_way; - wire [15:4] l15_transducer_inval_address_15_4; + wire [`L15_PADDR_MASK] l15_transducer_inval_address; wire l15_transducer_cross_invalidate; wire [1:0] l15_transducer_cross_invalidate_way; wire l15_transducer_inval_dcache_inval; @@ -807,7 +808,7 @@ if (TILE_TYPE == `SPARC_TILE) begin : g_sparc_core .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), - .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_transducer_inval_address_15_4 (l15_transducer_inval_address[15:4]), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), .l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval), @@ -936,7 +937,7 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core l15_transducer_data_3, l15_transducer_inval_icache_all_way, l15_transducer_inval_dcache_all_way, - l15_transducer_inval_address_15_4, + l15_transducer_inval_address, l15_transducer_cross_invalidate, l15_transducer_cross_invalidate_way, l15_transducer_inval_dcache_inval, @@ -944,14 +945,13 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core l15_transducer_inval_way, l15_transducer_blockinitstore }; - wire [2:0] transducer_l15_size_pcx_standard; // see serpent_cache_pkg.sv for definition of the packed struct type "l15_req_t", // note that the constants defined in l15.tmp.h and serpent_cache_pkg.sv need to coincide! assign { transducer_l15_val, transducer_l15_req_ack, transducer_l15_rqtype, transducer_l15_nc, - transducer_l15_size_pcx_standard, + transducer_l15_size[2:0], transducer_l15_threadid, transducer_l15_prefetch, transducer_l15_invalidate_cacheline, @@ -962,17 +962,8 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core transducer_l15_data, transducer_l15_data_next_entry, transducer_l15_csm_data, - transducer_l15_amo_op} = l15_req; - - // Could remove this converter after Ariane is changed to send the - // PMesh standard data size - assign transducer_l15_size = (transducer_l15_size_pcx_standard == `PCX_SZ_1B) ? `MSG_DATA_SIZE_1B : - (transducer_l15_size_pcx_standard == `PCX_SZ_2B) ? `MSG_DATA_SIZE_2B : - (transducer_l15_size_pcx_standard == `PCX_SZ_4B) ? `MSG_DATA_SIZE_4B : - (transducer_l15_size_pcx_standard == `PCX_SZ_8B) ? `MSG_DATA_SIZE_8B : - (transducer_l15_size_pcx_standard == `PCX_SZ_16B && - transducer_l15_rqtype == `PCX_REQTYPE_IFILL && - ~transducer_l15_invalidate_cacheline) ? `MSG_DATA_SIZE_32B : `MSG_DATA_SIZE_16B; + transducer_l15_amo_op, + transducer_l15_be} = l15_req; wire [63:0] ariane_bootaddr; @@ -1047,6 +1038,10 @@ str = ''' .ExecuteRegionAddrBase ( %s ), .ExecuteRegionLength ( %s ), .NrCachedRegionRules ( 1 ), + `ifdef WRITE_BYTE_MASK + .WriteCoalescingEn (1'b1), + .WriteCoalescingTh (32'd2), + `endif .CachedRegionAddrBase ( {64'h%s} ), .CachedRegionLength ( {64'h%s} )''' % (dmBase, numRules, execBase, execLength, cacheBase, cacheLength) print(str) @@ -1096,6 +1091,9 @@ print(str) .transducer_l15_csm_data (transducer_l15_csm_data), .transducer_l15_data (transducer_l15_data), .transducer_l15_data_next_entry (transducer_l15_data_next_entry), + `ifdef WRITE_BYTE_MASK + .transducer_l15_be (transducer_l15_be), + `endif .l15_transducer_ack (l15_transducer_ack), .l15_transducer_header_ack (l15_transducer_header_ack), @@ -1115,7 +1113,7 @@ print(str) .l15_transducer_data_3 (l15_transducer_data_3), .l15_transducer_inval_icache_all_way(l15_transducer_inval_icache_all_way), .l15_transducer_inval_dcache_all_way(l15_transducer_inval_dcache_all_way), - .l15_transducer_inval_address_15_4 (l15_transducer_inval_address_15_4), + .l15_transducer_inval_address (l15_transducer_inval_address), .l15_transducer_cross_invalidate (l15_transducer_cross_invalidate), .l15_transducer_cross_invalidate_way(l15_transducer_cross_invalidate_way), .l15_transducer_inval_dcache_inval (l15_transducer_inval_dcache_inval), diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index fdbfddf60..e72bdd944 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -700,8 +700,11 @@ end `ifndef PITON_BOARD `ifndef PITONSYS_INC_PASSTHRU + `ifndef PITON_NO_CHIP_BRIDGE assign io_clk_loopback = io_clk; - `endif + `endif // PITON_NO_CHIP_BRIDGE + `endif // PITONSYS_INC_PASSTHRU + `ifdef PITON_CLKS_CHIPSET // If we are generating clocks, they are just the same as diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 3e8f62a38..f3c2d69c4 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -356,17 +356,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. `define L15_CONTROL_BLOCKSTORE_1B (`L15_CONTROL_NC_1B + 1) `define L15_CONTROL_WIDTH (`L15_CONTROL_BLOCKSTORE_1B + 1) -// define the width of the flattened, native L15 interface, used for ARIANE_RV64 option +`define L15_BYTE_MASK_WIDHT 8 `define L15_REQ_WIDTH (14 + 40 + 2*64 + \ `PCX_REQTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ `L15_WAY_WIDTH + \ - `TLB_CSM_WIDTH ) - -`define L15_RTRN_WIDTH (16 + 4*64 + (15 - 4 + 1) + \ + `TLB_CSM_WIDTH + `L15_BYTE_MASK_WIDHT) +`define L15_RTRN_WIDTH (16 + 4*64 + \ `CPX_RESTYPE_WIDTH + \ `L15_THREADID_WIDTH + \ - 2 * `L15_WAY_WIDTH) + 2 * `L15_WAY_WIDTH + `L15_PADDR_WIDTH) `define L15_FETCH_STATE_WIDTH 3 `define L15_FETCH_STATE_NORMAL 3'd0 diff --git a/piton/piton_settings.bash b/piton/piton_settings.bash index 79754ada4..075f57646 100644 --- a/piton/piton_settings.bash +++ b/piton/piton_settings.bash @@ -10,6 +10,8 @@ export DV_ROOT=$PITON_ROOT/piton export MODEL_DIR=$PITON_ROOT/build +export HPDCACHE_ROOT=$ARIANE_ROOT/cv-hpdcache +export HPDCACHE_DIR=../ if [ `uname -s` = "SunOS" ] then diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 2f6fc0c81..45d01776e 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -60,6 +60,8 @@ #endif #ifdef FLIST_ARIANE -flist=$DV_ROOT/design/chip/tile/ariane/Flist.ariane + -flist=$HPDCACHE_ROOT/rtl/hpdcache.Flist + -flist=$DV_ROOT/design/chip/tile/ariane/Flist.hpdc_param -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" -vcs_build_args=-timescale=1ps/1ps @@ -71,6 +73,7 @@ -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC -config_rtl=WT_DCACHE + -config_rtl=HPDCACHE_OPENPITON #endif -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dlib_common diff --git a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv index df43d7254..da299903b 100644 --- a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv +++ b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv @@ -353,9 +353,14 @@ reg [`L15_WMT_ENTRY_MASK] wmt_read_data_TILE0 [0:3]; integer j_TILE0; reg is_csm_mshrid_TILE0; + reg wmt_read_val_s3_TILE0; always @ (posedge clk) + `ifdef PITON_ARIANE_HPDC + wmt_read_val_s3_TILE0 <= 0; + `else wmt_read_val_s3_TILE0 <= `L15_PIPE0.l15_wmt_read_val_s2; + `endif always @ (negedge clk) begin @@ -924,19 +929,27 @@ begin // $display(" WMT way3: %x 0x%x", `L15_PIPE0.wmt_data_s3[3][`L15_WMT_VALID_MASK], `L15_PIPE0.wmt_data_s3[3][`L15_WMT_DATA_MASK]); for (i = 0; i < `L1D_WAY_COUNT; i = i + 1) begin + `ifdef PITON_ARIANE_HPDC + $display(" WMT way%d: %x 0x%x", i, 0, 0); + `else $display(" WMT way%d: %x 0x%x", i, `L15_PIPE0.wmt_data_s3[i][`L15_WMT_VALID_MASK], `L15_PIPE0.wmt_data_s3[i][`L15_WMT_DATA_MASK]); + `endif end end - if (`L15_PIPE0.l15_wmt_write_val_s3) - begin - $display(" TILE0 WMT write index: %x", `L15_PIPE0.cache_index_l1d_s3[`L1D_SET_IDX_MASK]); - // $display(" WMT write mask: %x", `L15_PIPE0.l15_wmt_write_mask_s3); - // $display(" WMT write data: %x", `L15_PIPE0.l15_wmt_write_data_s3); - // $display(" WMT way0 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_0_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_0_MASK]); - // $display(" WMT way1 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_1_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_1_MASK]); - // $display(" WMT way2 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_2_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_2_MASK]); - // $display(" WMT way3 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_3_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_3_MASK]); - end + `ifdef PITON_ARIANE_HPDC + $display(" TILE0 WMT write index: %x", 0); + `else + if (`L15_PIPE0.l15_wmt_write_val_s3) + begin + $display(" TILE0 WMT write index: %x", `L15_PIPE0.cache_index_l1d_s3[`L1D_SET_IDX_MASK]); + // $display(" WMT write mask: %x", `L15_PIPE0.l15_wmt_write_mask_s3); + // $display(" WMT write data: %x", `L15_PIPE0.l15_wmt_write_data_s3); + // $display(" WMT way0 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_0_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_0_MASK]); + // $display(" WMT way1 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_1_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_1_MASK]); + // $display(" WMT way2 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_2_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_2_MASK]); + // $display(" WMT way3 m%x d0x%x", `L15_PIPE0.l15_wmt_write_mask_s3[`L15_WMT_ENTRY_3_MASK], `L15_PIPE0.wmt_write_data_s3[`L15_WMT_ENTRY_3_MASK]); + end + `endif end $display ("L15_MON_END"); $display (""); @@ -1178,6 +1191,7 @@ begin end // Monitor WMT duplicate error + `ifndef PITON_ARIANE_HPDC if (`L15_PIPE0.val_s3) begin {wmt_read_data_TILE0[3], wmt_read_data_TILE0[2], wmt_read_data_TILE0[1], wmt_read_data_TILE0[0]} = `L15_PIPE0.wmt_l15_data_s3; @@ -1196,6 +1210,7 @@ begin end end end + `endif // Monitor tags duplication error (bug #86) if (`L15_PIPE0.val_s2 && `L15_PIPE0.decoder_dtag_operation_s2 == `L15_DTAG_OP_READ) diff --git a/piton/verif/env/manycore/manycore_top.v.pyv b/piton/verif/env/manycore/manycore_top.v.pyv index b5dd22500..dd225655a 100644 --- a/piton/verif/env/manycore/manycore_top.v.pyv +++ b/piton/verif/env/manycore/manycore_top.v.pyv @@ -305,10 +305,14 @@ system system( `endif // endif PITON_CHIPSET_DIFF_CLK `else // ifndef PITON_CHIPSET_CLKS_GEN `ifndef VERILATOR +`ifndef PITON_NO_CHIP_BRIDGE .chipset_clk(chipset_clk), `else .chipset_clk(core_ref_clk), -`endif +`endif // endif PITON_NO_CHIP_BRIDGE +`else + .chipset_clk(core_ref_clk), +`endif // endif VERILATOR `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 .mc_clk(mem_clk),